DS0147

Microchip Technology

PolarFire SoC Advanced Datasheet December 2019

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PDF pages: 128

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Datasheet sections

1 Revision History
2 Overview
3 Device Offering
4 Silicon and Libero Tool Status
5 DC Characteristics
5.1 Absolute Maximum Rating
5.2 Recommended Operating Conditions
5.2.1 DC Characteristics over Recommended Operating Conditions
5.2.2 Maximum Allowed Overshoot and Undershoot
5.3 Input and Output
5.3.1 DC Input and Output Levels
5.3.2 Differential DC Input and Output Levels
5.3.3 Complementary Differential DC Input and Output Levels
5.3.4 HSIO On-Die Termination
5.3.5 GPIO On-Die Termination
6 AC Switching Characteristics
6.1 Microprocessor Subsystem
6.1.1 CPU Performance
6.1.2 Clocks
6.1.3 MSS DDR
6.1.4 Gigabit Ethernet MAC
6.1.5 SD_SDIO
6.1.7 USB
6.1.8 CAN
6.1.9 MMUART
6.1.10 QSPI
6.1.11 SPI
6.1.12 I2C
6.1.13 Watchdog Timer
6.1.14 Timers
6.1.15 Fabric Interface
6.2 I/O Standards Specifications
6.2.1 Input Delay Measurement Methodology Maximum PHY Rate for Memory Interface IP
6.2.2 Output Delay Measurement Methodology
6.2.3 Input Buffer Speed
6.2.4 Output Buffer Speed
6.2.5 Maximum PHY Rate for FPGA Memory Interface IP
6.2.6 User I/O Switching Characteristics
6.3 Clocking Specifications
6.3.1 Clocking
6.3.2 PLL
6.3.3 DLL
6.3.4 RC Oscillators

PolarFire SoC Advanced Datasheet December 2019

iiiMicrosemi Proprietary and Confidential. DS0147 Revision 1.0

ivMicrosemi Proprietary and Confidential. DS0147 Revision 1.0

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 1.0 Revision 1.0 was the first publication of this document. 1Microsemi Proprietary and Confidential. DS0147 Revision 1.0

Revision History

2 Overview

This datasheet describes PolarFire SoC device characteristics with industrial temperature range (–40 °C to 100 °C TJ) and extended commercial temperature range (0 °C to 100 °C TJ). The devices are provided with a standard speed grade (STD) and a –1 speed grade with higher performance. The FPGA core supply VDD can operate at 1.0 V for lower-power or 1.05 V for higher performance. Similarly, the transceiver core supply VDDA can also operate at 1.0 V or 1.05 V. Users select the core operating voltage while creating the Libero project. 2Microsemi Proprietary and Confidential. DS0147 Revision 1.0 Overview

3 Device Offering

The following table lists the PolarFire SoC device options using the MPFS250T as an example. The MPFS025T, MPFS095T, MPFS160T, and MPFS460T device densities have identical offerings. Table 1 • PolarFire SoC Device Options Data Security S Lower Static Power L Transceivers T–1STDIndustrial –40 °C–100 °C Extended Commercial 0 °C–100 °C Device Options YesYesYesYesYesMPFS250T YesYesYesYesYesMPFS250TL YesYesYesYesYesMPFS250TS YesYesYesYesYesMPFS250TLS 3Microsemi Proprietary and Confidential. DS0147 Revision 1.0 Device Offering

4 Silicon and Libero Tool Status

There are three status levels:

Advanced—initial estimated information based on simulations
Preliminary—information based on simulation and/or initial characterization
Production—final production data The following tables list the status of the PolarFire SoC silicon and Libero Timing and Power tool. Table 2 • PolarFire SoC Silicon Status SiliconProduct AdvancedMPFS250T, TS, TL, TLS Table 3 • PolarFire SoC Tool Status Libero VersionStatusProduct PowerTiming IndustrialExtended CommercialIndustrialExtended Commercial –1STD–1STD–1STD–1STD T, TS, TL, TLS 4Microsemi Proprietary and Confidential. DS0147 Revision 1.0 Silicon and Libero Tool Status

5 DC Characteristics

This section lists the DC characteristics of the PolarFire SoC device.

5.1 Absolute Maximum Rating

The following table lists the absolute maximum ratings for PolarFire SoC devices. Table 4 • Absolute Maximum Rating UnitMaxMinSymbolParameter V1.13–0.5VDDDevice core power sup- ply V1.13–0.5VDDATransceiver Tx and Rx lanes supply V2.0–0.5VDD18Programming and HSIO receiver supply V2.7–0.5VDD25Device core and device PLL high-voltage supply V2.7–0.5VDDA25Transceiver PLL high- voltage supply V3.6–0.5VDD_XCVR_CLKTransceiver reference clock supply V3.6–0.5XCVRVREFGlobal VREF for transceiver reference clocks V2.0–0.5VDDIxHSIO DC I/O supply2 V3.6–0.5VDDIxGPIO DC I/O supply2 V3.6–0.5VDDI3Dedicated I/O DC supply for JTAG and SPI V3.6–0.5VDDAUXxGPIO auxiliary power supply for I/O bank x2 V3.8–0.5VINMaximum DC input voltage on GPIO V2.2–0.5VINMaximum DC input voltage on HSIO V1.26–0.5Transceiver VINTransceiver receiver ab- solute input voltage V3.6–0.5Transceiver REFCLK VINTransceiver reference clock absolute input voltage 5Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

°C150–65TSTGStorage temperature (ambient)1 °C135–55TJJunction temperature1 °C260TSOLROHSMaximum soldering temperature RoHS 1. See FPGA Programming Cycles vs Retention Characteristics for retention time vs temperature. The total time used in calculating the device retention includes the device operating temperature time and temperature during storage time. 2. The power supplies for a given I/O bank x are shown as VDDIx and VDDAUXx.

5.2 Recommended Operating Conditions

The following table lists the recommended operating conditions. Table 5 • Recommended Operating Conditions ConditionUnitMaxTypMinSymbolParameter V1.031.000.97VDDDevice core sup- ply at 1.0 V mode1, 6 V1.081.051.02VDDDevice core sup- ply at 1.05 V mode1, 6 When all lane rates are 10.312 5 Gbps or less.1 V1.031.000.97VDDATransceiver TX and RX lanes supply (1.0 V mode)6, 7 Must when any lane rate is V1.081.051.02VDDATransceiver TX and RX lanes greater than 10.supply (1.05 V mode)6 3125 Gbps. L- ane rates 10.31

25 Gbps or less

powered in 1.05 V mode.1 V1.891.801.71VDD18Programming and HSIO receiv- er supply6 V2.5752.502.425VDD25Device core and device PLL high- voltage supply6 V2.5752.502.425VDDA25Transceiver PLL high-voltage supply6 6Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

ConditionUnitMaxTypMinSymbolParameter 3.3 V nominalV3.4653.33.135VDD_XCVR_CLKTransceiver ref- erence clock supply6, 7 2.5 V nominalV2.6252.52.375 VVDD_XCVR_ CLKGroundXCVRVREFGlobal VREF for transceiver refer- ence clocks3 Allowed nomi- nal options: 1.2 V1.89Various1.14VDDIxHSIO DC I/O supply6 V, 1.35 V, 1.5 V, and 1.8 V4, 5 Allowed nomi- nal options: 1.2 V3.465Various1.14VDDIxGPIO DC I/O supply6 V, 1.5 V, 1.8 V, 2 .5 V, and 3.3 V2, 4, 5 Allowed nomi- nal options: 1.8 V3.465Various1.71VDDI3Dedicated I/O DC supply for JT- V, 2.5 V, and 3.3 V AG and SPI (GPI- O Bank 3)6 For I/O bank x with VDDIx = 3.3 V nominal2, 4, 5 V3.4653.33.135VDDAUXxGPIO auxiliary supply6 For I/O bank x with VDDIx = 2.5 V2.6252.52.375 V nominal or lower2, 4, 5 °C1000TJExtended com- mercial temper- ature range °C100–40TJIndustrial tem- perature range °C1000TPRGExtended com- mercialprogram- ming tempera- ture range °C100–40TPRGIndustrial pro- gramming tem- perature range 1. VDD and VDDA can independently operate at 1.0 V or 1.05 V nominal. These supplies are not dynamically adjustable. 2. For GPIO buffers where I/O bank is designated as bank number, if VDDIx is 2.5 V nominal or 3.3 V nominal, VDDAUXx must be connected to the VDDIx supply for that bank. If VDDIx for a given GPIO bank is <2.5 V nominal, VDDAUXx per I/O bank must be powered at 2.5 V nominal. 3. XCVRVREF globally sets the reference voltage of the transceiver's single-ended reference clock input buffers. It is typically near VDD_XCVR _CLK/2 V but is allowed in the specified range. 7Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

The power supplies for a given I/O bank x are shown as VDDIx and VDDAUXx. 5. At power up and power down the VDDIx and VDDAUXx supply sequencing can cause signal glitches. Refer to UG0686: PolarFire FPGA I/O User Guide and UG0726: PolarFire FPGA Board Design User Guide for detailed explanation and recommended steps. 6. The recommended power supply tolerances include DC offset of the supply plus any power supply ripple over the customer design frequencies of interest, as measured at the device package pins. An example for a valid power supply that meets the recommendations for the VDD supply is 1.0 V ±10 mV or 1.05 V ±10 mV for DC offset with an additional power supply ripple of ±20 mV for a total of 1.0 V ±30 mV or 1.05 V ±30 mV. 7. Both VDDA and VDD_XCVR_CLK supplies must be powered when any of the transceivers are used. VDD_XCVR_CLK must power on within the I/O calibration time (as specified for the device in Libero). VDDA and VDD_XCVR_CLK must both then remain powered during operation. If VDDA needs to be powered down, VDD_XCVR_CLK must also be powered down. There is no required sequence for powering up or down VDDA and VDD_XCVR_CLK.

5.2.1 DC Characteristics over Recommended Operating Conditions

The following table lists the DC characteristics over recommended operating conditions. Table 6 • DC Characteristics over Recommended Operating Conditions ConditionUnitMaxMinSymbolParameter pf5.6CIN (GPIO) Dedicated input pins Input pin capacitance1 pf2.8CIN (HSIO) I/O disabled, high—ZµA10IL (GPIO)Input or output leakage current per pin I/O disabled, high—ZµA10IL (HSIO) VDDIx = 3.3 VµA220137IPUPad pull-up when VIN = 0 VDDIx = 2.5 VµA166102Pad pull-up when VIN = 0 VDDIx = 1.8 VµA11568Pad pull-up when VIN = 0 VDDIx = 1.5 VµA8851Pad pull-up when VIN = 0 VDDIx = 1.35 VµA7329Pad pull-up when VIN = 0 VDDIx = 1.2 VµA4616Pad pull-up when VIN = 0 VDDIx = 3.3 VµA18765IPDPad pull-down when VIN = 3.3 V (GPIO only) VDDIx = 2.5 VµA16063Pad pull-down when VIN = 2.5 V (GPIO only) VDDIx = 1.8 VµA11760Pad pull-down when VIN = 1.8 V VDDIx = 1.5 VµA9557Pad pull-down when VIN = 1.5 V 8Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

ConditionUnitMaxMinSymbolParameter VDDIx = 1.35 VµA8652Pad pull-down when VIN = 1.35 V VDDIx = 1.2 VµA7947Pad pull-down when VIN = 1.2 V 1. Represents the die input capacitance at the pad (not the package). Table 7 • Minimum and Maximum Rise and Fall times ConditionMaximum fre- quency UnitMaxMinSymbolParameter Not to exceed 1 μs

100 KHzps10% bit period200 ps2,3TRISE

Input rise time1,4 Input fall time1,4 Not to exceed 30 0 ns 400 KHzps12.5% bit period Not to exceed 50 ns

50 MHzps20% bit period

800 MHzns4

Voltage ramp must be monotonic. For single-ended IO standards, input rise time is specified from 10%–90% of VDDIx and input fall time is specified from 90%–10% of VDDIx. For voltage referenced and differential IO configurations, ramp times must always comply with I/O standard requirements to ensure compliance. 2. Input slew rates must be controlled to never exceed PAD overshoot/undershoot requirements. Input pad overshoot and undershoot specifications are shown in section Maximum Allowed Overshoot and Undershoot. 3. Rise and fall times in this table are for unterminated inputs. When inputs are terminated, minimum ramp time is not restricted. Recommended minimum ramp time is 25% of bit period, not to exceed a rate of 5 V/ns. 4. Ramp times must not exceed I/O standard requirements to ensure compliance.

5.2.2 Maximum Allowed Overshoot and Undershoot

The following table lists the maximum AC input voltage (VIN) overshoot duration for HSIO. During transitions, input signals may overshoot and undershoot the voltage listed as follows. Input currents must be limited to less than 100 mA per latch-up specifications. The maximum overshoot duration is specified as a high-time percentage over the lifetime of the device. A DC signal is equivalent to 100% of the duty-cycle. Table 8 • Maximum Overshoot During Transitions for HSIO Condition (V)AC (VIN) Overshoot Duration as % at TJ = 100 °C 1.8100 1.85100 1.9100 9Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Condition (V)AC (VIN) Overshoot Duration as % at TJ = 100 °C 1.95100 2100 2.05100 2.1100 2.15100 2.2100 2.2590 2.330 2.357.5 2.41.9 Note: Overshoot level is for VDDI at 1.8 V. The following table lists the maximum AC input voltage (VIN) undershoot duration for HSIO. Table 9 • Maximum Undershoot During Transitions for HSIO Condition (V)AC (VIN) Undershoot Duration as % at TJ = 100 °C –0.05100 –0.1100 –0.15100 –0.2100 –0.25100 –0.3100 –0.35100 –0.4100 –0.4544 –0.514 –0.554.8 –0.61.6 The following table lists the maximum AC input voltage (VIN) overshoot duration for GPIO. 10Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Table 10 • Maximum Overshoot During Transitions for GPIO Condition (V)AC (VIN) Overshoot Duration as % at TJ = 100 °C 3.8100 3.85100 3.9100 3.95100 470 4.0550 4.133 4.1522 4.214 4.259.8 4.36.5 4.354.4 4.43 4.452 4.51.4 4.550.9 4.60.6 Note: Overshoot level is for VDDI at 3.3 V. The following table lists the maximum AC input voltage (VIN) undershoot duration for GPIO. Table 11 • Maximum Undershoot During Transitions for GPIO Condition (V)AC (VIN) Undershoot Duration as % at TJ = 100 °C –0.5100 –0.55100 –0.6100 –0.65100 –0.7100 –0.75100 –0.8100 11Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Condition (V)AC (VIN) Undershoot Duration as % at TJ = 100 °C –0.85100 –0.9100 –0.95100 –1100 –1.05100 –1.1100 –1.15100 –1.2100 –1.2569 –1.345

5.2.2.1 Power Supply Ramp Times

The following table lists the allowable power-up ramp times. Times shown correspond to the ramp of the supply from 0 V to the minimum recommended voltage as specified in the section Recommended Operating Conditions. All supplies must rise and fall monotonically. Table 12 • Power Supply Ramp Times UnitMaxMinSymbolParameter ms500.2VDDFPGA core supply ms500.2VDDATransceiver core supply ms500.2VDD18Must connect to 1.8 V supply ms500.2VDD25Must connect to 2.5 V supply ms500.2VDDA25Must connect to 2.5 V supply ms500.2VDDI[0,1,6,7]HSIO bank I/O power supplies ms500.2VDDI[2,4,5]GPIO bank I/O power supplies ms500.2VDDI3Bank 3 dedicated I/O buffers (GPIO) ms500.2VDDAUX[2,4,5]GPIO bank auxiliary power supplies 12Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

ms500.2VDD_XCVR_CLKTransceiver reference clock supply ms500.2XCVRVREFGlobal VREF for transceiver reference clocks Note: For proper operation of programming recovery mode, if a VDD supply brownout occurs during programming, a minimum supply ramp down time for only the VDD supply is recommended to be 10 ms or longer by using a programmable regulator or on-board capacitors.

5.2.2.2 Hot Socketing

The following table lists the hot socketing DC characteristics over recommended operating conditions. Table 13 • Hot Socketing DC Characteristics over Recommended Operating Conditions ConditionUnitMaxTypMinSymbolParameter VDDA = 0 VmA±4XCVRRX_HSCurrent per transceiver Rx input pin (P or N single-ended)1 , 2 VDDA = 0 VmA±10XCVRTX_HSCurrent per transceiver Tx output pin (P or N single-ended)3 VDD_XCVR_CLK = 0 V mA±1XCVRREF_HSCurrent per transceiverrefer- ence clock input pin (P or N sin- gle-ended)4 VDDIx = 0 VmA±1IGPIO_HSCurrent per GPI- O pin (P or N single-ended)5 Hot socketing is not supported in HSIO. Current per HSI- O pin (P or N single-ended) 1. Assumes device is powered-down, all supplies are grounded, AC-coupled interface, and input pin pairs are driven by a CML driver at the maximum amplitude (1 V pk–pk) that is toggling at any rate with PRBS7 data. 2. Each P and N transceiver input has less than the specified maximum input current. 3. Each P and N transceiver output is connected to a 40 Ω resistor (50 Ω CML termination—20% tolerance) to the maximum allowed output voltage (VDDAmax + 0.3 V = 1.4 V) through an AC-coupling capacitor with all PolarFire SoC device supplies grounded. This shows the current for a worst-case DC coupled interface. As an AC-coupled interface, the output signal will settle at ground and no hot socket current will be seen. 4. VDD_XCVR_CLK is powered down and the device is driven to –0.3 V < VIN < VDD_XCVR_CLK. 13Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

VDDIx is powered down and the device is driven to –0.3 V < VIN < GPIO VDDImax. Note: The following dedicated pins do not support hot socketing: TMS, TDI, TRSTB, and DEVRST_N. Weak pull-up (as specified in GPIO) is always enabled.

5.3 Input and Output

The following section describes DC I/O levels, differential and complementary differential DC I/O levels, HSIO and GPIO on-die termination specifications, and LVDS specifications.

5.3.1 DC Input and Output Levels

The following tables list the DC I/O levels. Table 14 • DC Input Levels VIH Max (V) VIH Min (V) VIL Max (V) VIL Min (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Standard 14Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Max (V) VIH Min (V) VIL Max (V) VIL Min (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Standard 1. GPIO VIH max is 3.45 V with PCI clamp diode turned off regardless of mode, that is, over-voltage tolerant. 2. For external stub-series resistance. This resistance is on-die for GPIO. Note: 3.3 V and 2.5 V are only supported in GPIO banks. Table 15 • DC Output Levels IOH 2,6 mA IOL 2,6 mA VOH Min (V) VOL Max (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Standard Refer to note (VDDI – VOH)/4 (VDDI – VOH)/3 (VDDI – VOH)/4 15Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

2,6 mA IOL 2,6 mA VOH Min (V) VOL Max (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Standard (VDDI – VOH)/3 (VDDI – VOH)/5 (VDDI – VOH)/2 (VDDI – VOH)/5 (VDDI – VOH)/2 (VDDI – VOH)/5 (VDDI – VOH)/2 (VDDI – VOH)/4 (VDDI – VOH)/4 VOL/480.5 × VDDI1.261.21.14POD12I4,5 (VDDI – VOH)/3 VOL/340.5 × VDDI1.261.21.14POD12II4,5 1. Drive strengths per PCI specification V/I curves. 2. Refer to UG0686: PolarFire FPGA User I/O User Guide for details on supported drive strengths. 3. For external stub-series resistance. This resistance is on-die for GPIO. 4. IOL/IOH units for impedance standards in amps (not mA). 5. VOH_MAX based on external pull-up termination (pseudo-open drain). 6. The total DC sink/source current of all IOs within a lane is limited as follows: a. HSIO lane: 120 mA per 12 IO buffers. b. GPIO lane: 160 mA per 12 IO buffers. Note: 3.3 V and 2.5 V are only supported in GPIO banks.

5.3.2 Differential DC Input and Output Levels

The follow tables list the differential DC I/O levels. 16Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Table 16 • Differential DC Input Levels VID Max (V) VID Typ (V) VID Min (V) VICM 1,3 Max (V) VICM 1,3 Typ (V) VICM 1,3 Min (V) VICM_RAN- GE Libero S- etting Bank TypeI/O Stan- dard fault) GPIOLVDS33 fault) GPIOLVDS25 7 fault) GPIOLVDS184 fault) HSIOLVDS18 7 fault) GPIOLCMDS33 fault) HSIOLCMDS18 fault) GPIOLCMDS25 fault) GPIORSDS33 fault) GPIORSDS25 fault) HSIORSDS185 fault) GPIOMINILVDS3 17Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Max (V) VID Typ (V) VID Min (V) VICM 1,3 Max (V) VICM 1,3 Typ (V) VICM 1,3 Min (V) VICM_RAN- GE Libero S- etting Bank TypeI/O Stan- dard fault) GPIOMINILVDS2 fault) HSIOMINILVDS1 fault) GPIOSUBLVDS33 fault) GPIOSUBLVDS25 fault) HSIOSUBLVDS1 fault) GPIOPPDS33 fault) GPIOPPDS25 fault) HSIOPPDS185 fault) GPIOSLVS336 fault) GPIOSLVS256 fault) HSIOSLVS185 18Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Max (V) VID Typ (V) VID Min (V) VICM 1,3 Max (V) VICM 1,3 Typ (V) VICM 1,3 Min (V) VICM_RAN- GE Libero S- etting Bank TypeI/O Stan- dard fault) GPIOHCSL336 fault) GPIOHCSL256 fault) HSIOHCSL185 fault) GPIOBUSLVDSE2 fault) GPIOMLVDSE25 fault) GPIOLVPECL33 fault) GPIOLVPECLE33 fault) GPIOMIPI25 1. V ICM is the input common mode. 2. VID is the input differential voltage. 3. VICM rules are as follows: a. VICM must be less than VDDI – 0.4 V; b. VICM + VID/2 must be <VDDI + 0.4 V; c. VICM – VID/2 must be >VSS – 0.3 V; d. Any differential input with VICM ≤0.6 V requires the low common mode setting in Libero (VICM_RANGE=LOW). 4. VDDI = 1.8 V, VDDAUX = 2.5 V. 19Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

HSIO receiver only. 6. GPIO receiver only. 7. LVDS25 (GPIO) and LVDS18 (HSIO) configurations should be used in conjunction with I/O CDR when implementing SGMII receivers. Table 17 • Differential DC Output Levels VOD Max (V) VOD Typ (V) VOD Min (V) VOCM Max (V) VOCM Typ (V) VOCM Min (V) Bank TypeI/O Standard 1. VOCM is the output common mode voltage. 2. VOD is the output differential voltage. 3. Emulated output only, using external resistors. 4. LVDS25 configuration should be used when implementing SGMII transmitters.

5.3.3 Complementary Differential DC Input and Output Levels

The following tables list the complementary differential DC I/O levels. 20Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Table 18 • Complementary Differential DC Input Levels VID2 Max (V) VID Min (V) VICM 1,3 Max (V) VICM 1,3 Typ (V) VICM 1,3 Min (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Stan- dard VDDAUX (GPI- VDDAUX (GPI- VDDAUX (GPI- O) VDDI (HSI- VDDAUX (GPI- O) VDDI (HSI- VDDAUX (GPI- O) VDDI (HSI- VDDAUX (GPI- O) VDDI (HSI- VDDAUX (GPI- O) VDDI (HSI- VDDAUX (GPI- O) VDDI (HSI- 1. VICM is the input common mode voltage. 21Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

VID is the input differential voltage. 3. VICM rules are as follows: a. VICM must be less than VDDI – 0.4 V; b. VICM + VID/2 must be <VDDI + 0.4 V; c. VICM – VID/2 must be >VSS – 0.3 V. Table 19 • Complementary Differential DC Output Levels IOH Min (mA) IOL Min (mA) VOH 1,3 Min (V) VOL Max (V) VOL Min (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Stan- dard (VDDI – VO- H)/40 (VDDI – VO- H)/34 (VDDI – VO- H)/40 (VDDI – VO- H)/34 (VDDI – VO- H)/50 (VDDI – VO- H)/25 (VDDI – VO- H)/50 (VDDI – VO- H)/25 (VDDI – VO- H)/55 (VDDI – VO- H)/25 (VDDI – VO- H)/40 22Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

Min (mA) IOL Min (mA) VOH 1,3 Min (V) VOL Max (V) VOL Min (V) VDDI Max (V) VDDI Typ (V) VDDI Min (V) I/O Stan- dard (VDDI – VO- H)/48 VOL/480.5 × VDDI1.261.21.14POD12I3,4 (VDDI – VO- H)/34 VOL/340.5 × VDDI1.261.21.14POD12II3,4 1. VOH is the single-ended high-output voltage. 2. The total DC sink/source current of all I/Os within a lane is limited as follows: a. HSIO lane: 120 mA per 12 I/O buffers. b. GPIO lane: 160 mA per 12 I/O buffers. 3. VOH_MAX is based on external pull-up termination (pseudo-open drain). 4. IOL/IOH units for impedance standards are in amps (not mA).

5.3.4 HSIO On-Die Termination

The following tables list the on-die termination calibration accuracy specifications for the HSIO bank. Table 20 • Single-Ended (Internal Parallel) Thevenin Termination ConditionUnitMax (%)TypMin (%) VDDI = 1.8 V/1.5 V/1.35 V/1.2 V Ω2050–40 VDDI = 1.8 VΩ2075–40 VDDI = 1.8 VΩ20150–40 VDDI = 1.5 V/1.35 VΩ2020–20 VDDI = 1.5 V/1.35 VΩ2030–20 VDDI = 1.5 V/1.35 VΩ2040–20 VDDI = 1.5 V/1.35 VΩ2060–20 VDDI = 1.5 V/1.35 VΩ20120–20 VDDI = 1.2 VΩ2060–20 VDDI = 1.2 VΩ20120–20 Note: Thevenin impedance is calculated based on independent P and N as measured at 50% of VDDI. For 50 Ω/75 Ω/150 Ω cases, the nearest supported values of 40 Ω/60 Ω/120 Ω are used. Table 21 • Single-Ended (Internal Parallel) Termination to VDDI ConditionUnitMax (%)TypMin (%) VDDI = 1.2 VΩ2034–20 23Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

ConditionUnitMax (%)TypMin (%) VDDI = 1.2 VΩ2040–20 VDDI = 1.2 VΩ2048–20 VDDI = 1.2 VΩ2060–20 VDDI = 1.2 VΩ2080–20 VDDI = 1.2 VΩ20120–20 VDDI = 1.2 VΩ20240–20 Note: Measured at 80% of VDDI. Table 22 • Single-Ended (Internal Parallel) Termination to VSS ConditionUnitMax (%)TypMin (%) VDDI = 1.8 V/1.5 VΩ20120–20 VDDI = 1.8 V/1.5 VΩ20240–20 VDDI = 1.2 VΩ20120–20 VDDI = 1.2 VΩ20240–20 Note: Measured at 50% of VDDI.

5.3.5 GPIO On-Die Termination

The following table lists the on-die termination calibration accuracy specifications for the GPIO bank. Table 23 • On-Die Termination Calibration Accuracy Specifications for GPIO Bank ConditionUnitMax (%)TypMin (%)DescriptionParameter VICM < 0.8 V 6Ω20100–20Internaldifferen- tial termination Differential ter- mination1 0.6 V < VICM < 1.

65 V 6

Ω40100–20

1.4 V < VICM

6Ω80100–20 VDDI = 1.8 V/1.5 V Ω2050–40Internal parallel thevenin termi- nation Single-ended thevenin termi- nation2, 3 VDDI = 1.8 VΩ2075–40 VDDI = 1.8 VΩ20150–40 VDDI = 1.5 VΩ2020–20 VDDI = 1.5 VΩ2030–20 VDDI = 1.5 VΩ2040–20 24Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

ConditionUnitMax (%)TypMin (%)DescriptionParameter VDDI = 1.5 VΩ2060–20 VDDI = 1.5 VΩ20120–20 VDDI = 2.5 V/1.8 V/1.5 V/1.2 V Ω20120–20Internal parallel termination to VSS Single-ended termination to VSS 4, 5 VDDI = 2.5 V/1.8 V/1.5 V/1.2 V Ω20240–20 1. Measured across P to N with 400 mV bias. 2. Thevenin impedance is calculated based on independent P and N as measured at 50% of VDDI. 3. For 50 Ω/75 Ω/150 Ω cases, the nearest supported values of 40 Ω/60 Ω/120 Ω are used. 4. Measured at 50% of VDDI. 5. Supported terminations vary with the I/O type regardless of VDDI nominal voltage. Refer to Libero for available combinations and default settings. 6. When VICM complies with more than one range, use the maximum percentage tolerance of the two ranges. 25Microsemi Proprietary and Confidential. DS0147 Revision 1.0 DC Characteristics

6 AC Switching Characteristics

This section contains the AC switching characteristics of the PolarFire SoC device.

6.1 Microprocessor Subsystem

The following tables describe microprocessor subsystem.

6.1.1 CPU Performance

The following tables describe CPU performance. Table 24 • Extended Commercial Speed Grades (TJ 0 °C–100 °C) Units–1 Max Min STD Max STD Min SymbolParameter MHz667600FE51CPUCLKMaximum E51 CPU clock fre- quency MHz667600FU54CPUCLKMaximum U54 CPU clock fre- quency MHz667/2300FAXICLKAXI Intercon- nect maximum clock frequency MHz667/4150FAHBCLKAHB bus maxi- mum clock fre- quency MHz667/4150FAPBCLKAPB bus maxi- mum clock fre- quency µS66FLOCKMSSPLLMSS PLL maxi- mum lock time MHz667600FMSSPLLMAXMSS PLL maxi- mum outut fre- quency MHz100100FMSSPLLMINMSS PLL mini- mum outut fre- quency MHz20002000FMSSVCOMAXMSS PLL maxi- mum VCO fre- quency MHz800800FMSSVCOMINMSS PLL mini- mum VCO fre- quency 26Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 25 • Industrial Speed Grades (TJ –40 °C–100 °C) Units–1 Max Min STD Max STD Min SymbolParameter MHz667600FE51CPUCLKMaximum E51 CPU clock fre- quency MHz667600FU54CPUCLKMaximum U54 CPU clock fre- quency MHz667/2300FAXICLKAXI Intercon- nect maximum clock frequency MHz667/4150FAHBCLKAHB bus maxi- mum clock fre- quency MHz667/4150FAPBCLKAPB bus maxi- mum clock fre- quency µS66FLOCKMSSPLLMSS PLL maxi- mum lock time MHz667600FMSSPLLMAXMSS PLL maxi- mum outut fre- quency MHz100100FMSSPLLMINMSS PLL mini- mum outut fre- quency MHz20002000FMSSVCOMAXMSS PLL maxi- mum VCO fre- quency MHz800800FMSSVCOMINMSS PLL mini- mum VCO fre- quency Table 26 • MSS Input Clock UnitMaxMinSymbolParameter psTRMSMSSCLKRMS clock jitter ps1000TP2PMSSCLKPeriod jitter peak-to- peak (over 10,000 cy- cles) %7525FDCMSSREFCLKReferenceclockfrequen- cy duty cycle nsFMSSREFCLKReference clock rise time (20%–80%)and fall time (80%–20%) 27Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

MHz125100FMSSREFCLKReferenceclockfrequen- cy

6.1.2 Clocks

The following table describes the clocks. Table 27 • Clocks UnitsMaxMinSymbolParameter MHz667FMSSCLKMSS clock MHz1FRTCCLKRTC clock

6.1.3 MSS DDR

The following table describes the MSS DDR speed grades. Table 28 • MSS DDR Speed Grades Unit–1 Max Min STD Max STD Min DRAM TypePackageMemory Standard Mbps16001600Single rank component AllDDR4 Mbps1 rank DIMM1 All Mbps2 rank DIMM1 ,3, 8 All Mbps16001600Single die package7 AllLPDDR4 MbpsDual die pack- age6,7 All Mbps1333106613331066Single rank component AllDDR3 Mbps1 rank DIMM1 All Mbps2 rank DIMM1 ,3, 8 All Mbps13331333Single rank component AllDDR3L Mbps1 rank DIMM1 All 28Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1 Max Min STD Max STD Min DRAM TypePackageMemory Standard Mbps2 rank DIMM1 ,3, 8 All Mbps1333106613331066Single die package AllLPDDR3 Mbps1333106613331066Dual die pack- age All 1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, and UDIMM. 2. Includes: 1 rank 1 slot, dual-die package 2 rank. 3. Includes: 2 rank 1 slot. 4. The JEDEC JESD79-4B standard for DDR4 SDRAM limits the maximum tCK to 1.6 ns. Because of this limitation, Microsemi recommends working with your DRAM vendor to verify support for data rates at or less than 1066 Mbps. 5. Byte-mode LPDDR4 devices are not supported. 6. Dual die package includes single die with ECC. 7. LPDDR4 support is only available as a 32-bit interface. 8. Refer to board design guidelines for trace matching requirements.

6.1.4 Gigabit Ethernet MAC

The following tables describe the Gigabit Ethernet MAC (GEM). Table 29 • Serial-GMII Protocol Characteristics (Dedicated MSS SGMIO PHY) UnitsMaxMinLine Rate (Mbps)Parameter UI0.251250SGMII deterministic transmitter jitter UI0.251250SGMII total receiver jit- ter tolerance Table 30 • GEM External Filter Clock UnitsMaxMinParameter MHz62.5GEM external filter clock Table 31 • MII Protocol (Interface to FPGA Fabric) UnitsMaxMinSymbolParameter ns5.0TMIIDCKInput setup to MII clocks, all inputs ns0.0TMIICKDInput hold to MII clocks, all inputs 29Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitsMaxMinSymbolParameter ns5.0TMIICKOMII clock to output valid, all outputs MHz2.5 (at 10 Mbps), 25 (at 100 Mbps) FMIICLKMIIdeviceclockfrequen- cy Table 32 • GMII Protocol (Interface to FPGA Fabric) UnitsMaxMinSymbolParameter ns2.0TGMIIDCKInput setup to GMII clocks, all inputs ns0.0TGMIICKDInput hold to GMII clocks, all inputs ns2.0TGMIICKOGMII clock to output valid, all outputs MHz125FGMIICLKGMII device clock fre- quency

6.1.5 SD_SDIO

The following tables describe SD_SDIO. The test conditions for SD/SDIO standard mode (default speed mode) use an 8 mA drive strength, fast slew rate, and a 30 pF load. For SD/SDIO high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other SD/SDIO high-speed modes, the test conditions use a 12 mA drive strength, fast slew rate, and a 15 pF load. Table 33 • SD/SDIO Interface DDR50 Mode UnitsMaxTypMinSymbolParameter %5545TDCDDRCLKSD device clock du- ty cycle ns6.81.0TSDDDRCKO1Clock to output de- lay, data ns3.5TSDDDRIVWInput valid data window ns4.7TSDDDRDCK2Input setup time, command ns1.5TSDDDRCKD2Input hold time, command ns13.81.0TSDDDRCKO2Clock to output de- lay, command MHz50FSDDDRCLKHigh-speed mode SD device clock fre- quency 30Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 34 • SD/SDIO Interface SDR104 UnitsMaxTypMinSymbolParameter %6040TDCSDHSCLK1SD device clock du- ty cycle ns3.21.0TSDSDRCKO1Clock to output de- lay, all outputs UI0.5TSDSDR1IVWInput valid data window MHz200FSDSDRCLK1SDR104 mode de- vice clock frequen- cy Table 35 • SD/SDIO Interface SDR50/25 UnitsMaxTypMinSymbolParameter %6040TDCSDHSCLK2SD device clock du- ty cycle ns6.81.0TSDSDRCKO2Clock to output de- lay, all outputs UI0.3TSDSDR2IVWInput valid data window MHz100FSDSDRCLK2SDR50mode device clock frequency MHz50FSDSDRCLK2SDR25mode device clock frequency Table 36 • SD/SDIO Interface SDR12 UnitsMaxTypMinSymbolParameter %6040TDCSDHSCLK3SD device clock du- ty cycle ns36.81.0TSDSDRCKO3Clock to output de- lay, all outputs ns10.0TSDSDRDCK3Input setup time, all inputs ns1.5TSDSDRCKD3Input hold time, all inputs MHz25FSDSDRCLK3SDR12mode device clock frequency 31Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 37 • SD/SDIO Interface High-Speed Mode UnitsMaxTypMinSymbolParameter %5347TDCSDHSCLKSD device clock du- ty cycle ns13.82.2TSDHSCKOClock to output de- lay, all outputs UI0.4TSDHSDIVWInput valid data window MHz50FSDHSCLKHigh-speed mode SD device clock fre- quency Table 38 • SD/SDIO Interface Standard Mode UnitsMaxTypMinSymbolParameter %5545TDCSDHSCLKSD device clock du- ty cycle ns4.5–2.0TSDSCKOClock to output de- lay, all outputs ns2.0TSDSDCKInput setup time, all inputs ns2.0TSDSCKDInput hold time, all inputs KHz400FSDIDCLKClock frequency in identification mode MHz19FSDSCLKStandard SD device clock frequency 6.1.6 eMMC The following tables describe the eMMC. The test conditions for eMMC standard mode use an 8 mA drive strength, fast slew rate, and a 30 pF load (I/O voltage of 3 V/1.8 V/1.2 V). For eMMC high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and 30 pF load (I/O voltage of 3 V/1.8 V/1.2 V). For other eMMC modes, the test conditions use a 12 mA drive strength, fast slew rate, and 15 pF load (I/O voltage of 1.8 V/1.2 V) Table 39 • eMMC Standard Interface UnitsMaxTypMinSymbolParameter %5545TDCEMMCHSCLKeMMC clock duty cycle ns4.5–2.0TEMMCHSCKOClock to output de- lay, all outputs ns2.0TEMMCHSDCKInput setup time, all inputs 32Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitsMaxTypMinSymbolParameter ns2.0TEMMCHSCKDInput hold time, all inputs MHz25FEMMCHSCLKeMMC clock fre- quency Table 40 • eMMC High-Speed SDR Interface UnitsMaxTypMinSymbolParameter %5545TDCEMMCHSCLKeMMC high-speed SDR clock duty cy- cle ns16.83.2TEMMCHSCKOClock to output de- lay, all outputs2 UI0.4TEMMCDIVWInput valid data window3 MHz50TEMMCHSCLKeMMC high-speed SDR clock frequen- cy Table 41 • eMMC High-Speed DDR Interface UnitsMaxTypMinSymbolParameter %5545TDCEMMCDDRCLKeMMC high-speed DDR clock duty cy- cle ns7.32.7TEMMCDDRSCKO1Data clock to out- put delay ns3.5TEMMCDDRIVWInput valid data window3 ns16.03.2TEMMCDDRSCKO2Command clock to output delay ns3.9TEMMCDDRSCK2Command input setup time ns2.5TEMMCDDRSCKD2Command input hold time MHz50TEMMCDDRCLKeMMC high-speed DDR clock frequen- cy Table 42 • eMMC HS200 Interface UnitsMaxTypMinSymbolParameter %6040TDCEMMCHS200CLKeMMC HS200 clock duty cycle 33Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitsMaxTypMinSymbolParameter ns3.41.0TEMMCHS200CKOClock to output de- lay, all outputs2 UI0.4TEMMCSDR1IVWInput valid data window3 MHz200TEMMCHS200CLKeMMC HS200 clock frequency Table 43 • eMMC HS400 Interface UnitsMaxTypMinSymbolParameter %6040TDCEMMCHS400CLKeMMC HS400 clock duty cycle ns3.41.0TDCEMMCHS400CKOClock to output de- lay, all outputs2 UI0.4TDCEMMCSDRIVWInput valid data window3 MHz200TEMMCHS400CLKeMMC HS400 clock frequency Table 44 • eMMC HS400 Enhanced Strobe Interface UnitsMaxTypMinSymbolParameter %6040TDCEMMCHS400ESCLKeMMC HS400ES clock duty cycle ns3.41.0TDCEMMCHS400ESCKOClock to output de- lay, all outputs2 UI0.4TDCEMMCSDRIVWInput valid data window3 MHz200TEMMCHS400ESCLKeMMC HS400ES clock frequency

6.1.7 USB

The following table describes the USB. Test conditions are LVCMOS33, slow slew rate, 8 mA drive strength, 15 pF loads, and 60 MHz device clock frequency. Table 45 • USB UnitsMaxMinSymbolParameter ns4.5TULPIDCKInput setup to ULPI clocks, all inputs ns0.0TULPICKDInput hold to ULPI clocks, all inputs 34Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitsMaxMinSymbolParameter ns8.52.0TULPICKOULPI clock to poutput valid, all outputs MHz60FULPICLKULPI device clock fre- quency

6.1.8 CAN

The following table describes CAN. The reference clock should be fixed to achieve the 1 Mbps bus rate. Table 46 • CAN UnitsMaxMinSymbolParameter µs1TPWCANRXReceive pulse width µs1TPWCANTXTransmit pulse width MHz80Internally sourced CAN reference clockfrequen- cy NANAExternally sourced CAN reference clockfrequen- cy

6.1.9 MMUART

The following table describes MMUART. Table 47 • MMUART UnitsMaxMinSymbolParameter Mbps6.25BAUDTXMAXTransmit baud rate Mbps6.25BAUDRXMAXReceive baud rate MHz150FUART_REF_CLKUART reference clock frequency

6.1.10 QSPI

The following tables describe the QSPI switching characteristics. Table 48 • Feedback Clock Enabled UnitsMaxMinLoad Conditions SymbolParameter %5545All1, 2TDCQSPICLK1Quad-SPI clock duty cycle ns4.52.915 pF1TQSPICKO1Data and slave se- lect output delay 35Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ns4.52.930 pF2 ns2.315 pF1TQSPIDCK1Input data setup time ns2.330 pF2 ns0.015 pF1TQSPICKD1Input data hold time ns0.030 pF2 ns5.0All1, 2TQSPISSCLK1Slave select assert- ed to next clock edge ns5.0All1, 2TQSPICLKSS1Clock edge to slave select deasserted MHz15015 pFFQSPICLK1Quad-SPI device clock frequency MHz15030 pF Table 49 • Feedback Clock Disabled UnitsMaxMinLoad Conditions SymbolParameter %5545All1, 2TDCQSPICLK2Quad-SPI clock duty cycle ns14.85.215 pF1TQSPICKO2Data and slave se- lect output delay ns14.85.230 pF2 ns2.3All1, 2TQSPIDCK2Input data setup time ns0.0All1, 2TQSPICKD2Input data hold time ns7.0All1, 2TQSPISSCLK2Slave select assert- ed to next clock edge ns7.0All1, 2TQSPICLKSS2Clock edge to slave select deasserted MHz40All1, 2FQSPICLK2Quad-SPI device clock frequency 36Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 50 • Feedback Clock Enabled or Disabled UnitsMaxMinLoad Conditions SymbolParameter MHz150All1, 2FQSPI_REF_CLKQuad-SPI reference clock frequency

6.1.11 SPI

The following tables describes the SPI master and slave mode switching characteristics. The test conditions are configured to the LVCMOS 3.3 V I/O standard with a 12 mA drive strength, fast slew rate, and a 30 pF load. Table 51 • SPI Master Mode Switching Characteristics UnitsMaxMinSymbolParameter %5545TDCMSPICLKSPI master mode clock duty cycle FSPI_REF_CLK cycles1.0TMSPISSCLKSlave select asserted to first active clock edge FSPI_REF_CLK cycles1.0TMSPICLKSSLast active clock edge to slave select deasserted ns–2.0TMSPIDCKInput setup time for MI- SO ns0.3TMSPICKDInput hold time for MIS- O ns5.0–2.0TMSPICKOMOSI and slave select clock to out delay MHz50FMSPICLKSPI master mode device clock frequency MHz150FSPI_REF_CLKSPI reference clock fre- quency Table 52 • SPI Slave Mode Switching Characteristics UnitsMaxMinSymbolParameter FSPI_REF_CLK cycles2.0TSSPISSCLKSlave select asserted to first active clock edge FSPI_REF_CLK cycles2.0TSSPICLKSSLast active clock edge to slave select deasserted ns5.0TSSPIDCKInput setup time for M- OSI ns1.0TSSPICKDInput hold time for MO- SI ns13.00.0TSSPIOCKMISO clock to out delay 37Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitsMaxMinSymbolParameter MHz25FSSPICLKSPI slave mode device clock frequency

6.1.12 I2C

The following table describes I2C. Table 53 • I2C ConditionsUnitsMaxTypMinSymbolParameter See Single-End- ed I/O Stan- V0.8–0.3VILInput low volt- age dards for more information. I/ O standard used for illustration: MSSIO bank–LV- TTL 8 mA low drive. See Single-End- ed I/O Stan- V3.452VIHInput high volt- age dards for more information. I/ O standard used for illustration: MSSIO bank–LV- TTL 8 mA low drive. V0.05 x VDDIVhysHysterisis of S- chmitt trigger inputs for VDDI > 2 V See Single-End- ed I/O Stan- V0.4VOLOutput low volt- age (open drain) dards for moreat 3 mA sink information. I/current for VDDI > 2 V O standard used for illustration: MSSIO bank–LV- TTL 8 mA low drive. Standard modens1000trRise time for in- put clock and data Fast modens300 CLOAD=400 pFns21tfoOutput fall time from Vihmin to Vilmax CLOAD=100 pFns6 Fast modeKHz400FI2CSCL clock fre- quency Standard modeKHz100 38Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionsUnitsMaxTypMinSymbolParameter VIN = 0, f = 1.0 M- Hz pF10CiInput capaci- tance pFCbCapacitive load for each bus line PCLK1TI2CLLow period of S- CL clock cycles PCLK1TI2CHHigh period of SCL clock cycles PCLK1Tsu(start)Setup time for a repeated START condition cycles PCLK1Th(start)Hold time for a repeated START cycles condition (after this period, the first clock pulse is generated) PCLK1Tsu(data)Data setup time cycles PCLK1Th(data)Data input hold time cycles PCLK1Tod(data)Data output de- lay time cycles PCLK1Tsu(stop)Setup time for STOP condition cycles PCLK1TbufBus free time between a STOP cycles andSTART condi- tion

6.1.13 Watchdog Timer

The following table describes the watchdog timer (WDT). Table 54 • Watchdog timer UnitsMaxMinSymbolParameter MHz250FWDTCLKWatchdog timer input clock frequency

6.1.14 Timers

The following table describes the timers. 39Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 55 • Timers UnitsMaxMinSymbolParameters MHz250FTIMERCLKTimer input clock fre- quency

6.1.15 Fabric Interface

The following tables describe the fabric interface. Table 56 • Maximum Clock Frequency UnitsMaxMinSymbolParameter MHz250FFABRICAXICLKAXI MHz250FFABRICAHBCLKAPB

6.2 I/O Standards Specifications

This section describes I/O delay measurement methodology, buffer speed, switching characteristics, digital latency, gearing training calibration, and maximum physical interface (PHY) rate for memory interface IP.

6.2.1 Input Delay Measurement Methodology Maximum PHY Rate for Memory Interface IP

The following table provides information about the methodology for input delay measurement. Table 57 • Input Delay Measurement Methodology UnitVREF 1, 5VMEAS 3, 4VICM 2VID 2VH 1VL 1DescriptionStandard VVDDI/2VDDI0PCIE 3.3 VPCI VVDDI/2VDDI0LVTTL 3.3 VLVTTL VVDDI/2VDDI0LVCMOS 3.3 V LVCMOS33 VVDDI/2VDDI0LVCMOS 2.5 V LVCMOS25 VVDDI/2VDDI0LVCMOS 1.8 V LVCMOS18 VVDDI/2VDDI0LVCMOS 1.5 V LVCMOS15 VVDDI/2VDDI0LVCMOS 1.2 V LVCMOS12 V1.25VREFVREF + 0.5VREF – 0.5SSTL 2.5 V Class I SSTL25I V1.25VREFVREF + 0.5VREF – 0.5SSTL 2.5 V Class II SSTL25II 40Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

1, 5VMEAS 3, 4VICM 2VID 2VH 1VL 1DescriptionStandard V0.90VREFVREF + 0.5VREF – 0.5SSTL 1.8 V Class I SSTL18I V0.90VREFVREF + 0.5VREF – 0.5SSTL 1.8 V Class II SSTL18II V0.75VREFVREF + .175VREF – .175SSTL 1.5 V Class I SSTL15I V0.75VREFVREF + .175VREF – .175SSTL 1.5 V Class II SSTL15II V0.675VREFVREF + .16VREF – .16SSTL 1.35 V Class I SSTL135I V0.675VREFVREF + .16VREF – .16SSTL 1.35 V Class II SSTL135II V0.75VREFVREF + .5VREF – .5HSTL 1.5 V Class I HSTL15I V0.75VREFVREF + .5VREF – .5HSTL 1.5 V Class II HSTL15II V0.675VREFVREF + .45VREF – .45HSTL 1.35 V Class I HSTL135I V0.675VREFVREF + .45VREF – .45HSTL 1.35 V Class II HSTL135II V0.60VREFVREF + .4VREF – .4HSTL 1.2 V Class I HSTL12I V0.60VREFVREF + .4VREF – .4HSTL 1.2 V Class II HSTL12II V0.90VREFVREF + .54VREF – .54HSUL 1.8 V Class I HSUL18I V0.90VREFVREF + 0.54VREF – .54HSUL 1.8 V Class II HSUL18II V0.60VREFVREF + .22VREF – .22HSUL 1.2 VHSUL12I V0.84VREFVREF + .15VREF – .15Pseudo open drain POD12I (POD) logic

1.2 V Class I

V0.84VREFVREF + .15VREF – .15POD 1.2 V Class II POD12II V01.2500.250VICM + .125VICM – .125Low-voltage differential LVDS33 signaling (L- VDS) 3.3 V 41Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

1, 5VMEAS 3, 4VICM 2VID 2VH 1VL 1DescriptionStandard V01.2500.250VICM + .125VICM – .125Low-com- mon mode LCMDS33 differential signaling (L- CMDS) 3.3 V V LCMDS25 V LCMDS18 V01.2500.250VICM + .125VICM – .125Mini-LVDS 3 .3 V MINILVDS3 V01.2500.250VICM + .125VICM – .125Mini-LVDS 2 .5 V MINILVDS2 V01.2500.250VICM + .125VICM – .125Mini-LVDS 1 .8 V MINILVDS1 3 V SUBLVDS33 5 V SUBLVDS25 8 V SUBLVDS18 V00.8000.250VICM + .125VICM – .125Point-to- point differ- PPDS33 entialsignal- ing 3.3 V V00.2000.250VICM + .125VICM – .125Scalable low-voltage SLVS33 signaling 3. 3 V 42Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

1, 5VMEAS 3, 4VICM 2VID 2VH 1VL 1DescriptionStandard V00.3500.250VICM + .125VICM – .125High-speed current HCSL33 steeringlog- ic (HCSL) 3. 3 V 5 V BLVDSE256 V01.2500.250VICM + .125VICM – .125Multipoint LVDS 2.5 V MLVDSE256 V01.6500.250VICM + .125VICM – .125Low-voltage positive LVPECL33 emitter cou- pled logic V01.6500.250VICM + .125VICM – .125Low-voltage positive LVPECLE336 emitter cou- pled logic V01.2500.250VICM + .125VICM – .125Differential SSTL 2.5 V Class I SSTL25I V01.2500.250VICM + .125VICM – .125Differential SSTL 2.5 V Class II SSTL25II V00.9000.250VICM + .125VICM – .125Differential SSTL 1.8 V Class I SSTL18I V00.9000.250VICM + .125VICM – .125Differential SSTL 1.8 V Class II SSTL18II V00.7500.250VICM + .125VICM – .125Differential SSTL 1.5 V Class I SSTL15I V00.7500.250VICM + .125VICM – .125Differential SSTL 1.5 V Class II SSTL15II V00.6750.250VICM + .125VICM – .125Differential SSTL 1.35 V Class I SSTL135I V00.6750.250VICM + .125VICM – .125Differential SSTL 1.35 V Class I SSTL135II 43Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

1, 5VMEAS 3, 4VICM 2VID 2VH 1VL 1DescriptionStandard V00.7500.250VICM + .125VICM – .125Differential HSTL 1.5 V Class I HSTL15I V00.7500.250VICM + .125VICM – .125Differential HSTL 1.5 V Class II HSTL15II V00.6750.250VICM + .125VICM – .125Differential HSTL 1.35 V Class I HSTL135I V00.6750.250VICM + .125VICM – .125Differential HSTL 1.35 V Class II HSTL135II V00.6000.250VICM + .125VICM – .125Differential HSTL 1.2 V Class I HSTL12I V00.6000.250VICM + .125VICM – .125Differential HSTL 1.2 V Class II HSTL12II V00.9000.250VICM + .125VICM – .125Differential HSUL 1.8 V Class I HSUL18I V00.9000.250VICM + .125VICM – .125Differential HSUL 1.8 V Class II HSUL18II V00.6000.250VICM + .125VICM – .125Differential HSUL 1.2 V HSUL12I V00.8400.250VICM + .125VICM – .125Differential POD 1.2 V Class I POD12I V00.8400.250VICM + .125VICM – .125Differential POD 1.2 V Class II POD12II V00.2000.250VICM + .125VICM – .125Mobile I- ndustry Pro- MIPI25 cessorInter- face 1. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst-case of these measurements. VREF values listed are typical. Input waveform switches between VIL and VIH. All rise and fall rates must be 1 V/ns for non-mixed mode input buffers as one-third the minimum period for mixed-mode input buffers. 2. Differential receiver standards all use 250 mV VID for timing. V ICM is different between different standards. 3. Input voltage level from which measurement starts. 4. The value given is the differential input voltage. 44Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

This is an input voltage reference that bears no relation to the VREF/VMEAS parameters found in IBIS models or shown in the figure Output Delay Measurement—Single-Ended Test Setup. 6. Emulated bidirectional interface.

6.2.2 Output Delay Measurement Methodology

The following section provides information about the methodology for output delay measurement. Table 58 • Output Delay Measurement Methodology VREF (V)VMEAS (V)CREF (pF)RREF (Ω)DescriptionStandard 1.651025PCIE 3.3 VPCI 1.6501MLVTTL 3.3 VLVTTL 1.6501MLVCMOS 3.3 VLVCMOS33 1.2501MLVCMOS 2.5 VLVCMOS25 0.9001MLVCMOS 1.8 VLVCMOS18 0.7501MLVCMOS 1.5 VLVCMOS15 0.6001MLVCMOS 1.2 VLVCMOS12 1.25VREF050Stub-series termi- nated logic 2.5 V C- lass I SSTL25I 1.25VREF050SSTL 2.5 V Class IISSTL25II 0.9VREF050SSTL 1.8 V Class ISSTL18I 0.9VREF050SSTL 1.8 V Class IISSTL18II 0.75VREF050SSTL 1.5 V Class ISSTL15I 0.75VREF050SSTL 1.5 V Class IISSTL15II 0.675VREF050SSTL 1.35 V Class ISSTL135I 0.675VREF050SSTL 1.35 V Class IISSTL135II 0.75VREF050High-speed transceiver logic (HSTL) 1.5 V Class I HSTL15I 0.75VREF050HSTL 1.5 V Class IIHSTL15II 0.675VREF050HSTL 1.35 V Class IHSTL135I 0.675VREF050HSTL 1.35 V Class IIHSTL135II 0.6VREF050HSTL 1.2 V Class IHSTL12I 0.6VREF050HSTL 1.2 V Class IIHSTL12II 45Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

VREF (V)VMEAS (V)CREF (pF)RREF (Ω)DescriptionStandard 0.9VREF050High-speeduntermi- nated logic 1.8 V C- lass I HSUL18I 0.9VREF050HSUL 1.8 V Class IIHSUL18II 0.6VREF050HSUL 1.2 V Class IHSUL12I 0.84VREF050Pseudo open drain (POD) logic 1.2 V C- lass I POD12I 0.84VREF050POD 1.2 V Class IIPOD12II 0010100LVDS 3.3 VLVDS33 0010100LVDS 2.5 VLVDS25 0010100Low-common mode differential LCMDS33 signaling (LCMDS) 3.3 V 000100LCMDS 2.5 VLCMDS25 0010100Reduced swing dif- ferential signaling 3 .3 V RSDS33 0010100RSDS 2.5 VRSDS25 0010100Mini-LVDS 3.3 VMINILVDS33 0010100Mini-LVDS 2.5 VMINILVDS25 0010100Sub-LVDS 3.3 VSUBLVDS33 0010100Sub-LVDS 2.5 VSUBLVDS25 0010100Point-to-point dif- ferential signaling 3 .3 V PPDS33 0010100PPDS 2.5 VPPDS25 0010100Scalable low-volt- age signaling 3.3 V SLVS33 0010100SLVS 2.5 VSLVS25 0010100SLVS 1.5 VSLVSE15 0010100High-speed current steering logic 3.3 V HCSL33 0010100HCSL 2.5 VHCSL25 46Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

VREF (V)VMEAS (V)CREF (pF)RREF (Ω)DescriptionStandard 0010100Bus LVDSBUSLVDSE25 0010100Multipoint LVDS 2. 5 V MLVDSE25 0010100Low-voltage posi- tive emitter-cou- pled logic LVPECLE33 0010100Mobile industry processor interface 2.5 V MIPIE25 001050Differential SSTL 2.

5 V Class I

001050Differential SSTL 2.

5 V Class II

001050Differential SSTL 1.

8 V Class I

001050Differential SSTL 1.

8 V Class II

001050Differential SSTL 1. 001050Differential SSTL 1. 001050Differential SSTL 1.

35 V Class I

001050Differential SSTL 1.

35 V Class II

001050Differential HSTL 1. 001050Differential HSTL 1. 001050Differential HSTL 1. 001050Differential HSTL 1. 001050Differential HSTL 1.

2 V Class I

001050Differential HSTL 1.

2 V Class II

.8 V Class I HSUL18I 47Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

VREF (V)VMEAS (V)CREF (pF)RREF (Ω)DescriptionStandard 001050Differential HSUL 1 .8 V Class II HSUL18II 001050Differential HSUL 1 .2 V Class I HSUL12I 001050Differential POD 1. 001050Differential POD 1.

The value given is the differential output voltage. Figure 1 • Output Delay Measurement—Single-Ended Test Setup Figure 2 • Output Delay Measurement—Differential Test Setup

6.2.3 Input Buffer Speed

The following tables describe input buffer speed. 48Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 59 • HSIO Maximum Input Buffer Speed Unit–1STDStandard Mbps12501250LVDS18 Mbps12501250LCMDS18 Mbps800800HCSL18 Mbps800800RSDS18 Mbps800800MINILVDS18 Mbps800800SUBLVDS18 Mbps800800PPDS18 Mbps800800SLVS18 Mbps1066800SSTL18I Mbps1066800SSTL18II Mbps13331066SSTL15I Mbps13331066SSTL15II Mbps13331066SSTL135I Mbps13331066SSTL135II Mbps1100900HSTL15I Mbps1100900HSTL15II Mbps10661066HSTL135I Mbps10661066HSTL135II Mbps400400HSUL18I Mbps400400HSUL18II Mbps13331066HSUL12I Mbps12661066HSTL12I Mbps12661066HSTL12II Mbps16001333POD12I Mbps16001333POD12II Mbps500500LVCMOS18 (12 mA) Mbps500500LVCMOS15 (10 mA) Mbps300300LVCMOS12 (8 mA) 49Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Notes:

Performance is achieved with VID ≥200 mV.
LVDS18 configuration should be used in conjunction with I/O CDR when implementing SGMII receivers. Table 60 • GPIO Maximum Input Buffer Speed Unit–1STDStandard Mbps16001250LVDS25/LVDS33/LCMDS25/LC- MDS33 Mbps800800RSDS25/RSDS33 Mbps800800MINILVDS25/MINILVDS33 Mbps800800SUBLVDS25/SUBLVDS33 Mbps800800PPDS25/PPDS33 Mbps800800SLVS25/SLVS33 Mbps800800SLVSE15 Mbps800800HCSL25/HCSL33 Mbps800800BUSLVDSE25 Mbps800800MLVDSE25 Mbps800800LVPECL33 Mbps800800SSTL25I Mbps800800SSTL25II Mbps800800SSTL18I Mbps800800SSTL18II Mbps1066800SSTL15I Mbps1066800SSTL15II Mbps900800HSTL15I Mbps900800HSTL15II Mbps400400HSUL18I Mbps400400HSUL18II Mbps500500PCI Mbps500500LVTTL Mbps500500LVCMOS33 Mbps500500LVCMOS25 50Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1STDStandard Mbps500500LVCMOS18 Mbps500500LVCMOS15 Mbps300300LVCMOS12 Mbps15001000MIPI253 1. All SSTLD/HSTLD/HSULD/LVSTLD/POD type receivers use the LVDS differential receiver. 2. Performance is achieved with VID ≥200 mV. 3. VID ≥ 200 mV, VICM ≥100 mV, Tj= 0.4 UI. 4. LVDS25 configuration should be used in conjunction with I/O CDR when implementing SGMII receivers.

6.2.4 Output Buffer Speed

The following tables describe output buffer speed. Table 61 • HSIO Maximum Output Buffer Speed Unit–1STDStandard Mbps1066800SSTL18I Mbps1066800SSTL18II Mbps1066800SSTL18I (differential) Mbps1066800SSTL18II (differential) Mbps13331066SSTL15I Mbps13331066SSTL15II Mbps13331066SSTL15I (differential) Mbps13331066SSTL15II (differential) Mbps13331066SSTL135I Mbps13331066SSTL135II Mbps13331066SSTL135I (differential) Mbps13331066SSTL135II (differential) Mbps1100900HSTL15I Mbps1100900HSTL15II Mbps1100900HSTL15I (differential) Mbps1100900HSTL15II (differential) Mbps10661066HSTL135I 51Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1STDStandard Mbps10661066HSTL135II Mbps10661066HSTL135I (differential) Mbps10661066HSTL135II (differential) Mbps400400HSUL18I Mbps400400HSUL18II Mbps400400HSUL18I (differential) Mbps400400HSUL18II (differential) Mbps13331066HSUL12I Mbps13331066HSUL12I (differential) Mbps12661066HSTL12I Mbps12661066HSTL12II Mbps12661066HSTL12I (differential) Mbps12661066HSTL12II (differential) Mbps16001333POD12I Mbps16001333POD12II Mbps500500LVCMOS18 (12 mA) Mbps500500LVCMOS15 (10 mA) Mbps300250LVCMOS12 (8 mA) Table 62 • GPIO Maximum Output Buffer Speed Unit–1STDStandard Mbps12501250LVDS25/LCMDS25 Mbps16001250LVDS33/LCMDS33 Mbps800800RSDS25 Mbps800800MINILVDS25 Mbps800800SUBLVDS25 Mbps800800PPDS25 Mbps500500SLVSE15 Mbps500500BUSLVDSE25 52Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1STDStandard Mbps500500MLVDSE25 Mbps500500LVPECLE33 Mbps800800SSTL25I Mbps800800SSTL25II Mbps800800SSTL25I (differential) Mbps800800SSTL25II (differential) Mbps800800SSTL18I Mbps800800SSTL18II Mbps800800SSTL18I (differential) Mbps800800SSTL18II (differential) Mbps1066800SSTL15I Mbps1066800SSTL15II Mbps1066800SSTL15I (differential) Mbps1066800SSTL15II (differential) Mbps900900HSTL15I Mbps900900HSTL15II Mbps900900HSTL15I (differential) Mbps900900HSTL15II (differential) Mbps400400HSUL18I Mbps400400HSUL18II Mbps400400HSUL18I (differential) Mbps400400HSUL18II (differential) Mbps500500PCI Mbps500500LVTTL (20 mA) Mbps500500LVCMOS33 (20 mA) Mbps500500LVCMOS25 (16 mA) Mbps500500LVCMOS18 (12 mA) Mbps500500LVCMOS15 (10 mA) 53Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1STDStandard Mbps300250LVCMOS12 (8 mA) Mbps10001000MIPIE25 Note: LVDS25 configuration should be used when implementing SGMII transmitters.

6.2.5 Maximum PHY Rate for FPGA Memory Interface IP

The following tables describe the maximum PHY rate for FPGA memory interface IP. Table 63 • Maximum PHY Rate for FPGA Memory Interfaces IP for HSIO Banks Fabric –1 (M- Hz) Fabric STD (MHz) –1 (Mbps)STD (Mbps)VDDIVDDAUXGearing RatioMemoryStan- dard 200167160013331.2 V1.8 V8:1DDR4 167133133310671.5 V1.8 V8:1DDR3 167133133310671.35 V1.8 V8:1DDR3L1 16713313338001.2 V1.8 V8:1LPDDR3 137.5112.511009001.5 V1.8 V8:1QDRII+ 133133106710671.35 V1.8 V8:1RLDRAM31 2001678006671.35 V1.8 V4:1RLDRAM31 2001674003331.35 V1.8 V2:1RLDRAM31 13310010678001.8 V1.8 V8:1RLDRAMII 1 2001678006671.8 V1.8 V4:1RLDRAMII 1 2001674003331.8 V1.8 V2:1RLDRAMII 1 1. Simulation data only. Microchip does not provide a soft controller for RLDRAMII, RLDRAM3, or DDR3L. 2. Simulation data only. RLDRAMII is currently not supported with a soft IP controller. Table 64 • Maximum PHY Rate for FPGA Memory Interfaces IP for GPIO Banks Fabric –1 (M- Hz) Fabric STD (MHz) –1 (Mbps)STD (Mbps)VDDIVDDAUXGearing RatioMemoryStan- dard 13310010678001.5 V2.5 V8:1DDR3 1131139009001.5 V2.5 V8:1QDRII+ 2002008008001.8 V2.5 V4:1RLDRAMII1 2002004004001.8 V2.5 V2:1RLDRAMII1 1. Simulation data only. RLDRAMII is currently not supported with a soft IP controller. 54Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.2.6 User I/O Switching Characteristics

The following section describes user I/O switching characteristics. For more information about user I/O timing, see the PolarFire SoC I/O Timing Spreadsheet (to be released). The following interface names are described in UG0686: PolarFire FPGA User I/O User Guide.

6.2.6.1 I/O Digital

The following tables describe I/O digital. Table 65 • I/O Digital Receive Single-Data Rate Switching Characteristics Clock-to-D- ata Condi- tion –1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter From a global clock 500500500500HSIO, GPIORx SDRRX_SDR_G_ A Input FMAX source, aligned From a re- gional clock 250250250250HSIO, GPIORx SDRRX_SDR_R_ A Input FMAX source, aligned From a global clock 500500500500HSIO, GPIORx SDRRX_SDR_G_ C Input FMAX source, cen- tered From a re- gional clock 250250250250HSIO, GPIORx SDRRX_SDR_R_ C Input FMAX source, cen- tered Table 66 • I/O Digital Receive Double Data Rate Switching Characteristics Clock-to-D- ata Condi- tion –1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter From a global clock 690670345335HSIORx DDRRX_DDR_G_ A Input FMAX 650620325310GPIO source, aligned From a re- gional clock 500500250250HSIORx DDRRX_DDR_R_ A Input FMAX 500500250250GPIO source, aligned From a global clock 690670345335HSIORx DDRRX_DDR_G_ C Input FMAX 650620325310GPIO source, cen- tered From a re- gional clock 500500250250HSIORx DDRRX_DDR_R_ C Input FMAX 500500250250GPIO 55Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

–1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter source, cen- tered From a HS_ IO_CLK 700700350350HSIORx DDR digi- tal mode RX_DDRX_ B_G_A Input FMAX 2:1 620600310300GPIO clock source, aligned, global fab- ric clock From a HS_ IO_CLK 700700350350HSIORx DDR digi- tal mode RX_DDRX_ B_G_A Input FMAX 4:1 620600310300GPIO clock source, aligned, global fab- ric clock From a HS_ IO_CLK 700700350350HSIORx DDR digi- tal mode RX_DDRX_ B_G_FA Input FMAX 3.5:1 640640320320GPIO clock source, for fraction- al aligned, global fab- ric clock, fractional input From a HS_ IO_CLK 700700350350HSIORx DDR digi- tal mode RX_DDRX_ B_G_C Input FMAX 2:1 620600310300GPIO clock source, cen- tered, glob- al fabric clock From a HS_ IO_CLK 700700350350HSIORx DDR digi- tal mode RX_DDRX_ B_G_C Input FMAX 4:1 Input FMAX 5:1 620600310300GPIO clock source, cen- tered, glob- al fabric clock From a HS_ IO_CLK 150011000175015001GPIORx DDR digi- tal mode for MIPI RX_DDRX_ B_G_DYN_ MIPI Input FMAX 4:1 clock source, cen- tered, glob- al fabric clock From a HS_ IO_CLK 540440270220HSIORx DDR digi- tal mode RX_DDRX_ B_R_A Input FMAX 2:1 500410250205GPIO clock source, aligned, re- 56Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

–1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter gional fab- ric clock From a HS_ IO_CLK 540440270220HSIORx DDR digi- tal mode RX_DDRX_ B_R_A Input FMAX 4:1 Input FMAX 5:1 500410250205GPIO clock source, aligned, re- gional fab- ric clock From a HS_ IO_CLK 540440270220HSIORx DDR digi- tal mode RX_DDRX_ B_R_C Input FMAX 2:1 500410250205GPIO clock source, cen- tered, re- gional fab- ric clock From a HS_ IO_CLK 540440270220HSIORx DDR digi- tal mode RX_DDRX_ B_R_C Input FMAX 4:1 Input FMAX 5:1 500410250205GPIO clock source, cen- tered, re- gional fab- ric clock 1. VID ≥ 200 mV, VICM ≥100 mV, Tj=0.4 UI. 2. A centered clock-to-data interface can be created with a negedge launch of the data. Table 67 • I/O Digital Transmit Single Data Rate Switching Characteristics Forwarded Clock-to-D- ata Skew –1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter From a global clock 500500500500HSIO, GPIOTx SDRTX_SDR_G_ A Output FMA- X source, aligned1 From a global clock 500500500500HSIO, GPIOTx SDRTX_SDR_G_ C source, cen- tered1 1. A centered clock-to-data interface can be created with a negedge launch of the data. Table 68 • I/O Digital Transmit Double Data Rate Switching Characteristics Forwarded Clock-to-D- ata Skew –1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter From a global clock 10001000500500HSIO, GPIOTx DDRTX_DDR_G_ A Output FMA- X 57Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

–1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter source, aligned From a global clock 10001000500500HSIO, GPIOTx DDRTX_DDR_G_ C source, cen- tered From a HS_ IO_CLK 1000800500400HSIOTx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 2:1 clock source, aligned From a HS_ IO_CLK 16001333800667HSIOTx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 4:1 Output FMA- X 5:1 clock source, aligned From a HS_ IO_CLK 1000800500400HSIOTx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 2:1 clock source, cen- tered with PLL From a HS_ IO_CLK 16001333800667HSIOTx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 4:1 Output FMA- X 5:1 clock source, cen- tered with PLL From a HS_ IO_CLK 1000800500400GPIOTx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 2:1 clock source, aligned From a HS_ IO_CLK 16001250800625GPIOTx DDR digi- tal mode TX_DDRX_ B_A Output FMA- X 4:1 Output FMA- X 5:1 clock source, aligned From a HS_ IO_CLK 1000800500400GPIOTx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 2:1 clock source, cen- tered with PLL From a HS_ IO_CLK 16001250800625GPIOTx DDR digi- tal mode TX_DDRX_ B_C Output FMA- X 4:1 Output FMA- X 5:1 clock source, cen- tered with PLL 58Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

–1 (Mbps)STD (Mbps)–1 (MHz)STD (MHz)I/O TypeTopologyInterface N- ame Parameter From a HS_ IO_CLK 1000800500400GPIOTx DDR digi- tal mode for MIPI TX_DDRX_ B_C_ MIPI Output FMA- X 4:1 clock source, cen- tered with PLL Table 69 • Programmable Delay Unit–1 Max–1 Typ–1 MinSTD MaxSTD TypSTD MinParameter ps29.52512.7353012.7In delay, out delay, DLL delay step sizes Note: Refer to Libero timing reports for configuration specific intrinsic and incremental delays. Figure 3 • LVDS Jitter Tolerance Plot Table 70 • I/O CDR Switching Characteristics Jtolmin (UI)Max Tx to Rx Fre- quency Offset (ppm) Max Data Rate (M- bps) Min Data Rate (M- bps) I/O ConfigurationBuffer Type 0.08±2001250266LVDS18HSIO1, 2 59Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Jtolmin (UI)Max Tx to Rx Fre- quency Offset (ppm) Max Data Rate (M- bps) Min Data Rate (M- bps) I/O ConfigurationBuffer Type 0.1±1001250266LVDS18HSIO1, 2 0.1±1001250266LVDS25GPIO1, 3 1. Jitter tolerance of applied sinusoidal jitter from 1 KHz to 120 MHz, as shown in figure LVDS Jitter Tolerance Plot. It is measured in addition to a stressed eye of Tj= 0.24 UI with VICM of 1.25 V and VIDmin of 250 mV, with the CDR operating at a rate of 1250 Mbps plus or minus the ppm offset listed. 2. HSIO LVDS uses an external 100 Ω differential termination resistor. For more information, see LVDS specification in table Differential DC Input Levels. 3. GPIO LVDS uses an internal 100 Ω differential termination resistor. For more information, see LVDS specification in table Differential DC Input Levels.

6.3 Clocking Specifications

This section describes the PLL and DLL clocking and oscillator specifications.

6.3.1 Clocking

The following table describes clocking specifications. Table 71 • Global and Regional Clock Characteristics (–40 °C to 100 °C) ConditionUnitV DD = 1.05 V V DD = 1.05 V STD V DD = 1.0 V V DD = 1.0 V S- TD SymbolParameter MHz500500500500FMAXGGlobal clock FMAX Transceiver interfaces on- ly MHz375375375375FMAXRRegional clock FMAX Allotherinter- faces MHz250250250250FMAXR At 500 MHzps190190190190TDCDGGlobal clock duty cycle dis- tortion At 250 MHzps120120120120TDCDRRegional clock duty cy- cle distortion The following table describes clocking specifications from –40 °C to 100 °C. Table 72 • High-Speed I/O Clock Characteristics (–40 °C to 100 °C) ConditionUnitVDD = 1.05 V VDD = 1.05 V STD VDD = 1.0 V –1VDD= 1.0V ST- D SymbolParameter HSIO and GPI- O MHz1250100012501000FMAXBHigh-speed I/ O clock FMAX 60Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitVDD = 1.05 V VDD = 1.05 V STD VDD = 1.0 V –1VDD= 1.0V ST- D SymbolParameter HSIO without bridging ps20302030FSKEWBHigh-speed I/ O clock skew1 HSIO with bridging psSee table HSI- O Clock Skew with Bridging. FSKEWB GPIO without bridging ps35453545FSKEWB GPIO with bridging ps60756075FSKEWB HSIO without bridging ps90909090TDCBHigh-speed I/ O clock duty cycle distor- tion2 HSIO with bridging ps115115115115TDCB GPIO without bridging ps90909090TDCB GPIO with bridging ps115115115115TDCB 1. FSKEWB is the worst-case clock-tree skew observable between sequential I/O elements. Clock-tree skew is significantly smaller at I/O registers close to each other because they are fed by the same or adjacent clock-tree branches. Use the Microsemi Timing Analyzer tool to evaluate clock skew specific to the design. 2. Parameters listed in this table correspond to the worst-case duty cycle distortion observable at the I/O flip flops. IBIS should be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times for any I/O standard. The following table describes high-speed I/O clock skew (FSKEWB) with bridging from –40 °C to 100 °C. Note: FSKEWB is the worst-case clock-tree skew observable between sequential I/O elements. Clock-tree skew is significantly smaller at I/O registers close to each other and fed by the same or adjacent clock-tree branches. Use the Microsemi Timing Analyzer tool to evaluate clock skew specific to the design. Table 73 • HSIO Clock Skew with Bridging (–40 °C to 100 °C) UnitVDD = 1.05 V VDD = 1.05 V STD VDD = 1.0 V –1VDD= 1.0V ST- D Bridging S- ource Total I/O B- anks Device ps8012080120NNW12MPF100T ps7011070110NNE22 ps8012080120NNW12MPF200T ps7011070110NNE22 ps8012080120NNW13MPF300T ps200280200280NNE23 61Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitVDD = 1.05 V VDD = 1.05 V STD VDD = 1.0 V –1VDD= 1.0V ST- D Bridging S- ource Total I/O B- anks Device ps8512585125NNW13MPF500T ps220300220300NNE23 1. NNW source designates bridging that originates from the North West Corner or PIOs inside I/O bank 0 (the most western I/O bank at the north edge). 2. NNE source designates bridging that originates from the North East Corner or PIOs inside I/O bank 1 (the most eastern I/O bank at the north edge).

6.3.2 PLL

The following table describes PLL. Table 74 • PLL Electrical Characteristics ConditionUnitMaxTypMinSymbolParameter MHz12501FINIInput clock fre- quency (integer mode) MHz125010FINFInput clock fre- quency(fraction- al mode) ps200FINPULSEMinimum refer- ence or feed- back pulse width1 MHz3121FPHDETIFrequency at the Frequency Phase Detector (PFD) (integer mode) MHz22510FPHDETFFrequency at the PFD (frac- tional mode) %7525FINDUTYAllowable input duty cycle ps1000120FMAXINJMaximum input period clock jit- ter (reference and feedback clocks)2 MHz5000800FVCOPLL VCO fre- quency MHzFPHDET/30FPHDET/44FPHDET/55FBWLoop bandwidth (Int)3 62Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter MHzFPHDET/56FPHDET/77FPHDET/91FBWLoop bandwidth (FRAC)3 psMax (±60 ps, ±0 .5 degrees) TSPOStatic phase off- set of the PLL outputs4

1.5 MHz ≤ Fout

< 15 MHz ps0.025*output_ period TOUTJITTERPLL output peri- od jitter10 Fout ≥ 15 MHzps135 %5448TOUTDUTYPLL output duty cycle precision μsMax (6.0 μs, 62

5 PFD cycles)

PFD cycles82TUNLOCKPLL unlocktime6 MHz12500.050FOUTPLL output fre- quency μs1TMPDPWMinimum pow- er-down pulse width PFD cycles1.5FMAXDFBMaximum delay in the feedback path7 %3.10.1Mod_SpreadSpread spec- trum modula- tion spread8 KHzFPHDETF/(128)32FPHDETF/ (128x6 Mod_FreqSpread spec- trum modula- tion frequency9 1. Minimum time for high or low pulse width. 2. Maximum jitter the PLL can tolerate without losing lock. 3. Default bandwidth setting of BW_PROP_CTRL = "01" for Integer and Fraction modes leads to the typical estimated bandwidth. This bandwidth can be lowered by setting BW_PROP_CTRL = "00" and can be increased if BW_PROP_CTRL = "10" and will be at the highest value if BW_PROP_CTRL = "11". 4. Maximum (±3-Sigma) phase error between any two outputs with nominally aligned phases. 5. Input clock cycle is REFDIV/FREF. For example, FREF = 25 MHz, REFDIV = 1, lock time = 10.0 (assumes LOCKCOUNTSEL setting = 4'd8 (256 cycles)). 6. Unlock occurs if two cycles slip within LOCKCOUNT/4 PFD cycles. 7. Maximum propagation delay of external feedback path in Deskew mode. 8. Programmable capability for depth of down spread or center spread modulation. 9. Programmable modulation rate based on the modulation divider setting (1 to 63). 63Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Period jitter is measured at the output of the device using HSUL12 output buffers and includes the jitter effects of the reference clock source, PLL, clock routing networks, and output buffer. PLL is configured with internal feedback enabled and in integer mode. FPGA fabric is active during testing (75% utilization). Note: In order to meet all datasheet specifications, the PLL must be programmed such that the PLL Loop Bandwidth < (0.0017 * VCO Frequency) – 0.4863 MHz. The Libero PLL configuration tool will enforce this rule when creating PLL configurations.

6.3.3 DLL

The following table provides information about DLL. Table 75 • DLL Electrical Characteristics UnitMaxTypMinSymbolParameter1 MHz800133FINFInput reference clock frequency MHz800133FINFDBFInput feedback clock frequency MHz800133FOUTPFPrimary output clock frequency MHz80033.3FOUTSFSecondary output clock frequency2 ps200FINJInput clock cycle- to-cycle jitter psMax (250 ps, 15% of clock period) TOUTJITTERCCOutput clock cycle- to-cycle jitter (with clean input clock) psMax (300 ps, 20% of clock period) TOUTJITTERPOutputclockperiod jitter (with clean in- put clock) ps±150TSKEWOutput clock-to- clock skew be- tween two outputs with the same phase settings Reference clock cy- cles 16K16TLOCKDLL lock time ns3TMRPWMinimum reset pulse width ns20TMIPWMinimum input pulse width3 ps400TMPWHMinimum input clock pulse width high ps400TMPWLMinimum input clock pulse width low 64Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxTypMinSymbolParameter1 ps353012.7TDELDelay step size ns4.81.8TDELMAXMaximum delay block delay4 %6040TDUTYOutput clock duty cycle (with 50% du- ty cycle input)5 %5545TDUTY50Output clock duty cycle (with 50% du- ty cycle input)6 1. For all DLL modes. 2. Secondary output clock divided by four option. 3. On load, direction, move, hold, and update input signals. 4. 128 delay taps in one delay block. 5. Without duty cycle correction enabled. 6. With duty cycle correction enabled.

6.3.4 RC Oscillators

The following tables describe internal RC clock resources for user designs. They also describe system design with RF front-end information about emitters generated on-chip to support programming operations. Table 76 • 2 MHz RC Oscillator Electrical Characteristics UnitMaxTypMinSymbolParameter MHz2RC2FREQOperating frequen- cy %4–4RC2FACCAccuracy %5446RC2DCDuty cycle ns105RC2PJITPeak-to-peak out- put period jitter ns105RC2CJITPeak-to-peak out- put cycle-to-cycle jitter µA60RC2IVPPAOperating current (VDD25) µA2.6RC2IVDDOperating current (VDD) 65Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 77 • 160 MHz RC Oscillator Electrical Characteristics UnitMaxTypMinSymbolParameter MHz160RCSCFREQOperating frequen- cy %4–4RCSCFACCAccuracy %5247RCSCDCDuty cycle ps600RCSCPJITPeak-to-peak out- put period jitter ps172RCSCCJITPeak-to-peak out- put cycle-to-cycle jitter µA599RCSCVPPAOperating current (VDD25) µA0.1RCSCVPPOperating current (VDD18) µA60.7RCSCVDDOperating current (VDD)

6.4 Fabric Specifications

The following section describes specifications for the fabric.

6.4.1 Math Blocks

The following table lists the maximum operating frequency (FMAX) of the math block in the extended commercial temperature range (0 °C to 100 °C). Table 78 • Math Block Performance Extended Commercial Range (0 °C to 100 °C) UnitVDD = 1.05 V – 1VDD = 1.05 V – STDVDD = 1.0 V – 1VDD = 1.0 V – STDModes MHz50044047037018 × 18 multiplica- tion MHz50044047037018 × 18 multiplica- tion summed with 48-bit input MHz50043546536518 × 19 multiplier pre-adder ROM mode MHz500440470370Two 9 × 9 multipli- cation MHz5004404703709 × 9 dot product (DOTP) MHz500430455360Complex 18 × 19 multiplication 66Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

The following table lists the maximum operating frequency (FMAX) of the math block in the industrial temperature range (–40 °C to 100 °C). Table 79 • Math Block Performance Industrial Range (–40 °C to 100 °C) UnitVDD = 1.05 V – 1VDD = 1.05 V – STDVDD = 1.0 V – 1VDD = 1.0 V – STDModes MHz50043546536518 × 18 multiplica- tion MHz50043546536518 × 18 multiplica- tion summed with 48-bit input MHz50043046035518 × 19 multiplier pre-adder ROM mode MHz500435465365Two 9 × 9 multipli- cation MHz5004354653659 × 9 DOTP MHz500425450350Complex 18 × 19 multiplication

6.4.2 SRAM Blocks

The following table lists the maximum operating frequency (FMAX) of the LSRAM block in the industrial temperature range (–40 °C to 100 °C). Table 80 • LSRAM Performance Industrial Temperature Range (–40 °C to 100 °C) ConditionUnitV DD = 1.05 V – 1V DD = 1.05 V – STDV DD = 1.0 V – 1V DD = 1.0 V – STD Two-port, all sup- ported widths, MHz428343428343 pipelined, simple- write, and write- feed-through Two-port, all sup- ported widths,non- MHz428309428309 pipelined, simple- write, and write- feed-through Dual-port, all sup- ported widths, MHz428343428343 pipelined, simple- write, and write- feed-through Dual-port, all sup- ported widths,non- MHz428309428309 pipelined, simple- write, and write- feed-through Two-port pipelined ECC mode, MHz428343428343 67Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitV DD = 1.05 V – 1V DD = 1.05 V – STDV DD = 1.0 V – 1V DD = 1.0 V – STD pipelined, simple- write, and write- feed-through Two-port non- pipelined ECC MHz295279295279 mode, pipelined, simple-write, and write-feed-through Two-port pipelined ECC mode, non- MHz428343428343 pipelined, simple- write, and write- feed-through Two-port non- pipelined ECC MHz285196285196 mode, non- pipelined, simple- write, and write- feed-through Two-port, all sup- ported widths, MHz285274285274 pipelined, and read-before-write Two-port, all sup- ported widths,non- MHz285274285274 pipelined, and read-before-write Dual-port, all sup- ported widths, MHz285274285274 pipelined, and read-before-write Dual-port, all sup- ported widths,non- MHz285274285274 pipelined, and read-before-write Two-port pipelined ECC mode, MHz285274285274 pipelined, and read-before-write Two-port non- pipelined ECC MHz285274285274 mode, pipelined, and read-before- write Two-port pipelined ECC mode, non- MHz285274285274 pipelined, and read-before-write 68Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitV DD = 1.05 V – 1V DD = 1.05 V – STDV DD = 1.0 V – 1V DD = 1.0 V – STD Two-port non- pipelined ECC MHz285193285193 mode, non- pipelined, and read-before-write The following table lists the maximum operating frequency (FMAX) of the µSRAM block in the industrial temperature range (–40 °C to 100 °C). Table 81 • µSRAM Performance ConditionUnitV DD = 1.05 V – 1 V DD = 1.05 V – STD V DD = 1.0 V – V DD = 1.0 V – STD SymbolParameter Write-portMHz480450415400FMAXOperating fre- quency Read-portns22TacRead access time The following table lists the maximum operating frequency (FMAX) of the µPROM block in the industrial temperature range (–40 °C to 100 °C). Table 82 • µPROM Performance UnitV DD = 1.05 V – V DD = 1.05 V – STD V DD = 1.0 V – 1V DD = 1.0 V – ST- D SymbolParameter ns10101010TacRead access time

6.5 Transceiver Switching Characteristics

This section describes transceiver switching characteristics.

6.5.1 Transceiver Performance

The following table describes transceiver performance. Table 83 • PolarFire SoC Transceiver and TXPLL Performance Unit–1 Max–1 Typ–1 MinSTD MaxSTD TypSTD MinSymbolParameter Gbps12.70.2510.31250.25FTXRateTx data rate1,2 Gbps1.5DC1.5DCFTXRateOOBTx OOB (se- rializer by- pass) data rate Gbps12.70.2510.31250.25FRxRateACRx data rate when AC coupled2 69Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1 Max–1 Typ–1 MinSTD MaxSTD TypSTD MinSymbolParameter Gbps3.20.253.20.25FRxRateDCRx data rate when DC coupled Gbps1.25DC1.25DCFTXRateOOBRx OOB (de- serializer bypass) da- ta rate GHz6.351.65.15631.6FTXPLLTXPLL out- putfrequen- cy3 Gbps10.31250.2510.31250.25FRXCDRRx CDR mode Gbps12.73.010.31253.0FRXAUTOCALRx DFE and CDR auto- calibration modes2 Gbps12.73.010.31253.0FRXEyeMonRx Eye Mon- itor mode 2 [Tx|Rx]_CLK Cycles4 1616MPWPCS_RES- ET PCS reset minimum pulse width [Tx|Rx]_CLK Cycles4 1616MPWPMA_RE- SET PMA reset minimum pulse width 1. The reference clock is required to be a minimum of 75 MHz for data rates of 10 Gbps and above. 2. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 3. The Tx PLL rate is between 0.5x to 5.5x the Tx data rate. The Tx data rate depends on per XCVR lane Tx post-divider settings. 4. Minimum pulse width should reference TX_CLK when Tx only or both Tx and Rx are used. Reference RX_CLK if only Rx is used.

6.5.2 Transceiver Reference Clock Performance

The following table describes performance of the transceiver reference clock. Table 84 • PolarFire SoC Transceiver Reference Clock AC Requirements Unit–1 Max–1 Typ–1 MinSTD MaxSTD TypSTD MinSymbolParameter MHz4002040020FTXREFCLKReference clock input rate1, 2 MHz1562015620FXCVRREFCLKM- AX CASCADE Reference clock input rate1, 2, 3 70Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1 Max–1 Typ–1 MinSTD MaxSTD TypSTD MinSymbolParameter MHz1752015620FTXREFCLKPFDReference clock rate at the Tx PLL PFD4 MHz1757515675FTXREFCLKPFD- 10G Reference clock rate recommend- ed at the PF- D for Tx rates 10 G- bps and above4 dBc/Hz–110–110FTXREFPNTx refer- ence clock phase noise require- ments to meet jitter specifica- tions (156 MHz clock at reference clock in- put)5 dBc/Hz–110–110FTXREFPNPhase noise at 10 KHz dBc/Hz–115–115FTXREFPNPhase noise at 100 KHz dBc/Hz–135–135FTXREFPNPhase noise at 1 MHz ps500200500200TREFRISEReference clock input rise time (1 0%–90%) ps500200500200TREFFALLReference clock input fall time (90 %–10%) MHz1562015620FRXREFCLKCDRReference clock rate at RX CDR %60406040TREFDUTYReference clock duty cycle pread Spread spectrum modulation spread6 71Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1 Max–1 Typ–1 MinSTD MaxSTD TypSTD MinSymbolParameter KHzTxREF CLKP- FD/ (128*6 32TxREF CLKP- FD/ (128) TxREF CLKP- FD/ (128*6 32TxREF CLKP- FD/ (128) Mod_FreqSpread spectrum modulation frequency7 1. See the maximum reference clock rate allowed per input buffer standard. 2. The minimum value applies to this clock when used as an XCVR reference clock. It does not apply when used as a non-XCVR input buffer (DC input allowed). 3. Cascaded reference clock. 4. After reference clock input divider. 5. To calculate the FTXREFPN phase noise requirement at frequencies other than 156 MHz use the following formula: FTXREFPN at f(MHz) = FTXREFPN at 156 MHz + 20*log(f/156) 6. Programmable capability for depth of down-spread or center-spread modulation. 7. Programmable modulation rate based on the modulation divider setting (1 to 63).

6.5.3 Transceiver Reference Clock I/O Standards

The following differential I/O standards are supported as transceiver reference clocks.

LVDS25/33
HCLS25 (for PCIe)
RSDS25/33
MINILVDS25/33
SUBLVDS25/33
PPDS25/33
SLVS25/33
BUSLVDS25
MLVDS25
LVPECL33
MIPI25 For DC input levels, see table Differential DC Input and Output Levels. Note: The transceiver reference clock differential receiver supports VICM common mode. Note: The amount of jitter from the input receiver increases at common modes of less 0.2 V or greater than VDDSREF–0.4 V. Therefore, for improved SerDes operation, it is recommended that the VCM of the signal into the SerDes reference clock input be at a minimum of 0.2 V and below VDDSREF–0.4 V. The following single-ended I/O standards are supported as transceiver reference clocks.
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
SSTL25I/II
SSTL18I/II
HSUL18I/II 72Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

For DC input levels, see table DC Input and Output Levels. Note: Generally, Hysteresis = Off is recommended. In extremely high noise systems with degraded reference clock input, Hysteresis = On may improve results.

6.5.4 Transmitter Performance

The following tables describe performance of the transmitter. Table 85 • Transceiver Reference Clock Input Termination UnitMaxTypMinSymbolParameter Ω50RefTermSingle-endedtermi- nation Ω75RefTermSingle-endedtermi- nation Ω150RefTermSingle-endedtermi- nation Ω1151RefDiffTermDifferentialtermina- tion Ω>50KPower-up termina- tion 1. Measured at VCM= 1.2 V and VID= 350 mV. Note: All pull-ups are disabled at power-up to allow hot plug capability. The following tables describe the PolarFire SoC Transceiver User Interface Clocks Note: Until specified, all modes are non-deterministic. For more information, see UG0677: PolarFire FPGA Transceiver User Guide. Table 86 • Transceiver TX_CLK Range (Nondeterministic PCS Mode with Global or Regional Fabric Clocks) Unit–1 Max–1 MinSTD MaxSTD MinMode MHz2002008-bit, max data rate = 1.6 Gbps MHz16016010-bit, max data rate = 1.6 Gbps MHz30030016-bit, max data rate = 4.8 Gbps MHz30030020-bit, max data rate = 6.0 Gbps MHz32532532-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz32026040-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 73Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1 Max–1 MinSTD MaxSTD MinMode MHz20016564-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz16013080-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz150150Fabric pipe mode 3 2-bit, max data rate = 6.0 Gbps 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. Table 87 • Transceiver RX_CLK Range (Non-Deterministic PCS Mode with Global or Regional Fabric Clocks) Unit–1 Max–1 MinSTD MaxSTD MinMode MHz2002008-bit, max data rate = 1.6 Gbps MHz16016010-bit, max data rate = 1.6 Gbps MHz30030016-bit, max data rate = 4.8 Gbps MHz30030020-bit, max data rate = 6.0 Gbps MHz32532532-bit, max data rate = 10.3125 G- bps MHz32026040-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz20016564-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz16013080-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz150150Fabric pipe mode 3 2-bit, max data rate = 6.0 Gbps 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 74Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 88 • Transceiver TX_CLK Range (Deterministic PCS Mode with Regional Fabric Clocks) Unit–1 Max–1 MinSTD MaxSTD MinMode MHz2002008-bit, max data rate = 1.6 Gbps MHz16016010-bit, max data rate = 1.6 Gbps MHz26622516-bit, max data rate = 3.6 Gbps (–S- TD) / 4.25 Gbps (–1 MHz26622520-bit, max data rate = 4.5 Gbps (–S- TD) / 5.32 Gbps (–1 MHz26622532-bit, max data rate = 7.2 Gbps (–S- TD) / 8.5 Gbps (–1) Mhz26622540-bit, max data rate = 9.0 Gbps (–S- TD) / 10.6 Gbps (–1 MHz20016564-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz16013080-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. Table 89 • Transceiver RX_CLK Range (Deterministic PCS Mode with Regional Fabric Clocks) Unit–1 Max–1 MinSTD MaxSTD MinMode MHz2002008-bit, max data rate = 1.6 Gbps MHz16016010-bit, max data rate = 1.6 Gbps MHz26622516-bit, max data rate = 3.6 Gbps (–S- TD) / 4.25 Gbps (–1 MHz26622520-bit, max data rate = 4.5 Gbps (–S- TD) / 5.32 Gbps (–1 75Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Unit–1 Max–1 MinSTD MaxSTD MinMode MHz26622532-bit, max data rate = 7.2 Gbps (–S- TD) / 8.5 Gbps (–1) MHz26622540-bit, max data rate = 9.0 Gbps (–S- TD) / 10.6 Gbps (–1 MHz20016564-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 MHz16013080-bit, max data rate = 10.3125 G- bps (–STD) / 12.7 Gbps (–1)1 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. Table 90 • PolarFire SoC Transceiver Transmitter Characteristics ConditionUnitMaxTypMinSymbolParameter Ω85VOTERMDifferential ter- mination Ω100VOTERM Ω150VOTERM DC coupled 50% setting V0.59 × VDDA0.525 × VDDA0.44 × VDDAVOCMCommon mode voltage1 DC coupled 60% setting V0.66 × VDDA0.6 × VDDA0.52 × VDDAVOCM DC coupled 70% setting V0.75 × VDDA0.7 × VDDA0.61 × VDDAVOCM DC coupled 80% setting V0.83 × VDDA0.8 × VDDA0.63 × VDDAVOCM 20% to 80%ps6140TTxRFRise time2 Fall time2 80% to 20%ps5839 1000 mV settingmV132011401080VODPPDifferential peak-to-peak amplitude 800 mV settingmV122010601010VODPP 500 mV settingmV670580550VODPP 400 mV settingmV560490465VODPP 76Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter 300 mV settingmV425370350VODPP 200 mV settingmV300260250VODPP 100 mV settingmV185160150VODPP ps158TOSKEWTransmit lane P to N skew3 Single PLL, 2–4 bonded lanes, 8 ps75TLLSKEWLane to lane transmit skew4 –40-bit fabric width10 Single PLL, 2–4 bonded lanes, 6 UI8 4–80-bit fabric width11 Multiple PLL, 2 –4 bonded UI8 + Refclk skew lanes, 8–40-bit fabric width11, 1 Multiple PLL, 2 –4 bonded UI32 + Refclk skew lanes, 64–80-bit fabric width11, 1 ns20TTxEITrEntryElectrical idle transition entry time7 ns19TTxEITrExitElectrical idle transition exit time7 mV7VTxEIppElectrical idle amplitude PFD cycles1600TTXLockTXPLL lock time Frequency lockREFCLK UIs75,000TDPLLLockDigital PLL lock time8 Phase lockREFCLK UIs150,000 Data rate ≥10.3 125 Gbps to 12. UI UI0.22 0.1TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 7 Gbps9 (Tx VCO rate 5.16 GHz to

6.35 GHz)

77Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter Data rate ≥10.3 125 to 12.7 G- UI UI0.28 0.1TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps9 (Tx VCO rate 5.16 GHz to Data rate ≥8.5 Gbps to 10.3125 UI UI0.22 0.09TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 Gbps (Tx VCO rate 4.25 GHz to

5.16 GHz)

Data rate ≥8.5 Gbps to 10.3125 UI UI0.28 0.09TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 Gbps (Tx VCO rate 4.25 GHz to

5.16 GHz) TXPLL

Data rate ≥5.0 Gbps to 8.5 G- UI UI 0.21 0.09TJ TDJTotal jitter5, 6, 13 Deterministic jitter5,6 bps (Tx VCO rate 2.5 GHz to 4.25 GHz) TXPLL in integer mode Data rate ≥5.0 Gbps to 8.5 G- UI UI0.25 0.09TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps (Tx VCO rate 2.5 GHz to 4.25 GHz) TXPLLinfraction- al mode Data rate ≥1.6 Gbps to 5.0 G- UI UI0.17 0.03TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps (Tx VCO rate 1.6 GHz to 2.5 GHz) TXPLL in integer mode Data rate ≥1.6 Gbps to 5.0 G- UI UI0.2 0.03TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps (Tx VCO rate 1.6 GHz to 2.5 GHz) TXPLLinfraction- al mode Data rate ≥ 800 Mbps to 1.6 G- UI UI0.08 0.02TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 78Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter bps (Tx VCO rate

1.6 GHz)

Data rate ≥ 800 Mbps to 1.6 G- UI UI0.11 0.02TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps (Tx VCO rate Data rate = 250 Mbps to 800 M- UI UI0.05 0.01TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps (Tx VCO rate 1.48 GHz to 1.6 GHz) TXPLL in integer mode Data rate = 250 Mbps to 800 M- UI UI0.06 0.01TJ TDJTotal jitter5, 6, 13 Deterministic jitter5, 6 bps (Tx VCO rate 1.48 GHz to 1.6 GHz) TXPLLinfraction- al mode 1. Increased DC common mode settings above 50% reduce allowed VOD output swing capabilities. 2. Adjustable through transmit emphasis. 3. With estimated package differences. 4. Single PLL applies to all four lanes in the same quad location with the same TxPLL. Multiple PLL applies to N lanes using multiple TxPLLs from different quad locations. 5. Improved jitter characteristics for a specific industry standard are possible in many cases due to improved reference clock or higher VCO rate used. 6. Tx jitter is specified with all transmitters on the device enabled, a 10–12-bit error rate (BER) and Tx data pattern of PRBS7. 7. From the PMA mode, the TX_ELEC_IDLE port to the XVCR TXP/N pins. 8. FTxRefClk = 75 MHz with typical settings. 9. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 10. Transmit alignment in this case will automatically align upon the TX PLL obtaining lock. For details on transmit alignment, see UG0677: PolarFire FPGA Transceiver User Guide. 11. In order to obtain the required alignment for these configurations, an FPGA fabric TX alignment circuit must be implemented. For details on transmit alignment, see UG0677: PolarFire FPGA Transceiver User Guide. 12. Refclk skew is the amount of skew between the reference clocks of the two PLL. 13. Jitter decomposition can be found in the protocol characterization reports. 79Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.5.5 Receiver Performance

The following table describes performance of the receiver. Table 91 • PolarFire SoC Transceiver Receiver Characteristics ConditionUnitMaxTypMinSymbolParameter VVDDA + 0.30VINInput voltage range mV1250140VIDPPDifferential peak-to-peak amplitude Ω85VITERMDifferential ter- mination Ω100 Ω150 DC coupledV0.9 × VDDA0.7 × VDDAVICMDC 1Common mode voltage ns10050TEIDETExit electrical idle detection time UI200CIDRun length of consecutive identical digits (CID) %UI1.17CDRPPMCDR PPM toler- ance2 Disabled: E- nhancedReceiv- CDRREFCLK cycles1024 * CDRREFDI- V 512 * CDRREFDIVTLTDCDR lock-to-da- ta time13 er Management Enabled: E- nhancedReceiv- (5200/TCDRREF + (1024 + (6380 * (1900/TCDRREF + (512 + (1020 * er Management (WXCVRFABRX/ CD- RFBDIV)) * CDRRE- FDIV) (WXCVRFABRX/ CD- RFBDIV)) * CDRRE- FDIV) CDRREFCLK cycles(13000/TCDRREF) + (1536 * CDRRE- FDIV) (1000/TCDRREF) + (1024* CDRREFD- IV) TLTFCDR lock-to-ref time13 For Burst mode receiver (BMR) ns10.8THGLTHigh-gain lock time For Burst mode receiver (BMR) ns3264THGSTATEHigh-gain state time12 Setting= 3mV295145VDETHIGHLoss-of-signal detect (peak de- 80Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter tect range set- ting= high)9,10 Setting= 4mV340155 Setting= 5mV365180 Setting= 6mV375195 Setting= 7mV385210 Setting= PCIe3, 7mV17565VDETLOWLoss-of-signal detect (peak de- tect range set- ting=low)9,10 Setting= SATA4, mV19095 Setting= 1mV17075 Setting= 2mV18595 Setting= 3mV190100 Setting= 4mV210140 Setting= 5mV240155 Setting= 6mV245165 Setting= 7mV250170 >8.5 Gbps –12.7 Gbps5, 11 UI0.34TSJTOLSinusoidal jitter tolerance >8.0–8.5 Gbps5UI0.43 >3.2–8.0 Gbps5UI0.45 >1.6 to 3.2 G- bps5 UI0.45 >0.8 to 1.6 G- bps5 UI0.42 250 to 800 M- bps5 UI0.41 3.125 Gbps5UI0.65TTJTOLSETotal jitter toler- ance with stressed eye 6.25 Gbps6UI0.65 10.3125 Gbps6UI0.7 12.7 Gbps6, 11UI0.7 3.125 Gbps5UI0.1TSJTOLSESinusoidal jitter tolerance with stressed eye 6.25 Gbps6UI0.05 10.3125 Gbps6UI0.05 81Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter 12.7 Gbps6, 11UI0.05 dB100.1CTLE DC gain (all stages, max set- tings) dB160.05CTLE AC gain (all stages, max set- tings) dB7.50.05DFE AC gain (per 5 stages, max settings) ms4512TCTLEAuto adaptive calibration time (CTLE) s1.4TCTLE+DFEAuto adaptive calibration time (CTLE+DFE) MHz41.64038.4FERMCTRLCLKEnhancedreceiv- er mangement control clock in- put (CTRL_CLK) 1. Valid at 3.2 Gbps and below. 2. Data vs Rx reference clock frequency. 3. Achieves compliance with PCIe electrical idle detection. 4. Achieves compliance with SATA OOB specification. 5. Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of Rx CTLE enabled, DFE disabled, 80 MHz sinusoidal jitter injected to Rx data. 6. Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of Rx CTLE enabled, DFE enabled, 80 MHz sinusoidal jitter injected to Rx data. 7. For PCIe: Low Threshold Setting= 0, High Threshold Setting= 2. 8. For SATA: Low Threshold Setting= 2, High Threshold Setting= 3. 9. Loss of signal is valid for data rates of 1 Gbps to 5 Gbps for PRBS7 (8B/10B) or PRBS31 (64b/6xb) data formats. It is also valid for detection of SATA out-of-band signals at data rates up to 6 Gbps. If the default settings for the low threshold (0x0) and high threshold (0x2) using the low range option for the peak detector are used, then the Rx VAmplitude pk-pk (outside of data eye) at the receiver input package pins must be a minimum of 300 mV for short reach (6.5 dB insertion loss at 5 GHz) applications, 350 mV for medium reach (17.0 dB insertion loss at 5 GHz) applications, and 450 mV for long reach (25.0 dB insertion loss at 5 GHz) applications—generally the settings are less limiting than what is required for good BER operation of the SerDes. Note that if the option to force CDR Lock2Ref upon Rx Idle is set (default at data rates of 5 Gbps and below), this minimum VAmplitude pk-pk must be enforced for proper CDR operation. 10. Detect values measured at 1.5 Gbps with PRBS7 data pattern. 82Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 12. THGSTATE is based on the condition where the CDR was in lock (to reference or data) for at least 5.2 μs before moving to the high-gain state. At this point, if the receive data is outside the ppm tolerance of the CDR, the CDR will unlock after the time specified by the parameter. 13. The following definitions apply: a. TCDRREF is the transceiver CDR reference clock period in nanoseconds. b. WXCVRFABRX is the parallel interface width of the transceiver receive fabric interface. c. CDRFBDIV is the feedback divider of the transceiver. d. CDRCDRREFDIV is the reference divider of the transceiver CDR. 14. For details on the Enhanced Receiver Management feature, refer to UG0677: PolarFire FPGA Transceiver User Guide.

6.5.6 Transceiver and Receiver Return Loss Characteristics

This section describes transmitter and receiver return loss characteristics compliant with OIF-CEI-03.1. Figure 4 • Differential Return Loss Table 92 • Differential Return Loss UnitValueParameter dB–8A0 MHz100f0 Hz(3/4) * T_Baudf1 HzT_Baudf2 83Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

dB/dec16.6Slope Figure 5 • Common Mode Return Loss Table 93 • Common Mode Return Loss UnitValueParameter dB–6A0 MHz100f0 Hz(3/4) * T_Baudf1

6.6 Transceiver Protocol Characteristics

The following section describes transceiver protocol characteristics.

6.6.1 PCI Express

The following tables describe the PCI express. Table 94 • PCI Express Gen1 UnitMaxMinData RateParameter UI0.252.5 GbpsTotal transmit jitter UI0.42.5 GbpsReceiver jitter tolerance Note: With add-in card, as specified in PCI Express CEM Rev 2.0. 84Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 95 • PCI Express Gen2 UnitMaxMinData RateParameter UI0.355.0 GbpsTotal transmit jitter UI0.45.0 GbpsReceiver jitter tolerance Note: With add-in card as specified in PCI Express CEM Rev 2.0.

6.6.2 Interlaken

The following table describes Interlaken. Table 96 • Interlaken UnitMaxMinData RateParameter UI0.36.375 GbpsTotal transmit jitter UI0.310.3125 Gbps UI0.312.7 Gbps1 UI0.66.375 GbpsReceiver jitter tolerance UI0.6510.3125 Gbps UI0.6512.7 Gbps1 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions. 6.6.3 10GbE (10GBASE-R and 10GBASE-KR) The following table describes 10GbE (10GBASE-R). Table 97 • 10GbE (10GBASE-R) UnitMaxMinData RateParameter UI0.2810.3125 GbpsTotal transmit jitter UI0.710.3125 GbpsReceiver jitter tolerance The following table describes 10GbE (10GBASE-KR). Table 98 • 10GbE (10GBASE-KR) UnitMaxMinData RateParameter UI0.2810.3125 GbpsTotal transmit jitter UI0.11510.3125 GbpsReceiver jitter tolerance (SJ) UI0.1310.3125 GbpsReceiver jitter tolerance (RJ) 85Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxMinData RateParameter UI0.03510.3125 GbpsReceiver jitter tolerance (DCD) The following table describes 10GbE (XAUI). Table 99 • 10GbE (XAUI) UnitMaxMinData RateParameter UI0.353.125 GbpsTotal transmit jitter (near end) UI0.55Total transmit jitter (far end) UI0.653.125 GbpsReceiver jitter tolerance The following table describes 10GbE (RXAUI). Table 100 • 10GbE (RXAUI) UnitMaxMinData RateParameter UI0.356.25 GbpsTotal transmit jitter (near-end) UI0.556.25 GbpsTotal transmit jitter (far- end) UI0.656.25 GbpsReceiver jitter tolerance 6.6.4 1GbE (1000BASE-X) The following table describes 1GbE (1000BASE-X). Table 101 • 1GbE (1000BASE-X) UnitMaxMinData RateParameter UI0.241.25 GbpsTotal transmit jitter UI0.7491.25 GbpsReceiver jitter tolerance

6.6.5 SGMII and QSGMII

The following table describes SGMII. Table 102 • SGMII UnitMaxMinData RateParameter UI0.241.25 GbpsTotal transmit jitter UI0.7491.25 GbpsReceiver jitter tolerance The following table describes QSGMII. 86Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 103 • QSGMII UnitMaxMinData RateParameter UI0.35.0 GbpsTotal transmit jitter UI0.655.0 GbpsReceiver jitter tolerance

6.6.6 CPRI

The following table describes CPRI. Table 104 • CPRI UnitMaxMinData RateParameter UI0.350.6144 GbpsTotal transmit jitter UI0.351.2288 Gbps UI0.352.4576 Gbps UI0.353.0720 Gbps UI0.34.9152 Gbps UI0.36.1440 Gbps UI0.3358.11008 Gbps UI0.3359.8304 Gbps UI0.750.6144 GbpsReceive jitter tolerance UI0.751.2288 Gbps UI0.752.4576 Gbps UI0.753.0720 Gbps UI0.74.9152 Gbps UI0.76.1440 Gbps UI0.78.11008 Gbps UI0.79.8304 Gbps

6.6.7 JESD204B

The following table describes JESD204B. Table 105 • JESD204B UnitMaxMinData RateParameter UI0.353.125 GbpsTotal transmit jitter 87Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxMinData RateParameter UI0.36.25 Gbps UI0.312.5 Gbps1 UI0.563.125 GbpsReceive jitter tolerance UI0.66.25 Gbps UI0.712.5 Gbps1 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions.

6.6.8 Display Port

The following table describes Display Port. Table 106 • Display Port UnitMaxMinConditionData RateParameter UI0.27Test point: TP21.62 GbpsTotal transmit jitter UI0.42Test point: TP22.7 Gbps UI0.62Test point: TP3_EQ5.4 Gbps UI0.747SJ at 20 MHz1.62 GbpsReceive jitter toler- ance UI0.491SJ at 100 MHz2.7 Gbps UI0.636SJ at 10 MHz5.4 Gbps

6.6.9 Serial RapidIO

The following table describes Serial RapidIO. Table 107 • Serial RapidIO UnitMaxMinConditionData RateParameter UI0.351.25 GbpsTotal transmit jitter UI0.352.5 Gbps UI0.353.125 Gbps UI0.35.0 Gbps UI0.36.25 Gbps UI0.2810.3125 Gbps UI0.651.25 GbpsReceive jitter toler- ance 88Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxMinConditionData RateParameter UI0.652.5 Gbps UI0.653.125 Gbps UI0.6Short reach5.0 Gbps UI0.95Long reach UI0.6Short reach6.25 Gbps UI0.95Long reach UI0.62Short reach10.3125 Gbps

6.6.10 SDI

The following table describes SDI. Table 108 • SDI UnitMaxMinConditionData RateParameter UI1.0Timing jitter (10 H- z–27 MHz)

270 MbpsTotal transmit jitter

UI0.2Alignment jitter (1 KHz–27 MHz) UI1.0Timing jitter (10 H- z–148.5 MHz)

1.485 Gbps

UI0.2Alignment jitter (10 0 KHz–148.5 MHz) UI2.0Timing jitter (10 H- z–297 MHz)

2.97 Gbps

UI0.3Alignment jitter (10

0 KHz–297 MHz)

UI0.2Alignment jitter270 MbpsReceive jitter toler- ance UI0.2Alignment jitter1.485 Gbps UI0.3Alignment jitter2.97 Gbps

6.6.11 OTN

The following table describes OTN. Table 109 • OTN UnitMaxMinConditionData RateParameter UI0.33 dB BW: 5 KHz to

20 MHz

2.66 GbpsTotal transmit jitter

89Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxMinConditionData RateParameter UI0.13 dB BW: 1 MHz to UI0.33 dB BW: 20 KHz to

80 MHz

10.70 Gbps

UI0.13 dB BW: 4 MHz to UI0.33 dB BW: 20 KHz to

11.09 Gbps1

UI0.13 dB BW: 4 MHz to UI1.5SJ at 5 KHz2.66 MbpsReceive jitter toler- ance UI0.15SJ at 20 MHz UI1.5SJ at 20 KHz10.70 Gbps UI0.15SJ at 80 MHz UI1.5SJ at 20 KHz11.09 Gbps1 UI0.15SJ at 80 MHz 1. For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05 V mode. See supply tolerance in the section Recommended Operating Conditions.

6.6.12 Fiber Channel

The following table describes Fiber Channel. Table 110 • Fiber Channel UnitMaxMinConditionData RateParameter UI0.231.0625 GbpsTotal transmit jitter UI0.332.125 Gbps UI0.524.25 Gbps UI0.318.5 Gbps UI0.681.0625 GbpsReceive jitter toler- ance UI0.622.125 Gbps UI0.624.24 Gbps UI0.718.5 Gbps 90Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.6.13 HiGig and HiGig+

The following table describes HiGig and HiGig+. Table 111 • HiGig and HiGig+ UnitMaxMinConditionData RateParameter UI0.35Near-end3.75 GbpsTotal transmit jitter UI0.55Far-end3.75 Gbps UI0.653.75 GbpsReceive jitter toler- ance

6.6.14 HiGig II

The following table describes HiGig II. Table 112 • HiGig II UnitMaxMinConditionData RateParameter UI0.35Near-end6.875 GbpsTotal transmit jitter UI0.55Far-end6.875 Gbps UI0.656.875 GbpsReceive jitter toler- ance

6.6.15 Firewire IEEE 1394

The following table describes Firewire. Table 113 • FireWire IEEE1394 UnitMaxMinConditionData RateParameter ps557S400 Near-end393.22 MbpsTotal transmit jitter ps200S800 Near-end786.43 Mbps ps1025S400393.22 MbpsReceive jitter toler- ance ps375S800786.43 Mbps

6.7 Non-Volatile Characteristics

The following section describes non-volatile characteristics.

6.7.1 FPGA Programming Cycle and Retention

The following table describes FPGA programming cycle and retention. 91Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 114 • FPGA Programming Cycles vs Retention Characteristics Retention Years at TJRetention YearsProgramming Cycles, MaxProgramming TJ 85 °C2010000 °C to 85 °C 100 °C205000 °C to 100 °C 100 °C20500–20 °C to 100 °C 100 °C20500–40 °C to 100 °C 100 °C161000–40 °C to 85 °C 100 °C122000–40 °C to 55 °C Note: Power supplied to the device must be valid during programming operations such as programming and verify . Programming recovery mode is available only for in-application programming mode and requires an external SPI flash.

6.7.2 FPGA Programming Time

The following tables describe FPGA programming time. Table 115 • Master SPI Programming Time (IAP) UnitMaxTypDevicesSymbolParameter s2517MPF100T, TL, TS, T- LS TPROGProgramming time s2517MPF200T, TL, TS, T- LS s3226MPF300T, TL, TS, T- LS s3731MPF500T, TL, TS, T- LS Table 116 • Slave SPI Programming Time UnitMaxTypDevicesSymbolParameter s3327MPF100T, TL, TS, T- LS1 TPROGProgramming time s5041MPF200T, TL, TS, T- LS1 s6050MPF300T, TL, TS, T- LS1 s10890MPF500T, TL, TS, T- LS1 1. SmartFusion2 as SPI Master with MSS running at 100 MHz, MSS_SPI_0 port running at 6.67 MHz. Bitstream stored in DDR. DirectC version 4.1. 92Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Programmer: FlashPro5 with TCK 10 MHz. PC Configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. Table 117 • JTAG Programming Time UnitMaxTypDevicesSymbolParameter s4235MPF100T, TL, TS, T- LS1 TPROGProgramming time s6856MPF200T, TL, TS, T- LS1 s11495MPF300T, TL, TS, T- LS1 s147122MPF500T, TL, TS, T- LS1 1. Programmer: FlashPro5 with TCK 10 MHz. PC Configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10.

6.7.3 FPGA Bitstream Sizes

The following table describes FPGA bitstream sizes. Table 118 • Initialization Client Sizes CiphertextPlaintextDevice

1630 KB1580 KBMPF100T, TL, TS, TLS

3006 KB2916 KBMPF200T, TL, TS, TLS

4403 KB4265 KBMPF300T, TL, TS, TLS

7045 KB6835 KBMPF500T, TL, TS, TLS

Note: Worst case initializing all fabric LSRAM, USRAM, and UPROM. Table 119 • Bitstream Sizes FPGA+SNV- M+ Sec SNVM+ SecFPGA+ SecFPGA+SNV- M SNVM (all pages) SecurityFPGADevicesFile TL, TS, TLS SPI TL, TS, TLS DAT TL, TS, TLS SPI TL, TS, TLS DAT TL, TS, TLS SPI 93Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

SNVM+ SecFPGA+ SecFPGA+SNV- M SNVM (all pages) SecurityFPGADevicesFile TL, TS, TLS DAT TL, TS, TLS SPI TL, TS, TLS DAT

6.7.4 Digest Cycles

Digests verify the integrity of the programmed non-volatile data. Digests are a cryptographic hash of various data areas. Any digest that reports back an error raises the digest tamper flag. Table 120 • Maximum Number of Digest Cycles Retention Since Programmed (N = Number Digests During that Time)1 Reten- tion UnitN = 6000N = 4000N = 2000N = 1500N = 1000N = 500N ≤30 Storage and Operating TJ Digest TJ Years°C2 × LF4 × LF8 × LF10 × LF12 × LF17 × LF20 × L- F –40 to 100–40 to 1 Years°C2 × LF4 × LF8 × LF10 × LF12 × LF17 × LF20 × L- F 0 to 100–40 to 1 Years°C4 × LF8 × LF16 × LF20 × LF20 × LF20 × LF20 × L- F –40 to 85–40 to 8 Years°C20 × LF20 × LF20 × LF20 × LF20 × LF20 × LF20 × L- F –40 to 55–40 to 5 1. LF = Lifetime factor as defined by the number of programming cycles the device has seen under the conditions listed in the following table. Table 121 • FPGA Programming Cycles Lifetime Factor LFProgramming CyclesProgramming TJ 1500–40 °C to 100 °C 0.81000–40 °C to 85 °C 0.62000–40 °C to 55 °C Notes:

The maximum number of device digest cycles is 100K.
Digests are operational only over the –40 °C to 100 °C temperature range.
After a program cycle, an additional N digests cycles are allowed with the resultant retention characteristics for the total operating and storage temperature shown.
Retention is specified for total device storage and operating temperature.
All temperatures are junction temperatures (TJ). 94Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Example 1—500 digests cycles are performed between programming cycles. N = 500. The operating conditions are –40 °C to 85 °C TJ. 501 programming cycles have occurred. The retention under these operating conditions is 20 × LF = 20 × .8 = 16 years.
Example 2—one programming cycle has occurred, N = 1500 digest cycles have occurred. Temperature range is –40 °C to 100 °C. The resultant retention is 10 × LF or 10 years over the industrial temperature range.

6.7.5 Digest Time

The following table describes digest time. Table 122 • Digest Times UnitMaxTypDevicesParameter μs2AllSetup time ms910880MPF100T, TL, TS, TLSFabric digest run time ms10721005MPF200T, TL, TS, TLS ms15821503.9MPF300T, TL, TS, TLS ms21502085MPF500T, TL, TS, TLS μs3533.5MPF100T, TL, TS, TLSUFS CC digest run time μs3533.5MPF200T, TL, TS, TLS μs3533.5MPF300T, TL, TS, TLS μs3533.5MPF500T, TL, TS, TLS ms54.5MPF100T, TL, TS, TLSsNVM digest run time1 ms54.5MPF200T, TL, TS, TLS ms54.5MPF300T, TL, TS, TLS ms54.5MPF500T, TL, TS, TLS μs4947MPF100T, TL, TS, TLSUFS UL digest run time μs4947MPF200T, TL, TS, TLS μs4947MPF300T, TL, TS, TLS μs4947MPF500T, TL, TS, TLS μs544526MPF100T, TL, TS, TLSUser key digest run time2 μs544526MPF200T, TL, TS, TLS μs544526MPF300T, TL, TS, TLS μs544526MPF500T, TL, TS, TLS μs3533.2MPF100T, TL, TS, TLSUFS UPERM digest run time 95Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxTypDevicesParameter μs3533.2MPF200T, TL, TS, TLS μs3533.2MPF300T, TL, TS, TLS μs3533.2MPF500T, TL, TS, TLS μs511494MPF100T, TL, TS, TLSFactory digest run time μs511494MPF200T, TL, TS, TLS μs511494MPF300T, TL, TS, TLS μs511494MPF500T, TL, TS, TLS 1. The entire sNVM is used as ROM. 2. Valid for user key 0 through 6. Note: These times do not include the power-up to functional timing overhead when using digest checks on power-up.

6.7.6 Zeroization Time

This section describes zeroization time. A zeroization operation counts as one programming cycle. Table 123 • Zeroization Times for MPF100T, TL, TS, and TLS Devices ConditionsUnitMaxTypParameter Zip flag setms98Time to enter zeroiza- tion Data erasedms253248Time to destroy the fabric data1 One iteration of scrub- bing ms522507Time to destroy data in non-volatile memory (like new)1, 2 One iteration of scrub- bing ms536520Time to destroy data in non-volatile memory (non-recoverable)1, 3 Full scrubbings0.90.8Time to scrub the fabric data1 Full scrubbings1.61.5Time to scrub the pNV- M data (like new)1, 2 Full scrubbings1.81.7Time to scrub the fabric data pNVM data (non- recoverable)1, 3 s1.21.1Time to verify5 s2.92.8Total time to zeroize (like new)1, 2 96Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionsUnitMaxTypParameter s3.23.1Total time to zeroize (non-recoverable)1, 3 1. Total completion time after entering zeroization. 2. Like new mode—zeroizes user design security setting and sNVM content. 3. Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 4. Time to verify after scrubbing completes. Table 124 • Zeroization Times for MPF200T, TL, TS, and TLS Devices ConditionsUnitMaxTypParameter Zip flag setms98Time to enter zeroiza- tion Data erasedms255250Time to destroy the fabric data1 One iteration of scrub- bing ms522507Time to destroy data in non-volatile memory (like new)1, 2 One iteration of scrub- bing ms536520Time to destroy data in non-volatile memory (non-recoverable)1, 3 Full scrubbings1.00.9Time to scrub the fabric data1 Full scrubbings1.61.5Time to scrub the pNV- M data (like new)1, 2 Full scrubbings1.81.7Time to scrub the fabric data PNVM data (non- recoverable)1, 3 s1.51.4Time to verify5 s3.02.9Total time to zeroize (like new)1, 2 s3.23.1Total time to zeroize (non-recoverable)1, 3 1. Total completion time after interning zeroization. 2. Like new mode—zeroizes user design security setting and sNVM content. 3. Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 4. Time to verify after scrubbing completes. 97Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 125 • Zeroization Times for MPF300T, TL, TS, and TLS Devices ConditionsUnitMaxTypParameter Zip flag setms98Time to enter zeroiza- tion One iteration of scrub- bing ms420390Time to destroy the fabric data1 One iteration of scrub- bing ms522507Time to destroy data in non-volatile memory (like new)1, 2 One iteration of scrub- bing ms536520Time to destroy data in non-volatile memory (non- recoverable)1, 3 Full scrubbings1.41.3Time to scrub the fabric data1 Full scrubbings1.61.5Time to scrub the pNV- M data (like new)1, 2 Full scrubbings1.81.7Time to scrub the fabric data pNVM data (non- recoverable)1, 3 s1.91.8Time to verify5 s3.83.7Total time to zeroize (like new)1, 2 s43.9Total time to zeroize (non-recoverable)1, 3 1. Total completion time after interning zeroization. 2. Like new mode—zeroizes user design security setting and sNVM content. 3. Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 4. Time to verify after scrubbing completes. Table 126 • Zeroization Times for MPF500T, TL, TS, and TLS Devices ConditionsUnitMaxTypParameter Zip flag setms98Time to enter zeroiza- tion One iteration of scrub- bing ms422392Time to destroy the fabric data1 One iteration of scrub- bing ms522507Time to destroy data in non-volatile memory (like new)1, 2 98Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionsUnitMaxTypParameter One iteration of scrub- bing ms536520Time to destroy data in non-volatile memory (non-recoverable)1, 3 Full scrubbings1.51.4Time to scrub the fabric data1 Full scrubbings1.61.5Time to scrub the pNV- M data (like new)1, 2 Full scrubbings1.81.7Time to scrub the fabric data pNVM data (non- recoverable)1, 3 s2.01.9Time to verify5 s3.93.8Total time to zeroize (like new)1, 2 s4.14.0Total time to zeroize (non-recoverable)1, 3 1. Total completion time after entering zeroization. 2. Like new mode—zeroizes user design security setting and sNVM content. 3. Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data required for programming. 4. Time to verify after scrubbing completes.

6.7.7 Verify Time

The following tables describe verify time. Table 127 • Standalone Fabric Verify Times UnitMaxDevicesParameter s33MPF100T, TL, TS, TLS1Standalone verification over J- TAG s53MPF200T, TL, TS, TLS1 s90MPF300T, TL, TS, TLS1 s114MPF500T, TL, TS, TLS1 s24MPF100T, TL, TS, TLS2Standalone verification over S- PI s37MPF200T, TL, TS, TLS2 s55MPF300T, TL, TS, TLS2 s89MPF500T, TL, TS, TLS2 1. Programmer: FlashPro5, TCK 10 MHz; PC configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. 99Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

SmartFusion2 with MSS running at 100 MHz, MSS_SPI_0 port running at 6.67 MHz. Bitstream stored in DDR. DirectC version 4.1. Notes:

Standalone verify is limited to 2,000 total device hours over the industrial –40 °C to 100 °C temperature.
Use the digest system service, for verify device time more than 2,000 hours.
Standalone verify checks the programming margin on both the P and N gates of the push-pull cell.
Digest checks only the P side of the push-pull gate. However, the push-pull gates work in tandem. Digest check is recommended if users believe they will exceed the 2,000-hour verify time specification. Table 128 • Verify Time by Programming Hardware UnitsSilicon SculptorBPFlashPro5FlashPro4IAPDevices s33426MPF100T, TL, TS- , TLS s53679MPF200T, TL, TS- , TLS s909514MPF300T, TL, TS- , TLS s11416915MPF500T, TL, TS- , TLS Notes:
FlashPro4 4 MHz TCK.
FlashPro5 10 MHz TCK.
PC configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10. Table 129 • Verify System Services UnitMaxTypDevicesServiceIDSymbolParameter s6.25.9MPF100T, TL, TS- , TLS 44HTIAP_Ver_IndexIn application verify by index s98.2MPF200T, TL, TS- , TLS s1312.4MPF300T, TL, TS- , TLS s1413.4MPF500T, TL, TS- , TLS s6.25.9MPF100T, TL, TS- , TLS 45HTIAP_Ver_AddrIn application verify by SPI ad- dress s98.2MPF200T, TL, TS- , TLS s1312.4MPF300T, TL, TS- , TLS s1413.4MPF500T, TL, TS- , TLS 100Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.7.8 Authentication Time

The following tables describe authentication system service time. Table 130 • Authentication Services UnitMaxTypDevicesServiceIDSymbolParameter s2.42.1MPF100T, TL, TS- , TLS 22HTBIT_AUTHBitstream A- uthentication s3.73.3MPF200T, TL, TS- , TLS s5.44.9MPF300T, TL, TS- , TLS s7.87.6MPF500T, TL, TS- , TLS s2.42.1MPF100T, TL, TS- , TLS 23HTIAP_AUTHIAP Image A- uthentication s3.73.3MPF200T, TL, TS- , TLS s5.44.9MPF300T, TL, TS- , TLS s7.87.6MPF500T, TL, TS- , TLS

6.7.9 Secure NVM Performance

The following table describes secure NVM performance. Table 131 • sNVM Read/Write Characteristics ConditionsUnitMaxTypMinSymbolParameter ms7.97.27.0Plain text pro- gramming ms9.47.47.2Authenticated text program- ming ms9.47.47.2Authenticated and encrypted text program- ming From TFAB_READYms1111310TPUF_OVHDAuthentication R/W 1st access from power-up overhead μs98.58Plain text read 101Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionsUnitMaxTypMinSymbolParameter μs119114.5113Authenticated text read μs167161159Authenticated and decrypted text read Notes:

Page size= 256 bytes (non-authenticated), 236 bytes (authenticated).
Only page reads and writes allowed.
TPUF_OVHD is an additional time that occurs on the first R/W, after cold or warm boot, to sNVM using authenticated or authenticated and encrypted text.

6.7.10 Secure NVM Programming Cycles

The following table describes secure NVM programming cycles. Table 132 • sNVM Programming Cycles vs. Retention Characteristics Retention YearsProgrammingCycles per Block, Max Programming Cycles per Page, Max Programming Temperature 20100,00010,000–40 °C to 100 °C 20100,00010,000–40 °C to 85 °C 20100,00010,000–40 °C to 55 °C Note: Page size = 256 bytes. Block size = 56 KBytes.

6.8 System Services

This section describes system switching and throughput characteristics.

6.8.1 System Services Throughput Characteristics

The following table describes system services throughput characteristics. Table 133 • System Services Throughput Characteristics ConditionsUnitMaxTypService IDSymbolParameter μs676500HTSerialSerial number μs1.20.801HTUserUser code μs32.502HTDesignDesign informa- tion ms27125503HTCertDevice certifi- cate μs21520104HTdigest_readRead digests 102Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionsUnitMaxTypService IDSymbolParameter μs171505HTsec_QueryQuery security locks μs383406HTRd_debugRead debug in- formation 07H–0FHReserved Note 110HTSNVM_Wr_PlainSecure NVM write plain text Note 111HTSNVM_Wr_AuthSecure NVM write authenti- cated plain text Note 112HTSNVM_Wr_CipherSecure NVM write authenti- cated cipher text 13H–17HReserved Note 118HTSNVM_RdSecure NVM read ms18717419HTSIG_RAWDigital signature service raw ms1871741AHTSIG_DERDigital signature service DER 1BH–1FHReserved ms2.01.820HTChallengePUF emulation ms1.51.221HTNonceNonce service Note 422HTBIT_AUTHBitstream au- thentication Note 423HTIAP_AUTHIAP Image au- thentication 26H–3FHReserved Note 242HTIAP_Prg_IndexIn application programmingby index Note 243HTIAP_Prg_AddrIn application programmingby SPI address Note 544HTIAP_Ver_IndexIn application verify by index 103Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionsUnitMaxTypService IDSymbolParameter Note 545HTIAP_Ver_AddrIn application verify by SPI ad- dress Note 246HTAutoUpdateAuto update Note 347HTdigest_chkDigest check 1. See sNVM Read/Write Characteristics. 2. See SPI Master Programming Time. 3. See Digest Times. 4. See Authentication Services Time. 5. See Verify Services Time. 6. Throughputs described are measured from SS_REQ assertion to BUSY de-assertion.

6.9 Fabric Macros

This section describes switching characteristics of UJTAG, UJTAG_SEC, USPI, system controller, and temper detectors and dynamic reconfiguration.

6.9.1 UJTAG Switching Characteristics

The following section describes characteristics of UJTAG switching. Table 134 • UJTAG Performance Characteristics ConditionUnitMaxTypMinSymbolParameter MHz25FTCKTCK frequency Figure 6 • UJTAG Timing Diagram 104Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.9.2 UJTAG_SEC Switching Characteristics

The following table describes characteristics of UJTAG_SEC switching. Table 135 • UJTAG Security Performance Characteristics ConditionUnitMaxTypMinSymbolParameter MHzFTCKTCK frequency

6.9.3 USPI Switching Characteristics

The following section describes characteristics of USPI switching. Table 136 • SPI Macro Interface Timing Characteristics UnitVDDI = 1.2 V Max VDDI = 1.5 V Max VDDI = 1.8 V Max VDDI = 2.5 V Max VDDI = 3.3 V Max SymbolParameter ns1.61.41.210.8TPD_MOSIPropagation delay from ns4.54.2543.753.5TPD_MISOthe fabric to pins1 ns4.54.2543.753.5TPD_SS ns4.54.2543.753.5TPD_SCK ns4.54.2543.753.5TPD_MOSI_O- E ns4.54.2543.753.5TPD_SS_OE ns4.54.2543.753.5TPD_SCK_OE 1. Assumes CL of the relevant I/O standard as described in the input and output delay measurement tables. Figure 7 • USPI Switching Characteristics 105Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.9.4 Tamper Detectors

The following section describes tamper detectors. Table 137 • ADC Conversion Rate UnitMaxTyp1MinDescriptionParameter μs470350Time from enable changing from zero TCONV1 to non-zero value to first conversion completes. Mini- mum value applies when POWEROFF = μs480Time between sub- sequent channel conversions. TCONVN ns0Data channel and output to valid as- TSETUP serted. Data is held until next conver- sion completes, that is >480 μs. μs2.51.5Width of the valid pulse. TVALID μsRate × 32Time from start of first set of conver- TRATE sions to the start of the next set. Can be considered as the conversion rate. Is set by the conver- sion rate parame- ter. 1. Min, typ, and max refer to variation due to functional configuration and the raw TVS value. The actual internal correction time will vary based on the raw TVS value. 2. The pulse width varies depending on the time taken to complete the internal calibration multiplication, this can be up to 375 ns. Note: Once the TVS block is active, the enable signal is sampled 25 ns before the falling edge of valid. The next enabled channel in the sequence 0-1-2-3 is started; that is, if channel 0 has just completed and only channels 0 and 3 are enabled, the next channel will be 3. When all the enabled channels in the sequence 0-1-2-3 are completed, the TVS waits for the conversion rate timer to expire. The enable signal may be changed at any time if it changes to 4’b0000 while valid is asserted (and 25 ns before valid is de-asserted), then no further conversions will be started. Table 138 • Temperature and Voltage Sensor Electrical Characteristics ConditionUnitMaxTypMinParameter °C125–40Temperature sens- ing range 106Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinParameter °C10–10Temperature sens- ing accuracy V2.80.9Voltage sensing range %3.0–3.0Voltage sensing ac- curacy Table 139 • Tamper Macro Timing Characteristics—Flags and Clearing UnitMaxTypSymbolParameter ns3528TJTAG_ACTIVE 1From event detection to flag generation μs2.51.8TMESH_ERR ns50TCLK_GLITCH μs4TCLK_FREQ μs100070TLOW_VDD 1, 3 μs100085THIGH_VDD18 1, 3 μs1000130THIGH_VDD25 1, 3 ns5TSECDEC μs1814TDRI_ERR ns5TWDOG ns5TLOCK_ERR μs54TINST_BUF_ACCESS 1, 2Time from system con- trollerinstructionexecu- tion to flag generation μs43.3TINST_DEBUG 1, 2 μs31.8TINST_CHK_DIGEST 1, 2 μs21.8TINST_EC_SETUP 1, 2 μs53.8TINST_FACT_PRIV 1, 2 μs3.52.5TINST_KEY_VAL 1, 2 μs21.5TINST_MISC 1, 2 μs32.5TINST_PASSCODE_MATCH 1, 2 μs54.2TINST_PASSCODE_SETUP 1, 2 μs4.53.8TINST_PROG 1, 2 107Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

μs4.54TINST_PUB_INFO 1, 2 μs32.5TINST_ZERO_RECO 1, 2 μs180170TINST_PASSCODE_FAIL 1, 2 μs11092TINST_KEY_VAL_FAIL 1, 2 μs54TINST_UNUSED 1, 2 ns2317TCLEAR_FLAGTime from sending the CLEAR to deassertionon FLAG 1. The timing does not impact the user design, but it is useful for security analysis. 2. System service requests from the fabric will interrupt the system controller delaying the generation of the flag. 3. Timing of these depends highly on supply ramp rate. Table 140 • Tamper Macro Response Timing Characteristics UnitMaxTypSymbolParameter ns6345TIO_DISABLETime from triggering the response to all I/Os dis- abled ns5134TCLR_IO_DISABLETime from negation of RESPONSE to all I/Os re- enabled ns20TLOCKDOWNTime from triggering the response to security locked ns20TCLR_LOCKDOWNTime from negation of RESPONSE to earlier se- curity unlock condition μs1411.7Ttr_RESETTime from triggering the response to device en- ters RESET ms8.27.4Ttr_ZEROLISETime from triggering the response to start of ze- roization

6.9.5 System Controller Suspend Switching Characteristics

The following table describes the characteristics of system controller suspend switching. 108Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 141 • System Controller Suspend Entry and Exit Characteristics UnitMaxTypDefinitionSymbolParameter ns4442Suspend entry time from TRST_N asser- tion Tsuspend_Tr 1, 2Time from TRSTb falling edge to SUS- PEND_EN signal as- sertion ns372361Suspend exit time from TRST_N nega- tion Tsuspend_exitTime from TRSTb rising edge to ACTI- VE signal assertion 1. ACTIVE indicates that the system controller is inactive or active regardless of the state of SUSPEND_EN. 2. ACTIVE signal must never be asserted with SUSPEND_EN is asserted.

6.9.6 Dynamic Reconfiguration Interface

The following table provides interface timing information for the DRI, which is an embedded APB slave interface within the FPGA fabric that does not use FPGA resources. Table 142 • Dynamic Reconfiguration Interface Timing Characteristics UnitMaxSymbolParameter MHz200FPD _PCLKPCLK frequency

6.9.7 User Voltage Detector Characteristics

The following table provides the electrical characteristics of the VDD (1.0 V), VDD18, and VDD25 voltage detectors. For proper operation of the voltage detectors, Vdd must be set to 1.0 V. Table 143 • User Voltage Detector Electrical Characteristics ConditionUnitMaxTypMinParameter Temp= –40 ºC to 1 00 ºC; VDD18 = 1.8 V1.071.04VDD_HIGH_DET V ±5%; VDD25= 2.5 V ±5% Temp= –40 ºC to 1 00 ºC; VDD = 1.0 V V1.961.9VDD18_HIGH_DET ±3%; VDD25= 2.5 V ±5% Temp= –40 ºC to 1 00 ºC; VDD = 1.0 V V2.742.66VDD25_HIGH_DET ±3%; VDD18= 1.8 V ±5% Temp= –40 ºC to 1 00 ºC; VDD18 = 1.8 V0.9150.945VDD_LOW_DET ±5%; VDD25= 2.5 V ±5% Temp= –40 ºC to 1 00 ºC; VDD = 1.0 ±3 V1.571.62VDD18_LOW_DET 109Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinParameter %; VDD25= 2.5 V ±5 Temp= –40 ºC to 1 00 ºC; VDD = 1.0 ±3 V2.212.31VDD25_LOW_DET %; VDD18= 1.8 V ±5

6.10 Power-Up to Functional Timing

Microsemi non-volatile FPGA technology offers the fastest boot-time of any mid-range FPGA in the market. The following tables describes both cold-boot (from power-on) and warm-boot (assertion of DEVRST_N pin or assertion of reset from the tamper macro) timing. The power-up diagrams assume all power supplies to the device are stable.

6.10.1 Power-On (Cold) Reset Initialization Sequence

The following cold reset timing diagram shows the initialization sequencing of the device. Figure 8 • Cold Reset Timing Notes:

The previous diagram shows the case where VDDI/VDDAUX of I/O banks are powered either before or sufficiently soon after VDD/VDD18/VDD25 that the I/O bank enable time is measured from the assertion time of VDD/VDD18/VDD25 (that is, the PUFT specification). If VDDI/VDDAUX of I/O banks are powered sufficiently after VDD/VDD18/VDD25, then the I/O bank enable time is measured from the assertion of VDDI/VDDAUX and is not specified by the PUFT specification. In this case, I/O operation is indicated by the assertion of BANK_i_VDDI_STATUS, rather than being measured relative to FABRIC_POR_N negation.
AUTOCALIB_DONE assertion indicates the completion of calibration for any I/O banks specified by the user for auto-calibration. AUTOCALIB_DONE asserts independently of DEVICE_INIT_DONE. It may assert before or after DEVICE_INIT_DONE and is determined by the following: ◦ How long after VDD/VDD18/VDD25 that VDDI/VDDAUX are powered on. Note that if any of the user-specified I/O banks are not powered on within the auto-calibration timeout window, then AUTOCALIB_DONE doesn't assert until after this timeout. ◦ The specified ramp times of VDDI of each I/O bank designated for auto-calibration. ◦ How much auto-initialization is to be performed for the PCIe, SERDES transceivers, and fabric LSRAMs. 110Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

If any of the I/O banks specified for auto-calibration do not have their VDDI/VDDAUX powered on within the auto-calibration timeout window, then it will be approximately auto-calibrated whenever VDDI/VDDAUX is subsequently powered on. To obtain an accurate calibration however, on such IO banks, it is necessary to initiate a re-calibration (using CALIB_START from fabric).
AVM_ACTIVE only asserts if avionics mode is being used. It is asserted when the later of DEVICE_INIT_DONE or AUTOCALIB_DONE assert.

6.10.2 Warm Reset Initialization Sequence

The following warm reset timing diagram shows the initialization sequencing of the device when either DEVRST_N or TAMPER_RESET_DEVICE signals are asserted. Figure 9 • Warm Reset Timing

6.10.3 Power-On Reset Voltages

The following sections describe the power-on reset voltages.

6.10.3.1 Main Supplies

The start of power-up to functional time (TPUFT) is defined as the point at which the latest of the main supplies (VDD, VDD18, VDD25) reach the reference voltage levels specified in the following table. This starts the process of releasing the reset of the device and powering on the FPGA fabric and IOs. Table 144 • POR Ref Voltages NotePower-On Reset Start Point (V)Supply Applies to both 1.0 V and 1.05 V opera- tion. 0.95VDD 1.71VDD18 2.25VDD25

6.10.3.2 I/O-Related Supplies

For the I/Os to become functional (for low speed, sub-400 MHz operation), the (per-bank) I/O supplies (VDDI, VDDAUX) must reach the trip point voltage levels specified in the following table and the main supplies above must also be powered on. 111Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 145 • I/O-Related Supplies I/O Power-Up Start Point (V)Supply 0.85VDDI 1.6VDDAUX There are no sequencing requirements for the power supplies. However, VDDI3 and must be valid at same time as the main supplies. The other I/O supplies (VDDI, VDDAUX) have no effect on power-up of FPGA fabric (that is, the fabric still powers up even if the I/O supplies of some I/O banks remain powered off).

6.10.4 User Design Dependence of Power-Up Times

Some phases of the device initialization are user design dependent, as the device automatically initializes certain resources to user-specified configurations if those resources are used in the design. It is necessary to compute the overall power-up to functional time by referencing the following tables and adding the relevant phases, according to the design configuration. The following equation refers to timing parameters specified in the above timing diagrams. Please note TPCIE , TXCVR, TLSRAM, and TUSRAM can be found in the PolarFire SoC device power-up and resets user guide UG0725. TPUFT = TFAB_READY(cold) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB) TWRFT = TFAB_READY(warm) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB) Note: TPCIE, TXCVR, TLSRAM, TUSRAM, and TCALIB are common to both cold and warm reset scenarios. Auto-initialization of FPGA (if required) occurs in parallel with I/O calibration. The device may be considered fully functional only when the later of these two activities has finished, which may be either one, depending on the configuration, as may be calculated from the following tables. Note that I/O calibration may extend beyond TPUFT (as I/O calibration process is independent of main device power-on and is instead dependent on I/O bank supply relative power-on time and ramp times). The previous timing diagram for power-on initialization shows the earliest that I/Os could be enabled, if the I/O power supplies are powered on before or at the same time as the main supplies.

6.10.5 Cold Reset to Fabric and I/Os (Low Speed) Functional

The following table specifies the minimum, typical, and maximum times from the power supplies reaching the above trip point levels until the FPGA fabric is operational and the FPGA IOs are functional for low-speed (sub-400 MHz) operation. Table 146 • Cold Boot UnitMaxTypMinPower-On (Cold) Reset to Fabric and I/O Oper- ational ms7.844.380.92Time when input pins start working – TIN_ACTIV- E(cold) ms7.844.380.92Time when weak pull- ups are enabled – TPU_ PD_ACTIVE(cold) ms7.874.410.95Time when fabric is op- erational – TFAB_READY- (cold) 112Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

UnitMaxTypMinPower-On (Cold) Reset to Fabric and I/O Oper- ational ms7.894.430.97Time when output pins start driving – TOUT_ACTI- VE(cold)

6.10.6 Warm Reset to Fabric and I/Os (Low Speed) Functional

The following table specifies the minimum, typical, and maximum times from the negation of the warm reset event until the FPGA fabric is operational and the FPGA IOs are functional for low-speed (sub-400 MHz) operation. Table 147 • Warm Boot UnitMaxTypMinWarm Reset to Fabric and I/O Operational ms2.621.630.65Time when input pins start working – TIN_ACTIV- E(warm) ms2.621.630.65Time when weak pull- ups/pull-downs are en- abled – TPU_PD_ACTIVE- (warm) ms2.651.660.68Time when fabric is op- erational – TFAB_READY- (warm) ms2.671.680.70Time when output pins start driving – TOUT_ACTI- VE(warm)

6.10.7 Miscellaneous Initialization Parameters

In the following table, TFAB_READY refers to either TFAB_READY(cold) or TFAB_READY(warm) as specified in the previous tables, depending on whether the initialization is occurring as a result of a cold or warm reset, respectively. Table 148 • Cold and Warm Boot ConditionUnitMaxTypMinSymbolParameter ms000The time from TFAB_READY to ready to pro- gram throughJT- AG/SPI-Slave msTPUF_OVHD 1TPUF_OVHD 1The time from TFAB_READY to au- to-update start msTPUF_OVHD 1TPUF_OVHD 1The time from TFAB_READY to programming recovery start 113Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter ms000TTAMPER_READYThe time from TFAB_READY to the tamper flags be- ing available ms000TCRYPTO_READYThe time from TFAB_READY to the Athena Crypto co-processor being available (for S devices only) 1. Programming depends on the PUF to power up. Refer to TPUF_OVHD at section Secure NVM Performance.

6.10.8 I/O Calibration

The following tables specify the initial I/O calibration time for the fastest and slowest supported VDDI ramp times of 0.2 ms to 50 ms, respectively. This only applies to I/O banks specified by the user to be auto-calibrated. Table 149 • I/O Initial Calibration Time (TCALIB) ConditionMax (ms)Min (ms)Ramp Time Applies to HSIO and GPIO banks 2.630.980.2 ms Applies to HSIO and GPIO banks 62.1941.6250 ms Notes:

The user may specify any VDDI ramp time in the range specified above. The nominal initial calibration time is given by the specified VDDI ramp time plus 2 ms.
In order for IO calibration to start, VDDI and VDDAUX of the I/O bank must be higher than the trip point levels specified in I/O-Related Supplies. Table 150 • I/O Fast Recalibration Time (TRECALIB) ConditionMax (ms)Typ (ms)Min (ms)I/O Type GPIO configured for 3.3 V operation 0.240.140.04GPIO bank HSIO configured for 1.8 V operation 0.300.200.11HSIO bank Note: In order to obtain fast re-calibration, the user must assert the relevant clock request signal from the FPGA fabric to the I/O bank controller.

6.11 Dedicated Pins

The following section describes the dedicated pins. 114Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

6.11.1 JTAG Switching Characteristics

The following table describes characteristics of JTAG switching. Table 151 • JTAG Electrical Characteristics ConditionUnitMaxTypMinDescriptionSymbol ns0.0TDI input setup time TDISU ns2.0TDI input hold time TDIHD ns1.5TMS input setup time TTMSSU ns1.5TMS input hold time TTMSHD MHz25TCK frequencyFTCK %6040TCK duty cycleTTCKDC CLOAD = 40 pfns8.4TDO clock to Q out TTDOCQ CLOAD = 40 pfns23.5TRSTB clock to Q out TRSTBCQ ns50TRSTB min pulse width TRSTBPW ns0.0TRSTB removal time TRSTBREM ns12.0TRSTB recovery time TRSTBREC pf5.3TDI input pin ca- pacitance CINTDI pf5.3TMS input pin capacitance CINTMS pf5.3TCK input pin capacitance CINTCK pf5.3TRSTB input pin capacitance CINTRSTB

6.11.2 SPI Switching Characteristics

The following tables describe characteristics of SPI switching. 115Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 152 • SPI Master Mode (PolarFire SoC Master) ConditionUnitMaxTypMinSymbolParameter DuringProgram- ming MHz Mhz sp1SCK frequency During Initializa- tion nsSCK_period/2sp2SCK minimum pulse width high nsSCK_period/2sp3SCK minimum pulse width low Refer to PolarF- ire SoC IBIS models3 nssp4 sp5 Rise and fall time ns(SCK_period/2) – 3.0 sp6mSDO setup time ns(SCK_period/2) – 2.0 sp7mSDO hold time ns10.0sp8mSDI setup time ns–1.0sp9mSDI hold time Notes: 1. Parameters are referenced to the active edge of SCK, which depends on the configured SPI protocol (for example, Motorola SPI mode uses rising edge as active edge if SPO= 0). 2. SDI is clocked into SPI on active edge and clocked out on inactive edge. Therefore, SDO delay parameters are dependent on SCK frequency (nominally SCK_period/2). 3. For specific rise/fall times, board design considerations, and detailed output buffer resistances, use the corresponding IBIS models located online at Microsemi SoC Products Group. Table 153 • SPI Slave Mode (PolarFire SoC Slave) ConditionUnitMaxTypMinSymbolParameter MHz80sp1SCK frequency nsSCK_period/2sp2SCK minimum pulse width high nsSCK_period/2sp3SCK minimum pulse width low Refer to PolarF- ire SoC IBIS models3 nssp4 sp5 Rise and fall time ns(SCK_period/2) – 8.0 sp6sSDO setup time nsSCK_period/2sp7sSDO hold time 116Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

ConditionUnitMaxTypMinSymbolParameter ns4.0sp8sSDI setup time ns2.0sp9sSDI hold time Notes: 1. Parameters are referenced to the active edge of SCK, which depends on the configured SPI protocol (for example, Motorola SPI mode uses rising edge as active edge if SPO= 0). 2. SDI is clocked into SPI on active edge and clocked out on inactive edge. Therefore, SDO delay parameters are dependent on SCK frequency (nominally SCK_period/2). 3. For specific rise/fall times, board design considerations, and detailed output buffer resistances, use the corresponding IBIS models located online at Microsemi SoC Products Group. Figure 10 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)

6.11.3 SmartDebug Probe Switching Characteristics

The following table describes characteristics of SmartDebug probe switching. Table 154 • SmartDebug Probe Performance Characteristics UnitVDD = 1.05 V – 1VDD = 1.05 V ST- D VDD = 1.0 V – 1VDD = 1.0 V STDSymbolParameter MHz100100100100FMAXMaximum fre- quency of probe signal nsTMin_delayMinimum delay of probe signal nsTMax_delayMaximum delay of probe signal

6.11.4 DEVRST_N Switching Characteristics

The following table describes characteristics of DEVRST_N switching. 117Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 155 • DEVRST_N Electrical Characteristics ConditionUnitMaxTypMinSymbolParameter It must be a nor- mal clean digital μs10DRRAMPDEVRST_N ramp time signal, with typi- cal rise and fall times The minimum timefor DEVRST- μs1DRASSERTDEVRST_N as- sert time _N assertion to be recognized The minimum time DEVRST_N ms2.75DRDEASSERTDEVRST_N de- assert time needs to be de- asserted before assertion

6.12 User Crypto

The following section describes user crypto.

6.12.1 TeraFire 5200B Switching Characteristics

The following table describes TeraFire 5200B switching characteristics. Table 156 • TeraFire F5200B Switching Characteristics ConditionUnitVDD = 1.05 V – 1 VDD = 1.05 V STD VDD = 1.0 V – VDD = 1.0 V STD SymbolParameter –40 °C to 100 MHz189189189189FMAX_DLLFMAX with DLL –40 °C to 100 MHz125125125125FMIN_DLLFMIN with DLL –40 °C to 100 MHz70707070FMAX_DLL_BYPA- SS FMAX with DLL in bypass mode –40 °C to 100 MHz0000FMIN_DLL_BYPAS- S FMIN with DLL in bypass mode

6.12.2 TeraFire 5200B Throughput Characteristics

The following tables for each algorithm describe the TeraFire 5200B throughput characteristics. Note: Throughput cycle count collected with Athena TeraFire Core and RISCV running at 70 MHz. 118Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 157 • AES CAL Delay in CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 1011511128AES-ECB-128 encrypt1 9274810964K 1328557128AES-ECB-128 decrypt1 12824838564K 1333527128AES-ECB-256 encrypt1 13035630164K 1356589128AES-ECB-256 decrypt1 14105667364K 1316588128AES-CBC-256 encrypt1 12865869164K 1676617128AES-CBC-256 decrypt1 17305685364K 17011921128AES-GCM-128 encrypt1, 128- bit tag, (full message encrypt- ed/authenticated) 16405802264K 17181969128AES-GCM-256 encrypt1, 128- bit tag, (full message encrypt- ed/authenticated) 18035805464K 1. With DPA counter measures. Table 158 • GMAC CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 17521859128AES-GCM-2561, 128-bit tag, (message is only authenticat- ed) 18544765964K 1. With DPA counter measures. Table 159 • HMAC CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 16167461512HMAC-SHA-2561, 256-bit key 13508631964K 119Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 1438130171024HMAC-SHA-3841, 384-bit key 143810405564K 1. With DPA counter measures. Table 160 • CMAC CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 8434446128AES-CMAC-2561 (message is only authenticated) 1102094549464K 1. With DPA counter measures. Table 161 • KEY TREE CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 2173102457128-bit nonce + 8-bit optype 2359103218256-bit nonce + 8-bit optype Table 162 • SHA CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 8162370512SHA-11 7097552864K 6562500512SHA-2561 6568270464K 71241221024SHA-3841 6569817464K 65241221024SHA-5121 6539817464K 1. With DPA counter measures. 120Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 163 • ECC CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 5072125256471024ECDSA SigGen, P-384/SHA-38 5072125403878K 507155028961024ECDSA SigGen, P-384/SHA-384 507155137188K 468362438211024ECDSA SigVer, P-384/SHA-3841 442263211108K 442262438211024ECDSA SigVer, P-384/SHA-384 442263211108K 103185039125Key Agreement (KAS), P-384 44345177474Point Multiply, P-2561 508612055519Point Multiply, P-3841 647026889271Point Multiply, P-5211 53033018067Point Addition, P-384 790912052230KeyGen (PKG), P-384 33545091Point Verification, P-384 1. With DPA counter measures. Table 164 • IFC (RSA) CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 82874369722048Encrypt, RSA-2048, e=65537 120639621623072Encrypt, RSA-3072, e=65537 15261268476162048Decrypt, RSA-20481, CRT 22488751686893072Decrypt, RSA-30721, CRT 23585887896294096Decrypt, RSA-4096, CRT 18838382027173072Decrypt, RSA-3072, CRT 19562751569731024SigGen, RSA-3072/SHA-3841 , CRT, PKCS #1 V 1 1.5 18880752220268K 121Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 136221480923031024SigGen, RSA-3072/SHA-384, P- KCS #1, V 1.5 136221481023198K 117699709591024SigVer, RSA-3072/SHA-384, e = 65537, PKCS #1 V 1.5 117699817558K 84904435931024SigVer, RSA-2048/SHA-256, e = 65537, PKCS #1 V 1.5 84434527518K 136241471438791024SigGen, RSA-3072/SHA-384,A- NSI X9.31 134171471531098K 112689727881024SigVer, RSA-3072/SHA-384, e = 65537, ANSI X9.31 112159836438K 1. With DPA counter measures. Table 165 • FFC (DH) CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 13271279324341024SigGen, DSA-3072/SHA-3841 13166279466368K 13028120863241024SigGen, DSA-3072/SHA-384 12862120971388K 14689247117961024SigVer, DSA-3072/SHA-384 14689244189308K 1071796732221024SigVer, DSA-2048/SHA-256 1071798030288K 95194920705Key Agreement (KAS), DH-307 2 (p=3072,security=256) 949578871914Key Agreement (KAS), DH-307 2 (p=3072,security=256)1 1. With DPA counter measures. 122Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

Table 166 • NRBG CAL Delay In CPU Clock-CyclesAthena TeraFire Crypto Core Clock-Cycles Message Size (Bits)Modes 307618221Instantiate: strength, s=256, 3 84-bit nonce, 384-bit personal- ization string 105613585Reseed: no additional input, s=256 99515922Reseed: 384-bit additional in- put, s=256 167215262128Generate: (no additional in- put), prediction resistance en- abled, s=256 7837271698K 7812138128Generate: (no additional in- put), prediction resistance dis- abled, s=256 7837140458K 162021299128Generate: (384-bit additional input), prediction resistance enabled, s=256 8563332068K 150711657128Generate: (384-bit additional input), prediction resistance disabled, s=256 8563235648K 502761Un-instantiate 123Microsemi Proprietary and Confidential. DS0147 Revision 1.0 AC Switching Characteristics

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Product Information

DS0147 specifications and overview.

Summary

PolarFire SoC Advanced Datasheet December 2019

Description

PolarFire SoC Advanced Datasheet December 2019

Source title DS0147 Datasheet(PDF) - Microchip Technology

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Document overview

Technical content

Datasheet sections

Contents

1 Revision History

Revision History

2 Overview

3 Device Offering

4 Silicon and Libero Tool Status

5 DC Characteristics

5.1 Absolute Maximum Rating

5.2 Recommended Operating Conditions

25 Gbps or less

5.2.1 DC Characteristics over Recommended Operating Conditions

100 KHzps10% bit period200 ps2,3TRISE

50 MHzps20% bit period

800 MHzns4

5.2.2 Maximum Allowed Overshoot and Undershoot

5.2.2.1 Power Supply Ramp Times

5.2.2.2 Hot Socketing

5.3 Input and Output

5.3.1 DC Input and Output Levels

5.3.2 Differential DC Input and Output Levels

5.3.3 Complementary Differential DC Input and Output Levels

5.3.4 HSIO On-Die Termination

5.3.5 GPIO On-Die Termination

65 V 6

1.4 V < VICM

6 AC Switching Characteristics

6.1 Microprocessor Subsystem

6.1.1 CPU Performance

6.1.2 Clocks

6.1.3 MSS DDR

6.1.4 Gigabit Ethernet MAC

6.1.5 SD_SDIO

6.1.7 USB

6.1.8 CAN

6.1.9 MMUART

6.1.10 QSPI

6.1.11 SPI

6.1.12 I2C

6.1.13 Watchdog Timer

6.1.14 Timers

6.1.15 Fabric Interface

6.2 I/O Standards Specifications

6.2.1 Input Delay Measurement Methodology Maximum PHY Rate for Memory Interface IP

1.2 V Class I

6.2.2 Output Delay Measurement Methodology

5 V Class I

5 V Class II

8 V Class I

8 V Class II

35 V Class I

35 V Class II

2 V Class I

2 V Class II

6.2.3 Input Buffer Speed

6.2.4 Output Buffer Speed

6.2.5 Maximum PHY Rate for FPGA Memory Interface IP

6.2.6 User I/O Switching Characteristics

6.2.6.1 I/O Digital

6.3 Clocking Specifications

6.3.1 Clocking

6.3.2 PLL

1.5 MHz ≤ Fout

5 PFD cycles)

6.3.3 DLL

6.3.4 RC Oscillators

6.4 Fabric Specifications

6.4.1 Math Blocks

6.4.2 SRAM Blocks

6.5 Transceiver Switching Characteristics

6.5.1 Transceiver Performance

6.5.2 Transceiver Reference Clock Performance

6.5.3 Transceiver Reference Clock I/O Standards

6.5.4 Transmitter Performance

6.35 GHz)