DS0128

Microsemi Corporation

IGLOO2 FPGA and SmartFusion2 SoC FPGA Revision 12.0

Manufacturer: Microsemi Corporation

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PDF pages: 140

Technical content

Datasheet sections

1 Revision History
2 IGLOO2 FPGA and SmartFusion2 So C FPGA
2.1 Device Status
2.2 References
2.3 Electrical Specifications
2.3.1 Operating Conditions
2.3.2 Power Consumption
2.3.3 Average Fabric Temperature and Voltage Derating Factors
2.3.4 Timing Model
2.3.5 User I/O Characteristics
2.3.6 Logic Element Specifications
2.3.7 Global Resource Characteristics
2.3.8 FPGA Fabric SRAM
2.3.9 Programming Times
2.3.10 Math Block Timing Charac teristics
2.3.11 Embedded NVM (eNVM) Chara cteristics
2.3.12 SRAM PUF
2.3.13 Non-Deterministic Random B it Generator (NRBG) Characteristics
2.3.14 Cryptographic Block Characteristics
2.3.15 Crystal Oscillator
2.3.16 On-Chip Oscillator
2.3.17 Clock Conditioning Circ uits (CCC)
2.3.18 JTAG
2.3.19 System Controller SPI Characteristics
2.3.20 Power-up to Functional Times
2.3.21 DEVRST_N Characteristi cs
2.3.22 DEVRST_N to Functional Times
2.3.23 Flash*Freeze Timing Characteristics
2.3.24 DDR Memory Interface Chara cteristics
2.3.25 SFP Transceiver Characteristics
2.3.26 SerDes Electrical and Timi ng AC and DC Characteristics
2.3.27 SmartFusion2 Specifications
2.3.28 CAN Controller Characte ristics
2.3.29 USB Characteristics
2.3.30 MMUART Characteristics
2.3.31 IGLOO2 Specifications

IGLOO2 FPGA and SmartFusion2 SoC FPGA

12.0 8/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com ©2018 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com.

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 v Tables Table 14 SmartFusion2 and IGLOO 2 Quiescent Supply Current (VDD = 1.26 V) – Worst-Case Process . . 14 Table 18 Maximum Data Rate Summar y Table for Single-Ended I/O in Worst-Case Industrial Conditions . 20 Table 19 Maximum Data Rate Summar y Table for Voltage-Referenced I/O in Worst-Case Table 20 Maximum Data Rate Summar y Table for Differential I/O in Worst-Case Industrial Conditions . . . 21 Table 21 Maximum Frequency Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions . 21 Table 22 Maximum Frequency Summary Table for Voltage-Referenced I/O in Worst-Case Industrial Table 23 Maximum Frequency Summary Table for Differential I/O in Worst-Case Industrial Conditions . . . 22 Table 29 LVTTL/LVCMOS 3.3 V DC Recommended DC Operating Conditions (Applicable to MSIO I/O Bank Table 34 LVTTL/LVCMOS 3.3 V AC Te st Parameter Specifications (Applicable to MSIO I/O Bank Only) . . 26 Table 37 LVTTL/LVCMOS 3.3 V Trans mitter Characteristics for MSIO I/O Bank (Output and

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 vi Table 57 LVCMOS 1.8 V Transmitt er Characteristics for DDRIO I/O Bank with Fixed Code (Output and Tristate Table 67 LVCMOS 1.5 V Receiver Ch aracteristics for DDRIO I/O Bank with Fixed Codes (Input Buffers) . 35 Table 70 LVCMOS 1.5 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) . . 35 Table 71 LVCMOS 1.5 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) . . . 36 Table 72 LVCMOS 1.5 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) . . 37 Table 80 LVCMOS 1.2 V Receiver Ch aracteristics for DDRIO I/O Bank with Fixed Code (Input Buffers) . . 38 Table 83 LVCMOS 1.2 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) . . 39 Table 84 LVCMOS 1.2 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) . . . 39 Table 85 LVCMOS 1.2 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) . . 40 Table 92 PCI/PCIX AC switching Characteristics for Transmitter f or MSIO I/O Bank (Output and Tristate

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 vii Table 114 SSTL2 Class I Transmitter Characteristics for DDRIO I/ O Bank (Output and Tristate Buffers) . . . 46 Table 115 DDR1/SSTL2 Class I Transmi tter Characteristics for MSIO I/O Bank (Output and Table 116 DDR1/SSTL2 Class I Transmi tter Characteristics for MSIOD I/O Bank (Output and Table 117 DDR1/SSTL2 Class II Trans mitter Characteristics for DDRIO I/O Bank (Output and Table 118 DDR1/SSTL2 Class II Trans mitter Characteristics for MSIO I/O Bank (Output and Table 133 SSTL15 AC SSTL15 Minim um and Maximum AC Switching Speed (for DDRIO I/O Bank Only) . 50 Table 158 LPDDR-LVCMOS 1.8V AC Switching Characteristics for Receiver (for DDRIO I/O Bank with Fixed Table 159 LPDDR-LVCMOS 1.8 V AC S witching Characteristics for Transmitter for DDRIO I/O Bank (Output

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 viii Table 182 B-LVDS AC Switching Characteristics for Transmitter (f or MSIO I/O Bank - Output and Tristate Table 192 M-LVDS AC Switching C haracteristics for Transmitter (for MSIO I/O Bank - Output and Tristate Table 201 Mini-LVDS AC Switching Characteristics for Transmitter for MSIO I/O Bank (Output and Tristate Table 202 Mini-LVDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and Tristate Table 212 RSDS AC Switching Char acteristics for Transmitter (for MSIO I/O Bank - Output and Table 213 RSDS AC Switching Char acteristics for Transmitter (for MSIOD I/O Bank - Output and

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 ix Table 255 Programming T imes with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (Fabric and eNVM) . 98 Table 267 Programming T imes with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric and eNVM) 102

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 x Table 301 HCSL Minimu m and Maximum AC Switching Speeds (Applicable to SerDes REFCLK Only) . . . 122

Revision History

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 1

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the current publication. 1.1 Revision 12.0 The following is a summary of the changes in revision 11.0 of this document.

A note about SERDES_[ 01]_VDD supply was added to recommended operating conditions table. See Table 4, page 7.
A note about V ID was added to LVDS DC differential voltage specification. See Table 163, page 56.
Updated Table 286, page 113. Table 288, page 114, Table 289, page 115, Table 290, page 116, Table 291, page 116, and Table 292, page 118.
Updated Table 297, page 121 with RX-CID details. 1.2 Revision 11.0 The following is a summary of the changes in revision 11.0 of this document.
Updated Table 24, page 23 with minimum and maximum values for input current low and high (SAR 73114 and 80314).
Added Non-Deterministic Random Bit Generator (NRBG) Characteristics, page 106 (SAR 73114 and 79517).
Added 060 device in Table 282, page 110 (SAR 79860).
Added DEVRST_N to Functional Times, page 116 (SAR 73114).
Added Cryptographic Block Characteristics, page 106 (SAR 73114 and 79516).
Update Table 296, page 120 with VTX-AMP details (SAR 81756).
Update note in Table 297, page 121 (SAR 74570 and 80677).
Update Table 298, page 121 with generic EPCS details (SAR 75307).
Added Table 308, page 128 (SAR 50424). 1.3 Revision 10.0 The following is a summary of the changes in revision 10.0 of this document.
The Surge Current on VDD during DEVRST_B Assertion and Surge Current on VDD during Digest Check using System Services tables were deleted and added reference to AC393: Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Application Note. (SAR 76865 and 76623).
Added 060 device in Table 4, page 7 (SAR 76383).
Updated Table 24, page 23 for ramp time input (SAR 72103).
Added 060 device details in Table 284, page 111 (SAR 74927).
Updated Table 290, page 116 for name change (SAR 74925).
Updated Table 283, page 111 for 060 FG676 Package details (SAR 78849).
Updated Table 305, page 125 for SmartFusion2 and Table 310, page 128 for IGLOO2 for SPI timing and Fmax (SAR 56645, 75331).
Updated Table 293, page 119 for Flash*Freeze entry and exit times (SAR 75329, 75330).
Updated Table 297, page 121 for RX-CID information (SAR 78271).
Added Table 8, page 9 and Figure 1, page 10 (SAR 78932).
Updated Table 223, page 76 for timing characteristics and Table 224, page 77(SAR 75998).
Added SRAM PUF, page 105 (SAR 64406).
Added a footnote o n digest cycle in Table 5, page 8 (SAR 79812). 1.4 Revision 9.0 The following is a summary of the changes in revision 9.0 of this document.
Added a note in Table 5, page 8 (SAR 71506).
Added a note in Table 6, page 9 (SAR 74616).
Added a note in Figure 3, page 18 (SAR 71506).

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 2

Updated Quiescent Supply Current for 060 in Table 11, page 13 and Table 12, page 14 (SAR 74483).
Updated programming currents for 060 in Table 13, page 14, Table 14, page 14, and Table 15, page 15.
Added DEVRST_B assertion tables (SAR 74708).
Updated I/O speeds for LVDS 3.3 V in Table 18, page 20 and Table 21, page 21 (SAR 69829).
Updated Table 24, page 23 (SAR 69418).
Updated Table 25, page 23, Table 26, page 24, Table 27, page 24 (SAR 74570).
Updated all AC/DC table to link to the Input Capacitance, Leakage Current, and Ramp Time, page 23 for reference (SAR 69418).
Added Table 244, page 94 and Table 256, page 99 (SAR 73971).
Updated the SerDes Electrical and Timing AC and DC Characteristics, page 120 (SAR 71171).
Added the DEVRST_N Characteristics, page 116 (SAR 64100, 72103).
Added Table 298, page 121 (SAR 71897).
Updated Table 25, page 23, Table 26, page 24, and Table 27, page 24 (SAR 74570).
Added 060 devices in Table 277, page 107, Table 278, page 108, and Table 279, page 108 (SAR 57898).
Updated duty cycle para meter of crystal in Table 280, page 109 and Table 281, page 109 (SAR 57898).
Added 32 KHz mode PLL acquisition time in Table 282, page 110 (SAR 68281).
Updated Table 293, page 119 for 060 devices (SAR 57828).
Updated Table 297, page 121 for CID value (SAR 70878). 1.5 Revision 8.0 The following is a summary of the changes in revision 8.0 of this document.
Updated Table 11, page 13 (SAR 69218).
Updated Table 12, page 14 (SAR 69218).
Updated Table 283, page 111 (SAR 69000). 1.6 Revision 7.0 The following is a summary of the changes in revision 7.0 of this document.
Updated Table 1, page 5(SAR 68620). 1.7 Revision 6.0 The following is a summary of the changes in revision 6.0 of this document.
Updated Table 5, page 8 (SAR 65949).
Updated Table 9, page 11 (SAR 62995).
Updated Table 123, page 47 and Table 133, page 50 (SAR 67210).
Added Embedded NVM (eNVM) Characteristics, page 104 (SAR 52509).
Updated Table 277, page 107 (SAR 64855).
Updated Table 282, page 110 (SAR 65958 and SAR 56666).
Added DDR Memory Interface Characteristics, page 119 (SAR 66223).
Added SFP Transceiver Characteristics, page 120 (SAR 63105).
Updated Table 302, page 122 and Table 309, page 128 (SAR 66314). 1.8 Revision 5.0 The following is a summary of the changes in revision 5.0 of this document.
Updated Table 1, page 5.
Updated Table 4, page 7 for TJ symbol information.
Updated Table 5, page 8 (SAR 63109).
Updated Table 9, page 11.
Updated Table 282, page 110 (SAR 62012).
Added Table 290, page 116 (SAR 64100).
Added Table 306, page 127, Table 307, page 127 (SAR 50424).

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 3 1.9 Revision 4.0 The following is a summary of the changes in revision 4.0 of this document.

Updated Table 1, page 5. Changed the Status of 090 devices to "Production" (SAR 62750).
Updated Figure 10, page 70. Removed inverter bubble from DDR_IN latch (SAR 61418).
Updated SerDes Electrical and Timing AC and DC Characteristics, page 120 (SAR 62836). 1.10 Revision 3.0 In revision 3.0 of this document, the Theta B/C columns and FCS325 package was updated. For more information, see Table 9, page 11 (SAR 62002). 1.11 Revision 2.0 The following is a summary of the changes in revision 2.0 of this document.
Table 1, page 5 was updated (SAR 59056).
Table 7, page 9 temperature and data retention information was updated SAR (61363).
Storage Operating Ta ble was updated and split into three tables – Table 5, page 8, Table 7, page 9 (SAR 58725).
Updated Theta B/C column s and FCS325 package in Table 9, page 11 (SAR 62002).
Added 090-FCS325 therm al resistance to Table 9, page 11 (SAR 59384).
TQ144 package was added to Table 9, page 11 (SAR 57708).
Added PLL jitter data for the VF400 package (SAR 53162).
Added Additional Worst Case IDD to Table 11, page 13 and Table 12, page 14 (SAR 59077).
Table 13, page 14, Table 14, page 14, and Table 15, page 15 were added to verify Inrush currents (SAR 56348).
Table 18, page 20 and Table 21, page 21 – I/O speeds were replaced.
Max speed was changed in Table 41, page 27 (SAR 57221) and in Table 52, page 30 (SAR 57113).
Minimum and Maximum DC/AC Input and Output Levels Specification, page 30 and Table 49, page 30–Table 57, page 32 were added.
Added Cload to Table 89, page 40 (SAR 56238).
Removed "Rs" information in DDR Timing Measurement Table 123, page 47, Table 133, page 50, and Table 144, page 52.
Updated drive programming for M/B-LVDS outputs (SAR 58154).
Added an inverter bubbl e to DDR_IN latch in Figure 10, page 70 (SAR 61418).
QF waveform in Figure 11, page 71 was updated (SAR 59816).
uSRAM Write Clock minimum values were updated in Table 237, page 86–Table 243, page 93 (SAR 55236).
Fixed typo in the 32 kHz Crystal (XTAL) oscillator accuracy data section (SAR 59669).
T h e "On-Chip Oscillator" section was split, and the Embedded NVM (eNVM) Characteristics, page 104 was added. Table 277, page 107–Table 281, page 109 were revised.(SARs 57898 and 59669).
PLL VCP Frequency and co nditions were added to Table 282, page 110 (SAR 57416).
Fixed typo for PLL jitter dat a in the 100-400 MHz range (SAR 60727).
Updated FCCC i nformation in Table 282, page 110 and Table 283, page 111 (SAR 60799).
Device 025 specific ations were added to Table 283, page 111 (SAR 51625).
J T A G Table 284, page 111 was replaced (SAR 51188).
Flash*Freeze Table 293, page 119 was replaced (SAR 57828).
Added support for HCSL I/O Stan dard for SERDES reference clocks in Table 300, page 122 and Table 301, page 122 (SAR 50748).
Tir and Tif parameters were added to Table 303, page 123 (SAR 52203).
Speed grade consistency was fixe d in tables throughout the datasheet (SAR 50722).
Added jitter attenuation information (SAR 59405).

Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 4 1.12 Revision 1.0 The following is a summary of the changes in revision 1.0 of this document.

The IGLOO2 v2 and the SmartFusi on2 v5 datasheets are combined into this single product family datasheet.

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 5

2 IGLOO2 FPGA and SmartFusion2 SoC FPGA

Microsemi’s mainstream SmartFusion®2 SoC and IGLOO®2 FPGA families integrate an industry standard 4-input lookup table-based (LUT) FPGA fabric with integrated math blocks, multiple embedded memory blocks, and high-performance SerDes communication interfaces on a single chip. Both families benefit from low-power flash technology and are the most secure and reliable FPGAs in the industry. These next generation devices offer up to 150K Logic Elements, up to 5 MBs of embedded RAM, up to

16 SerDes lanes, and up to four PCI Express Gen 2 endpoints, as well as integrated hard DDR3 memory

controllers with error correction. SmartFusion2 devices integrate an entire low-power, real-time microcontroller subsystem (MSS) with a rich set of industry-standard peripherals including Ethernet, USB, and CAN, while IGLOO2 devices integrate a high-performance memory subsystem with on-chip flash, 32 Kbyte embedded SRAM, and multiple DMA controllers.

2.1 Device Status

The following table shows the design security densities and development status of the IGLOO2 FPGA and SmartFusion2 SoC FPGA devices. The following table shows the data security densities and development status of the IGLOO2 FPGA and SmartFusion2 SoC FPGA devices. Table 1 • IGLOO2 and SmartFusion2 Design Security Densities Design Security Device Densities Status

005 Production

010, 010T Production 025, 025T Production 050, 050T Production 060, 060T Production 090, 090T Production 150, 150T Production Table 2 • IGLOO2 and SmartFusion2 Data Security Densities Data Security Device Densities Status 005S Production 010TS Production 025TS Production 050TS Production 060TS Production 090TS Production 150TS Production

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 6

2.2 References

The following documents are recommended references:

PB0121: IGLOO2 Product Brief
DS0124: IGLOO2 Pin Descriptions
PB0115: SmartFusion2 SoC FPGA Product Brief
DS0115: SmartFusion2 Pin Descriptions All product documentation for IGLOO2 and SmartFusion2 is available at: http://www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga http://www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#overview

2.3 Electrical Specifications

2.3.1 Operating Conditions

The following table lists the stress limits. Stress applied above the specified limit may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions specified in the following table are not implied. Table 3 • Absolute Maximum Ratings Parameter Symbol Min Max Unit DC core supply voltage. Must always power this pin. V DD –0.3 1.32 V Power supply for charge pumps (for normal operation and programming). Must always power this pin. VPP –0.3 3.63 V Analog power pad for MDDR PLL MSS_MDDR_PLL_VDDA –0.3 3.63 V Analog power pad for MDDR PLL HPMS_MDDR_PLL_VDDA –0.3 3.63 V Analog power pad for FDDR PLL FDDR_PLL_VDDA –0.3 3.63 V Analog power pad for MDDR PLL PL L0_PLL1_MSS_MDDR_VDDA –0.3 3.63 V Analog power pad for MDDR PLL PL L0_PLL1_HPMS_MDDR_VDDA –0.3 3.63 V Analog power pad for PLL0–5 CCC_XX[01]_PLL_VDDA –0.3 3.63 V High supply voltage for PLL SerDes[01] SERDES_[01]_PLL_VDDA –0.3 3 .63 V Analog power for SerDes[01] PLL lane0 to lane3. This is a 2.5 V SerDes internal PLL supply. SERDES_[01]_L[0123]_VDDAPLL –0.3 2.75 V TX/RX analog I/O voltage. Low voltage power for the lanes of SerDesIF0. This is a 1.2 V SerDes PMA supply. SERDES_[01]_L[0123]_VDDAIO –0.3 1.32 V PCIe/PCS power supply SERDES_[01]_VDD –0.3 1.32 V DC FPGA I/O buffer supply voltage for MSIO I/O bank V DDIx –0.3 3.63 V DC FPGA I/O buffer supply voltage for MSIOD/DDRIO I/O banks VDDIx –0.3 2.75 V I/O Input voltage for MSIO I/O bank V I –0.3 3.63 V I/O Input voltage for MSIOD/DDRIO I/O bank V I –0.3 2.75 V Analog sense circuit supply of embedded nonvolatile memory (eNVM). Must be shorted to VPP. VPPNVM – 0 . 3 3 . 6 3 V Storage temperature1 TSTG –65 150 °C Junction temperature T J –55 135 °C

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 7 1. For flash programming and retention maximum limits, see Table 5, page 8. For recommended operating conditions, see Table 4, page 7. Table 4 • Recommended Operating Conditions1 Parameter Symbol Min Typ Max Unit Conditions Operating junction temperature T J 0 25 85 °C Commercial –40 25 100 °C Industrial Programming junction temperatures2 TJ 0 25 85 °C Commercial –40 25 100 °C Industrial DC core supply voltage. Must always power this pin. V DD 1.14 1.2 1.26 V Power supply for charge pumps (for normal operation and programming) for the 005, 010, 025, 050, 060 devices V PP 2.375 2.5 2.625 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range Power supply for charge pumps (for normal operation and programming) for the 090 and 150 devices VPP 3.15 3.3 3.45 V 3.3 V range Analog power pad for MDDR PLL M SS_MDDR_PLL_VDDA 2.375 2.5 2.625 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range Analog power pad for MDDR PLL HP MS_MDDR_PLL_VDDA 2.375 2.5 2.625 V 2. 5 V range 3.15 3.3 3.45 V 3.3 V range Analog power pad for FDDR PLL FDDR_ PLL_VDDA 2.375 2.5 2.625 V 2.5 V r ange 3.15 3.3 3.45 V 3.3 V range Analog power pad for MDDR PLL PLL0_PLL1_MSS_MDDR_V DDA 2.375 2.5 2.625 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range Analog power pad for MDDR PLL PLL0_PLL1_HPMS_MDDR_ VDDA 2.375 2.5 2.625 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range Analog power pad for PLL0 to PLL5 CCC_XX[01]_PLL_VDDA 2.375 2.5 2.6 25 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range High supply voltage for PLL SerDes[01] SERDES_[01]_PLL_VDDA 2.375 2.5 2.625 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range Analog power for SerDes[01] PLL Lane 0 to Lane 3. This is a 2.5 V SerDes internal PLL supply. SERDES_[01]_L[0123]_VD DAPLL 2.375 2.5 2.625 V TX/RX analog I/O voltage. Low voltage power for the lanes of SerDesIF0. This is a 1.2 V SerDes PMA supply. SERDES_[01]_L[0123]_VD DAIO 1.14 1.2 1.26 V PCIe/PCS power supply SERDES_[01]_VDD 1.14 1.2 1.26 V 1.2 V DC supply voltage V DDIx 1.14 1.2 1.26 V 1.5 V DC supply voltage V DDIx 1.425 1.5 1.575 V 1.8 V DC supply voltage V DDIx 1.71 1.8 1.89 V 2.5 V DC supply voltage V DDIx 2.375 2.5 2.625 V

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 8 Note: Power supply ramps must all be strictly monotonic, without plateaus. Note: The retention specification is defined as the total number of programing and digest cycles. For example, 20 years of retention after 500 programming cycles. Note: The digest cycle specification is 2000 digest cycles for every program cycle with a maximum of 500 programming cycles. Note: If your product qualification requires accelerated programming cycles, see Microsemi SoC Products Quality and Reliability Report about recommended methodologies. 3.3 V DC supply voltage V DDIx 3.15 3.3 3.45 V LVDS differential I/O V DDIx 2.375 2.5 3.45 V B-LVDS, M-LVDS, Mini-LVDS, RSDS differential I/O VDDIx 2.375 2.5 2.625 V LVPECL differential I/O V DDIx 3.15 3.3 3.45 V Reference voltage supply for FDDR (Bank0) and MDDR (Bank5) VREFx 0.49 × VDDIx 0.5 × V DDIx 0.51 × V DDIx V Analog sense circuit supply of embedded nonvolatile memory (eNVM). Must be shorted to VPP. VPPNVM 2.375 2.5 2.625 V 2.5 V range 3.15 3.3 3.45 V 3.3 V range 1. The SERDES_[01]_VDD supply must be connected to VDD. 2. Programming at Industrial temperature range is available only with VPP = 3.3 V. Table 5 • FPGA Operating Limits Product Grade Element Programming Temperature Operating Temperature Programming Cycles Digest Temperature Digest Cycles Retention (Biased/ Unbiased) Commercial FPGA Min T J = 0 °C Max TJ = 85 °C Min TJ = 0 °C Max TJ = 85 °C

500 Min T J = 0 °C

Max TJ = 85 °C 2000 20 years Industrial1 1. Programming at Industrial tem perature range is available only with VPP = 3.3 V. FPGA Min T J = –40 °C Max TJ = 100 °C Min TJ = –40 °C Max TJ = 100 °C

500 Min T J = –40 °C

Max TJ = 100 °C 2000 20 years Table 4 • Recommended Operating Conditions1 (continued) Parameter Symbol Min Typ Max Unit Conditions

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 9 The following table lists the embedded operating flash limits. Note: If your product qualification requires accelerated programming cycles, see Microsemi SoC Products Quality and Reliability Report about recommended methodologies. Table 6 • Embedded Operating Flash Limits Product Grade Element Programming Temperature Maximum Operating Temperature Programming Cycles Retention (Biased/Unbiased) Commercial Embedded flash Min T J = 0 °C Max TJ = 85 °C Min TJ = 0 °C Max TJ = 85 °C < 1000 cycles per page, up to two million cycles per eNVM array 20 years Min TJ = 0 °C Max TJ = 85 °C < 10000 cycles per page, up to 20 million cycles per eNVM array 10 years Industrial Embedded flash Min T J = –40 °C Max TJ = 100 °C Min TJ = –40 °C Max TJ = 100 °C < 1000 cycles per page, up to two million cycles per eNVM array 20 years Min T J = –40 °C Max TJ = 100 °C < 10000 cycles per page, up to 20 million cycles per eNVM array 10 years Table 7 • Device Storage Temperature and Retention Product Grade Storage Tempe rature (Tstg) Retention Commercial Min T J = 0 °C Max TJ = 85 °C 20 years Industrial Min T J = –40 °C Max TJ = 100 °C 20 years Table 8 • High Temperature Data Retention (HTR) Lifetime TJ (C) HTR Lifetime 1 (yrs) 1. HTR Lifetime is the period during which a verify failure is n ot expected due to flash leakage. 90 20.5 95 20.5 100 20.5 105 17.0 110 15.0 115 13.0 120 11.5 125 10.0 130 8.0 135 6.0 140 4.5 145 3.0 150 1.5

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 10 Figure 1 • High Temperature Data Retention (HTR)

2.3.1.1 Overshoot/Undershoot Limits

For AC signals, the input signal may undershoot during transitions to –1.0 V for no longer than 10% of the period. The current during the transition must not exceed 100 mA. For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period. The current during the transition must not exceed 100 mA. Note: The above specifications do not apply to the PCI standard. The IGLOO2 and SmartFusion2 PCI I/Os are compliant with the PCI standard including the PCI overshoot/undershoot specifications.

2.3.1.2 Thermal Characteristics

The temperature variable in the Microsemi SoC Products Group Designer software refers to the junction temperature, not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power consumption causes the chip's junction temperature to be higher than the ambient, case, or board temperatures. EQ1 through EQ3 give the relationship between thermal resistance, temperature gradient, and power. EQ 1 EQ 2 EQ 3 JA TJ TA– JB TJ TB– JC TJ TC–

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 11 where JA = Junction-to-air thermal resistance JB = Junction-to-board thermal resistance JC = Junction-to-case thermal resistance TJ = Junction temperature TA = Ambient temperature TB = Board temperature (measured 1.0 mm away from the package edge) TC = Case temperature P = Total power dissipated by the device Table 9 • Package Thermal Resistance of SmartFusion2 and IGLOO2 Devices Device Still Air 1.0 m/s 2.5 m/s JB JC UnitJA 005 010 025 050 060 090

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2.3.1.2.1 Theta-JA

Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JEDEC (JESD-51), but it has little relevance in the actual performance of the product. It must be used with caution, but it is useful for comparing the thermal performance of one package with another. The maximum power dissipation allowed is calculated using EQ4. EQ 4 The absolute maximum junction temperature is 100 °C. EQ5 shows a sample calculation of the absolute maximum power dissipation allowed for the M2GL050T-FG896 package at commercial temperature and in still air, where: EQ 5 The power consumption of a device can be calculated using the Microsemi SoC Products Group power calculator. The device's power consumption must be lower than the calculated maximum power dissipation by the package. If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink may be attached to the top of the case, or the airflow inside the system must be increased.

2.3.1.2.2 Theta-JB

Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from the junction to the board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.

2.3.1.2.3 Theta-JC

Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip to the top or bottom surface of the package. It is applicable to packages used with external heat sinks. Constant temperature is applied to the surface, which acts as a boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration.

2.3.1.3 ESD Performance

See RT0001: Microsemi Corporation - SoC Products Reliability Report for information about ESD. 150 JA = 14.7 °C/W (taken from Table 9, page 11). TA = 85 °C Table 9 • Package Thermal Resistance of SmartFusion2 and IGLOO2 Devices (continued) Device Still Air 1.0 m/s 2.5 m/s JB JC UnitJA Maximum power allowed TJ(MAX) TA(MAX)– JA Maximum power allowed 100 °C 85 °C–

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2.3.2 Power Consumption

The following sections describe the power consumptions of the devices.

2.3.2.1 Quiescent Supply Current

Table 10 • Quiescent Supply Current Characteristics Power Supplies/Blocks Modes and Configurations Non-Flash*Freeze Flash*Freeze FPGA Core On Off VDD/SERDES_[01]_VDD1 1. SERDES_[01]_VDD Power Supply is shorted to V DD. On On VPP/VPPNVM On On HPMS_MDDR_PLL_VDDA/FDDR_PLL_VDDA/ CCC_XX[01]_PLL_VDDA/PLL0_PLL1_HPMS_MDDR_VDD A

0 V 0 V

SERDES_[01]_PLL_VDDA 2. SerDes and DDR blocks to be unused. SERDES_[01]_L[0123]_VDDAPLL/VDD_2V52 On On SERDES_[01]_L[0123]_VDDAIIO2 On On VDDIx 3, 4 3. V DDIx has been set to ON for test conditions as described. Banks on the east side should always be powered with the appropriate VDDI bank supplies. For details on bank power supplies, see “Recommendation for Unused Bank Supplies” table in the AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note. 4. No Differential (that is to s ay, LVDS) I/Os or ODT attributes to be used. On On VREFx On On MSSDDR CLK 32 kHz 32 kHz RAM On Sleep state System controller 50 MHz 50 MHz

50 MHz oscillator (enable/disable) Enable Disabled

1 MHz oscillator (enable/disable) Disabled Disabled

Crystal oscillator (enable/disable) Disabled Disabled Table 11 • SmartFusion2 and IGLOO2 Quiescent Supply Current (V DD = 1.2 V) – Typical Process Symbol Modes 005 010 025 050 060 090 150 Unit Conditions IDC1 Non- Flash*Freeze (TJ = 25 °C) (TJ = 85 °C) (TJ = 100 °C)

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2.3.2.2 Programming Currents

The following tables represent programming, verify and Inrush currents for SmartFusion2 SoC and IGLOO2 FPGA devices. (TJ = 25 °C) (TJ = 85 °C) (TJ = 100 °C) Table 12 • SmartFusion2 and IGLOO2 Quiescent Supply Current (VDD = 1.26 V) – Worst-Case Process Symbol Modes 005 010 025 050 060 090 150 Unit Conditions IDC1 Non- Flash*Freeze (TJ= 85 °C) (TJ = 100 °C) (TJ = 85 °C) (TJ = 100 °C) Table 13 • Currents During Program Cycle, 0 °C < = TJ <= 85 °C – Typical Process Power Supplies Voltage (V) 005 010 025 050 060 090 150 1 1. V PP and VPPNVM are internally shorted. Unit VDD 1.26 46 53 55 58 30 42 52 mA VPP 3.46 8 11 6 10 9 12 12 mA VPPNVM 3 . 4 6 122333 m A VDDI 2.62 31 16 17 1 12 12 81 mA 3.46 62 31 36 1 12 17 84 mA Number of banks 7 8 8 10 10 9 19 Table 14 • Currents During Verify Cycle, 0 °C <= TJ <= 85 °C – Typical Process Power Supplies Voltage (V) 005 010 025 050 060 090 150 1 1. V PP and VPPNVM are internally shorted. Unit VDD 1.26 44 53 55 58 33 41 51 mA VPP 3 . 4 6 6531 5 81 1 1 2 m A VPPNVM 3 . 4 6 100111 m A VDDI 2.62 31 16 17 1 12 11 81 mA 3.46 61 32 36 1 12 17 84 mA Number of banks 7 8 8 10 10 9 19 Table 11 • SmartFusion2 and IGLOO2 Quiescent Supply Current (V DD = 1.2 V) – Typical Process Symbol Modes 005 010 025 050 060 090 150 Unit Conditions

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2.3.3 Average Fabric Temperature and Voltage Derating Factors

The following table lists the average temperature and voltage derating factors for fabric timing delays normalized to TJ = 85 °C, in worst-case VDD = 1.14 V. Table 15 • Inrush Currents at Power up, –40 °C <= TJ <= 100 °C – Typical Process Power Supplies Voltage (V) 005 010 025 050 060 090 150 Unit VDD 1.26 25 32 38 48 45 77 109 mA VPP 3.46 33 49 36 180 13 36 51 mA VDDI 2.62 134 141 161 187 93 272 388 mA Number of banks 7 8 8 10 10 9 19 Table 16 • Average Junction Temperature and Voltage Derating Factors for Fabric Timing Delays Array Voltage VDD (V) –40 °C 0 °C 25 °C 70 °C 85 °C 100 °C

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2.3.4 Timing Model

This section describes timing model and timing parameters. Figure 2 • Timing Model The following table lists the timing model parameters in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 17 • Timing Model Parameters Index Symbol Description –1 Unit For More Information AT PY Propagation delay of DDR3 receiver 1.605 ns See Table 137, page 50 BT ICLKQ Clock-to-Q of the input data register 0.16 ns See Table 221, page 71 TISUD Setup time of the input data register 0.357 ns See Table 221, page 71 CT RCKH Input high delay for global clock 1.53 ns See Table 227, page 78 TRCKL Input low delay for global clock 0.897 ns See Table 227, page 78 DT PY Input propagation delay of LVDS receiver 2.774 ns See Table 167, page 57 ET DP Propagation delay of a three-input AND gate 0.198 ns See Table 223, page 76

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 17 FT DP Propagation delay of an OR gate 0.179 ns See Table 223, page 76 GT DP Propagation delay of an LVDS transmitter 2.136 ns See Table 169, page 57 HT DP Propagation delay of a three-input XOR Gate 0.241 ns See Table 223, page 76 IT DP Propagation delay of LVCMOS 2.5 V transmitter, drive strength of 16 mA on the MSIO bank 2.412 ns See Table 46, page 28 JT DP Propagation delay of a two-input NAND gate 0.179 ns See Table 223, page 76 KT DP Propagation delay of LVCMOS 2.5 V transmitter, drive strength of 8 mA on the MSIO bank 2.309 ns See Table 46, page 28 LT CLKQ Clock-to-Q of the data register 0.108 ns See Table 224, page 77 TSUD Setup time of the data register 0.254 ns See Table 224, page 77 MT DP Propagation delay of a two-input AND gate 0.179 ns See Table 223, page 76 NT OCLKQ Clock-to-Q of the output data register 0.263 ns See Table 220, page 69 TOSUD Setup time of the output data register 0.19 ns See Table 220, page 69 OT DP Propagation delay of SSTL2, Class I transmitter on the MSIO bank 2.055 ns See Table 114, page 46 PT DP Propagation delay of LVCMOS 1.5 V transmitter, drive strength of 12 mA, fast slew on the DDRIO bank 3.316 ns See Table 70, page 35 Table 17 • Timing Model Parameters (continued) Index Symbol Description –1 Unit For More Information

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2.3.5 User I/O Characteristics

There are three types of I/Os supported in the IGLOO2 FPGA and SmartFusion2 SoC FPGA families: MSIO, MSIOD, and DDRIO I/O banks. The I/O standards supported by the different I/O banks is described in the I/Os section of the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide.

2.3.5.1 Input Buffer and AC Loading

The following figure shows the input buffer and AC loading. Figure 3 • Input Buffer AC Loading TPY (R) IN Y GND TPY (F) TPYS (R) TPYS (F) 50%50% PAD Y TPY VIH VCCA VTRIPVTRIP VIL TPYS TPY = MAX(TPY(R), TPY(F)) IN TPYS = MAX(TPYS(R), TPYS(F)) Note: TPYS = Schmitt Trigger Input

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2.3.5.2 Output Buf fer and AC Loading

The following figure shows the output buffer and AC loading. Figure 4 • Output Buffer AC Loading PAD TDP VTT/VDDI CLOAD D TDP TDP = MAX(TDP(R), TDP(F)) PAD CLOAD Rtt_testD TDP = MAX(TDP(R), TDP(F)) Single-Ended I/O Test Setup HSTL/PCI Test Setup TDP PAD CLOAD Rtt_testD TDP = MAX(TDP(R), TDP(F)) Voltage-Referenced, Singled-Ended I/O Test Setup Differential I/O Test Setup TDP TPY PAD_P PAD_P IND TDP = MAX(TDP(R), TDP(F)) TPY = MAX(TPY(R), TPY(F)) TPYS = MAX(TPYS(R), TPYS(F)) PAD_N PAD_N OUT OUT OUT OUT VTT

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2.3.5.3 Tristate Buffer and AC Loading

The tristate path for enable path loadings is described in the respective specifications. The following figure shows the methodology of characterization illustrated by the enable path test point. Figure 5 • Tristate Buffer for Enable Path Test Point

2.3.5.4 I/O Speeds

This section describes the maximum data rate summary of I/O in worst-case industrial conditions. See the individual I/O standards for operating conditions. Table 18 • Maximum Data Rate Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions I/O MSIO MSIOD DDRIO Unit PCI 3.3 V 630 Mbps LVTTL 3.3 V 600 Mbps LVCMOS 3.3 V 600 Mbps LVCMOS 2.5 V 410 420 400 Mbps LVCMOS 1.8 V 295 400 400 Mbps LVCMOS 1.5 V 160 220 235 Mbps LVCMOS 1.2 V 120 160 200 Mbps LPDDR-LVCMOS 1.8 V mode 400 Mbps THZ TZH TLZ 90% VDDI 90% VDDI 10% VDDI 50% PAD Data (D) Enable (E) 50% 10% VDDI TZL 50% PAD E D OUT TZL, TZH, THZ, TLZ Rent to GND for TZH, THZ 50% Cent TZL, TLZ, TZH, THZ Rent to VDDI for TZL, TLZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 21 Table 19 • Maximum Data Rate Summary Table for Voltage-Referenced I/O in Worst-Case Industrial Conditions I/O MSIO MSIOD DDRIO Unit LPDDR 400 Mbps HSTL1.5 V 400 Mbps SSTL 2.5 V 510 700 400 Mbps SSTL 1.8 V 667 Mbps SSTL 1.5 V 667 Mbps Table 20 • Maximum Data Rate Summary Table for Differential I/O in Worst-Case Industrial Conditions I/O MSIO MSIOD Unit LVPECL (input only) 900 Mbps LVDS 3.3 V 535 Mbps LVDS 2.5 V 535 700 Mbps RSDS 520 700 Mbps BLVDS 500 Mbps MLVDS 500 Mbps Mini-LVDS 520 700 Mbps Table 21 • Maximum Frequency Summary Table for Single-Ended I/O in Worst-Case Industrial Conditions I/O MSIO MSIOD DDRIO Unit PCI 3.3 V 315 MHz LVTTL 3.3 V 300 MHz LVCMOS 3.3 V 300 MHz LVCMOS 2.5 V 205 210 200 MHz LVCMOS 1.8 V 147.5 200 200 MHz LVCMOS 1.5 V 80 110 118 MHz LVCMOS 1.2 V 60 80 100 MHz LPDDR– LVCMOS 1.8 V mode 200 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 22 Table 22 • Maximum Frequency Summary Table for Voltage-Referenced I/O in Worst- Case Industrial Conditions I/O MSIO MSIOD DDRIO Unit LPDDR 200 MHz HSTL1.5 V 200 MHz SSTL 2.5 V 255 350 200 MHz SSTL 1.8 V 334 MHz SSTL 1.5 V 334 MHz Table 23 • Maximum Frequency Summary Table for Differential I/O in Worst-Case Industrial Conditions I/O MSIO MSIOD Unit LVPECL (input only) 450 MHz LVDS 3.3 V 267.5 MHz LVDS 2.5 V 267.5 350 MHz RSDS 260 350 MHz BLVDS 250 MHz MLVDS 250 MHz Mini-LVDS 260 350 MHz

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2.3.5.5 Detailed I/O Characteristics

The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of DDRIO I/O bank at VOH/VOL Level. Table 24 • Input Capacitance, Leakage Current, and Ramp Time Symbol Description Maximum Unit Conditions CIN Input capacitance 10 pF IIL (dc) Input current low (Applicable to HSTL/SSTL inputs only) 400 µA V DDI = 2.5 V 500 µA V DDI = 1.8 V 600 µA V DDI = 1.5 V1 1. Applicable when I/O pair is programmed with an HSTL/SSTL I/O type on IOP and an un- terminated I/O type (LVCMOS, for example) on ION pad. Input current low (Applicable to all other digital inputs) 10 µA IIH (dc) Input current high (Applicable to HSTL/SSTL inputs only) 400 µA V DDI = 2.5 V 500 µA V DDI = 1.8 V 600 µA V DDI = 1.5 V1 Input current high (Applicable to all other digital inputs) 10 µA TRAMPIN 2. Voltage ramp must be monotonic. Input ramp time (Applicable to all digital inputs) 50 ns Table 25 • I/O Weak Pull-up/Pull-down Resistances for DDRIO I/O Bank VDDI Domain R(WEAK PULL-UP) at VOH () R(WEAK PULL-DOWN) at V OL ( Min Max Min Max

2.5 V1, 2

R(WEAK PULL-DOWN) = (VOLs pec)/I(WEAK PULL-DOWN MAX). 2. R(WEAK PULL-UP) = (VDDImax – V OHspec)/I(WEAK PULL-UP MIN). 10K 17.8K 9.98K 18K

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 24 The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of MSIO I/O bank at VOH/VOL Level. The following table lists the minimum and maximum I/O weak pull-up/pull-down resistance values of MSIOD I/O bank at VOH/VOL Level. The following table lists the hysteresis voltage value for schmitt trigger mode input buffers. Table 26 • I/O Weak Pull-Up/Pull-Down Resistances for MSIO I/O Bank VDDI Domain R(WEAK PULL-UP) at VOH ( R(WEAK PULL-DOWN) at VOL ( Min Max Min Max

R(WEAK PULL-DOWN) = (VOLs pec)/I(WEAK PULL-DOWN MAX). 2. R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN). 10K 17.6K 10.1K 18.4K Table 27 • I/O Weak Pull-up/Pull-down Resistances for MSIOD I/O Bank VDDI Domain R(WEAK PULL-UP) at VOH () R(WEAK PULL -DOWN) at VOL () Min Max Min Max
R(WEAK PULL-DOWN) = (VOLs pec)/I(WEAK PULL-DOWN MAX). 2. R(WEAK PULL-UP) = (VDDImax – VOHspec)/I(WEAK PULL-UP MIN). 9.6K 16.6K 9.5K 16.4K 1.5 V1, 2 9.9K 18K 9.8K 17.6K 1.2 V1, 2 10.3K 19.6K 10K 19.1K Table 28 • Schmitt Trigger Input Hysteresis Input Buffer Configuration Hysteresis Valu e (Typical, unless otherwise noted)

3.3 V LVTTL/LVCMOS/

0.05 × VDDI (worst-case) 2.5 V LVCMOS 0.05 × V DDI (worst-case) 1.8 V LVCMOS 0.1 × V DDI (worst-case)

1.5 V LVCMOS 60 mV

1.2 V LVCMOS 20 mV

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2.3.5.6 Single-Ende d I/O Standards

2.3.5.6.1 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined by JEDEC (JESD 8-5). The LVCMOS standards supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33. LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V applications. Minimum and Maximum DC/AC Input and Output Levels Specification Table 29 • LVTTL/LVCMOS 3.3 V DC Recommended DC Operating Conditions (Applicable to MSIO I/O Bank Only) Parameter Symbol Min Typ Max Unit Supply voltage V DDI 3.15 3.3 3.45 V Table 30 • LVTTL/LVCMOS 3.3 V Input Voltage Specification (Applicable to MSIO I/O Bank Only) Parameter Symbol Min Max Unit DC input logic high V IH (DC) 2.0 3.45 V DC input logic low V IL (DC) –0.3 0.8 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 31 • LVCMOS 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only) Parameter Symbol Min Max Unit DC output logic high1 1. The V OH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B requirements. VOH VDDI – 0.4 V DC output logic low1 VOL 0.4 V Table 32 • LVTTL 3.3 V DC Output Voltage Specification (Applicable to MSIO I/O Bank Only) Parameter Symbol Min Max Unit DC output logic high V OH 2.4 V DC output logic low V OL 0.4 V Table 33 • LVTTL/LVCMOS 3.3 V AC Maximum Switching Speed (Applicable to MSIO I/O Bank Only) Parameter Symbol Max Unit Conditions Maximum data rate (for MSIO I/O bank) DMAX 600 Mbps AC loading: 17 pF load, maximum drive/slew

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 26 Note: For a detailed I/V curve, use the corresponding IBIS models: www.microsemi.com/soc/download/ibis/default.aspx. AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 3.0 V Table 34 • LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO I/O Bank Only) Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 1.4 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F Capacitive loading for data path (TDP)C LOAD 5p F Table 35 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications for MSIO I/O Bank Output Drive Selection VOH (V) VOL (V) IOH (at VOH) mA IOL (at VOL) mA 2 mA V DDI – 0.4 0.4 2 2 4 mA V DDI – 0.4 0.4 4 4 8 mA V DDI – 0.4 0.4 8 8 12 mA V DDI – 0.4 0.4 12 12 16 mA V DDI – 0.4 0.4 16 16 20 mA V DDI – 0.4 0.4 20 20 Table 36 • LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std None 2.262 2.663 2.289 2.695 ns Table 37 • LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ 1. Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. TLZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 27 2.3.5.7 2.5 V LVCMOS LVCMOS 2.5 V is a general standard for 2.5 V applications and is supported in IGLOO2 FPGA and SmartFusion2 SoC FPGAs that are in compliance with the JEDEC specification JESD8-5A. Minimum and Maximum DC/AC Input and Output Levels Specification Table 38 • LVCMOS 2.5 V DC Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 2.375 2.5 2.625 V Table 39 • LVCMOS 2.5 V DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high (for MSIOD and DDRIO I/O banks) VIH (DC) 1.7 2.625 V DC input logic high (for MSIO I/O bank) VIH (DC) 1.7 3.45 V DC input logic low V IL (DC) –0.3 0.7 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 40 • LVCMOS 2.5 V DC Output Voltage Specification Parameter Symbol Min Max Unit DC output logic high V OH 1. The VOH/VOL test points sele cted ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements. VDDI – 0.4 – V DC output logic low V OL 1 0.4 V Table 41 • LVCMOS 2.5 V AC Minimum and Maximum Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank) D MAX 400 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIO I/O bank) D MAX 410 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIOD I/O bank) D MAX 420 Mbps AC loading: 17 pF load, maximum drive/slew Table 42 • LVCMOS 2.5 V AC Calibrated Impedance Option Parameter Symbol Typ Unit Supported output driver calibrated impedance (for DDRIO I/O bank) Rodt_cal 75, 60, 50, 33, 25, 20

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 28 Note: For board design considerations, output slew rates extraction, detailed output buffer resistances, and I/V Curve, use the corresponding IBIS models located at: www.microsemi.com/soc/download/ibis/default.aspx. AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V Table 43 • LVCMOS 2.5 V AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 1.2 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F Capacitive loading for data path (TDP)C LOAD 5p F Table 44 • LVCMOS 2.5 V Transmitter Drive Strength Specifications Output Drive Selection VOH (V) VOL (V) IOH (at VOH) mA IOL (at VOL) mA MSIO I/O Bank MSIOD I/O Bank DDRIO I/O Bank (With Software Default Fixed Code) Min Max 2 mA 2 mA 2 mA V DDI – 0.4 0.4 2 2 4 mA 4 mA 4 mA V DDI – 0.4 0.4 4 4 6 mA 6 mA 6 mA V DDI – 0.4 0.4 6 6 8 mA 8 mA 8 mA V DDI – 0.4 0.4 8 8 12 mA 12 mA 12 mA V DDI – 0.4 0.4 12 12 16 mA 16 mA V DDI – 0.4 0.4 16 16 Table 45 • LVCMOS 2.5 V Receiver Characteristics (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std Table 46 • LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ

1 TLZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 29 1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. Table 47 • LVCMOS 2.5 V Transmitter Characteristics for MSIO Bank (Output and Tristate Buffers) Output Drive Selection Slew Control T DP TZL TZH THZ

Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. Table 46 • LVCMOS 2.5 V Transmitter Characteristics for DDRIO Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 30 2.3.5.8 1.8 V LVCMOS LVCMOS 1.8 is a general standard for 1.8 V applications and is supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs in compliance to the JEDEC specification JESD8-7A. Minimum and Maximum DC/AC Input and Output Levels Specification Table 48 • LVCMOS 2.5 V Transmitter Characteristics for MSIOD Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ 1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. TLZ Table 49 • LVCMOS 1.8 V DC Recommended Operating Conditions Parameter Symbol Min Typ Max Unit LVCMOS 1.8 V DC Recommended Operating Conditions Supply voltage V DDI 1.710 1.8 1.89 V Table 50 • LVCMOS 1.8 V DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high (for MSIOD and DDRIO I/O banks) VIH (DC) 0.65 × V DDI 1.89 V DC input logic high (for MSIO I/O bank) VIH (DC) 0.65 × V DDI 3.45 V DC input logic low V IL (DC) –0.3 0.35 × V DDI V Input current high1 1. See Table 24, page 23. IIH (DC) – Input current low1 IIL (DC) – Table 51 • LVCMOS 1.8 V DC Output Voltage Specification Parameter Symbol Min Max Unit DC output logic high V OH VDDI – 0.45 V DC output logic low V OL 0.45 V Table 52 • LVCMOS 1.8 V Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank)1 1. Maximum Data Rate applies for Drive Strength 8 mA and above, All Slews. DMAX 400 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIO I/O bank) D MAX 295 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIOD I/O bank)1 DMAX 400 Mbps AC loading: 17 pF load, maximum drive/slew

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 31 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.71 V Table 53 • LVCMOS 1.8 V AC Calibrated Impedance Option Parameter Symbol Typ Unit Supported output driver calibrated impedance (for DDRIO I/O bank) Rodt_cal 75, 60, 50, 33, 25, 20 Table 54 • LVCMOS 1.8 V AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 0.9 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2k  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) CENT 5p F Capacitive loading for data path (TDP)C LOAD 5p F Table 55 • LVCMOS 1.8 V Transmitter Drive Strength Specifications Output Drive Selection V OH (V) V OL (V) IOH (at VOH) mA IOL (at VOL) mAMSIO I/O Bank MSIOD I/O B ank DDRIO I/O Bank Min Max 2 mA 2 mA 2 mA V DDI – 0.45 0.45 2 2 4 mA 4 mA 4 mA V DDI – 0.45 0.45 4 4 6 mA 6 mA 6 mA V DDI – 0.45 0.45 6 6 8 mA 8 mA 8 mA V DDI – 0.45 0.45 8 8 10 mA 10 mA 10 mA V DDI – 0.45 0.45 10 10 12 mA 12 mA V DDI – 0.45 0.45 12 12 16 mA1 1. 16 mA drive strengths, all sle ws, meets LPDDR JEDEC electrical compliance. VDDI – 0.45 0.45 16 16 Table 56 • LVCMOS 1.8 V Receiver Characteristics (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std LVCMOS 1.8 V (for DDRIO I/O bank with Fixed Codes) None 1.968 2.315 2.099 2.47 ns LVCMOS 1.8 V (for MSIO I/O bank) None 2.898 3.411 2.883 3.393 ns 50 3.05 3.59 3.044 3.583 ns 75 2.999 3.53 2.987 3.516 ns 150 2.947 3.469 2.933 3.452 ns LVCMOS 1.8 V (for MSIOD I/O bank) None 2.611 3.071 2.598 3.057 ns 50 2.775 3.264 2.775 3.265 ns 75 2.72 3.2 2.712 3.19 ns 150 2.666 3.137 2.655 3.123 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 32 Table 57 • LVCMOS 1.8 V Transmitter Characteristics for DDRIO I/O Bank with Fixed Code (Output and Tristate Buffers) Output Drive Selection Slew Control T DP TZL TZH THZ

Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management.

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 33 2.3.5.9 1.5 V LVCMOS LVCMOS 1.5 is a general standard for 1.5 V applications and is supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs in compliance to the JEDEC specification JESD8-11A. Minimum and Maximum DC/AC Input and Output Levels Specification Table 58 • LVCMOS 1.8 V Transmitter Characteristics for MSIO I/O Bank Output Drive Selection Slew Control TDP TZL TZH THZ 1. Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. TLZ Table 59 • LVCMOS 1.8 V Transmitter Characteristics for MSIOD I/O Bank Output Drive Selection Slew Control TDP TZL TZH THZ 1. Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. TLZ Table 60 • LVCMOS 1.5 V DC Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 1.425 1.5 1.575 V Table 61 • LVCMOS 1.5 V DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high for (MSIOD and DDRIO I/O banks) VIH (DC) 0.65 × V DDI 1.575 V DC input logic high (for MSIO I/O bank) V IH (DC) 0.65 × V DDI 3.45 V DC input logic low V IL (DC) –0.3 0.35 × V DDI V Input current high1 1. See Table 24, page 23. IIH (DC) – Input current low1 IIL (DC –

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 34 Note: For a detailed I/V curve, use the corresponding IBIS models: www.microsemi.com/soc/download/ibis/default.aspx. Table 62 • LVCMOS 1.5 V DC Output Voltage Specification Parameter Symbol Min Max Unit DC output logic high VOH V DDI × 0.75 V DC output logic low VOL V DDI × 0.25 V Table 63 • LVCMOS 1.5 V AC Minimum and Maximum Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank) D MAX 235 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIO I/O bank) D MAX 160 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIOD I/O bank) D MAX 220 Mbps AC loading: 17 pF load, maximum drive/slew Table 64 • LVCMOS 1.5 V AC Calibrated Impedance Option Parameter Symbol Typ Unit Supported output driver calibrated impedance (for DDRIO I/O bank) RODT_CA L 75, 60, 50, 40 Table 65 • LVCMOS 1.5 V AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point V TRIP 0.75 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F Capacitive loading for data path (TDP)C LOAD 5p F Table 66 • LVCMOS 1.5 V Transmitter Drive Strength Specifications Output Drive Selection V OH (V) V OL (V) IOH (at VOH) mA IOL (at VOL) mAMSIO I/O Bank MSI OD I/O Bank DDRIO I/O Bank Min Max 2 mA 2 mA 2 mA V DDI × 0.75 V DDI × 0.25 2 2 4 mA 4 mA 4 mA V DDI × 0.75 V DDI × 0.25 4 4 6 mA 6 mA 6 mA V DDI × 0.75 V DDI × 0.25 6 6 8 mA 8 mA V DDI × 0.75 V DDI × 0.25 8 8 10 mA V DDI × 0.75 V DDI × 0.25 10 10 12 mA V DDI × 0.75 V DDI × 0.25 12 12

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 35 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.425 V Table 67 • LVCMOS 1.5 V Receiver Characteristics for DDRIO I/O Bank with Fixed Codes (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std None 2.051 2.413 2.086 2.455 ns Table 68 • LVCMOS 1.5 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std None 3.311 3.896 3.285 3.865 ns 50 3.654 4.299 3.623 4.263 ns 75 3.533 4.156 3.501 4.119 ns 150 3.415 4.018 3.388 3.986 ns Table 69 • LVCMOS 1.5 V Receiver Characteristics for MSIOD I/O Bank (Input Buffers) On-Die Termination (ODT) T PY TPYS Unit–1 –Std –1 –Std None 2.959 3.481 2.93 3.447 ns 50 3.298 3.88 3.268 3.845 ns 75 3.162 3.719 3.128 3.68 ns 150 3.053 3.592 3.021 3.554 ns Table 70 • LVCMOS 1.5 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control T DP TZL TZH THZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 36 Medium fast Medium fast Medium fast Medium fast 1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. Table 71 • LVCMOS 1.5 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ

Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. Table 70 • LVCMOS 1.5 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 37 2.3.5.10 1.2 V LVCMOS LVCMOS 1.2 is a general standard for 1.2 V applications and is supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs in compliance to the JEDEC specification JESD8-12A. Minimum and Maximum DC/AC Input and Output Levels Specification Table 72 • LVCMOS 1.5 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ 1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. TLZ Table 73 • LVCMOS 1.2 V DC Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 1.140 1.2 1.26 V Table 74 • LVCMOS 1.2 V DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high (for MSIOD and DDRIO I/O banks) VIH (DC) 0.65 × V DDI 1.26 V DC input logic high (for MSIO I/O bank) VIH (DC) 0.65 × V DDI 3.45 V DC input logic low V IL (DC) –0.3 0.35 × V DDI V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 75 • LVCMOS 1.2 V DC Output Voltage Specification Parameter Symbol Min Max Unit DC output logic high V OH VDDI × 0.75 V DC output logic low V OL VDDI × 0.25 V Table 76 • LVCMOS 1.2 V Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank) D MAX 200 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIO I/O bank) D MAX 120 Mbps AC loading: 17 pF load, maximum drive/slew Maximum data rate (for MSIOD I/O bank) D MAX 160 Mbps AC loading: 17 pF load, maximum drive/slew

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 38 Note: For a detailed I/V curve, use the corresponding IBIS models: www.microsemi.com/soc/download/ibis/default.aspx. AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.14 V Table 77 • LVCMOS 1.2 V AC Calibrated Impedance Option Parameter Symbol Typ Unit Supported output driver calibrated impedance (for DDRIO I/O bank) RODT_CAL 75, 60, 50, 40  Table 78 • LVCMOS 1.2 V AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point V TRIP 0.6 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F Capacitive loading for data path (TDP)C LOAD 5p F Table 79 • LVCMOS 1.2 V Transmitter Drive Strength Specifications Output Drive Selection V OH (V) V OL (V) IOH (at VOH) mA IOL (at VOL) mAMSIO I/O Bank MSIOD I/O Bank DDRIO I/O Bank Min Max 2 mA 2 mA 2 mA V DDI × 0.75 V DDI × 0.25 2 2 4 mA 4 mA 4 mA V DDI × 0.75 V DDI × 0.25 4 4 6 mA V DDI × 0.75 V DDI × 0.25 6 6 Table 80 • LVCMOS 1.2 V Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std None 2.448 2.88 2.466 2.901 ns Table 81 • LVCMOS 1.2 V Receiver Characteristics for MSIO I/O Bank (Input Buffers) On-Die Termination ODT) TPY TPYS Unit–1 –Std –1 –Std None 4.714 5.545 4.675 5.5 ns 50 6.668 7.845 6.579 7.74 ns 75 5.832 6.862 5.76 6.777 ns 150 5.162 6.073 5.111 6.014 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 39 Table 82 • LVCMOS 1.2 V Receiver Characteristics for MSIOD I/O Bank (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std None 4.154 4.887 4.114 4.84 ns 50 6.918 8.139 6.806 8.008 ns 75 5.613 6.603 5.533 6.509 ns 150 4.716 5.549 4.657 5.479 ns Table 83 • LVCMOS 1.2 V Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control T DP TZL TZH THZ

Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. Table 84 • LVCMOS 1.2 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ
Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management.

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 40 2.3.5.11 3.3 V PCI/PCIX Peripheral Component Interface (PCI) for 3.3 V standards specify support for 33 MHz and 66 MHz PCI bus applications. Minimum and Maximum DC/AC Input and Output Levels Specification (Applicable to MSIO Bank Only) Table 85 • LVCMOS 1.2 V Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ 1. Delay increases with drive st rength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management. TLZ Table 86 • PCI/PCI-X DC Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 3.15 3.3 3.45 V Table 87 • PCI/PCI-X DC Input Voltage Specification Parameter Symbol Min Max Unit DC input voltage V I 03 . 4 5 V Input current high1 1. See Table 24, page 23. IIH(DC) Input current low1 IIL(DC) Table 88 • PCI/PCI-X DC Output Voltage Specification Parameter Symbol Min Typ Max Unit DC output logic high V OH Per PCI specification V DC output logic low V OL Per PCI specification V Table 89 • PCI/PCI-X Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (MSIO I/O bank) D MAX 630 Mbps AC Loading: per JEDEC specifications Table 90 • PCI/PCI-X AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path (falling edge) V TRIP 0.615 × VDDI V Measuring/trip point for data path (rising edge) V TRIP 0.285 × VDDI V Resistance for data test path RTT_TEST 25  Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 41 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 3.0 V

2.3.6 Memory Interface and Voltage Referenced I/O Standards

This section describes High-Speed Transceiver Logic (HSTL) memory interface and voltage reference I/O standards.

2.3.6.1 High-Speed Transceiver Logic (HSTL)

The HSTL standard is a general purpose high-speed bus standard sponsored by IBM (EIA/JESD8-6). IGLOO2 FPGA and SmartFusion2 SoC FPGA devices support two classes of the 1.5 V HSTL. These differential versions of the standard require a differential amplifier input buffer and a push-pull output buffer. Minimum and Maximum DC/AC Input and Output Levels Specification (Applicable to DDRIO Bank Only) Capacitive loading for data path (TDP)C LOAD 10 pF Table 91 • PCI/PCIX AC Switching Characteristics for Receiver for MSIO I/O Bank (Input Buffers) On-Die Termination (ODT) TPY TPYS Unit–1 –Std –1 –Std None 2.229 2.623 2.238 2.633 ns Table 92 • PCI/PCIX AC switching Characteristics for Transmitter for MSIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 93 • HSTL Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 1.425 1.5 1.575 V Termination voltage V TT 0.698 0.750 0.803 V Input reference voltage V REF 0.698 0.750 0.803 V Table 94 • HSTL DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high V IH (DC) V REF + 0.1 1.575 V DC input logic low V IL (DC) –0.3 V REF – 0.1 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 90 • PCI/PCI-X AC Test Parameter Specifications

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 42 Table 95 • HSTL DC Output Voltage Specification Applicable to DDRIO I/O Bank Only Parameter Symbol Min Max Unit HSTL Class I DC output logic high V OH VDDI – 0.4 V DC output logic low V OL 0.4 V Output minimum source DC current (MSIO and DDRIO I/O banks) I OH at VOH –8.0 mA Output minimum sink current (MSIO and DDRIO I/O banks) I OL at VOL 8.0 mA HSTL Class II DC output logic high V OH VDDI – 0.4 V DC output logic low V OL 0.4 V Output minimum source DC current I OH at VOH –16.0 mA Output minimum sink current I OL at VOL 16.0 mA Table 96 • HSTL DC Differential Voltage Specification Parameter Symbol Min Unit DC input differential voltage V ID (DC) 0.2 V Table 97 • HSTL AC Differential Voltage Specifications Parameter Symbol Min Max Unit AC input differential voltage V DIFF 0.4 V AC differential cross point voltage V x 0.68 0.9 V Table 98 • HSTL Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate D MAX 400 Mbps AC loading: per JEDEC specifications Table 99 • HSTL Impedance Specification Parameter Symbol Typ Unit Conditions Supported output driver calibrated impedance (for DDRIO I/O bank) RREF 25.5, 47.8  Reference resistance = 191  Effective impedance value (ODT for DDRIO I/O bank only) RTT 47.8  Reference resistance = 191  Table 100 • HSTL AC Test Parameter Specification Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 0.75 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F Reference resistance for data test path for HSTL15 Class I (TDP)R T T _ T E S T 5 0  Reference resistance for data test path for HSTL15 Class II (TDP)R T T _ T E S T 2 5  Capacitive loading for data path (TDP)C LOAD 5p F

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 43 AC Switching Characteristics Worst-case commercial conditions: TJ = 85 °C, VDD = 1.14 V, worst-case VDDI.

2.3.6.2 Stub-Series Terminated Logic

Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is supported in IGLOO2 and SmartFusion2 SoC FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is defined by JEDEC standard JESD8-15. IGLOO2 SSTL I/O configurations are designed to meet double data rate standards DDR/2/3 for general purpose memory buses. Double data rate standards are designed to meet their JEDEC specifications as defined by JEDEC standard JESD79F for DDR, JEDEC standard JESD79-2F for DDR, JEDEC standard JESD79-3D for DDR3, and JEDEC standard JESD209A for LPDDR. Table 101 • HSTL Receiver Characteristics for DDRIO I/O Bank with Fixed Code (Input Buffers) On-Die Termination (ODT) TPY Unit –1 –Std Pseudo differential None 1.605 1.888 ns 47.8 1.614 1.898 ns True differential None 1.622 1.909 ns 47.8 1.628 1.916 ns Table 102 • HSTL Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ HSTL Class I HSTL Class II

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 44 2.3.6.3 Stub-Series Terminated Logic 2.5 V (SSTL2) SSTL2 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs and also comply with reduced and full drive of double data rate (DDR) standards. IGLOO2 and SmartFusion2 SoC FPGA I/Os supports both standards for single-ended signaling and differential signaling for SSTL2. This standard requires a differential amplifier input buffer and a push-pull output buffer. Minimum and Maximum DC/AC Input and Output Levels Specification Table 103 • DDR1/SSTL2 DC Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 2.375 2.5 2.625 V Termination voltage V TT 1.164 1.250 1.339 V Input reference voltage V REF 1.164 1.250 1.339 V Table 104 • DDR1/SSTL2 DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high V IH (DC) V REF + 0.15 2.625 V DC input logic low V IL (DC) –0.3 VREF – 0.15 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 105 • DDR1/SSTL2 DC Output Voltage Specification Parameter Symbol Min Max Unit SSTL2 Class I (DDR Reduced Drive) DC output logic high V OH VTT + 0.608 V DC output logic low V OL VTT – 0.608 V Output minimum source DC current I OH at VOH 8.1 mA Output minimum sink current I OL at VOL –8.1 mA SSTL2 Class II (DDR Full Drive) – Applicable to MSIO and DDRIO I/O Bank Only DC output logic high V OH VTT + 0.81 V DC output logic low V OL VTT – 0.81 V Output minimum source DC current I OH at VOH 16.2 mA Output minimum sink current I OL at VOL –16.2 mA Table 106 • DDR1/SSTL2 DC Differential Voltage Specification Parameter Symbol Min Unit DC input differential voltage V ID (DC) 0.3 V Table 107 • SSTL2 AC Differential Voltage Specifications Parameter Symbol Min Max Unit AC input differential voltage V DIFF (AC) 0.7 V AC differential cross point voltage V x (AC) 0.5 × V DDI – 0.2 0.5 × V DDI + 0.2 V

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 45 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V Table 108 • SSTL2 Minimum and Maximum AC Switching Speeds Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank) DMAX 400 Mbps AC loading: per JEDEC specifications Maximum data rate (for MSIO I/O bank) DMAX 575 Mbps AC loading: 17pF load Maximum data rate (for MSIOD I/O bank) DMAX 700 Mbps AC loading: 3 pF / 50  load

510 Mbps AC loading: 17pF load

Table 109 • SSTL2 AC Impedance Specifications Parameter Typ Unit Conditions Supported output driver calibrated impedance (for DDRIO I/O bank) 20, 42  Reference resistor = 150  Table 110 • DDR1/SSTL2 AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 1.25 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F Reference resistance for data test path for SSTL2 Class I (TDP) RTT_TEST 50  Reference resistance for data test path for SSTL2 Class II (TDP) RTT_TEST 25  Capacitive loading for data path (TDP)C LOAD 5p F Table 111 • SSTL2 Receiver Characteristics for DDRIO I/O Bank (Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std Pseudo differential None 1.549 1.821 ns True differential None 1.589 1.87 ns Table 112 • SSTL2 Receiver Characteristics for MSIO I/O Bank (Input Buffers) On-Die Termination (ODT) T PY Unit–1 –Std Pseudo differential None 2.798 3.293 ns True differential None 2.733 3.215 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 46 2.3.6.4 Stub-Series Terminated Logic 1.8 V (SSTL18) SSTL18 Class I and Class II are supported in IGLOO2 and SmartFusion2 SoC FPGAs, and also comply with the reduced and full drive double date rate (DDR2) standard. IGLOO2 and SmartFusion2 SoC FPGA I/Os support both standards for single-ended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer. Table 113 • DDR1/SSTL2 Receiver Characteristics for MSIOD I/O Bank (Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std Pseudo differential None 2.476 2.913 ns True differential None 2.475 2.911 ns Table 114 • SSTL2 Class I Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 115 • DDR1/SSTL2 Class I Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 116 • DDR1/SSTL2 Class I Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 117 • DDR1/SSTL2 Class II Transmitter Characteristics for DDRIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 118 • DDR1/SSTL2 Class II Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 47 Minimum and Maximum DC/AC Input and Output Levels Specification Table 119 • SSTL18 DC Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 1.71 1.8 1.89 V Termination voltage V TT 0.838 0.900 0.964 V Input reference voltage V REF 0.838 0.900 0.964 V Table 120 • SSTL18 DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high V IH (DC) V REF + 0.125 1.89 V DC input logic low V IL (DC) –0.3 V REF – 0.125 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 121 • SSTL18 DC Output Voltage Specification Parameter Symbol Min Max Unit SSTL18 Class I (DDR2 Reduced Drive) DC output logic high V OH VTT + 0.603 V DC output logic low V OL VTT– 0.603 V Output minimum source DC current (DDRIO I/O bank only) IOH at VOH 6.5 mA Output minimum sink current (DDRIO I/O bank only) I OL at VOL –6.5 mA SSTL18 Class II (DDR2 Full Drive)1 1. To meet JEDEC Electrical Compliance, use DDR2 Full Drive Tran smitter. DC output logic high V OH VTT + 0.603 V DC output logic low V OL VTT– 0.603 V Output minimum source DC current (DDRIO I/O bank only) IOH at VOH 13.4 mA Output minimum sink current (DDRIO I/O bank only) I OL at VOL –13.4 mA Table 122 • SSTL18 DC Differential Voltage Specification Parameter Symbol Min Unit DC input differential voltage V ID (DC) 0.3 V Table 123 • SSTL18 AC Differential Voltage Specifications (Applicable to DDRIO Bank Only) Parameter Symbol Min Max Unit AC input differential voltage VDIFF (AC) 0.5 V AC differential cross point voltage Vx (AC) 0.5 × V DDI – 0.175 0.5 × V DDI + 0.175 V

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 48 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.71 V Table 124 • SSTL18 Minimum and Maximum AC Switching Speed (Applicable to DDRIO Bank Only) Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank) D MAX 667 Mbps AC loading: per JEDEC specification Table 125 • SSTL18 AC Impedance Specifications (Applicable to DDRIO Bank Only) Parameter Symbol Typ Unit Conditions Supported output driver calibrated impedance (for DDRIO I/O bank) RREF 20, 42  Reference resistor = 150  Effective impedance value (ODT) R TT 50, 75, 150  Reference resistor = 150  Table 126 • SSTL18 AC Test Parameter Specifications (Applicable to DDRIO Bank Only) Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 0.9 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F Reference resistance for data test path for SSTL18 Class I (TDP) RTT_TEST 50  Reference resistance for data test path for SSTL18 Class II (TDP) RTT_TEST 25  Capacitive loading for data path (TDP)C LOAD 5p F Table 127 • DDR2/SSTL18 Receiver Characteristics for DDRIO I/O Bank with Fixed Code On-Die Termination (ODT) TPY Unit–1 –Std Pseudo differential None 1.567 1.844 ns True differential None 1.588 1.869 ns Table 128 • DDR2/SSTL18 Transmitter Characteristics (Output and Tristate Buffers) T DP TZL TZH THZ TLZ SSTL18 Class I (for DDRIO I/O Bank) SSTL18 Class II (for DDRIO I/O Bank)

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 49 2.3.6.5 Stub-Series Terminated Logic 1.5 V (SSTL15) SSTL15 Class I and Class II are supported in IGLOO2 FPGAs and SmartFusion2 SoC FPGAs, and also comply with the reduced and full drive double data rate (DDR3) standard. IGLOO2 FPGA and SmartFusion2 SoC FPGA I/Os supports both standards for single-ended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer. Minimum and Maximum DC/AC Input and Output Levels Specification The following table lists the SSTL15 DC voltage specifications for DDRIO bank. Note: To meet JEDEC electrical compliance, use DDR3 full drive transmitter. Table 129 • SSTL15 DC Recommended DC Operating Conditions (for DDRIO I/O Bank Only) Parameter Symbol Min Typ Max Unit Supply voltage V DDI 1.425 1.5 1.575 V Termination voltage V TT 0.698 0.750 0.803 V Input reference voltage V REF 0.698 0.750 0.803 V Table 130 • SSTL15 DC Input Voltage Specification (for DDRIO I/O Bank Only) Parameter Symbol Min Max Unit DC input logic high V IH(DC) V REF + 0.1 1.575 V DC input logic low V IL(DC) –0.3 V REF – 0.1 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 131 • SSTL15 DC Output Voltage Specification (for DDRIO I/O Bank Only) Parameter Symbol Min Max Unit DDR3/SSTL15 Class I (DDR3 Reduced Drive) DC output logic high V OH 0.8 × VDDI V DC output logic low V OL 0.2 × VDDI V Output minimum source DC current IOH at VOH 6.5 mA Output minimum sink current I OL at VOL –6.5 mA DDR3/SSTL15 Class II (DDR3 Full Drive) DC output logic high V OH 0.8 × VDDI V DC output logic low V OL 0.2 × VDDI V Output minimum source DC current IOH at VOH 7.6 mA Output minimum sink current I OL at VOL –7.6 mA Table 132 • SSTL15 DC Differential Voltage Specification (for DDRIO I/O Bank Only) Parameter Symbol Min Unit DC input differential voltage V ID 0.2 V

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 50 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 1.425 V Table 133 • SSTL15 AC SSTL15 Minimum and Maximum AC Switching Speed (for DDRIO I/O Bank Only) Parameter Symbol Min Max Unit AC input differential voltage V DIFF (AC) 0.3 V AC differential cross point voltage V x (AC) 0.5 × V DDI – 0.150 0.5 × V DDI + 0.150 V Table 134 • SSTL15 Minimum and Maximum AC Switching Speed (for DDRIO I/O Bank Only) Parameter Symbol Max Unit Conditions Maximum data rate D MAX 667 Mbps AC loading: per JEDEC specifications Table 135 • SSTL15 AC Calibrated Impedance Option (for DDRIO I/O Bank Only) Parameter Symbol Typ Unit Conditions Supported output driver calibrated impedance R REF 34, 40  Reference resistor = 240  Effective impedance value (ODT) R TT 20, 30, 40, 60, 120  Reference resistor = 240  Table 136 • SSTL15 AC Test Parameter Specifications (for DDRIO I/O Bank Only) Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 0.75 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F Reference resistance for data test path for SSTL15 Class I (TDP) RTT_TEST 50  Reference resistance for data test path for SSTL15 Class II (TDP) RTT_TEST 25  Capacitive loading for data path (TDP)C LOAD 5p F Table 137 • DDR3/SSTL15 Receiver Characteristics for DDRIO I/O Bank – with Calibration Only On-Die Termination (ODT) TPY Unit –1 –Std Pseudo differential None 1.605 1.888 ns 20 1.616 1.901 ns 30 1.613 1.897 ns 40 1.611 1.895 ns 60 1.609 1.893 ns 120 1.607 1.89 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 51

2.3.6.6 Low Power Double Data Rate (LPDDR)

LPDDR reduced and full drive low power double data rate standards are supported in IGLOO2 FPGA and SmartFusion2 SoC FPGA I/Os. This standard requires a differential amplifier input buffer and a push-pull output buffer. Minimum and Maximum DC/AC Input and Output Levels Specification True differential None 1.623 1.91 ns 20 1.637 1.926 ns 30 1.63 1.918 ns 40 1.626 1.914 ns 60 1.622 1.91 ns 120 1.619 1.905 ns Table 138 • DDR3/SSTL15 Transmitter Characteristics (Output and Tristate Buffers) T DP TZL TZH THZ TLZ Unit– 1– S t d – 1 – S t d– 1– S t d– 1– S t d– 1– S t d DDR3 Reduced Drive/SSTL15 Class I (for DDRIO I/O Bank) DDR3 Full Drive/SSTL15 Class II (for DDRIO I/O Bank) Table 139 • LPDDR DC Recommended DC Operating Conditions Parameter Symbol Min Typ Max Supply voltage V DDI 1.71 1.8 1.89 Termination voltage V TT 0.838 0.900 0.964 Input reference voltage V REF 0.838 0.900 0.964 Table 140 • LPDDR DC Input Voltage Specification Parameter Symbol Min Max DC input logic high V IH (DC) 0.7 × V DDI 1.89 DC input logic low V IL (DC) –0.3 0.3 × V DDI Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 137 • DDR3/SSTL15 Receiver Characteristics for DDRIO I/O Bank – with Calibration Only On-Die Termination (ODT) TPY Unit –1 –Std

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 52 Table 141 • LPDDR DC Output Voltage Specification Reduced Drive Parameter Symbol Min Max DC output logic high V OH 0.9 × VDDI DC output logic low V OL 0.1 × VDDI Output minimum source DC current IOH at VOH 0.1 Output minimum sink current I OL at VOL –0.1 Table 142 • LPDDR DC Output Voltage Specification Full Drive1 Parameter Symbol Min Max DC output logic high V OH 0.9 × VDDI DC output logic low V OL 0.1 × VDDI Output minimum source DC current I OH at VOH 0.1 Output minimum sink current I OL at VOL –0.1 1. To meet JEDEC Electrical Compliance, use LPDDR Full Drive Tra nsmitter. Table 143 • LPDDR DC Differential Voltage Specification Parameter Symbol Min DC input differential voltage V ID (DC) 0.4 × V DDI Table 144 • LPDDR AC Differential Voltage Specifications (for DDRIO I/O Bank Only) Parameter Symbol Min Max Unit AC input differential voltage V DIFF 0.6 × VDDI V AC differential cross point voltage V x 0.4 × VDDI 0.6 × VDDI V Table 145 • LPDDR AC Specifications (for DDRIO I/O Bank Only) Parameter Symbol Max Unit Conditions Maximum data rate D MAX 400 Mbps AC loading: per JEDEC specifications Table 146 • LPDDR AC Calibrated Impedance Option (for DDRIO I/O Bank Only) Parameter Symbol Typ Unit Conditions Supported output driver calibrated impedance R REF 20, 42  Reference resistor = 150  Effective impedance value (ODT) R TT 50, 70, 150  Reference resistor = 150  Table 147 • LPDDR AC Test Parameter Specifications (for DDRIO I/O Bank Only) Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 0.9 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F Reference resistance for data test path for LPDDR (TDP) RTT_TEST 50  Capacitive loading for data path (TDP)C LOAD 5 

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 53 AC Switching Characteristics Worst-case commercial conditions: TJ = 85 °C, VDD = 1.14 V, worst-case VDDI. Minimum and Maximum DC/AC Input and Output Levels Specification using LPDDR-LVCMOS

1.8 V Mode

Table 148 • LPDDR Receiver Characteristics for DDRIO I/O Bank with Fixed Codes On-Die Termination (ODT) TPY Unit–1 –Std Pseudo differential None 1.568 1.845 ns True differential None 1.588 1.869 ns Table 149 • LPDDR Reduced Drive for DDRIO I/O Bank (Output and Tristate Buffers) TDP TENZL TENZH TENHZ TENLZ Table 150 • LPDDR Full Drive for DDRIO I/O Bank (Output and Tristate Buffers) TDP TENZL TENZH TENHZ TENLZ Table 151 • LPDDR-LVCMOS 1.8 V Mode Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 1.710 1.8 1.89 V Table 152 • LPDDR-LVCMOS 1.8 V Mode DC Input Voltage Specification Parameter Symbol Min Max Unit DC input logic high (for MSIOD and DDRIO I/O banks) VIH (DC) 0.65 × V DDI 1.89 V DC input logic high (for MSIO I/O bank) V IH (DC) 0.65 × V DDI 3.45 V DC input logic low V IL (DC) –0.3 0.35 × V DDI V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 153 • LPDDR-LVCMOS 1.8 V Mode DC Output Voltage Specification Parameter Symbol Min Max Unit DC output logic high V OH VDDI – 0.45 V DC output logic low V OL 0.45 V

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 54 Table 154 • LPDDR-LVCMOS 1.8 V Minimum and Maximum AC Switching Speeds Parameter Symbol Max Unit Conditions Maximum data rate (for DDRIO I/O bank) D MAX 400 Mbps AC loading: 17pf load, 8 ma drive and above/all slew Table 155 • LPDDR-LVCMOS 1.8 V Calibrated Impedance Option Parameter Symbol Typ Unit Supported output driver calibrated impedance (for DDRIO I/O bank) RODT_CAL 75, 60, 50, 33, 25, 20  Table 156 • LPDDR-LVCMOS 1.8 V AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP 0.9 V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F Capacitive loading for data path (TDP) CLOAD 5p F Table 157 • LPDDR-LVCMOS 1.8 V Mode Transmitter Drive Strength Specification for DDRIO Bank Output Drive Selection VOH (V) Min VOL (V) Max I OH (at VOH) mA I OL (at VOL) mA 2 mA V DDI – 0.45 0.45 2 2 4 mA V DDI – 0.45 0.45 4 4 6 mA V DDI – 0.45 0.45 6 6 8 mA V DDI – 0.45 0.45 8 8 10 mA V DDI – 0.45 0.45 10 10 12 mA V DDI – 0.45 0.45 12 12 16 mA1 VDDI – 0.45 0.45 16 16 1. 16 mA Drive Strengths, All Slews, meet LPDDR JEDEC electrical compliance. Table 158 • LPDDR-LVCMOS 1.8V AC Switching Characteristics for Receiver (for DDRIO I/O Bank with Fixed Code - Input Buffers) ODT (On Die Termination) –1 –Std –1 –Std Unit None 1.968 2.315 2.099 2.47 ns Table 159 • LPDDR-LVCMOS 1.8 V AC Switching Characteristics for Transmitter for DDRIO I/O Bank (Output and Tristate Buffers) Output Drive Selection Slew Control TDP TZL TZH THZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 55

2.3.7 Differential I/O Standards

Configuration of the I/O modules as a differential pair is handled by Microsemi SoC Products Group Libero software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input register (InReg), Output register (OutReg), Enable register (EnReg), and Double Data Rate registers (DDR).

2.3.7.1 LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. Minimum and Maximum Input and Output Levels 1. Delay increases with drive strength are inherent to built-in slew control circuitry for simultaneous switching output (SSO) management). Table 160 • LVDS Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Conditions Supply voltage V DDI 2.375 2.5 2.625 V 2.5 V range Supply voltage V DDI 3.15 3.3 3.45 V 3.3 V range Table 159 • LPDDR-LVCMOS 1.8 V AC Switching Characteristics for Transmitter for DDRIO I/O Bank (Output and Tristate Buffers) (continued)

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 56 Table 161 • LVDS DC Input Voltage Specification Parameter Symbol Min Max Unit Conditions DC Input voltage V I 0 2.925 V 2.5 V range DC input voltage V I 0 3.45 V 3.3 V range Input current high1 IIH (DC) Input current low1 IIL (DC) 1. See Table 24, page 23. Table 162 • LVDS DC Output Voltage Specification Parameter Symbol Min Typ Max Unit DC output logic high V OH 1.25 1.425 1.6 V DC output logic low V OL 0.9 1.075 1.25 V Table 163 • LVDS DC Differential Voltage Specification1 Parameter Symbol Min Typ Max Unit Differential output voltage swing V OD 250 350 450 mV Output common mode voltage V OCM 1.125 1.25 1.375 V Input common mode voltage V ICM 0.05 1.25 2.35 V Input differential voltage V ID 100 350 600 mV 1. when V ID is < 300 mV, the input signal is delayed by up to an additional 450 ps for LVDS25 and 280 ps for LVDS33. This delay is not accounted in the timing model. Clock insertion delays, propagation delays, and I/O to FF delays are marginally affected. Adding a parallel termination resistor of 200 ohms +/- 5% across the receiver pins can mitigate this additional delay when VID is < 300 mV. Table 164 • LVDS Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for MSIO I/O bank) D MAX 535 Mbps AC loading: 12 pF / 100  differential load Maximum data rate (for MSIOD I/O bank) no pre-emphasis DMAX 620 Mbps AC loading: 10 pF / 100  differential load

700 Mbps AC loading: 2 pF / 100  differential load

Table 165 • LVDS AC Impedance Specifications Parameter Symbol Typ Max Unit Termination resistance RT 100  Table 166 • LVDS AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP Cross point V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 57 LVDS25 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V LVDS33 AC Switching Characteristics Table 167 • LVDS25 Receiver Characteristics for MSIO I/O Bank (Input Buffers) On-Die Termination (ODT) TPY Unit –1 –Std None 2.774 3.263 ns 100 2.775 3.264 ns Table 168 • LVDS25 Receiver Characteristics for MSIOD I/O Bank (Input Buffers) On-Die Termination (ODT) TPY Unit –1 –Std None 2.554 3.004 ns 100 2.549 2.999 ns Table 169 • LVDS25 Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) T DP TZL TZH THZ TLZ Table 170 • LVDS25 Transmitter Characteristics for MSIOD I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 171 • LVDS33 Receiver Characteristics for MSIO I/O Bank (Input Buffers) On Die Termination (ODT) TPY Unit–1 –Std None 2.572 3.025 ns 100 2.569 3.023 ns Table 172 • LVDS33 Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) TDP TZL TZH THZ TLZ

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 58

2.3.7.2 B-LVDS

Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Minimum and Maximum DC/AC Input and Output Levels Specification Table 173 • B-LVDS Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 2.375 2.5 2.625 V Table 174 • B-LVDS DC Input Voltage Specification Parameter Symbol Min Max Unit DC input voltage V I 02 . 9 2 5 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low1 IIL (DC) Table 175 • B-LVDS DC Output Voltage Specification (for MSIO I/O Bank Only) Parameter Symbol Min Typ Max Unit DC output logic high V OH 1.25 1.425 1.6 V DC output logic low V OL 0.9 1.075 1.25 V Table 176 • B-LVDS DC Differential Voltage Specification Parameter Symbol Min Max Unit Differential output voltage swing (for MSIO I/O bank only) V OD 65 460 mV Output common mode voltage (for MSIO I/O bank only) V OCM 1.1 1.5 V Input common mode voltage V ICM 0.05 2.4 V Input differential voltage V ID 0.1 V DDI V Table 177 • B-LVDS Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for MSIO I/O bank) D MAX 500 Mbps AC loading: 2 pF / 100  differential load Table 178 • B-LVDS AC Impedance Specifications Parameter Symbol Typ Unit Termination resistance R T 27  Table 179 • B-LVDS AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP Cross point V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ) C ENT 5p F

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 59 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.

2.3.7.3 M-LVDS

M-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Minimum and Maximum Input and Output Levels Table 180 • B-LVDS AC Switching Characteristics for Receiver for MSIO I/O Bank (Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std None 2.738 3.221 ns 100 2.735 3.218 ns Table 181 • B-LVDS AC Switching Characteristics for Receiver for MSIOD I/O Bank (Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std None 2.495 2.934 ns 100 2.495 2.935 ns Table 182 • B-LVDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 183 • M-LVDS Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage1 1. Only M-LVDS TYPE I is supported. VDDI 2.375 2.5 2.625 V Table 184 • M-LVDS DC Input Voltage Specification Parameter Symbol Min Max Unit DC input voltage V I 02 . 9 2 5 V Input current high1 1. See Table 24, page 23. IIH (DC) Input current low2 IIL (DC)

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 60 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V Table 185 • M-LVDS DC Voltage Specification Output Voltage Specification (for MSIO I/O Bank Only) Parameter Symbol Min Typ Max Unit DC output logic high V OH 1.25 1.425 1.6 V DC output logic low V OL 0.9 1.075 1.25 V Table 186 • M-LVDS Differential Voltage Specification Parameter Symbol Min Max Unit Differential output voltage swing (for MSIO I/O bank only) V OD 300 650 mV Output common mode voltage (for MSIO I/O bank only) V OCM 0.3 2.1 V Input common mode voltage V ICM 0.3 1.2 V Input differential voltage V ID 50 2400 mV Table 187 • M-LVDS Minimum and Maximum AC Switching Speed for MSIO I/O Bank Parameter Symbol Max Unit Conditions Maximum data rate D MAX 500 Mbps AC loading: 2 pF / 100  differential load Table 188 • M-LVDS AC Impedance Specifications Parameter Symbol Typ Unit Termination resistance R T 50  Table 189 • M-LVDS AC Test Parameter Specifications Parameter Sym bol Typ Unit Measuring/trip point for data path V TRIP Cross point V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5 pF Table 190 • M-LVDS AC Switching Characteristics for Receiver (for MSIO I/O Bank - Input Buffers) On-Die Termination (ODT) TPY Unit –1 –Std None 2.738 3.221 ns 100 2.735 3.218 ns Table 191 • M-LVDS AC Switching Characteristics for Receiver (for MSIOD I/O Bank - Input Buffers) On-Die Termination (ODT) TPY Unit –1 –Std None 2.495 2.934 ns 100 2.495 2.935 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 61

2.3.7.4 Mini-LVDS

Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed to the Texas Instruments Standard SLDA007A. Mini-LVDS Minimum and Maximum Input and Output Levels Table 192 • M-LVDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 193 • Mini-LVDS Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 2.375 2.5 2.625 V Table 194 • Mini-LVDS DC Input Voltage Specification Parameter Symbol Min Max Unit DC Input voltage V I 02 . 9 2 5 V Table 195 • Mini-LVDS DC Output Voltage Specification Parameter Symbol Min Typ Max Unit DC output logic high V OH 1.25 1.425 1.6 V DC output logic low V OL 0.9 1.075 1.25 V Table 196 • Mini-LVDS DC Differential Voltage Specification Parameter Symbol Min Max Unit Differential output voltage swing V OD 300 600 mV Output common mode voltage V OCM 1 1.4 V Input common mode voltage V ICM 0.3 1.2 V Input differential voltage V ID 100 600 mV Table 197 • Mini-LVDS Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for MSIO I/O bank) D MAX 520 Mbps AC loading: 2 pF / 100  differential load Maximum data rate (for MSIOD I/O bank) D MAX 700 Mbps AC loading: 2 pF / 100  differential load Table 198 • Mini-LVDS AC Impedance Specifications Parameter Symbol Typ Unit Termination resistance R T 100 

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 62 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V. Table 199 • Mini-LVDS AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP Cross point V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F Table 200 • Mini-LVDS AC Switching Characteristics for Receiver (for MSIO I/O Bank - Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std None 2.855 3.359 ns 100 2.85 3.353 ns None 2.602 3.061 ns 100 2.597 3.055 ns Table 201 • Mini-LVDS AC Switching Characteristics for Transmitter for MSIO I/O Bank (Output and Tristate Buffers) T DP TZL TZH THZ TLZ Unit Table 202 • Mini-LVDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and Tristate Buffers) T DP TZL TZH THZ TLZ Unit

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 63

2.3.7.5 RSDS

Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using differential signaling. RSDS has a similar implementation to LVDS devices and is only intended for point-to-point applications. Minimum and Maximum Input and Output Levels Table 203 • RSDS Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 2.375 2.5 2.625 V Table 204 • RSDS DC Input Voltage Specification Parameter Symbol Min Max Unit DC input voltage V I 02 . 9 2 5 V Table 205 • RSDS DC Output Voltage Specification Parameter Symbol Min Typ Max Unit DC output logic high V OH 1.25 1.425 1.6 V DC output logic low V OL 0.9 1.075 1.25 V Table 206 • RSDS Differential Voltage Specification Parameter Symbol Min Max Unit Differential output voltage swing V OD 100 600 mV Output common mode voltage V OCM 0.5 1.5 V Input common mode voltage V ICM 0.3 1.5 V Input differential voltage V ID 100 600 mV Table 207 • RSDS Minimum and Maximum AC Switching Speed Parameter Symbol Max Unit Conditions Maximum data rate (for MSIO I/O bank) D MAX 520 Mbps AC loading: 2 pF / 100  differential load Maximum data rate (for MSIOD I/O bank) D MAX 700 Mbps AC loading: 2 pF / 100  differential load Table 208 • RSDS AC Impedance Specifications Parameter Symbol Typ Unit Termination resistance RT 100  Table 209 • RSDS AC Test Parameter Specifications Parameter Symbol Typ Unit Measuring/trip point for data path V TRIP Cross point V Resistance for enable path (TZH, TZL, THZ, TLZ)R ENT 2K  Capacitive loading for enable path (TZH, TZL, THZ, TLZ)C ENT 5p F

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 64 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.

2.3.7.6 LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Similar to LVDS, two pins are needed. It also requires external resistor termination. IGLOO2 and SmartFusion2 SoC FPGAs support only LVPECL receivers and do not support LVPECL transmitters. Minimum and Maximum Input and Output Levels (Applicable to MSIO I/O Bank Only) Table 210 • RSDS AC Switching Characteristics for Receiver (for MSIO I/O Bank - Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std None 2.855 3.359 ns 100 2.85 3.353 ns Table 211 • RSDS AC Switching Characteristics for Receiver (for MSIOD I/O Bank - Input Buffers) On-Die Termination (ODT) TPY Unit–1 –Std None 2.602 3.061 ns 100 2.597 3.055 ns Table 212 • RSDS AC Switching Characteristics for Transmitter (for MSIO I/O Bank - Output and Tristate Buffers) T DP TZL TZH THZ TLZ Table 213 • RSDS AC Switching Characteristics for Transmitter (for MSIOD I/O Bank - Output and Tristate Buffers) TDP TZL TZH THZ TLZ Table 214 • LVPECL Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage V DDI 3.15 3.3 3.45 V Table 215 • LVPECL DC Input Voltage Specification Parameter Symbol Min Max Unit DC input voltage V I 03 . 4 5 V

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 65 AC Switching Characteristics Worst commercial-case conditions: TJ = 85 °C, VDD = 1.14 V, VDDI = 2.375 V.

2.3.8 I/O Register Specifications

This section describes input and output register specifications.

2.3.8.1 Input Register

Figure 6 • Timing Model for Input Register Table 216 • LVPECL DC Differential Voltage Specification Parameter Symbol Min Typ Max Unit Input common mode voltage V ICM 0.3 2.8 V Input differential voltage V IDIFF 100 300 1,000 mV Table 217 • LVPECL Minimum and Maximum AC Switching Speeds Parameter Symbol Max Unit Maximum data rate D MAX 900 Mbps Table 218 • LVPECL Receiver Characteristics for MSIO I/O Bank On-Die Termination (ODT) TPY Unit –1 –Std None 2.572 3.025 ns 100 2.569 3.023 ns SLE D EN ALn ADn SLn SD LAT CLK Q EN ALn ADn SLn SD LAT CLK Q D G A B C D E F Input I/O Buffer

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 66 Figure 7 • I/O Register Input Timing Diagram W,5(0$/Q &/. $/Q W,+'W,68' W,$/Q4 W,&/.4 $'Q W,5(&$/Q 6/Q W,+6/QW,686/Q W,68( W,+( W,:$/Q W,&.03:/ W,&.03:+

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 67 The following table lists the input data register propagation delays in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 219 • Input Data Register Propagation Delays Parameter Symbol Measuring Nodes (from, to)1 1. For the derating values at s pecific junction temperature and voltage supply levels, see Table 16, page 15 for derating values. –1 –Std Unit Bypass delay of the input register T IBYP F, G 0.353 0.415 ns Clock-to-Q of the input register T ICLKQ E, G 0.16 0.188 ns Data setup time for the input register T ISUD A, E 0.357 0.421 ns Data hold time for the input register T IHD A, E 0 0 ns Enable setup time for the input register T ISUE B, E 0.46 0.542 ns Enable hold time for the input register T IHE B, E 0 0 ns Synchronous load setup time for the input register T ISUSL D, E 0.46 0.542 ns Synchronous load hold time for the input register T IHSL D, E 0 0 ns Asynchronous clear-to-Q of the input register (ADn=1) T IALN2Q C, G 0.625 0.735 ns Asynchronous preset-to-Q of the input register (ADn=0) C, G 0.587 0.69 ns Asynchronous load removal time for the input register T IREMALN C, E 0 0 ns Asynchronous load recovery time for the input register T IRECALN C, E 0.074 0.087 ns Asynchronous load minimum pulse width for the input register T IWALN C, C 0.304 0.357 ns Clock minimum pulse width high for the input register T ICKMPWH E, E 0.075 0.088 ns Clock minimum pulse width low for the input register T ICKMPWL E, E 0.159 0.187 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 68

2.3.8.2 Output/Enable Register

Figure 8 • Timing Model for Output/Enable Register SLE D EN ALn ADn SLn SD LAT CLK Q SLE D EN ALn ADn SLn SD LAT CLK Q Output/Enable Registers EN ALn ADn SLn SD LAT CLK D G A B C D E F IH Output I/O Buffer with Enable Control D2 J

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 69 Figure 9 • I/O Register Output Timing Diagram The following table lists the output/enable propagation delays in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 220 • Output/Enable Data Register Propagation Delays Parameter Symbol Measuring Nodes (from, to)1 1. For the derating values at specific junction temperature and voltage supply levels, see Table 16, page 15 for derating values. –1 –Std Unit Bypass delay of the output/enable register T OBYP F, G or H, I 0.353 0.415 ns Clock-to-Q of the output/enable register T OCLKQ E, G or E, I 0.263 0.309 ns Data setup time for the output/enable register T OSUD A, E or J, E 0.19 0.223 ns Data hold time for the output/enable register T OHD A, E or J, E 0 0 ns Enable setup time for the output/enable register T OSUE B, E 0.419 0.493 ns Enable hold time for the output/enable register T OHE B, E 0 0 ns Synchronous load setup time for the output/enable register T OSUSL D, E 0.196 0.231 ns Synchronous load hold time for the output/enable register T OHSL D, E 0 0 ns Asynchronous clear-to-q of the output/enable register (ADn = 1) TOALN2Q C, G or C, I 0.505 0.594 ns Asynchronous preset-to-q of the output/enable register (ADn = 0) C , G or C, I 0.528 0.621 ns Asynchronous load removal time for the output/enable register T OREMALN C, E 0 0 ns Asynchronous load recovery time for the output/enable register T ORECALN C, E 0.034 0.04 ns Asynchronous load minimum pulse width for the output/enable register TOWALN C, C 0.304 0.357 ns Clock minimum pulse width high for the output/enable register T OCKMPWH E, E 0.075 0.088 ns Clock minimum pulse width low for the output/enable register T OCKMPWL E, E 0.159 0.187 ns C W25(0$/Q W2+' W268' W2&/.4 &ON $/Q 2XW W2$/Q4 $'Q 6/Q W268( W2+'( W2686/Q W2+'6/Q W2&.03:/ W2&.03:+ W25(&$/Q

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 70

2.3.9 DDR Module Specification

This section describes input and output DDR module and timing specifications.

2.3.9.1 Input DDR Module

Figure 10 • Input DDR Module SLE D EN ALn ADn SLn SD LAT CLK Q SLE D EN ALn ADn SLn SD LAT CLK Q QR QF DDR_IN Latch D ALn ADn CLK Q D EN ALn ADn SLn SD LAT CLK A B C D E F G

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 71

2.3.9.2 Input DDR Timing Diagram

Figure 11 • Input DDR Timing Diagram

2.3.9.3 Timing Characteristics

The following table lists the input DDR propagation delays in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 221 • Input DDR Propagation Delays Symbol Description Measuring Nodes (from, to) –1 –Std Unit TDDRICLKQ1 Clock-to-Out Out_QR for input DDR B, C 0.16 0.188 ns TDDRICLKQ2 Clock-to-Out Out_QF for input DDR B, D 0.166 0.195 ns TDDRISUD Data setup for input DDR A, B 0.357 0.421 ns TDDRIHD Data hold for input DDR A, B 0 0 ns TDDRISUE Enable setup for input DDR E, B 0.46 0.542 ns TDDRIHE Enable hold for input DDR E, B 0 0 ns TDDRISUSLN Synchronous load setup for input DDR G, B 0.46 0.542 ns TDDRIHSLN Synchronous load hold for input DDR G, B 0 0 ns TDDRIAL2Q1 Asynchronous load-to-out QR for input DDR F, C 0.587 0.69 ns TDDRIAL2Q2 Asynchronous load-to-out QF for input DDR F, D 0.541 0.636 ns TDDRIREMAL Asynchronous load removal time for input DDR F, B 0 0 ns TDDRIRECAL Asynchronous load recovery time for input DDR F, B 0.074 0.087 ns W''5,$/4 W''5,5(0$/ &/. $/Q W''5,+'W''5,68' W''5,&/.4 W''5,$/4 W''5,&/.4 $'Q W''5,5(&$/ 6/Q W''5,68( W''5,+( W''5,:$/

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 72 TDDRIWAL Asynchronous load minimum pulse width for input DDR F, F 0.304 0.357 ns TDDRICKMPWH Clock minimum pulse width high for input DDR B, B 0.075 0.088 ns TDDRICKMPWL Clock minimum pulse width low for input DDR B, B 0.159 0.187 ns Table 221 • Input DDR Propagation Delays (continued) Symbol Description Measuring Nodes (from, to) –1 –Std Unit

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 73

2.3.9.4 Output DDR Module

Figure 12 • Output DDR Module SLE D EN ALn ADn SLn SD LAT CLK Q SLE D EN ALn ADn SLn SD LAT CLK Q QR QF DDR _ OUT EN ALn ADn SLn SD LAT CLK Q DR DF G A B C D E F

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 74 Figure 13 • Output DDR Timing Diagram

2.3.9.5 Timing Characteristics

The following table lists the output DDR propagation delays in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 222 • Output DDR Propagation Delays Symbol Description Measuring Nodes (from, to) –1 –Std Unit TDDROCLKQ Clock-to-out of DDR for output DDR E, G 0.263 0.309 ns TDDROSUDF Data_F data setup for output DDR F, E 0.143 0.168 ns TDDROSUDR Data_R data setup for output DDR A, E 0.19 0.223 ns TDDROHDF Data_F data hold for output DDR F, E 0 0 ns TDDROHDR Data_R data hold for output DDR A, E 0 0 ns TDDROSUE Enable setup for input DDR B, E 0.419 0.493 ns TDDROHE Enable hold for input DDR B, E 0 0 ns TDDROSUSLN Synchronous load setup for input DDR D, E 0.196 0.231 ns TDDROHSLN Synchronous load hold for input DDR D, E 0 0 ns TDDROAL2Q Asynchronous load-to-out for output DDR C, G 0.528 0.621 ns TDDROREMAL Asynchronous load removal time for output DDR C, E 0 0 ns TDDRORECAL Asynchronous load recovery time for output DDR C, E 0.034 0.04 ns C W''525(0$ W''52+'5 W''5268'5 W''52+')W''5268') W''52&/.4 W''525(&$/ &ON $/Q 2XW W''52$/4 $'Q 6/Q W''5268( W''52+'( W''52:$/

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 75

2.3.10 Logic Element Specifications

2.3.10.1 4-input LUT (LUT-4) The IGLOO2 and SmartFusion2 SoC FPGAs offer a fully permutable 4-input LUT. In this section, timing characteristics are presented for a sample of the library. For more details, see SmartFusion2 and IGLOO2 Macro Library Guide. Figure 14 • LUT-4 TDDROWAL Asynchronous load minimum pulse width for output DDR C, C 0.304 0.357 ns TDDROCKMPWH Clock minimum pulse width high for the output DDR E, E 0.075 0.088 ns TDDROCKMPWL Clock minimum pulse width low for the output DDR E, E 0.159 0.187 n s Table 222 • Output DDR Propagation Delays (continued) Symbol Description Measuring Nodes (from, to) –1 –Std Unit TPD PAD A B Y PAD PAD PAD D/S (whereapplicable) AND4 OR Any Combinational Logic PAD C TPD TPD VDD VDD VDD TPD TPD (RR) A, B, C, D, S OUT 50% GND (FF) 50% 50%50% GND (RF) 50% TPD = Max(tPD(RR), TPD(RF), TPD(FF), TPD(FR)) where edges are applicable for the particular combinatorial cell (FR) 50% OUT GND

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 76

2.3.10.2 Timing Characteristics

The following table lists the combinatorial cell propagation delays in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.

2.3.10.3 Sequ ential Module

IGLOO2 and SmartFusion2 SoC FPGAs offer a separate flip-flop which can be used independently from the LUT. The flip-flop can be configured as a register or a latch and has a data input and optional enable, synchronous load (clear or preset), and asynchronous load (clear or preset). Figure 15 • Sequential Module Table 223 • Combinatorial Cell Propagation Delays Combinatorial Cell Equation Symbol –1 –Std Unit INV Y = !A T PD 0.1 0.118 ns AND2 Y = A · B T PD 0.164 0.193 ns NAND2 Y = !(A · B) T PD 0.147 0.173 ns OR2 Y = A + B T PD 0.164 0.193 ns NOR2 Y = !(A + B) T PD 0.147 0.173 ns XOR2 Y = A  B T PD 0.164 0.193 ns XOR3 Y = A  B  C T PD 0.225 0.265 ns AND3 Y = A · B · C T PD 0.209 0.246 ns AND4 Y = A · B · C · D T PD 0.287 0.338 ns SLE D EN ALn ADn SLn SD LAT CLK Q

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 77 The following figure shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous clear) for a flip-flop (LAT = 0). Figure 16 • Sequential Module Timing Diagram

2.3.10.3.1 Timing Characteristics

The following table lists the register delays in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 224 • Register Delays Parameter Symbol –1 –Std Unit Clock-to-Q of the core register T CLKQ 0.108 0.127 ns Data setup time for the core register T SUD 0.254 0.298 ns Data hold time for the core register T HD 00 n s Enable setup time for the core register T SUE 0.335 0.394 ns Enable hold time for the core register T HE 00 n s Synchronous load setup time for the core register T SUSL 0.335 0.394 ns Synchronous load hold time for the core register T HSL 00 n s Asynchronous Clear-to-Q of the core register (ADn = 1) TALN2Q 0.473 0.556 ns Asynchronous preset-to-Q of the core register (ADn = 0) 0.451 0.531 ns Asynchronous load removal time for the core register T REMALN 00 n s Asynchronous load recovery time for the core register T RECALN 0.353 0.415 ns Asynchronous load minimum pulse width for the core register T WALN 0.266 0.313 ns Clock minimum pulse width high for the core register T CKMPWH 0.065 0.077 ns Clock minimum pulse width low for the core register T CKMPWL 0.139 0.164 ns $/Q &/. W68( W68' W+' W&/.4 W+( W686/ W+6/ W5(0$/Q W:$/Q W$/Q4 W&.03:+ W&.03:/ $'Q W5(&$/Q

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 78

2.3.11 Global Resource Characteristics

The IGLOO2 and SmartFusion2 SoC FPGA devices offer a powerful, low skew global routing network which provides an effective clock distribution throughout the FPGA fabric. See UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for the positions of various global routing resources. The following table lists the 150 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the 090 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the 050 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the 025 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 225 • 150 Device Global Resource Parameter Symbol –1 –Std UnitMin Max Min Max Input low delay for global clock T RCKL 0.83 0.911 0.831 0.913 ns Input high delay for global clock T RCKH 1.457 1.588 1.715 1.869 ns Maximum skew for global clock T RCKSW 0.131 0.154 ns Table 226 • 090 Device Global Resource Parameter Symbol –1 –Std UnitMin Max Min Max Input low delay for global clock T RCKL 0.835 0.888 0.833 0.886 ns Input high delay for global clock T RCKH 1.405 1.489 1.654 1.752 ns Maximum skew for global clock T RCKSW 0.084 0.098 ns Table 227 • 050 Device Global Resource Parameter Symbol –1 –Std UnitMin Max Min Max Input low delay for global clock T RCKL 0.827 0.897 0.826 0.896 ns Input high delay for global clock T RCKH 1.419 1.53 1.671 1.8 ns Maximum skew for global clock T RCKSW 0.111 0.129 ns Table 228 • 025 Device Global Resource Parameter Symbol –1 –Std UnitM i nM a x M i nM a x Input low delay for global clock T RCKL 0.747 0.799 0.745 0.797 ns Input high delay for global clock T RCKH 1.294 1.378 1.522 1.621 ns Maximum skew for global clock T RCKSW 0.084 0.099 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 79 The following table lists the 010 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the 005 device global resources in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.

2.3.12 FPGA Fabric SRAM

See UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for more information.

2.3.12.1 FPGA Fabric Large SRAM (LSRAM)

The following table lists the RAM1K18 – dual-port mode for depth × width configuration 1K × 18 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 229 • 010 Device Global Resource Parameter Symbol –1 –Std UnitMin Max Min Max Input low delay for global clock T RCKL 0.626 0.669 0.627 0.668 ns Input high delay for global clock T RCKH 1.112 1.182 1.308 1.393 ns Maximum skew for global clock T RCKSW 0.07 0.085 ns Table 230 • 005 Device Global Resource Parameter Symbol –1 –Std UnitMin Max Min Max Input low delay for global clock T RCKL 0.625 0.66 0.628 0.66 ns Input high delay for global clock T RCKH 1.126 1.187 1.325 1.397 ns Maximum skew for global clock T RCKSW 0.061 0.072 ns Table 231 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1K × 18 Parameter Symbol –1 –Std UnitMin Max Min Max Clock period T CY 2.5 2.941 ns Clock minimum pulse width high T CLKMPWH 1.125 1.323 ns Clock minimum pulse width low T CLKMPWL 1.125 1.323 ns Pipelined clock period T PLCY 2.5 2.941 ns Pipelined clock minimum pulse width high T PLCLKMPWH 1.125 1.323 ns Pipelined clock minimum pulse width low T PLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.334 0.393 ns Read access time without pipeline register 2.273 2.674 ns Access time with feed-through write timing 1.529 1.799 ns Address setup time T ADDRSU 0.441 0.519 ns Address hold time T ADDRHD 0.274 0.322 ns Data setup time T DSU 0.341 0.401 ns Data hold time T DHD 0.107 0.126 ns Block select setup time T BLKSU 0.207 0.244 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 80 The following table lists the RAM1K18 – dual-port mode for depth × width configuration 2K × 9 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Block select hold time T BLKHD 0.216 0.254 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 1.529 1.799 ns Block select minimum pulse width T BLKMPW 0.186 0.219 ns Read enable setup time T RDESU 0.449 0.528 ns Read enable hold time T RDEHD 0.167 0.197 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay T R2Q – 1.506 – 1.772 ns Asynchronous reset removal time T RSTREM 0.506 0.595 ns Asynchronous reset recovery time T RSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width T RSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time T PLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time T PLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width TPLRSTMPW 0.282 0.332 ns Synchronous reset setup time T SRSTSU 0.226 0.265 ns Synchronous reset hold time T SRSTHD 0.036 0.043 ns Write enable setup time T WESU 0.39 0.458 ns Write enable hold time T WEHD 0.242 0.285 ns Maximum frequency F MAX 400 340 MHz Table 232 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2K × 9 Parameter Symbol –1 –Std UnitMin Max Min Max Clock period T CY 2.5 2.941 ns Clock minimum pulse width high T CLKMPWH 1.125 1.323 ns Clock minimum pulse width low T CLKMPWL 1.125 1.323 ns Pipelined clock period T PLCY 2.5 2.941 ns Pipelined clock minimum pulse width high T PLCLKMPWH 1.125 1.323 ns Pipelined clock minimum pulse width low T PLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.334 0.393 ns Read access time without pipeline register 2.273 2.674 ns Access time with feed-through write timing 1.529 1.799 ns Table 231 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1K × 18 (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 81 The following table lists the RAM1K18 – dual-port mode for depth × width configuration 4K × 4 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Address setup time T ADDRSU 0.475 0.559 ns Address hold time T ADDRHD 0.274 0.322 ns Data setup time T DSU 0.336 0.395 ns Data hold time T DHD 0.082 0.096 ns Block select setup time T BLKSU 0.207 0.244 ns Block select hold time T BLKHD 0.216 0.254 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 1.529 1.799 ns Block select minimum pulse width T BLKMPW 0.186 0.219 ns Read enable setup time T RDESU 0.485 0.57 ns Read enable hold time T RDEHD 0.071 0.083 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay T R2Q 1.514 1.781 ns Asynchronous reset removal time T RSTREM 0.506 0.595 ns Asynchronous reset recovery time T RSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width T RSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time T PLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time T PLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width T PLRSTMPW 0.282 0.332 ns Synchronous reset setup time T SRSTSU 0.226 0.265 ns Synchronous reset hold time T SRSTHD 0.036 0.043 ns Write enable setup time T WESU 0.415 0.488 ns Write enable hold time T WEHD 0.048 0.057 ns Maximum frequency F MAX 400 340 MHz Table 233 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4K × 4 Parameter Symbol –1 –Std UnitMin Max Min Max Clock period T CY 2.5 2.941 ns Clock minimum pulse width high T CLKMPWH 1.125 1.323 ns Clock minimum pulse width low T CLKMPWL 1.125 1.323 ns Pipelined clock period T PLCY 2.5 2.941 ns Pipelined clock minimum pulse width high T PLCLKMPWH 1.125 1.323 ns Table 232 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2K × 9 (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 82 Pipelined clock minimum pulse width low T PLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.323 0.38 ns Read access time without pipeline register 2.273 2.673 ns Access time with feed-through write timing 1.511 1.778 ns Address setup time T ADDRSU 0.543 0.638 ns Address hold time T ADDRHD 0.274 0.322 ns Data setup time T DSU 0.334 0.393 ns Data hold time T DHD 0.082 0.096 ns Block select setup time T BLKSU 0.207 0.244 ns Block select hold time T BLKHD 0.216 0.254 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 1.511 1.778 ns Block select minimum pulse width T BLKMPW 0.186 0.219 ns Read enable setup time T RDESU 0.516 0.607 ns Read enable hold time T RDEHD 0.071 0.083 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay T R2Q 1.507 1.773 ns Asynchronous reset removal time T RSTREM 0.506 0.595 ns Asynchronous reset recovery time T RSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width T RSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time T PLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time T PLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width TPLRSTMPW 0.282 0.332 ns Synchronous reset setup time T SRSTSU 0.226 0.265 ns Synchronous reset hold time T SRSTHD 0.036 0.043 ns Write enable setup time T WESU 0.458 0.539 ns Write enable hold time T WEHD 0.048 0.057 ns Maximum frequency F MAX 400 340 MHz Table 233 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4K × 4 (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 83 The following table lists the RAM1K18 – dual-port mode for depth × width configuration 8K × 2 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 234 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8K × 2 Parameter Symbol –1 –Std UnitMin Max Min Max Clock period T CY 2.5 2.941 ns Clock minimum pulse width high T CLKMPWH 1.125 1.323 ns Clock minimum pulse width low T CLKMPWL 1.125 1.323 ns Pipelined clock period T PLCY 2.5 2.941 ns Pipelined clock minimum pulse width high T PLCLKMPWH 1.125 1.323 ns Pipelined clock minimum pulse width low T PLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.32 0.377 ns Read access time without pipeline register 2.272 2.673 ns Access time with feed-through write timing 1.511 1.778 ns Address setup time T ADDRSU 0.612 0.72 ns Address hold time T ADDRHD 0.274 0.322 ns Data setup time T DSU 0.33 0.388 ns Data hold time T DHD 0.082 0.096 ns Block select setup time T BLKSU 0.207 0.244 ns Block select hold time T BLKHD 0.216 0.254 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 1.511 1.778 ns Block select minimum pulse width T BLKMPW 0.186 0.219 ns Read enable setup time T RDESU 0.529 0.622 ns Read enable hold time T RDEHD 0.071 0.083 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) TRDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay T R2Q 1.528 1.797 ns Asynchronous reset removal time T RSTREM 0.506 0.595 ns Asynchronous reset recovery time T RSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width T RSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time T PLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time T PLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width T PLRSTMPW 0.282 0.332 ns Synchronous reset setup time T SRSTSU 0.226 0.265 ns Synchronous reset hold time T SRSTHD 0.036 0.043 ns Write enable setup time T WESU 0.488 0.574 ns Write enable hold time T WEHD 0.048 0.057 ns Maximum frequency F MAX 400 340 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 84 The following table lists the RAM1K18 – dual-port mode for depth × width configuration 16K × 1 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 235 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16K × 1 Parameter Symbol –1 –Std UnitMin Max Min Max Clock period T CY 2.5 2.941 ns Clock minimum pulse width high T CLKMPWH 1.125 1.323 ns Clock minimum pulse width low T CLKMPWL 1.125 1.323 ns Pipelined clock period T PLCY 2.5 2.941 ns Pipelined clock minimum pulse width high T PLCLKMPWH 1.125 1.323 ns Pipelined clock minimum pulse width low T PLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.32 0.377 ns Read access time without pipeline register 2.269 2.669 ns Access time with feed-through write timing 1.51 1.777 ns Address setup time T ADDRSU 0.626 0.737 ns Address hold time T ADDRHD 0.274 0.322 ns Data setup time T DSU 0.322 0.378 ns Data hold time T DHD 0.082 0.096 ns Block select setup time T BLKSU 0.207 0.244 ns Block select hold time T BLKHD 0.216 0.254 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 1.51 1.777 ns Block select minimum pulse width T BLKMPW 0.186 0.219 ns Read enable setup time T RDESU 0.53 0.624 ns Read enable hold time T RDEHD 0.071 0.083 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) T RDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay T R2Q 1.547 1.82 ns Asynchronous reset removal time T RSTREM 0.506 0.595 ns Asynchronous reset recovery time T RSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width T RSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time T PLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time T PLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width T PLRSTMPW 0.282 0.332 ns Synchronous reset setup time T SRSTSU 0.226 0.265 ns Synchronous reset hold time T SRSTHD 0.036 0.043 ns Write enable setup time T WESU 0.454 0.534 ns Write enable hold time T WEHD 0.048 0.057 ns Maximum frequency F MAX 400 340 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 85 The following table lists the RAM1K18 – two-port mode for depth × width configuration 512 × 36 in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 236 • RAM1K18 – Two-Port Mode for Depth × Width Configuration 512 × 36 Parameter Symbol –1 –Std UnitMin Max Min Max Clock period T CY 2.5 2.941 ns Clock minimum pulse width high T CLKMPWH 1.125 1.323 ns Clock minimum pulse width low T CLKMPWL 1.125 1.323 ns Pipelined clock period T PLCY 2.5 2.941 ns Pipelined clock minimum pulse width high T PLCLKMPWH 1.125 1.323 ns Pipelined clock minimum pulse width low T PLCLKMPWL 1.125 1.323 ns Read access time with pipeline register TCLK2Q 0.334 0.393 ns Read access time without pipeline register 2.25 2.647 ns Address setup time T ADDRSU 0.313 0.368 ns Address hold time T ADDRHD 0.274 0.322 ns Data setup time T DSU 0.337 0.396 ns Data hold time T DHD 0.111 0.13 ns Block select setup time T BLKSU 0.207 0.244 ns Block select hold time T BLKHD 0.201 0.237 ns Block select to out disable time (when pipelined register is disabled) TBLK2Q 2.25 2.647 ns Block select minimum pulse width T BLKMPW 0.186 0.219 ns Read enable setup time T RDESU 0.449 0.528 ns Read enable hold time T RDEHD 0.167 0.197 ns Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) TRDPLESU 0.248 0.291 ns Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) T RDPLEHD 0.102 0.12 ns Asynchronous reset to output propagation delay T R2Q 1.506 1.772 ns Asynchronous reset removal time T RSTREM 0.506 0.595 ns Asynchronous reset recovery time T RSTREC 0.004 0.005 ns Asynchronous reset minimum pulse width T RSTMPW 0.301 0.354 ns Pipelined register asynchronous reset removal time T PLRSTREM –0.279 –0.328 ns Pipelined register asynchronous reset recovery time T PLRSTREC 0.327 0.385 ns Pipelined register asynchronous reset minimum pulse width T PLRSTMPW 0.282 0.332 ns Synchronous reset setup time T SRSTSU 0.226 0.265 ns Synchronous reset hold time T SRSTHD 0.036 0.043 ns Write enable setup time T WESU 0.39 0.458 ns Write enable hold time T WEHD 0.242 0.285 ns Maximum frequency F MAX 400 340 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 86

2.3.12.2 FPGA Fabric Micro SRAM (µSRAM)

The following table lists the µSRAM in 64 × 18 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 237 • µSRAM (RAM64x18) in 64 × 18 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.266 0.313 ns Read access time without pipeline register 1.677 1.973 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.856 2.184 ns Read address hold time in synchronous mode TADDRHD 0.091 0.107 ns Read address hold time in asynchronous mode –0.778 –0.915 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.765 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.036 2.396 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.023 –0.027 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.839 0.987 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.115 0.135 ns Write input data hold time T DINCHD 0.15 0.177 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 87 The following table lists the µSRAM in 64 × 16 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Write address setup time T ADDRCSU 0.088 0.104 ns Write address hold time T ADDRCHD 0.128 0.15 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.026 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 238 • µSRAM (RAM64x16) in 64 × 16 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.266 0.313 ns Read access time without pipeline register 1.677 1.973 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.856 2.184 ns Read address hold time in synchronous mode TADDRHD 0.091 0.107 ns Read address hold time in asynchronous mode –0.778 –0.915 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.765 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.036 2.396 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.023 –0.027 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.835 0.983 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Table 237 • µSRAM (RAM64x18) in 64 × 18 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 88 The following table lists the µSRAM in 128 × 9 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.115 0.135 ns Write input data hold time T DINCHD 0.15 0.177 ns Write address setup time T ADDRCSU 0.088 0.104 ns Write address hold time T ADDRCHD 0.128 0.15 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.026 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 239 • µSRAM (RAM128x9) in 128 × 9 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.266 0.313 ns Read access time without pipeline register 1.677 1.973 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.856 2.184 ns Read address hold time in synchronous mode TADDRHD 0.091 0.107 ns Read address hold time in asynchronous mode –0.778 –0.915 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.765 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.036 2.396 ns Table 238 • µSRAM (RAM64x16) in 64 × 16 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 89 The following table lists the µSRAM in 128 × 8 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Read asynchronous reset removal time (pipelined clock) TRSTREM –0.023 –0.027 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.835 0.982 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.115 0.135 ns Write input data hold time T DINCHD 0.15 0.177 ns Write address setup time T ADDRCSU 0.088 0.104 ns Write address hold time T ADDRCHD 0.128 0.15 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.026 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 240 • µSRAM (RAM128x8) in 128 × 8 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.266 0.313 ns Read access time without pipeline register 1.677 1.973 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.856 2.184 ns Table 239 • µSRAM (RAM128x9) in 128 × 9 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 90 Read address hold time in synchronous mode TADDRHD 0.091 0.107 ns Read address hold time in asynchronous mode –0.778 –0.915 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.765 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.036 2.396 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.023 –0.027 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.835 0.982 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.115 0.135 ns Write input data hold time T DINCHD 0.15 0.177 ns Write address setup time T ADDRCSU 0.088 0.104 ns Write address hold time T ADDRCHD 0.128 0.15 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.026 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 240 • µSRAM (RAM128x8) in 128 × 8 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 91 The following table lists the µSRAM in 256 × 4 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 241 • µSRAM (RAM256x4) in 256 × 4 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.27 0.31 ns Read access time without pipeline register 1.75 2.06 ns Read address setup time in synchronous mode T ADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.931 2.272 ns Read address hold time in synchronous mode TADDRHD 0.121 0.142 ns Read address hold time in asynchronous mode –0.65 –0.76 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.77 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.09 2.46 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.02 –0.03 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.83 0.98 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.101 0.118 ns Write input data hold time T DINCHD 0.137 0.161 ns Write address setup time T ADDRCSU 0.088 0.104 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 92 The following table lists the µSRAM in 512 × 2 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Write address hold time T ADDRCHD 0.245 0.288 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.03 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 242 • µSRAM (RAM512x2) in 512 × 2 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.27 0.31 ns Read access time without pipeline register 1.76 2.08 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.96 2.306 ns Read address hold time in synchronous mode TADDRHD 0.137 0.161 ns Read address hold time in asynchronous mode –0.58 –0.68 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.77 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.14 2.52 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.02 –0.03 ns Read asynchronous reset removal time (non-pipelined clock) 0.046 0.054 ns Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.236 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.83 0.98 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Table 241 • µSRAM (RAM256x4) in 256 × 4 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 93 The following table lists the µSRAM in 1024 × 1 mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.101 0.118 ns Write input data hold time T DINCHD 0.137 0.161 ns Write address setup time T ADDRCSU 0.088 0.104 ns Write address hold time T ADDRCHD 0.247 0.29 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.03 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 243 • µSRAM (RAM1024x1) in 1024 × 1 Mode Parameter Symbol –1 –Std UnitMin Max Min Max Read clock period T CY 44 n s Read clock minimum pulse width high T CLKMPWH 1.8 1.8 ns Read clock minimum pulse width low T CLKMPWL 1.8 1.8 ns Read pipeline clock period T PLCY 44 n s Read pipeline clock minimum pulse width high T PLCLKMPWH 1.8 1.8 ns Read pipeline clock minimum pulse width low T PLCLKMPWL 1.8 1.8 ns Read access time with pipeline register TCLK2Q 0.27 0.31 ns Read access time without pipeline register 1.78 2.1 ns Read address setup time in synchronous mode TADDRSU 0.301 0.354 ns Read address setup time in asynchronous mode 1.978 2.327 ns Read address hold time in synchronous mode TADDRHD 0.137 0.161 ns Read address hold time in asynchronous mode –0.6 –0.71 ns Read enable setup time T RDENSU 0.278 0.327 ns Read enable hold time T RDENHD 0.057 0.067 ns Read block select setup time T BLKSU 1.839 2.163 ns Read block select hold time T BLKHD –0.65 –0.77 ns Read block select to out disable time (when pipelined register is disabled) TBLK2Q 2.16 2.54 ns Read asynchronous reset removal time (pipelined clock) TRSTREM –0.02 –0.03 ns Read asynchronous reset removal time (non-pipelined clock) 0.04 6 0.054 ns Table 242 • µSRAM (RAM512x2) in 512 × 2 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 94

2.3.13 Programming Times

The following tables list the programming times in typical conditions when TJ = 25 °C, VDD = 1.2 V. External SPI flash part# AT25DF641-s3H is used during this measurement. Read asynchronous reset recovery time (pipelined clock) TRSTREC 0.507 0.597 ns Read asynchronous reset recovery time (non-pipelined clock) 0.2 36 0.278 ns Read asynchronous reset to output propagation delay (with pipelined register enabled) TR2Q 0.83 0.98 ns Read synchronous reset setup time T SRSTSU 0.271 0.319 ns Read synchronous reset hold time T SRSTHD 0.061 0.071 ns Write clock period T CCY 44 n s Write clock minimum pulse width high T CCLKMPWH 1.8 1.8 ns Write clock minimum pulse width low T CCLKMPWL 1.8 1.8 ns Write block setup time T BLKCSU 0.404 0.476 ns Write block hold time T BLKCHD 0.007 0.008 ns Write input data setup time T DINCSU 0.003 0.004 ns Write input data hold time T DINCHD 0.137 0.161 ns Write address setup time T ADDRCSU 0.088 0.104 ns Write address hold time T ADDRCHD 0.247 0.29 ns Write enable setup time T WECSU 0.397 0.467 ns Write enable hold time T WECHD –0.03 –0.03 ns Maximum frequency F MAX 250 250 MHz Table 244 • JTAG Programming (Fabric Only) M2S/M2GL Device Image size Bytes Program Verify Unit 005 302672 22 10 Sec 010 568784 28 18 Sec 025 1223504 51 26 Sec 050 2424832 66 54 Sec 060 2418896 77 54 Sec 090 3645968 113 126 Sec 150 6139184 155 193 Sec Table 243 • µSRAM (RAM1024x1) in 1024 × 1 Mode (continued) Parameter Symbol –1 –Std UnitMin Max Min Max

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 95 Table 245 • JTAG Programming (eNVM Only) M2S/M2GL Device Image size Bytes Program Verify Unit 005 137536 39 4 Sec 010 274816 78 9 Sec 025 274816 78 9 Sec 050 278528 84 8 Sec 060 268480 76 8 Sec 090 544496 154 15 Sec 150 544496 155 15 Sec Table 246 • JTAG Programming (Fabric and eNVM) M2S/M2GL Device Image size Bytes Program Verify Unit 005 439296 59 11 Sec 010 842688 107 20 Sec 025 1497408 120 35 Sec 050 2695168 162 59 Sec 060 2686464 158 70 Sec 090 4190208 266 147 Sec 150 6682768 316 231 Sec Table 247 • 2 Step IAP Programming (Fabric Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 302672 4 17 6 Sec 010 568784 7 23 12 Sec 025 1223504 14 33 23 Sec 050 2424832 29 52 40 Sec 060 2418896 39 61 50 Sec 090 3645968 60 84 73 Sec 150 6139184 100 132 120 Sec

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 96 Table 248 • 2 Step IAP Programming (eNVM Only) M2S/M2GL Device Image size Bytes Auth enticate Program Verify Unit 005 137536 2 37 5 Sec 010 274816 4 76 11 Sec 025 274816 4 78 10 Sec 050 278528 3 85 9 Sec 060 268480 5 76 22 Sec 090 544496 10 152 43 Sec 150 544496 10 153 44 Sec Table 249 • 2 Step IAP Programming (Fabric and eNVM) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 439296 6 56 11 Sec 010 842688 11 100 21 Sec 025 1497408 19 113 32 Sec 050 2695168 32 136 48 Sec 060 2686464 43 137 70 Sec 090 4190208 68 236 115 Sec 150 6682768 109 286 162 Sec Table 250 • SmartFusion2 Cortex-M3 ISP Programming (Fabric Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 302672 6 19 8 Sec 010 568784 10 26 14 Sec 025 1223504 21 39 29 Sec 050 2424832 39 60 50 Sec 060 2418896 44 65 54 Sec 090 3645968 66 90 79 Sec 150 6139184 108 140 128 Sec Table 251 • SmartFusion2 Cortex-M3 ISP Programming (eNVM Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 137536 3 42 4 Sec 010 274816 4 82 7 Sec 025 274816 4 82 8 Sec 050 278528 4 80 8 Sec 060 268480 6 80 8 Sec 090 544496 10 157 15 Sec

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 97 150 544496 10 158 15 Sec Table 252 • SmartFusion2 Cortex-M3 ISP Programming (Fabric and eNVM) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 439296 9 61 11 Sec 010 842688 15 107 21 Sec 025 1497408 26 121 35 Sec 050 2695168 43 141 55 Sec 060 2686464 48 143 60 Sec 090 4190208 75 244 91 Sec 150 6682768 117 296 141 Sec Table 253 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (Fabric Only) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit 100 kHz 25 MHz 12.5 MHz 005 47 27 28 Sec 010 77 35 35 Sec 025 150 42 41 Sec 050 33

1 Not Supported Not Supported Sec

Auto Programming in 050 device is done through SC_SPI, and SP I CLK is set to 6.25 MHz. Table 254 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (eNVM Only) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit 100 kHz 25 MHz 12.5 MHz 005 41 48 49 Sec 010 86 87 87 Sec 025 87 85 86 Sec 050 85 Not Supported Not Supported Sec 060 78 86 86 Sec 090 154 162 162 Sec Table 251 • SmartFusion2 Cortex-M3 ISP Programming (eNVM Only) (continued) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 98 150 161 161 161 Sec Table 255 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (Fabric and eNVM) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit100 kHz 25 MHz 12.5 MHz 005 47 27 28 Sec 010 77 35 35 Sec 025 150 42 41 Sec 050 33 050 85 Not Supported Not Supported Sec 060 78 86 86 Sec 090 154 162 162 Sec 150 161 161 161 Sec 005 87 67 66 Sec 010 161 113 113 Sec 025 229 120 121 Sec 050 112 Not Supported Not Supported Sec 060 368 161 158 Sec 090 582 261 260 Sec 150 867 309 310 Sec 1. Auto Programming in 050 device is done through SC_SPI, and SP I CLK is set to 6.25 MHz. Table 254 • Programming Times with 100 kHz, 25 MHz, and 12.5 MHz SPI Clock Rates (eNVM Only) (continued) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit 100 kHz 25 MHz 12.5 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 99 The following table lists the programming times in worst-case conditions when TJ = 100 °C, VDD = 1.14 V. External SPI flash part# AT25DF641-s3H is used during this measurement. Table 256 • JTAG Programming (Fabric Only) M2S/M2GL Device Image size Bytes Program Verify Unit 005 302672 44 10 Sec 010 568784 50 18 Sec 025 1223504 73 26 Sec 050 2424832 88 54 Sec 060 2418896 99 54 Sec 090 3645968 135 126 Sec 150 6139184 177 193 Sec Table 257 • JTAG Programming (eNVM Only) M2S/M2GL Device Image size Bytes Program Verify Unit 005 137536 61 4 Sec 010 274816 100 9 Sec 025 274816 100 9 Sec 050 2,78,528 106 8 Sec 060 268480 98 8 Sec 090 544496 176 15 Sec 150 544496 177 15 Sec Table 258 • JTAG Programming (Fabric and eNVM) M2S/M2GL Device Image size Bytes Program Verify Unit 005 439296 71 11 Sec 010 842688 129 20 Sec 025 1497408 142 35 Sec 050 2695168 184 59 Sec 060 2686464 180 70 Sec 090 4190208 288 147 Sec 150 6682768 338 231 Sec

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 100 Table 259 • 2 Step IAP Programming (Fabric Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 302672 4 39 6 Sec 010 568784 7 45 12 Sec 025 1223504 14 55 23 Sec 050 2424832 29 74 40 Sec 060 2418896 39 83 50 Sec 090 3645968 60 106 73 Sec 150 6139184 100 154 120 Sec Table 260 • 2 Step IAP Programming (eNVM Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 137536 2 59 5 Sec 010 274816 4 98 11 Sec 025 274816 4 100 10 Sec 050 2,78,528 3 107 9 Sec 060 268480 5 98 22 Sec 090 544496 10 174 43 Sec 150 544496 10 175 44 Sec Table 261 • 2 Step IAP Programming (Fabric and eNVM) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 439296 6 78 11 Sec 010 842688 11 122 21 Sec 025 1497408 19 135 32 Sec 050 2695168 32 158 48 Sec 060 2686464 43 159 70 Sec 090 4190208 68 258 115 Sec 150 6682768 109 308 162 Sec

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 101 Table 262 • SmartFusion2 Cortex-M3 ISP Programming (Fabric Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 302672 6 41 8 Sec 010 568784 10 48 14 Sec 025 1223504 21 61 29 Sec 050 2424832 39 82 50 Sec 060 2418896 44 87 54 Sec 090 3645968 66 112 79 Sec 150 6139184 108 162 128 Sec Table 263 • SmartFusion2 Cortex-M3 ISP Programming (eNVM Only) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 137536 3 64 4 Sec 010 274816 4 104 7 Sec 025 274816 4 104 8 Sec 050 2,78,528 4 102 8 Sec 060 268480 6 102 8 Sec 090 544496 10 179 15 Sec 150 544496 10 180 15 Sec Table 264 • SmartFusion2 Cortex-M3 ISP Programming (Fabric and eNVM) M2S/M2GL Device Image size Bytes Authenticate Program Verify Unit 005 439296 9 83 11 Sec 010 842688 15 129 21 Sec 025 1497408 26 143 35 Sec 050 2695168 43 163 55 Sec 060 2686464 48 165 60 Sec 090 4190208 75 266 91 Sec 150 6682768 117 318 141 Sec

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 102 Table 265 • Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric Only) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit 100 kHz 25 MHz 12.5 MHz 005 69 49 50 Sec 010 99 57 57 Sec 025 150 64 63 Sec 050 55

Auto programming in 050 device is done through SC_SPI, and SP I CLK is set to 6.25 MHz. Table 266 • Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (eNVM Only) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit 100 kHz 25 MHz 12.5 MHz 005 63 70 71 Sec 010 108 109 109 Sec 025 109 107 108 Sec 050 107 Not Supported Not Supported Sec 060 100 108 108 Sec 090 176 184 184 Sec 150 183 183 183 Sec Table 267 • Programming Times with 100 kHz, 25 MHz. and 12.5 MHz SPI Clock Rates (Fabric and eNVM) M2S/M2GL Device Auto Programming Auto Update Programming Recovery Unit 100 kHz 25 MHz 12.5 MHz 005 109 89 88 Sec 010 183 135 135 Sec 025 251 142 143 Sec 050 134 Not Supported Not Supported Sec 060 390 183 180 Sec 090 604 283 282 Sec 150 889 331 332 Sec

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 103

2.3.14 Math Block Timing Characteristics

The fundamental building block in any digital signal processing algorithm is the multiply-accumulate function. Each IGLOO2 and SmartFusion2 SoC math block supports 18×18 signed multiplication, dot product, and built-in addition, subtraction, and accumulation units to combine multiplication results efficiently. The following table lists the math blocks with all registers used in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the math blocks with input bypassed and output registers used in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. Table 268 • Math Blocks with all Registers Used Parameter Symbol –1 –Std UnitMin Max Min Max Input, control register setup time T MISU 0.149 0.176 ns Input, control register hold time T MIHD 1.68 1.976 ns CDIN input setup time T MOCDINSU 0.185 0.218 ns CDIN input hold time T MOCDINHD 0.08 0.094 ns Synchronous reset/enable setup time TMSRSTENSU –0.419 –0.493 ns Synchronous reset/enable hold time T MSRSTENHD 0.011 0.013 ns Asynchronous reset removal time T MARSTREM 00n s Asynchronous reset recovery time T MARSTREC 0.088 0.104 ns Output register clock to out delay T MOCQ 0.232 0.273 ns CLK minimum period T MCLKMP 2.245 2.641 ns Table 269 • Math Block with Input Bypassed and Output Registers Used Parameter Symbol –1 –Std UnitM i nM a x M i nM a x Output register setup time T MOSU 2.294 2.699 ns Output register hold time T MOHD 1.68 1.976 ns CDIN input setup time T MOCDINSU 0.115 0.136 ns CDIN input hold time T MOCDINHD –0.444 –0.522 ns Synchronous reset/enable setup time TMSRSTENSU –0.419 –0.493 ns Synchronous reset/enable hold time T MSRSTENHD 0.011 0.013 ns Asynchronous reset removal time T MARSTREM 00n s Asynchronous reset recovery time T MARSTREC 0.014 0.017 ns Output register clock to out delay T MOCQ 0.232 0.273 ns CLK minimum period T MCLKMP 2.179 2.563 ns

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 104 The following table lists the math blocks with input register used and output in bypass mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V. The following table lists the math blocks with input and output in bypass mode in worst commercial-case conditions when TJ = 85 °C, VDD = 1.14 V.

2.3.15 Embedded NVM (eNVM) Characteristics

The following table lists the eNVM read performance in worst-case conditions when VDD = 1.14 V, VPPNVM = VPP = 2.375 V. The following table lists the eNVM page programming in worst-case conditions when VDD = 1.14 V, VPPNVM = VPP = 2.375 V. Table 270 • Math Block with Input Register Used and Output in Bypass Mode Parameter Symbol –1 –Std UnitMin Max Min Max Input register setup time T MISU 0.149 0.176 ns Input register hold time T MIHD 0.185 0.218 ns Synchronous reset/enable setup time TMSRSTENSU 0.08 0.094 ns Synchronous reset/enable hold time T MSRSTENHD –0.012 –0.014 ns Asynchronous reset removal time T MARSTREM –0.005 –0.005 ns Asynchronous reset recovery time T MARSTREC 0.088 0.104 ns Input register clock to output delay T MICQ 2.52 2.964 ns CDIN to output delay T MCDIN2Q 1.951 2.295 ns Table 271 • Math Block with Input and Output in Bypass Mode Parameter Symbol –1 –Std UnitMax Max Input to output delay T MIQ 2.568 3.022 ns CDIN to output delay T MCDIN2Q 1.951 2.295 ns Table 272 • eNVM Read Performance Symbol Description Operating Temperature Range TJ Junction temperature range –55 °C to 125 °C –40 ° C to 100 °C 0 °C to 85 °C °C FMAXREAD eNVM maximum read frequency 25 25 25 25 25 25 MHz Table 273 • eNVM Page Programming Symbol Description Operating Temperature Range TJ Junction temperature range –55 °C to 125 °C –40 °C to 100 °C 0 °C to 85 °C °C TPAGEPGM eNVM page programming time 40 40 40 40 40 40 ms

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 105

2.3.16 SRAM PUF

For more details on static random-access memory (SRAM) physical unclonable functions (PUF) services, see AC434: Using SRAM PUF System Service in SmartFusion2 Application Note. The following table lists the SRAM PUF in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 274 • SRAM PUF Service PUF Off PUF On UnitTyp Max Typ Max Create activation code 709.1 746.4 754.4 762.5 ms Delete activation code 1329.3 1399.3 1414.1 1429.3 ms Create intrinsic keycode 656.6 691.1 698.5 706.0 ms Create extrinsic keycode 656.6 691.1 698.5 706.0 ms Get number of keys 1.3 1.4 1.4 1.4 ms Export (Kc0, Kc1) 998.0 1050.5 1061.7 1073.1 ms Export 2 keycodes 2020.2 2126.5 2149.2 2172.3 ms Export 4 keycodes 3065.7 3227.0 3261.3 3296.4 ms Export 8 keycodes 5101.0 5369.5 5426.6 5485.0 ms Export 16 keycodes 9212.1 9697.0 9800.1 9905.5 ms Import (Kc0, Kc1) 39.7 41.8 42.2 42.7 ms Import 2 keycodes 50.1 52.7 53.3 53.9 ms Import 4 keycodes 60.6 63.8 64.5 65.2 ms Import 8 keycodes 80.9 85.1 86.1 87.0 ms Import 16 keycodes 123.8 130.4 131.7 133.2 ms Delete keycode 552.5 581.6 587.8 594.1 ms Fetch key 31.4 33.0 33.4 33.7 ms Fetch ecc key 20. 0 21.1 21.3 21.5 ms Get seed 2.0 2.1 2.2 2.2 ms

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 106

2.3.17 Non-Deterministic Random Bit Generator (NRBG)

For more information about NRBG, see AC407: Using NRBG Services in SmartFusion2 and IGLOO2 Devices Application Note. The following table lists the NRBG in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.18 Cryptographic Block Characteristics

For more information about cryptographic block and associated services, see AC410: Using AES System Services in SmartFusion2 and IGLOO2 Devices Application Note and AC432: Using SHA-256 System Services in SmartFusion2 and IGLOO2 Devices Application Note. The following table lists the cryptographic block characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 275 • Non-Deterministic Random Bit Generator (NRBG) Service Timing Unit Conditions Prediction Resistance Additional Input Instantiate 85 ms OFF X Generate (after Instantiate)1 1. If PUF_OFF, generate will incur additional PUF delay time for consecutive service calls. 4.5 ms + (6.25 us/byte x No. of Bytes) OFF 0 6.0 ms + (6.25 us/byte x No. of Bytes) OFF 64 7.0 ms + (6.25 us/byte x No. of Bytes) OFF 128 Generate (after Instantiate) 47 ms ON X Generate (subsequent) 0.5 ms + (6.25 us/byte x No. of Bytes) OFF 0 2.0 ms + (6.25 us/byte x No. of Bytes) OFF 64 3.0 ms + (6.25 us/byte x No. of Bytes) OFF 128 Generate (subsequent) 43 ms ON X Reseed 40 ms Uninstantiate 0.16 ms Reset 0.10 ms Self test 20 ms First time after power-up 6 ms Subsequent Table 276 • Cryptographic Block Characteristics Service Conditions Timing Unit Any service First certificate check penalty at boot 11.5 ms AES128/256 (encoding / decoding)1 100 blocks up to 64k blocks 700 kbps

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 107

2.3.19 Crystal Oscillator

The following table describes the electrical characteristics of the crystal oscillator in the IGLOO2 FPGA and SmartFusion2 SoC FPGAs. SHA256 512 bits 540 kbps 1024 bits 780 kbps 2048 bits 950 kbps 24 kbits 1140 kbps HMAC 512 bytes 820 kbps 1024 bytes 890 kbps 2048 bytes 930 kbps 24 kbytes 980 kbps KeyTree 1.8 ms Challenge-response PUF = OFF 25 ms PUF = ON 7 ms ECC point multiplication 590 ms ECC point addition 8 ms 1. Using cypher block chaining (CBC) mode. Table 277 • Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz) Parameter Symbol Min Typ M a x U n i t C o n d i t i o n Operating frequency FXTAL 20 MHz Accuracy ACCXTAL 0.0047 % 005, 010, 025, 050, 060, and 090 devices 0.0058 % 150 devices Output duty cycle CYCXTAL 49–51 47–53 % Output period jitter (peak to peak) JITPERXTAL 200 300 ps Output cycle to cycle jitter (peak to peak) JITCYCXTAL 200 300 ps 010, 025, 050, and 060 devices 250 410 ps 150 devices 250 550 ps 005 and 090 devices Operating current IDYNXTA L 1.5 mA 010, 050, and 060 devices 1.65 mA 005, 025, 090, and 150 devices Input logic level high VIHXTAL 0.9 V PP V Input logic level low VILXTAL 0.1 V PP V Table 276 • Cryptographic Block Characteristics (continued) Service Conditions Timing Unit

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 108 Startup time (with regard to stable oscillator output) SUXTAL 0.8 ms 005, 010, 025, and 050 devices 1.0 ms 090 and 150 devices Table 278 • Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz) Parameter Symbol Min Typ Max Unit Condition Operating frequency FXTAL 2 MHz Accuracy ACCXTAL 0.00105 % 050 devices 0.003 % 005, 010, 025, 090, and 150 devices 0.004 % 060 devices Output duty cycle CYCXTAL 49–51 47–53 % Output period jitter (peak to peak) JITPERXTAL 1 5 ns Output cycle to cycle jitter (peak to peak) JITCYCXTAL 1 5 ns Operating current IDYNXTAL 0.3 mA Input logic level high VIHXTAL 0.9 V PP V Input logic level low VILXTAL 0.1 V PP V Startup time (with regard to stable oscillator output) SUXTAL 4.5 ms 010 and 050 devices 5 ms 005 and 025 devices 7 ms 090 and 150 devices Table 279 • Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz) Parameter Symbol Min Typ Max Unit Condition Operating frequency FXTAL 32 kHz Accuracy ACCXTAL 0.004 % 005, 010, 025, 050, 060, and 090 devices 0.005 % 150 devices Output duty cycle CYCXTAL 49–51 47–53 % Output period jitter (peak to peak) JITPERXTAL 150 300 ns Output cycle to cycle jitter (peak to peak) JITCYCXTAL 150 300 ns Operating current IDYNXTAL 0 .044 mA 010 and 050 devices 0.060 mA 005, 025, 060, 090, and 150 devices Input logic level high VIHXTAL 0.9 V PP V Input logic level low VILXTAL 0.1 V PP V Startup time (with regard to stable oscillator output) SUXTAL 115 ms 005, 025, 050, 090, and 150 devices 126 ms 010 devices Table 277 • Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz) (continued) Parameter Symbol Min Typ M a x U n i t C o n d i t i o n

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 109

2.3.20 On-Chip Oscillator

The following tables describe the electrical characteristics of the available on-chip oscillators in the IGLOO2 FPGAs and SmartFusion2 SoC FPGAs. Table 280 • Electrical Characteristics of the 50 MHz RC Oscillator Parameter Symbol Typ Max Unit Condition Operating frequency F50RC 50 MHz Accuracy ACC50RC 1 4 % 050 devices 1 5 % 005, 025, and 060 devices 1 6.3 % 090 devices 1 7.1 % 010 and 150 devices Output duty cycle CYC50RC 49–51 46.5–53.5 % Output jitter (peak to peak) JIT50RC Period Jitter 200 300 ps 005, 010, 050, and 060 devices 200 400 ps 150 devices 300 500 ps 025 and 090 devices Cycle-to-Cycle Jitter 200 300 ps 005 and 050 devices 320 420 ps 010, 060, and 150 devices 320 850 ps 025 and 090 devices Operating current IDYN50RC 6.5 mA Table 281 • Electrical Characteristics of the 1 MHz RC Oscillator Parameter Symbol Typ Max Unit Condition Operating frequency F1RC 1 MHz Accuracy ACC1RC 1 3 % 005, 010, 025, and 050 devices 1 4.5 % 060, and 150 devices 1 5.6 % 090 devices Output duty cycle CYC1RC 49–51 46.5–53.5 % 005, 010, 025, 050, 090 and 150 devices 49-51 46.0-54.0 % 060 devices Output jitter (peak to peak) JIT1RC Period Jitter 10 20 ns 005, 010, 025, and 050 devices 10 28 ns 060, 090 and 150 devices Cycle-to-Cycle Jitter 10 20 ns 005, 010, and 050 devices 10 35 ns 025, 060, and 150 devices 10 45 ns 090 devices Operating current IDYN1RC 0.1 mA Startup time SU1RC 17 µs 050, 090, and 150 devices 18 µs 005, 010, and 025 devices

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 110

2.3.21 Clock Conditioning Circuits (CCC)

The following table lists the CCC/PLL specifications in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 282 • IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Specification Parameter Min Typ Max Unit Conditions Clock conditioning circuitry input frequency FIN_CCC 1 200 MHz All CCC 0.032 200 MHz 32 kHz capable CCC Clock conditioning circuitry output frequency FOUT_CCC 0.078 400 MHz PLL VCO frequency2 500 1000 MHz Delay increments in programmable delay blocks 75 100 ps Number of programmable values in each programmable delay block Acquisition time 70 100 µs F IN >= 1 MHz 11 6 m s F IN = 32 kHz Input duty cycle (reference clock) Internal Feedback 10 90 % 1 MHz ≤ F IN_CCC ≤ 25 MHz 25 75 % 25 MHz ≤ F IN_CCC≤ 100 MHz 35 65 % 100 MHz ≤ F IN_CCC ≤ 150 MHz 45 55 % 150 MHz ≤ F IN_CCC ≤ 200 MHz External Feedback (CCC, FPGA, Off-chip) 25 75 % 1 MHz ≤ F IN_CCC ≤ 25 MHz 35 65 % 25 MHz ≤ F IN_CCC ≤ 35 MHz 45 55 % 35 MHz ≤ F IN_CCC ≤ 50 MHz Output duty cycle 48 52 % 050 devices F OUT ≤ 400 MHz 48 52 % 005, 010, and 025 devices FOUT < 350 MHz 46 54 % 005, 010, and 025 devices

350 MHz ≤ Fout ≤ 400 MHz

48 52 % 060 and 090 devices FOUT ≤ 100 MHz 44 52 % 060 and 090 devices

100 MHz ≤ FOUT ≤ 400 MHz

48 52 % 150 devices FOUT ≤ 120 MHz 45 52 % 150 devices

120 MHz ≤ FOUT ≤ 400 MHz

Spread Spectrum Characteristics Modulation frequency range 25 35 50 k Modulation depth range 0 1.5 % Modulation depth control 0.5 %

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 111 The following table lists the CCC/PLL jitter specifications in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.22 JTAG

The minimum output clock frequen cy is limited by the PLL. For more information, see UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide. 2. The PLL is used in conjuncti on with the Clock Conditioning Circuitry. Performance is limited by the CCC output frequency. Table 283 • IGLOO2 and SmartFusion2 SoC FPGAs CCC/PLL Jitter Specifications CCC Output Maximum Peak-to-Peak Period Jitter FOUT_CCC Parameter Conditions/Package Combinations Unit

10 FG484, 050

SSO = 0 0 < SSO <= 2 SSO < = 4 SSO <= 8 SSO <= 16

20 MHz to 100 MHz Max(110, ± 1% x

(1/FOUT_CCC)) Max(150, ± 1% x (1/FOUT_CCC)) ps

100 MHz to 400 MHz Max(120, ± 1% x

(1/FOUT_CCC)) Max(150, ± 1% x (1/FOUT_CCC)) Max(170, ± 1% x (1/FOUT_CCC)) ps

025 FG484/FCS325

0 < SSO <=16

20 MHz to 74 MHz ± 1% x (1/F OUT_CCC)) ps

74 MHz to 400 MHz 210 ps

005 FG484 Package1 0 < SSO <=16

20 MHz to 53 MHz ± 1% x (1/F OUT_CCC)) ps

53 MHz to 400 MHz 270 ps

090 FG676 and FC325

0 < SSO <=16

20 MHz to 100 MHz ± 1% x (1/F OUT_CCC)) ps

100 MHz to 400 MHz 150 ps

060 FG676 Package1

SSO data is based on LVCMOS 2.5 V MSIO and/or MSIOD bank I/Os. 0 < SSO <=16

20 MHz to 100 MHz ± 1% x (1/F OUT_CCC)p s

100 MHz to 400 MHz 150

150 FC1152 Package1 0 < SSO <=16

100 MHz to 400 MHz 120 ps

Table 284 • JTAG 1532 for 005, 010, 025, and 050 Devices Parameter Symbol 005 010 025 050 Unit Clock to Q (data out) Reset to Q (data out)

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 112 Test data input setup time Test data input hold time Test mode select setup time TTMSSU Test mode select hold time TTMDHD ResetB removal time ResetB recovery time TCK maximum frequency F TCKMAX Table 285 • JTAG 1532 for 060, 090, and 150 Devices Parameter Symbol 060 090 150 Test data input setup time Test data input hold time Test mode select setup time Test mode select hold time TCK maximum frequency FTCKMAX 25 21.25 25 21.25 25 21.25 MHz Table 284 • JTAG 1532 for 005, 010, 025, and 050 Devices (continued) Parameter Symbol 005 010 025 050 Unit

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 113

2.3.23 System Controller SPI Characteristics

The following table lists the system controller characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 286 • System Controller SPI Characteristics for All Devices Symbol Description Conditions Min Typ Unit sp1 SC_SPI_SCK minimum period 20 ns sp2 SC_SPI_SCK minimum pulse width high 10 ns sp3 SC_SPI_SCK minimum pulse width low 10 ns sp4 1. For specific Rise/Fall Times , board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. Use the supported I/O Configurations for the System Controller SPI in the following table. SC_SPI_SCK, SC_SPI_SDO, SC_SPI_SS rise time (10%–90%) 1 I/O configuration: LVTTL 3.3 V– 20 mA AC loading: 35 pF Test conditions: Typical voltage, 25 °C 1.239 ns sp5

1 SC_SPI_SCK, SC_SPI_SDO,

SC_SPI_SS fall time (10%–90%) 1 I/O configuration: LVTTL 3.3 V– 20 mA AC loading: 35 pF Test conditions: Typical voltage, 25 °C 1.245 ns sp6 SC_SPI_SDO setup time 160 ns sp7 SC_SPI_SDO hold time 160 ns sp8 SC_SPI_SDI setup time 20 ns sp9 SC_SPI_SDI hold time 20 ns Table 287 • Supported I/O Configurations for System Controller SPI (for MSIO Bank Only) Voltage Supply I/O Drive Configuration Unit

3.3 V 20 mA

2.5 V 16 mA

1.8 V 12 mA

1.5 V 8 mA

1.2 V 4 mA

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 114

2.3.24 Power-up to Functional Times

The following table lists power-up to functional times in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Note: For more information about power-up times, see UG0331: SmartFusion2 Microcontroller Subsystem User Guide and UG0448: IGLOO2 FPGA High Performance Memory Subsystem User Guide. Table 288 • Power-up to Functional Times When MSS/HPMS is Used Symbol From To Description Maximum Power-up to Functional Time (uS) 005 010 025 050 060 090 150 TPOR2OUT POWER_ON _RESET_N Output available at I/O Fabric to output 647 500 531 483 474 524 647 T POR2MSSRST POWER_ON _RESET_N MSS_RESE T_N_M2F Fabric to MSS 644 497 528 480 468 518 641 TMSSRST2OUT MSS_RESET _N_M2F Output available at I/O MSS to output TVDD2OUT VDD Output available at I/O VDD at its minimum threshold level to output 3096 2975 3012 2959 2869 2992 3225 T VDD2POR VDD POWER_O N_RESET_ N VDD at its minimum threshold level to fabric 2476 2487 2496 2486 2406 2563 2602 T VDD2MSSRST VDD MSS_RESE T_N_M2F VDD at its minimum threshold level to MSS 3093 2972 3008 2956 2864 2987 3220 T VDD2WPU DEVRST_N DDRIO Inbuf weak pull DEVRST_N to Inbuf weak pull 2500 2487 2509 2475 2507 2519 2617 DEVRST_N MSIO Inbuf weak pull DEVRST_N to Inbuf weak pull 2504 2491 2510 2478 2517 2525 2620 DEVRST_N MSIOD Inbuf weak pull DEVRST_N to Inbuf weak pull 2479 2468 2493 2458 2486 2499 2595

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 115 Figure 17 • Power-up to Functional Timing Diagram for SmartFusion2 The following table lists power-up to functional times in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Note: For more information about power-up times, see UG0448: IGLOO2 FPGA High Performance Memory Subsystem User Guide and UG0331: SmartFusion2 Microcontroller Subsystem User Guide. Table 289 • Power-up to Functional Times When MSS/HPMS is not Used Symbol From To Description Maximum Power-up to Functional Time (uS) 005 010 025 050 060 090 150 TPOR2OUT POWER_ON _RESET_N Output available at I/O Fabric to output 114 114 114 113 114 114 114 T VDD2OUT VDD Output available at I/O VDD at its minimum threshold level to output 2587 2600 2607 2558 2591 2600 2699 TVDD2POR VDD POWER_ON_ RESET_N VDD at its minimum threshold level to fabric 2474 2486 2493 2445 2477 2486 2585 T VDD2WPU DEVRST_N D DRIO Inbuf weak pull DEVRST_N to Inbuf weak pull 2500 2487 2509 2475 2507 2519 2617 DEVRST_N MSIO Inbuf weak pull DEVRST_N to Inbuf weak pull 2504 2491 2510 2478 2517 2525 2620 DEVRST_N MSIOD Inbuf weak pull DEVRST_N to Inbuf weak pull 2479 2468 2493 2458 2486 2499 2595 '(9567B1 9339'',[ 9'' ,1%8) ,1%8):($.38// 06,206,2'''5,2 32:(5B21B5(6(7B1 066B5(6(7B1B0) 287%8) 79''325 79''066567 79''287 7325066567 7325287 7066567287 5&26&B0+] +LJK= +LJK= 7ULVWDWH 7ULVWDWH 79'':38

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 116 Figure 18 • Power-up to Functional Timing Diagram for IGLOO2

2.3.25 DEVRST_N Characteristics

2.3.26 DEVRST_N to Functional Times

The following table lists the DEVRST_N to functional times in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 290 • DEVRST_N Characteristics for All Devices Parameter Symbol Max Unit DEVRST_N ramp time T RAMPDEVRSTN 1u s DEVRST_N cycling rate F MAXPDEVRSTN 100 kHz Table 291 • DEVRST_N to Functional Times When MSS/HPMS is Used Symbol From To Description Maximum Power-up to Functional Time (uS) 005 010 025 050 060 090 150 TPOR2OUT POWER_ON _RESET_N Output available at I/O Fabric to output 518 501 527 521 422 419 694 TPOR2MSSRST POWER_ON _RESET_N MSS_RESE T_N_M2F Fabric to MSS 515 497 524 518 417 414 689 TMSSRST2OUT MSS_RESET _N_M2F Output available at I/O MSS to output T DEVRST2OUT DEVRST_N Output available at I/O VDD at its minimum threshold level to output 706 768 715 691 641 635 871 '(9567B1 9339'',[ 9'' ,1%8) ,1%8):($.38// 06,206,2'''5,2 32:(5B21B5(6(7B1 287%8) 79''325 79''287 7325287 5&26&B0+] +LJK= +LJK= 7ULVWDWH 7ULVWDWH 79'':38

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 117 Figure 19 • DEVRST_N to Functional Timing Diagram for SmartFusion2 TDEVRST2POR DEVRST_N POWER_O N_RESET_ N VDD at its minimum threshold level to fabric 233 289 216 213 237 234 219 T DEVRST2MSSRST DEVRST_N MSS_RESE T_N_M2F VDD at its minimum threshold level to MSS 702 765 712 688 636 630 866 TDEVRST2WPU DEVRST_N DDRIO Inbuf weak pull DEVRST_N to Inbuf weak pull 208 202 197 193 216 215 215 DEVRST_N MSIO Inbuf weak pull DEVRST_N to Inbuf weak pull 208 202 197 193 216 215 215 DEVRST_N MSIOD Inbuf weak pull DEVRST_N to Inbuf weak pull 208 202 197 193 216 215 215 Table 291 • DEVRST_N to Functional Times When MSS/HPMS is Used (continued) Symbol From To Description Maximum Power-up to Functional Time (uS) 005 010 025 050 060 090 150 9''9339'',[ 5&26&B0+] '(9567B1 ,1%8) ,1%8):($.38// 06,206,2'''5,2 32:(5B21B5(6(7B1 066B5(6(7B1B0) 287%8) 7'(9567325 7'(9567066567 7'(9567287 +LJK= 7ULVWDWH +LJK= 7ULVWDWH 7325066567 7066567287 7325287

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 118 Figure 20 • DEVRST_N to Functional Timing Diagram for IGLOO2 The following table lists the DEVRST_N to functional times in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 292 • DEVRST_N to Functional Times When MSS/HPMS is not Used Symbol From To Description Maximum Power-up to Functional Time (uS) 005 010 025 050 060 090 150 TPOR2OUT POWER_ON _RESET_N Output available at I/O Fabric to output 114 116 113 113 115 115 114 T DEVRST2OUT DEVRST_N Output available at I/O VDD at its minimum threshold level to output 314 353 314 307 343 341 341 T DEVRST2POR DEVRST_N POWER_O N_RESET_ N VDD at its minimum threshold level to fabric 200 238 201 195 230 229 227 T DEVRST2WPU DEVRST_N DDRIO Inbuf weak pull DEVRST_N to Inbuf weak pull 208 202 197 193 216 215 215 DEVRST_N MSIO Inbuf weak pull DEVRST_N to Inbuf weak pull 208 202 197 193 216 215 215 DEVRST_N MSIOD Inbuf weak pull DEVRST_N to Inbuf weak pull 208 202 197 193 216 215 215 9''9339'',[ 5&26&B0+] '(9567B1 ,1%8) ,1%8):($.38// 06,206,2'''5,2 32:(5B21B5(6(7B1 287%8) +LJK= 7ULVWDWH +LJK= 7ULVWDWH 7'(9567325 7'(9567287 7325287

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 119

2.3.27 Flash*Freeze Timing Characteristics

The following table lists the Flash*Freeze entry and exit times in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.28 DDR Memory Interface Characteristics

The following table lists the DDR memory interface characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 293 • Flash*Freeze Entry and Exit Times Parameter Symbol Entry/Exit Timing FCLK = 100MHz Entry/Exit Timing FCLK = 3 MHz Unit Conditions 005, 010, 025, 060, 090, and 150 050 All Devices Entry time TFF_ENTRY 160 150 320 μs eNVM and MSS/HPMS PLL = ON 215 200 430 μs eNVM and MSS/HPMS PLL= OFF Exit time with respect to the MSS PLL Lock TFF_EXIT 100 100 140 μs eNVM and MSS/HPMS PLL = ON during F*F 136 120 190 μs eNVM = ON and MSS/HPMS PLL = OFF during F*F and MSS/HPMS PLL turned back on at exit 200 200 285 μs eNVM and MSS/HPMS PLL = OFF during F*F and both are turned back on at exit 200 200 285 μs eNVM = OFF and MSS/HPMS PLL = ON during F*F and eNVM turned back on at exit Exit time with respect to the fabric PLL lock 1. PLL Lock Delay set to 1024 cycles (default). TFF_EXIT 1.5 1.5 1.5 ms eNVM and MSS/HPMS PLL = ON during F*F 1.5 1.5 1.5 ms eNVM and MSS/HPMS PLL = OFF during F*F and both are turned back on at exit Exit time with respect to the fabric buffer output TFF_EXIT 21 15 21 μs eNVM and MSS/HPMS PLL = ON during F*F 65 55 65 μs eNVM and MSS/HPMS PLL = OFF during F*F and both are turned back on at exit Table 294 • DDR Memory Interface Characteristics Standard Supported Data Rate UnitMin Max DDR3 667 667 Mbps DDR2 667 667 Mbps

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 120

2.3.29 SFP Transceiver Characteristics

IGLOO2 and SmartFusion2 SerDes complies with small form-factor pluggable (SFP) requirements as specified in SFP INF-80741. The following table provides the electrical characteristics. The following table lists the SFP transceiver electrical characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.30 SerDes Electrical and Timing AC and DC Characteristics

PCIe is a high-speed, packet-based, point-to-point, low-pin-count, serial interconnect bus. The IGLOO2 and SmartFusion2 SoC FPGAs has up to four hard high-speed serial interface blocks. Each SerDes block contains a PCIe system block. The PCIe system is connected to the SerDes block. The following table lists the transmitter parameters in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. LPDDR 50 400 Mbps Table 295 • SFP Transceiver Electrical Characteristics Pin Direction Differential Peak-Peak Voltage UnitMin Max RD+/-1 1. Based on default SerDes transmitter settings for PCIe Gen1. Lower amplitudes are available through programming changes to TX_AMP setting. Output 1600 2400 mV TD+/-2 2. Based on Input Voltage Common-Mode (VICM) = 0 V. Requires AC C oupling. Input 350 2400 mV Table 296 • Transmitter Parameters Symbol Description Min Max Unit VTX-DIFF-PP Differential swing (2.5 Gbps, 5.0 Gbps) 0.8 1.2 V VTX-CM-AC-P Output common mo de voltage (2.5 Gbps) 20 mV VTX-CM-AC-PP Output common mode voltage (5.0 Gbps) 100 mV VTX-RISE-FALL Rise and fall time (20% to 80%, 2.5 Gbps) 0.125 UI Rise and fall time (20% to 80%, 5.0 Gbps) 0.15 UI ZTX-DIFF-DC Output impeda nce–differential 80 120  LTX-SKEW Lane-to-lane TX skew within a SerDes block (2.5 Gbps) 500 ps + 2 UI ps Lane-to-lane TX skew within a SerDes block (5.0 Gbps) 500 ps + 4 UI ps RLTX-DIFF Return loss differential mode (2.5 Gbps) –10 dB Return loss differential mode (5.0 Gbps) 0.05 GHz to 1.25 GHz –10 dB 1.25 GHz to 2.5 GHz –8 dB RLTX-CM Return loss common mode (2.5 Gbps, 5.0 Gbps) –6 dB TX-LOCK-RST Transmit PLL lock time from reset 10 µs Table 294 • DDR Memory Interface Characteristics

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 121 The following table lists the receiver pa in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. VTX-AMP 100 mV setting 90 150 mV 400 mV setting 320 480 mV 800 mV setting 660 940 mV 1200 mV setting 950 1400 mV Table 297 • Receiver Parameters Symbol Description Min Typ Max Unit VRX-IN-PP-CC Differential input peak-to-peak sensitivity (2.5 Gbps) 0.238 1.2 V Differential input peak-to-peak sensitivity (2.5 Gbps, de-emphasized) 0.219 1.2 V Differential input peak-to-peak sensitivity (5.0 Gbps) 0.300 1.2 V Differential input peak-to-peak sensitivity (5.0 Gbps, de-emphasized) 0.300 1.2 V VRX-CM-AC-P Input common mode range (AC coupled) 150 mV ZRX-DIFF-DC Differential input termination 80 100 120  REXT External calibration resistor 1,188 1,200 1,212  CDR-LOCK-RST CDR relock time from reset 15 µs RLRX-DIFF Return loss differential mode (2.5 Gbps) –10 dB Return loss differential mode (5.0 Gbps) 0.05 GHz to 1.25 GHz –10 dB 1.25 GHz to 2.5 GHz –8 dB RLRX-CM Return loss common mode (2.5 Gbps,

5.0 Gbps)

–6 dB RX-CID 1. AC-coupled, BER = e -12. CID limit (set by 8B/10B coding, not the receiver PLL) 200 UI VRX-IDLE-DET-DIFF-PP Si gnal detect limit 65 175 mV Table 298 • SerDes Protocol Compliance Protocol Maximum Data Rate (Gbps) –1 –Std PCIe Gen 1 2.5 Yes Yes PCIe Gen 2 5.0 Yes XAUI 3.125 Yes Generic EPCS 3.2 Yes Generic EPCS 2.5 Yes Yes Table 296 • Transmitter Parameters (continued)

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 122 The following table lists the SerDes reference clock AC specifications in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.31 SmartFusion2 Specifications

2.3.31.1 MSS Cl ock Frequency

The following table lists the maximum frequency for MSS main clock in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 299 • SerDes Reference Clock AC Specifications Parameter Symbol Min Max Unit Reference clock frequency F REFCLK 100 160 MHz Reference clock rise time T RISE 0.6 4 V/ns Reference clock fall time T FALL 0.6 4 V/ns Reference clock duty cycle T CYC 40 60 % Reference clock mismatch M MREFCLK –300 300 ppm Reference spread spectrum clock SSCref 0 5000 ppm Table 300 • HCSL Minimum and Maximum DC Input Levels (Applicable to SerDes REFCLK Only) Parameter Symbol Min Typ Max Unit Recommended DC Operating Conditions Supply voltage V DDI 2.375 2.5 2.625 V HCSL DC Input Voltage Specification DC Input voltage V I 02 . 6 2 5 V HCSL Differential Voltage Specification Input common mode voltage V ICM 0.05 2.4 V Input differential voltage V IDIFF 100 1100 mV Table 301 • HCSL Minimum and Maximum AC Switching Speeds (Applicable to SerDes REFCLK Only) Parameter Symbol Min Typ Max Unit HCSL AC Specifications Maximum data rate (for MSIO I/O bank) F MAX 350 Mbps HCSL Impedance Specifications Termination resistance Rt 100  Table 302 • Maximum Frequency for MSS Main Clock Symbol Description –1 –Std Unit M3_CLK Maximum frequency for the MSS main clock 166 142 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 123

2.3.31.2 SmartFusion2 Inter-Integrated Circuit (I2C) Characteristics

This section describes the DC and switching of the IC interface. Unless otherwise noted, all output characteristics given are for a 100 pF load on the pins. For timing parameter definitions, see Figure 21, page 124. The following table lists the I2C characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V Table 303 • I2C Characteristics Parameter Symbol Min Typ Max Unit Conditions Input low voltage V IL –0.3 0.8 V See Single-Ended I/O Standards, page 25 for more information. I/O standard used for illustration: MSIO bank–LVTTL 8 mA low drive. Input high voltage V IH 23 . 4 5 V S e e Single-Ended I/O Standards, page 25 for more information. I/O standard used for illustration: MSIO bank–LVTTL 8 mA low drive. Hysteresis of schmitt triggered inputs for VDDI > VHYS 0.05 × VDDI V See Table 28, page 24 for more information. Input current high I IL 10 µA See Single-Ended I/O Standards, page 25 for more information. Input current low I IH 10 µA See Single-Ended I/O Standards, page 25 for more information. Input rise time T ir 1000 ns Standard mode 300 ns Fast mode Input fall time T if 300 ns Standard mode 300 ns Fast mode Maximum output voltage low (open drain) at 3 mA sink current for VDDI > 2 V VOL 0.4 V See Single-Ended I/O Standards, page 25 for more information. I/O standard used for illustration: MSIO bank–LVTTL 8 mA low drive. Pin capacitance Cin 10 pF V IN = 0, f = 1.0 MHz Output fall time from VIHMin to VILMax1 tOF 1 21.04 ns V IHmin to VILMax, CLOAD = 400 pF 5.556 ns V IHmin to VILMax, CLOAD = 100 pF Output rise time from VILMax to VIHMin1 tOR 1 19.887 ns V ILMax to VIHmin, CLOAD = 400 pF 5.218 ns V ILMax to VIHmin, CLOAD = 100 pF Output buffer maximum pull-down resistance2, 3 Rpull-up 2,3 50  Output buffer maximum pull-up resistance2, 4 Rpull-down 2,4 131.25 

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 124 The following table lists the I2C switching characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V Figure 21 • I2C Timing Parameter Definition Maximum data rate D MAX 400 Kbps Fast mode

100 Kbps Standard mode

These values are provided for MSIO Bank–LVTTL 8 mA Low Drive at 25 °C, typical conditions. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. 2. These maximum values are pro vided for information only. Minimum output buffer resistance values depend on VDDIx, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. 3. R(PULL-DOWN-MAX) = (VOLspec)/IOLspec. 4. R(PULL-UP-MAX) = (VDDImax–VOHspec)/IOHspec. Table 304 • I2C Switching Characteristics Parameter Symbol –1 Std UnitMin Min Low period of I2C_x_SCL T LOW 1 1 PCLK cycles High period of I2C_x_SCL T HIGH 1 1 PCLK cycles START hold time T HD;STA 1 1 PCLK cycles START setup time T SU;STA 1 1 PCLK cycles DATA hold time THD;DAT 1 1 PCLK cycles DATA setup time T SU;DAT 1 1 PCLK cycles STOP setup time T SU;STO 1 1 PCLK cycles Table 303 • I2C Characteristics (continued) Parameter Symbol Min Typ Max Unit Conditions SCL TRISE TFALL tLOW tHD;STA SDA tHIGH tHD;DAT tSU;DAT tSU;STOtSU;STA S P

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 125

2.3.31.3 Serial Peripheral Interface (SPI) Characteristics

20 MHz

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 126 sp5 SPI_[0|1]_CLK , SPI_[0|1]_DO, SPI_[0|1]_SS fall time (10%– 90%)1 2.906 ns IO Configuration: LVCMOS 2.5 V-8 mA AC Loading: 35 pF Test Conditions: Typical Voltage, 25 °C SPI master configuration (applicable for 005, 010, 025, and 050 devices) sp6m SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 8.0 ns sp7m SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) – 2.5 ns sp8m SPI_[0|1]_DI setup time 2 12 ns sp9m SPI_[0|1]_DI hold time 2 2.5 ns SPI slave configuration (applicable for 005, 010, 025, and 050 devices) sp6s SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 17.0 ns sp7s SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) + 3.0 ns sp8s SPI_[0|1]_DI setup time 2 2n s sp9s SPI_[0|1]_DI hold time 2 7n s SPI master configuration (applicable for 060, 090, and 150 devices) sp6m SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 7.0 ns sp7m SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) – 9.5 ns sp8m SPI_[0|1]_DI setup time 2 15 ns sp9m SPI_[0|1]_DI hold time 2 -–2.5 ns SPI slave configuration (applicable for 060, 090, and 150 devices) sp6s SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 16.0 ns sp7s SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) - 3.5 ns sp8s SPI_[0|1]_DI setup time 2 3n s sp9s SPI_[0|1]_DI hold time 2 2.5 ns 1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. 2. For allowable pclk configuratio ns, see Serial Peripheral Interface Controller section in the UG0331: SmartFusion2 Microcontroller Subsystem User Guide. Table 305 • SPI Characteristics for All Devices (continued) Symbol Description Min Typ Max Unit Conditions

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 127 Figure 22 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)

2.3.32 CAN Controller Characteristics

The following table lists the CAN controller characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.33 USB Characteristics

The following table lists the USB characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 306 • CAN Controller Characteristics Parameter Description –1 –Std Unit FCANREFCLK1 1. PCLK to CAN controller must be a multiple of 8 MHz. Internally sourced CAN reference clock frequency 160 136 MHz BAUDCANMAX Maximum CAN performance baud rate 11M b p s BAUDCANMIN Minimum CAN performance baud rate 0.05 0.05 Mbps Table 307 • USB Characteristics Parameter Description –1 –Std Unit FUSBREFCLK Internally sourc ed USB reference clock frequency 166 142 MHz TUSBCLK USB clock period 16.66 16.66 ns TUSBPD Clock to USB data pro pagation delay 9.0 9.0 ns TUSBSU Setup time for USB data 6.0 6.0 ns TUSBHD Hold time for USB data 0 0 ns SPI_0_CLK SPO = 0 SPI_0_DO SP6 SP7 50 %50 % MSB 50% 50% 50% SP2 SP1 90% 10% 10% SP4 SP5 SP8 SP9 50%50% MSBSPI_0_DI 10% 90% SP5 90% 10% SP4 90% 10%10% SP4SP5 90% SPI_0_SS SPI_0_CLK SPO = 1 SP3

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 128

2.3.34 MMUART Characteristics

The following table lists the MMUART characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.35 IGLOO2 Specifications

2.3.35.1 HPMS Clock Frequency

The following table lists the maximum frequency for HPMS main clock in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V.

2.3.35.2 IGLOO2 Serial Peripheral Interface (SPI) Characteristics

This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics given are for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_0_CLK. For timing parameter definitions, see Figure 23, page 130. The following table lists the SPI characteristics in worst-case industrial conditions when TJ = 100 °C, VDD = 1.14 V. Table 308 • MMUART Characteristics Parameter Description –1 –Std Unit FMMUART_REF_CLK Internally sourced MMUART reference clock frequency. 166 142 MHz BAUDMMUARTTx Maximum transmit baud rate 10.375 8.875 Mbps BAUDMMUARTRx Maximum receive baud rate 10.375 8.875 Mbps Table 309 • Maximum Frequency for HPMS Main Clock Symbol Description –1 –Std Unit HPMS_CLK Maximum frequency for the HPMS main clock 166 142 MHz Table 310 • SPI Characteristics for All Devices Symbol Description Min Typ Max Unit Conditions SPIFMAX Maximum operating frequency of SPI interface sp1 SPI_[0|1]_CLK minimum period SPI_[0|1]_CLK = PCLK/2 12 ns SPI_[0|1]_CLK = PCLK/4 24.1 ns SPI_[0|1]_CLK = PCLK/8 48.2 ns SPI_[0|1]_CLK = PCLK/16 0.1 µs SPI_[0|1]_CLK = PCLK/32 0.19 µs SPI_[0|1]_CLK = PCLK/64 0.39 µs SPI_[0|1]_CLK = PCLK/128 0.77 µs

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 129 sp2 SPI_[0|1]_CLK minim um pulse width high SPI_[0|1]_CLK = PCLK/2 6 ns SPI_[0|1]_CLK = PCLK/4 12.05 ns SPI_[0|1]_CLK = PCLK/8 24.1 ns SPI_[0|1]_CLK = PCLK/16 0.05 µs SPI_[0|1]_CLK = PCLK/32 0.095 µs SPI_[0|1]_CLK = PCLK/64 0.195 µs SPI_[0|1]_CLK = PCLK/128 0.385 µs sp3 SPI_[0|1]_CLK minimum pulse width low SPI_[0|1]_CLK = PCLK/2 6 ns SPI_[0|1]_CLK = PCLK/4 12.05 ns SPI_[0|1]_CLK = PCLK/8 24.1 ns SPI_[0|1]_CLK = PCLK/16 0.05 µs SPI_[0|1]_CLK = PCLK/32 0.095 µs SPI_[0|1]_CLK = PCLK/64 0.195 µs SPI_[0|1]_CLK = PCLK/128 0.385 µs sp4 SPI_[0|1]_CLK, rise time (10%–90%) 2.77 ns I/O Configuration: LVCMOS 2.5 V - 8 mA AC loading: 35 pF test conditions: Typical voltage, 25 °C sp5 SPI_[0|1]_CLK, fall time (10%–90%) 2.906 ns I/O Configuration: LVCMOS 2.5 V - 8 mA AC loading: 35 pF test conditions: Typical voltage, 25 °C SPI master configuration (applicable for 005, 010, 025, and 050 devices) sp6m SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 8.0 ns sp7m SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) – 2.5 ns sp8m SPI_[0|1]_DI setup time 2 12 ns sp9m SPI_[0|1]_DI hold time 2 2.5 ns SPI slave configuration (applicable for 005, 010, 025, and 050 devices) sp6s SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 17.0 ns sp7s SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) + 3.0 ns sp8s SPI_[0|1]_DI setup time 2 2n s sp9s SPI_[0|1]_DI hold time 2 7n s Table 310 • SPI Characteristics for All Devices (continued) Symbol Description Min Typ Max Unit Conditions

IGLOO2 FPGA and SmartFusion2 SoC FPGA Microsemi Proprietary and Confidential DS0128 Datasheet Revision 12.0 130 Figure 23 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) SPI master configuration (applicable for 060, 090, and 150 devices) sp6m SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 7.0 ns sp7m SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) – 9.5 ns sp8m SPI_[0|1]_DI setup time 2 15 ns sp9m SPI_[0|1]_DI hold time 2 –2.5 ns SPI slave configuration (applicable for 060, 090, and 150 devices) sp6s SPI_[0|1]_DO setup time 2 (SPI_x_CLK_period/2) – 16.0 ns sp7s SPI_[0|1]_DO hold time 2 (SPI_x_CLK_period/2) - 3.5 ns sp8s SPI_[0|1]_DI setup time 2 3n s sp9s SPI_[0|1]_DI hold time 2 2.5 ns 1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/download/ibis/default.aspx. 2. For allowable pclk configurat ions, see the Serial Peripheral Interface Controller section in the UG0331: SmartFusion2 Microcontroller Subsystem User Guide. Table 310 • SPI Characteristics for All Devices (continued) Symbol Description Min Typ Max Unit Conditions SPI_0_CLK SPO = 0 SPI_0_DO SP6 SP7 50 %50 % MSB 50% 50% 50% SP2 SP1 90% 10% 10% SP4 SP5 SP8 SP9 50%50% MSBSPI_0_DI 10% 90% SP5 90% 10% SP4 90% 10%10% SP4SP5 90% SPI_0_SS SPI_0_CLK SPO = 1 SP3

Product Information

DS0128 specifications and overview.

Summary

IGLOO2 FPGA and SmartFusion2 SoC FPGA Revision 12.0

Description

IGLOO2 FPGA and SmartFusion2 SoC FPGA Revision 12.0

Source title DS0128 Datasheet(PDF) - Microsemi Corporation

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