DS0115 MICROSEMI | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Revision History
  • 2 SmartFusion2 Pin Descriptions
  • 2.1 User I/Os
  • 2.2 Bank Location Diagrams
  • 2.3 Naming Conventions
  • 2.3.1 User I/O Naming Conventions
  • 2.3.2 Dedicated Global I/O Namin g Conventions
  • 2.3.3 Multi-Function I/Os
  • 2.4 MDDR/FDDR Interface
  • 2.4.1 DDR Controller Pins
  • 2.4.2 I/O Standards
  • 2.5 Supply Pins
  • 2.5.1 Additional Notes on Suppl y Pins
  • 2.6 JTAG Pins
  • 2.7 Programming SPI
  • 2.8 Dedicated I/Os
  • 2.9 SERDES I/Os
  • 2.10 Special Pins
  • 2.11 Input Only Pins
  • 2.12 Microcontroller Subsystem (MSS)
  • 2.13 I/O Programmable Features
  • 2.14 Package Ball Information
  • 2.14.1 FC1152
  • 2.14.2 FG896
  • 2.14.3 FG676
  • 2.14.4 FG484
  • 2.14.5 VF400
  • 2.14.6 FCS325
  • 2.14.7 VF256
  • 2.14.8 TQ144

SmartFusion2 Pin Descriptions

  1. 12.0 7/17 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Fax: +1 (949) 215-4996 Email: sales.support@microsemi.com www.microsemi.com © 2017 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www.microsemi.com.

DS0115 Datasheet Revision 12.0 v Tables Table 1 Organization of I/O Banks in SmartFusion2 Devices—FC1152, FCS536, FCV484, FG896, and

Revision History

DS0115 Datasheet Revision 12.0 1

1 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 12.0 The following is a summary of the changes in revision 12.0 of this document.

  • Information about unused conditions was added, see Table 9, page 26, Table 10, page 27, Table 11, page 28, and Table 12, page 28.
  • Information about VPPN VM and VSSNVM was added to table note of Supply pins, see Table 8, page 24. 1.2 Revision 11.0 The following is a summary of the changes in revision 11.0 of this document.
  • Updated Table 5, page 21, Table 8, page 24, Table 9, page 26 and Table 11, page 28.
  • Added reference to PD3068: Packa ge Mechanical Drawings for all the package devices. For more information, see Package Ball Information, page 33.
  • Updated Programming SPI, page 27. 1.3 Revision 10.0 The following is a summary of the changes in revision 10.0 of this document.
  • Added Figure 19, page 13.
  • Added MDDR/FDDR Interface, page 23. 1.4 Revision 9.0 The following is a summary of the changes in revision 9.0 of this document.
  • Added Figure 7, page 7.
  • Updated Table 1, page 17 and Table 2, page 18.
  • Added Figure 27, page 21.
  • Updated Programming SPI, page 27.
  • Updated Supply Pins, page 24.
  • Updated Table 14, page 30. 1.5 Revision 8.0 The following is a summary of the changes in revision 8.0 of this document.
  • Added Figure 4, page 6, Figure 5, page 6, Figure 12, page 10, and Figure 13, page 10.
  • Removed all instances of and ref erences to M2S100 device from Table 1, page 17.
  • Replaced VQ144 with TQ144 from Table 3, page 19.
  • Removed GPIO or USB_DIR_C from Table 15, page 31. 1.6 Revision 7.0 The following is a summary of the changes in revision 7.0 of this document.
  • Updated Notes for Bank Location figures.
  • Added Figure 23, page 15, Figure 24, page 16, Figure 25, page 16, and Figure 26, page 17.
  • Modified Table 1 • Organization of I/O Banks in SmartFusion2 D evices - FC1152, FCS536, FCV484, FG896, FG676, and FG484 by moving VF400 and FCS 325 devices to Table 2 • Organization of I/O Banks in SmartFusion2 Devices - VF400, FCS325, VF256, and TQ144 (SAR 58291).
  • Added VF256 and VQ144 devices to Table 2 • Organization of I/O Banks in SmartFusion2 Devices - VF400, FCS325, VF256, and TQ144 (SAR 58291).

DS0115 Datasheet Revision 12.0 3

  • Added Special Pins, page 29 section.
  • Connection information for some of the SERDES pins was clarifi ed in the notes to Table 12, page 28. 1.11 Revision 2.0 The document was revised extensively, including major changes to Table 8, page 24, new bank location diagrams, renaming of many pins and new pin tables for FG484 and FG896. 1.12 Revision 1.0 The following is a summary of the changes in revision 1.0 of this document.
  • Table 8, page 24 was revised to clarify instructions for unused pins.
  • Figure 1, page 4 was revised. The number of pairs in bank 1 was corrected to 10 (was 11) and the number of pairs in bank 3 was corrected to 23 (was 25).
  • Added Table 2, page 18.
  • The description for t he FLASH_GOLDEN pin in Table 10, page 27 was corrected to reverse the conditions for High and Low.
  • Table 12, page 28 was revised to clarify handling of pins with and without transceiver.
  • Added FG484, page 36, including pin tables for M2S010T, M2S025T, and M2S050T. 1.13 Revision 0.0 Revision 0.0 was the first publication of this document.

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 4

2 SmartFusion2 Pin Descriptions

2.1 User I/Os

SmartFusion®2 system-on-chip (SoC) field programmable gate array (FPGA) devices feature a flexible selection. The MSIO, MSIOD, and DDRIO can be configured as differential I/Os or two single-ended I/Os. These I/Os use one I/O slot to implement single-ended standards and two I/O slots for differential standards. The DDRIO is shared between fabric logic and MDDR/FDDR whereas MSIO/MSIOD is shared between MSS peripherals and fabric logic. When an MDDR/FDDR controller or MSS peripheral is not used, the respective I/Os are available to fabric logic. For functional block diagrams of MSIO, MSIOD, and DDRIO, refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide. For supported I/O standards, refer to the “Supported Voltage Standards” table in the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide.

2.2 Bank Location Diagrams

I/Os are grouped on the basis of I/O voltage standard. The grouped I/Os of each voltage standard form an I/O bank. Each I/O bank has dedicated I/O supply and ground voltages. Because of these dedicated supplies, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Figure 1 • SmartFusion2 M2S150TS/M2S150T/M2S150-FC1152 I/O Bank Locations Note: For M2S150-FC1152 device, SERDES blocks are not available in bank 9, 10, 12, and 13. West East Bank 1 DDRIO / FDDR (44 pairs) Bank 3 MSIO (21 pairs) Bank 15 MSIOD (18 pairs) Bank 16 MSIOD (27 pairs) Bank 4 MSIO (22 pairs)Bank 17 MSIO (20 pairs) North South SmartFusion2 SoC FPGA M2S150TS/M2S150T/M2S150 FC1152 Bank 5 MSIO (21 pairs) Bank 18 MSIO (21 pairs) Bank 7 JTAG Bank 6 MSIO (15 pairs) Bank 14 MSIO (7 pairs) Bank 13 MSIOD / SERDES0 (2 pairs) Bank 12 MSIOD / SERDES1 (2 pairs) Bank 11 MSIO (4 pairs) Bank 10 MSIOD / SERDES2 (2 pairs) Bank 9 MSIOD / SERDES3 (2 pairs) Bank 8 MSIO (9 pairs) Bank 2 DDRIO / MDDR (44 pairs) Bank 0 MSIO (6 pairs)

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 17 Figure 26 • SmartFusion2 M2S005S/M2S005-TQ144 I/O Bank Locations Table 1 • Organization of I/O Banks in SmartFusion2 Devices—FC1152, FCS536, FCV484, FG896, and FG6761 FC1152 FCS536 FCV484 FG896 FG676 Bank No. M2S150TS M2S150T M2S150 M2S150TS M2S150T M2S150 M2S150TS M2S150T M2S150 M2S050TS M2S050T M2S050 M2S090TS M2S090T M2S090 M2S060TS M2S060T M2S060 Bank 0 MSIO: fabric MSIO: fabric – DDRIO: MDDR or fabric MSIO: fabric MSIO: fabric Bank 1 DDRIO: FDDR or fabric DDRIO: FDDR or fabric DDRIO:FDDR or fabric MSIO: MSS or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric Bank 2 DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: fabric Bank 3 MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: fabric Bank 4 MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric JTAG/SWD JTAG/SWD MSIO: fabric Bank 5 MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric DDRIO: FDDR or fabric MSIO: fabric JTAG/SWD Bank 6 MSIO: fabric – MSIO: fabric MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric MSIO: fabric Bank 7 JTAG/ SWD JTAG/ SWD JTAG/ SWD MSIOD: fabric MSIOD: fabric MSIOD: SERDES 0 or fabric Bank 8 MSIO: fabric MSIO: fabric – MSIO: fabric MSIO: fabric MSIOD: SERDES 0 or fabric West East Bank 0 DDRIO (10 pairs) Bank 5 MSIOD (3 pairs) Bank 2 MSIO (7 pairs) Bank 6 MSIO (8 pairs) Bank 4 MSIO (10 pairs) North South SmartFusion2 SoC FPGA M2S005S/M2S005 TQ144 Bank 3 JTAG

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 18 Bank 9 MSIOD: SERDES 3 or fabric MSIOD: SERDES 3 or fabric MSIOD: SERDES 3 or fabric MSIOD: SERDES 1 or fabric – MSIO: fabric Bank 10 MSIOD: SERDES 2 or fabric MSIOD: SERDES 2 or fabric MSIOD: SERDES 2 or fabric ––– Bank 11 MSIO: fabric MSIO: fabric MSIO: fabric – – – Bank 12 MSIOD: SERDES 1 or fabric MSIOD: SERDES 1 or fabric MSIOD: SERDES 1 or fabric ––– Bank 13 MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric ––– Bank 14 MSIO: fabric MSIO: fabric MSIO: fabric – – – Bank 15 MSIOD: fabric MSIOD: fabric – – – – Bank 16 MSIOD: fabric MSIOD: fabric MSIOD: fabric – – – Bank 17 MSIO: fabric MSIO: fabric MSIO: fabric – – – Bank 18 MSIO: fabric MSIO: fabric – – – – 1. Banks that are shaded should always be powered with the appro priate VDDI bank supplies. Table 2 • Organization of I/O Banks in SmartFusion2 FG484 Device1 Bank No. M2S090TS M2S090T M2S090 M2S060TS M2S060T M2S060 M2S050TS M2S050T M2S050 M2S025TS M2S025T M2S025 M2S010TS M2S010T M2S010 M2S005S Bank 0 – – DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric Bank 1 DDRIO: MDDR or fabric DDRIO: MDDR or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric Bank 2 MSIO: MSS or fabric MSIO: fabric – MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric Bank 3 MSIO: MSS or fabric – MSIO: MSS or fabric JTAG/SWD JTAG/SWD JTAG/SWD Bank 4 JTAG/SWD MSIO: fabric JTAG/SWD MSIO: fabric MSIO: fabric MSIO: fabric Bank 5 MSIO: fabric JTAG/SWD DDRIO: FDDR or fabric MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric MSIOD: fabric Bank 6 MSIOD: SERDES 0 or fabric MSIO: fabric MSIOD: SERDES 0 or fabric MSIOD: fabric MSIOD: fabric MSIO: fabric Table 1 • Organization of I/O Banks in SmartFusion2 Devices—FC1152, FCS536, FCV484, FG896, and FG676 1 (continued) FC1152 FCS536 FCV484 FG896 FG676 Bank No. M2S150TS M2S150T M2S150 M2S150TS M2S150T M2S150 M2S150TS M2S150T M2S150 M2S050TS M2S050T M2S050 M2S090TS M2S090T M2S090 M2S060TS M2S060T M2S060

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 19 Bank 7 MSIOD: fabric MSIOD: SERDES 0 or fabric MSIOD: fabric MSIO: fabric MSIO: fabric – Bank 8 MSIO: fabric MSIOD : fabric MSIO: fabric – – – Bank 9 – MSIO: fabric – – – – 1. Banks that are shaded should always be powered with the appro priate VDDI bank supplies. Table 3 • Organization of I/O Banks in SmartFusion2 Devices—VF400 and TQ1441 VF400 TQ144 Bank No. M2S060TS M2S060T M2S060 M2S050TS M2S050T M2S050 M2S025TS M2S025T M2S025 M2S010TS M2S010T M2S010 M2S005S M2S010 M2S005S Bank 0 – DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: fabric DDRIO: fabric Bank 1 DDRIO: MDDR or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric Bank 2 MSIO: fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric Bank 3 – MSIO: MSS or fabric JTAG/SWD JTAG/SWD JTAG/SWD JTAG/SWD JTAG/SWD Bank 4 MSIO: fabric JTAG/SWD MSIO: fabric MSIO: fabric MSIO: fabric MSIO: fabric MSIO: fabric Bank 5 JTAG/SWD DDRIO: FDDR or fabric MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric MSIOD: fabric – MSIOD: fabric Bank 6 MSIO: fabric MSIOD: SERDES 0 or fabric MSIOD: fabric MSIOD: fabric MSIO: fabric MSIOD: fabric MSIO: fabric Bank 7 MSIOD: SERDES 0 or fabric MSIOD: fabric MSIO: fabric MSIO: fabric – MSIO: fabric – Table 2 • Organization of I/O Banks in SmartFusion2 FG484 Device 1 (continued) Bank No. M2S090TS M2S090T M2S090 M2S060TS M2S060T M2S060 M2S050TS M2S050T M2S050 M2S025TS M2S025T M2S025 M2S010TS M2S010T M2S010 M2S005S

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 20 Bank 8 MSIOD: fabric M S I O : f a b r i c ––––– B a n k 9 M S I O : f a b r i c –––––– 1. Banks that are shaded should always be powered with the appro priate VDDI bank supplies. Table 4 • Organization of I/O Banks in SmartFusion2 Devices—FCS325 and VF2561 FCS325 VF256 Bank No. M2S090TS M2S090T M2S090 M2S060TS M2S060T M2S060 M2S050TS M2S050T M2S050 M2S025TS M2S025T M2S025 M2S025TS M2S025T M2S025 M2S010TS M2S010T M2S010 M2S005S B a n k 0 ––D D R I O : MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: MDDR or fabric DDRIO: fabric Bank 1 DDRIO: MDDR or fabric DDRIO: MDDR or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric Bank 2 MSIO: fabric MSIO: fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric MSIO: MSS or fabric Bank 3 MSIO: fabric MSIO: fabric MSIO: MSS or fabric JTAG/SWD JTAG/SWD JTAG/SWD JTAG/SWD Bank 4 JTAG/SWD MSIO: fabric JTAG/SWD MSIO: fabric MSIO: fabric MSIO: fabric MSIO: fabric Bank 5 MSIO: fabric JTAG/SWD DDRIO: FDDR or fabric MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric MSIOD: SERDES 0 or fabric MSIOD: fabric Bank 6 MSIOD: SERDES 0 or fabric MSIO: fabric MSIOD: SERDES 0 or fabric MSIO: fabric MSIOD: fabric MSIOD: fabric MSIO: fabric Bank 7 MSIOD: fabric MSIOD: SERDES 0 or fabric MSIOD: fabric MSIO: fabric MSIO: fabric MSIO: fabric – Bank 8 MSIO: fabric MSIOD: fabric M S I O : f a b r i c –––– B a n k 9 –M S I O : f a b r i c ––––– 1. Banks that are shaded should always be powered with the appro priate VDDI bank supplies. Table 3 • Organization of I/O Banks in SmartFusion2 Devices—VF400 and TQ1441 (continued) VF400 TQ144 Bank No. M2S060TS M2S060T M2S060 M2S050TS M2S050T M2S050 M2S025TS M2S025T M2S025 M2S010TS M2S010T M2S010 M2S005S M2S010 M2S005S

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 21 Note: For more information on I/O status of MSIO, MSIOD and DDRIO pins during power up/down and default conditions, refer to AC396: SmartFusion2 and IGLOO2 in Hot Swapping and Cold Sparing Application Note. All user I/Os have internal clamp diode control circuitry. A pull-up clamp diode must not be present in the I/O circuitry if the hot-swap feature is used. The 3.3 V PCI standard requires a pull-up clamp diode on the I/O, so it cannot be selected if hot-swap capability is required. Figure 27 • Internal Clamp Diode Control Circuitry Table 5 • User I/O Types Name Type Description MSIOxyBz In/Out MSIOs provide pr ogrammable drive strength, weak pull-up, and weak-pull-down. In single ended mode, the I/O pair operates as two separate I/Os named P and N. Some of these pins are also multiplexed with integrated peripherals in the MSS (I2C, USB, SPI, UART, CAN, and fabric I/Os).This allows MSIO pins to be multiplexed as I/Os for the FPGA fabric, the ARM Cortex-M3 processor, or for given integrated MSS peripherals. MSIOs can be routed to dedicated I/O buffers (MSSIOBUF) or in some cases to the FPGA fabric interface through an IOMUX. SmartFusion2 I/O ports also support ESD protection. MSIO I/O cells operate at up to 3.3 V and are capable of high-speed LVDS2V5 and LVDS3V3 operation. MSIODxyBz In/Out MSIOD is very sim ilar to MSIO, but drops 3.3 V and hot-plug support and adds pre- emphasis, in order to achieve higher speeds. MSIODs provide programmable drive strength, weak pull-up, and weak pull-down. MSIOD I/O cells operate at up to 2.5 V and are capable of high-speed LVDS2V5 operation. Some of these pins are also multiplexed with the SERDES interface. SmartFusion2 I/O ports support ESD protection. DDRIOxyBz In/Out The double data i nput output (DDRIO) is a multi-standard I/O optimized for LPDDR/DDR2/DDR3 performance. In SmartFusion2 devices there are two DDR subsystems: the fabric DDR and MSS DDR controllers. All DDRIOs can be configured as differential I/Os or two single-ended I/Os. If you select MDDR/FDDR, Libero SoC automatically connects MDDR/FDDR signals to the DDRIOs. DDRIOs can be connected to the respective DDR subsystem PHYs or can be used as user I/Os. Depending on the memory configuration, only the required DDRIOs are used by Libero SoC. The unused DDRIOs are available to connect to the fabric. DDRIO supports a maximum of 2.5 V and does not support 3.3 V. ƵĨĨĞƌ WĂĚ WƵůůͲƵƉůĂŵƉĚŝŽĚĞƉƌĞƐĞŶƚƐ ŝŶϯ͘ϯsW/͕D^/KĂŶĚ Z/KƐ WƵůůͲĚŽǁŶůĂŵƉĚŝŽĚĞ ƉƌĞƐĞŶƚƐŝŶĂůůƵƐĞƌ/K ƐƚĂŶĚĂƌĚƐ

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 22

2.3 Naming Conventions

2.3.1 User I/O Naming Conventions

The naming convention used for each FPGA user I/O is IOxyBz, where: IO is the type of I/O—MSIO, MSIOD, or DDRIO. x refers the I/O pair number in bank z. y is P (positive) or N (negative). In single-ended mode, the I/O pair operates as two separate I/Os named P and N. Differential mode is implemented with a fixed I/O pair and cannot be split with an adjacent I/O. B is bank. z refers to bank number (0–9 for M2S050-FG896). Differential standards are implemented as true differential outputs and complementary single-ended outputs for SSTL/HSTL. In the single-ended mode, the I/O pair operates as two separate I/Os named P and N. All the configuration and data inputs/outputs are then separate and use names ending in P and N to differentiate between the two I/Os. For more information, refer to the "I/Os" chapter of the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide.

2.3.2 Dedicated Global I/O Naming Conventions

Dedicated global I/Os are dual-use I/Os which can drive the global blocks either directly or through clock conditioning circuits (CCC) or virtual clock conditioning circuits (VCCC). They can also be used as regular user I/Os. These global I/Os are the primary source for bringing in the external clock inputs into the SmartFusion2 device. In the M2S050T-FG896 device, there are 16 global blocks located in the center of the fabric and 32 global I/Os located 8 each on the north, east, south, and west sides of the fabric. There are 6 CCC blocks, located 2 each on northwest, northeast, and southwest side of the fabric and 2 VCCC blocks on the southeast side of the fabric. Dedicated global I/Os that drive the global blocks (GB) directly are named as GBn, where n is 0 to 15. Dedicated global I/Os that drive GBs through CCCs are named as CCC_xyz_CLKlw, where: xy is the location—NE, SW, or NW. z is 0 or 1. I represents input clock w refers to one of the four possible output clocks of the associated CCC_xyz—GL0, GL1, GL2, or GL3. Dedicated global I/Os that drive GBs through VCCCs are named as VCCC_SEz, where: SE is southeast. z is 0 or 1. Unused dedicated global I/Os behave similarly to unused regular User I/Os (MSIO, MSIOD, DDRIO). Libero configures unused User I/Os as input buffer disabled, output buffer tri-stated with weak pull-up. For further details, refer to the "Fabric Global Routing Resources" chapter of the UG0449: SmartFusion2 SoC FPGA and IGLOO2 FPGA Clocking Resources User Guide.

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 23

2.3.3 Multi-Function I/Os

Certain I/Os can have more than one function. Users select the functionality through Libero configuration tools. The name of a pin shows the functionalities for which that pin can be configured and used. Example pin name: MSIO48NB1/I2C_0_SCL/GPIO_31_B/USB_DATA1_C This I/O port is multi-purpose and can be configured as MSIO, I2C0 clock, fabric I/O, or USB_DATA1_C.

2.4 MDDR/FDDR Interface

SmartFusion2 devices have MDDR/ FDDR blocks. The DDR subsystems are hardened ASIC blocks for interfacing the LPDDR, DDR2, and DDR3 memories. It supports 8-/16-/32-bit data bus width modes. The DDRIO uses fixed impedance calibration for different drive strengths. These values can be programmed using Libero SoC software for the selected I/O standard. The values are fed to the pull-up/pull-down reference network to match the impedance with an external resistor. For more information about reference resistor values (for different drive modes), refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide.

2.4.1 DDR Controller Pins

The following table lists the DDR Controller pins. Table 6 • DDR Controller Pins1 Pin Name Type Reference Resistor (Ω) xDDR_CAS_N Output DRAM CASN. xDDR_CKE Output DRAM Clock enable. xDDR_CLK Output DRAM single-ended clock for differential pads. xDDR_CLK_N Output DRAM single-ended clock for differential pads. xDDR_CS_N Output DRAM Chip select. xDDR_ODT Output DRAM on-die termination (ODT). 0: Termination Off 1: Termination On xDDR_RAS_N Output DRAM RASN. xDDR_RESET_N Output DRAM reset for DDR3. xDDR_WE_N Output DRAM Write enable xDDR_ADDR[15:0] Output DRAM address bits. xDDR_BA[2:0] Output DRAM bank address. xDDR_DM_RDQS[3:0] Inpu t/Output DRAM data mask from bidirectional pads. xDDR_DQS[3:0] Input/Output DRAM single-ended data strobe output for bidirectional pads. xDDR_DQS[3:0]_N Input/Output DRA M single-ended data strobe output for bidirectional pads. xDDR_DQ[31:0] Input/Output DRAM dat a input or output for bidirectional pads. xDDR_DQ_ECC[3:0] Input/ Output DRAM data input or output for SECDE D. xDDR_DM_RDQS_ECC Input/Output DRAM single-ended data strobe outpu t for bidirectional pads. xDDR_DQS_ECC Input/Output DRAM single-ended data strobe output fo r bidirectional pads. xDDR_DQS_ECC_N Input/Output DRAM dat a input or output for bidirectional pads. xDDR_TMATCH_[0/1]_IN Input DQS enabl e input for timing match between DQS and system clock. For simulations, tie to xDDR_TMATCH_[0/1]_OUT.

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 24 For more information about DDR memory calibration, refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide. For DDR termination details refer AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note.

2.4.2 I/O Standards

The following table lists the supported I/O standards for different DDR memories.

2.5 Supply Pins

SmartFusion2 devices support multi-standard I/Os (MSIOs), MSIODs, double data rate I/Os (DDRIOs), microcontroller serial interfaces, high speed serial interfaces, and a debugging JTAG interface. SmartFusion2 devices require the power supplies listed in the following table. xDDR_TMATCH_[0/1]_OUT Output DQS enable output for timing match b etween DQS and system clock. For simulations, tie to xDDR_TMATCH_[0/1]_IN. xDDR_TMATCH_ECC_IN Input DQS enable input for timing match betwee n DQS and system clock. For simulations, tie to xDDR_TMATCH_ECC_OUT. xDDR_TMATCH_ECC_OUT Output DQS enable output for timing match bet ween DQS and system clock. For simulations, tie to xDDR_TMATCH_ECC_IN. xDDR_IMP_CALIB Ref Pull-down with resistor depending on voltage/s tandard: DDR2 - 150  DDR3 (1.5 V) - 240  LPDDR - 150  1. Though calibration is not required, it is recommended to use corresponding resistor placeholder to connect the xDDR_IMP_CALIB to the ground with or without a resistor. x represents Fabric or MSS DDR. Table 7 • Supported I/O Standards for Different DDR Memories Memory Type I/O Standard DDR3 SSTL15I, SSTL15II DDR2 SSTL18I, SSTL18II LPDDR LVCMOS18 Table 8 • Supply Pins Name Type Description VDD Supply DC core supply voltage . Must always power this pin. VPP Supply

1 Power supply for charge pumps (for normal operation and

programming). Must always power this pin. VPPNVM Supply 1 Analog sense circuit supply of embedded nonvolatile memory (eNVM). Must be shorted to VPP . VDDIx Bank power supplies2 VDDIx, Bank x power VREFx Supply 3 Reference voltage for MDDR/FDDR signals which is powered through the corresponding Bank Supply (VDDIx). When unused, VREFx can be DNC or grounded (VSS). Table 6 • DDR Controller Pins1 (continued)

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 25 CCC_NE0_PLL_VDDA PLL power supplies4 Analog power pad for PLL0 CCC_NE1_PLL_VDDA Analog power pad for PLL1 CCC_NW0_PLL_VDDA Analog power pad for PLL2 CCC_NW1_PLL_VDDA Analog power pad for PLL3 CCC_SW0_PLL_VDDA Analog power pad for PLL4 CCC_SW1_PLL_VDDA Analog power pad for PLL5 MSS_MDDR_PLL_VDDA Analog power pad for PLL of MDDR and MSS FDDR_PLL_VDDA Analog po wer pad for PLL of FDDR SERDES_x_VDD SERDESx power supplies It is a +1.2 V supply and for few devices SERDES_x_VDD is internally shorted to core VDD. For example, M2S150-FCV484 device. SERDES_x_L01_VDDAIO Tx/Rx analog I/O voltage. Low voltage power for Lane0 and Lane1 of SERDESIFx, located on the left side. It is a +1.2 V SERDES PMA supply. SERDES_x_L23_VDDAIO Tx/Rx analog I/O voltage. Low voltage power for Lane2 and Lane3 of SERDESIFx, located on the right side. It is a +1.2 V SERDES PMA supply. SERDES_x_L01_VDDAPLL Analog powe r for SERDESx PLL of Lane0 and Lane1. In used condition, it must be connected to +2.5 V. In unused condition, it can be connected to either +2.5 V or VDD (1.2 V). SERDES_x_L23_VDDAPLL Analog powe r for SERDESx PLL of Lane2 and Lane3. In used condition, it must be connected to +2.5 V. In unused condition, it can be connected to either +2.5 V or VDD (1.2 V). SERDES_x_L01_REFRET Local on-chi p ground return path for SERDES_x_L01_VDDAPLL for Lane0 and Lane1 of SERDESIF0, located on the left side. If unused, it must be grounded (VSS). SERDES_x_L23_REFRET Local on-chi p ground return path for SERDES_x_L23_VDDAPLL for Lane2 and Lane3 of SERDESIF0, located on the right side. If unused, it must be grounded (VSS). SERDES_x_PLL_VDDA High supply voltage for PLL SERDESx. It can be +2.5 V or +3.3 V. SERDES_x_PLL_VSSA VDDA to on-die VSSA high pass filter connection for PLL SERDESx. If unused, it must be grounded (VSS). CCC_NE0_PLL_VSSA PLL return paths Return path for corresponding analog PLL VDDA supply. High frequency noise should be eliminated by placing the R-C filter circuitry in between VDDA and VSSA pins.CCC_NE_PLL_VSSA CCC_NW0_PLL_VSSA CCC_NW1_PLL_VSSA CCC_SW0_PLL_VSSA CCC_SW1_PLL_VSSA MSS_MDDR_PLL_VSSA Analog ground pad for PLL of MDDR and MSS FDDR_PLL_VSSA Analog ground pad for PLL of FDDR VSS Ground Ground pad for core and I/Os. Must always connect to ground. VSSNVM Analog sense cir cuit ground of eNVM. Must always connect to ground. Table 8 • Supply Pins (continued) Name Type Description

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 26

2.5.1 Additional Notes on Supply Pins

  • As an alternative to leaving un used positive and ground level supplies floating (not connected, open), they can be shorted to VSS on-board. This could be considered a better practice in avionics, so that floating supplies do not pick up charge from radiation.
  • For on-board connectivity solutions, refer to the AC393: SmartFusion2 SoC FPGA and IGLOO2 FPGA Board Design Guidelines Application Note.

2.6 JTAG Pins

implemented using a serial wire JTAG debug port (SWJ-DP) rather than a serial wire debug port (SW-DP). This enables either the M3 JTAG or the SW protocol to be used for debugging. 1. Lower pin count packages. The VPPNVM and VSSNVM pins are inte rnal shorted to VPP and VSS, respectively and are not bonded out of silicon, for example, M2S150TS. For more information about VPP and VPPNVM power supplies, refer to Table 2 - Recommended Operating Conditions of the DS0128: IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet. 2. For details on bank power supplies, refer to the “Recommendation for Unused Bank Supplies" table in the AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note. For more details on user I/O pins (MSIO, MSIOD, DDRIO) and supported voltage standards, refer to the Supported Voltage Standards table in the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide. 3. Reference voltages should be powered with the appropriate bank supplies through voltage divider circuitry. If I/O banks are being used as single-ended I/Os (and MDDR or FDDR functionalities are not being used), then VREFx can be left floating (DNC) even though the VDDIx powered to the corresponding supplies. 4. If used as PLL, the supply mus t be connected over resistor and capacitors (filter circuitry) to a common PLL supply (2.5 V or 3.3 V) to the corresponding on-board PLL return path. If PLL is unused or used as divider, the supply must connect directly to Use either 2.5 V or 3.3 V PLL supply for all the PLL in the board as per the setting used in the Libero. 5. If used, all SERDES PLL pins must be powered through resistor and capacitors (filter circuitry) to the correct appropriate supply to the corresponding on-board return path. If unused must connect directly to the appropriate supplies (without filter circuitry). 6. If used, all CCC PLL pins must be powered through resistor an d capacitors (filter circuitry) to the appropriate supply to the corresponding on-board return path on-board. If unused must connect directly to the Ground (without filter circuitry). Table 9 • JTAG Pin Names and Descriptions Name Type Description Unused Conditions JTAGSEL Input JTAG controller selection. If JTAGSEL is pulled High, an external TAP controller connects to the JTAG interface—system controller TAP . If JTAGSEL is pulled Low, an external TAP controller connects to either the Cortex-M3 JTAG TAP (if debug is enabled) or an auxiliary TAP (if debug is disabled). Pull-up to VDDI (JTAG bank) through a 1 K resistor. JTAG_TCK/ M3_TCK Input Test clock. Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/pull-down resistor. If JTAG is not used, Microsemi recommends tying it off. Connect TCK through the 1 KΩ resistor to GND or +3.3 V through a resistor placed close to the FPGA pin. Connect to either VDDI# (JTAG) or VSS through a 200 Kto 1 K resistor. JTAG_TDI/ M3_TDI Input Test data. Serial input for JTAG boundary scan, ISP , and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. Do not connect (DNC) JTAG_TDO/ M3_TDO/ M3_SWO Output Test data. Serial output for JTAG boundary scan, ISP, and UJTAG usage. The TDO pin does not have an internal pull-up/-down resistor. M3_SWO: Serial Wire Viewer output DNC JTAG_TMS/ M3_TMS/ M3_SWDIO Input Test mode select. There is an internal weak pull-up resistor on the TMS pin. M3_SWDIO: Serial Wire Debug data input/output DNC

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 27

2.7 Programming SPI

The system controller contains a dedicated SPI block for programming. The SPI is operated in Slave mode. In Master mode, the SmartFusion2 device is interfaced with an external SPI flash device and the programming data is downloaded from it to the FPGA. In Slave mode, it is communicated with a remote device that initiates download of the programming data to the FPGA. SC_SPI interface can not be used to program the device in Master mode except for M2S050. SC_SPI work in Master and slave mode for M2S050 device. SC_SPI can be configured only in Slave mode. SPI_0 is used in SPI master mode. Note: For more details related to reset, clock, and programming, refer to the AC393: SmartFusion2 SoC FPGA and IGLOO2 FPGA Board Design Guidelines Application Note. Note: For more information on remaining programming modes, refer to the UG0451: SmartFusion2 SoC FPGA and IGLOO2 FPGA Programming User Guide. JTAG_TRSTB/ M3_TRSTB Input Boundary scan reset pin. The TRSTB pin functions as an active low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin. In critical applications, an upset in the JTAG circuit could allow entering an undesired JTAG state. In such cases, Microsemi recommends that you tie off TRSTB to GND through a resistor (1 k) placed close to the FPGA pin. DNC or pull-down to VSS through a 1 K resistor for upset immunity. Table 10 • Programming SPI Interface Name Type Description Unused Conditions SC_SPI_SS Output SPI slave select DNC SC_SPI_SDO Output SPI data output DNC SC_SPI_SDI Input SPI data input DNC SC_SPI_CLK Output SPI clock DNC FLASH_GOLDEN_N Input If pulled Low, th is indicates that the device is to be re-programmed from an image in the external SPI flash attached to the SPI interface. If pulled High, the SPI is put into slave mode. Add an external pull-up resistor value of 10 kΩ to VDDI (Bank). Pull-up to VDDI# through a 10 K resistor. Table 9 • JTAG Pin Names and Descriptions (continued) Name Type Description Unused Conditions

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 28

2.8 Dedicated I/Os

Dedicated I/Os (Table 11, page 28 and Table 12, page 28) can be used for a single purpose such as SERDES, device reset, or clock functions. SmartFusion2 dedicated I/Os:

  • Device reset pins
  • Crystal osc illator pins
  • SERDES I/Os
  • Programming SPI pins

2.9 SERDES I/Os

The SERDES I/Os available in SmartFusion2 devices are dedicated for high speed serial communication protocols. The SERDES I/Os support protocols such as PCI Express 2.0, XAUI, serial gigabit media independent interface (SGMII), serial rapid IO (SRIO), and any user-defined high speed serial protocol implementation in fabric. Refer to the AC393: SmartFusion2 SoC FPGA and IGLOO2 FPGA Board Design Guidelines Application Note for further information. Table 11 • Device Reset and Crystal Oscillator Pin Types and Descriptions Pin Type Description Unused Conditions Device Reset I/Os DEVRST_N Input Device reset; active Low and powered by VPP . It is an asynchronous signal and Schmitt trigger input with the maximum slew rate must not exceed µs. When DEVRST_N is asserted, all user IOs are fully tri-stated. In unused condition, pull up to VPP through 10 kΩ resistor. Use the 3.3 V I/O standards specification. Any of the

3.3 V I/O standards like

LVTTL/LVCMOS is applicable for DEVRST. Pull-up to VPP through a 10 K resistor. Crystal Oscillator I/Os 1. The M2S050 device has only a main crystal oscillator. XTLOSC_[MAIN/AUX]_EXTAL Input Cryst al connection or external RC network. DNC. Nominal 50 K internal weak pull-up to VPP . XTLOSC_[MAIN/AUX]_XTAL Input Input clock from the main/auxiliary crystal oscillator Table 12 • SERDES I/O Port Names and Descriptions Port Name Type Description Unused Conditions Data / Reference Pads SERDES_x_RXD[0:3]_P Input Receive data. SERDES differential input for each lane. Pull-down to VSS through a 10 k resistor. This is to improve latch-up immunity.SERDES_x_RXD[0:3]_N SERDES_x_TXD[0:3]_P Output Transm it data. SERDES differential output for each lane. DNC SERDES_x_TXD[0:3]_N

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 29

2.10 Special Pins

The two live probe I/O cells are dual-purpose. If live probe functionality will never be used on these I/Os, the user can configure the I/O as an input, output, or bidirectional. However, if the intent is to perform live switching between the user I/O and probe functionality, then use the I/O only as an output. If it were configured as an input during general use, then as soon as it is switched over to live probe operation, the probe circuitry would drive out onto this I/O, potentially causing device damage. Common I/O Pads per SERDES Interface SERDES_x_L01_REXT Reference Ext ernal reference resistor connection to calibrate TX/RX termination value. DNC SERDES_x_L23_REXT DNC SERDES_x_REFCLK[0:1]_P Clock Reference clock differential. DNC SERDES_x_REFCLK[0:1]_N Clock Reference clock differential. DNC Table 13 • Special Pins Name Type Description PROBE_A Input/ Output The two live probe I/O cells are dual-purpose—Live probe functionality and user I/OPROBE_B CCC_xyz_CLKI0 Input Input clock from dedicated input pad 0. The xy portion refers to the CCC location (NE, SW, SE, or NW) and z represents the CCC number (0 or 1). CCC_xyz_CLKI1 Input Input clock from dedicated input pad 1. The xy portion refers to the CCC location (NE, SW, SE, or NW) and z represents the CCC number (0 or 1). CCC_xyz_CLKI2 Input Input clock from dedicated input pad 2. The xy portion refers to the CCC location (NE, SW, SE, or NW) and z represents the CCC number (0 or 1). CCC_xyz_CLKI3 Input Input clock from dedicated input pad 3. The xy portion refers to the CCC location (NE, SW, SE, or NW) and z represents the CCC number (0 or 1). GBx Input GB is a multiplexer th at generates an independent global signal. The GBs can be driven from multiple sources such as dedicated global I/Os, fabric CCCs, VCCCs, and fabric routing xDDR_TMATCH_[0/1]_IN Input DQS enable input for timing match betw een DQS and system clock. TMATCH_IN and TMATCH_OUT pins need to be looped back with the trace length as short as possible. xDDR_TMATCH_[0/1]_OUT Output DQS e nable output for timing match between DQS and system clock. DNC – Do not connect. This pin should not be connected to any sig nals on the PCB; leave this pin unconnected. NC – Do not connect. This pin is not connected to circuitry within the device. This pin can be driven to any voltage or can be left floating with no effect on the operation of the device. Table 12 • SERDES I/O Port Names and Descriptions (continued) Port Name Type Description Unused Conditions

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 30

2.11 Input Only Pins

These pins are differentially paired with Flash_golden_n (input only pin) and are input only when used to connect to the FPGA fabric. These pins can be used as output for the listed MSS peripherals. Table 14 • Input Only Pins Device Pin Description M2S050T-FG896 H27 MSI46NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI46NB1 is an input only pin. M2S090T-FG676 D23 MSI59NB2/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI59NB2 is an input only pin. M2S090T-FG484 D21 MSI59NB2/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI59NB2 is an input only pin. M2S060T-FG484 D21 MSI47NB2/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI47NB2 is an input only pin. M2S050T-FG484 D21 MSI46NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI46NB1 is an input only pin. M2S025T-FG484 D21 MSI32NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI32NB1 is an input only pin. M2S010T-FG484 D21 MSI26NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI32NB1 is an input only pin. M2S005-FG484 D21 MSI16NB1/MMUART _0_TXD/GPIO_27_B/USB_DIR_C, cannot be configured as differential. The function MSI16NB1 is an input only pin. M2S050T-VF400 D18 MSI46NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI46NB1 is an input only pin. M2S025T-VF400 D18 MSI32NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI32NB1 is an input only pin. M2S010T-VF400 D18 MSI26NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, cann ot be configured as differential. The function MSI26NB1 is an input only pin. M2S005-VF400 D18 MSI16NB1/MMUART_0_TXD/GPIO_27_B/USB_DIR_C, canno t be configured as differential. The function MSI16NB1 is an input only pin. M2S025T-VF256 G12 MSI26NB1/MMUART_0_TXD/GPIO_27_B, cannot be conf igured as differential. The function MSI26NB1 is an input only pin. M2S010T-VF256 G12 MSI26NB1/MMUART_0_TXD/GPIO_27_B, cannot be conf igured as differential. The function MSI26NB1 is an input only pin. M2S005-VF256 D12 MSI16NB1/MMUART_0_TXD/GPIO_27_B, cannot be configured as differential. The function MSI16NB1 is an input only pin.

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 31

2.12 Microcontroller Subsystem (MSS)

Table 15 • MSS Pin Names and Descriptions Name Type Description Inter-Integrated Circuit (I2C) Peripherals I2C_0_SCL Input/Output I 2C bus serial clock output. I2C_0_SDA Input/Output I 2C bus serial data input/output. I2C_1_SCL Input/Output I 2C bus serial clock output. I2C_1_SDA Input/Output I 2C bus serial data input/output. Universal Asynchronous Receiver/Transmitter (UART) Peripherals MMUART_0_CLK Output UART clock. MMUART_0_TXD Output UART transmit data. MMUART_0_RXD Input UART receive data. MMUART_0_CTS Input UART clear to send. MMUART_0_RTS Output UART request to send. MMUART_0_DTR Output Modem data terminal ready. MMUART_0_DCD Input Modem data carrier detects. MMUART_0_DSR Input Modem data set ready. MMUART_0_RI Input Modem ring indicator. MMUART_1_CLK Output UART Clock. MMUART_1_TXD Output UART transmit data. MMUART_1_RXD Input UART receive data. MMUART_1_CTS Input UART clear to send. MMUART_1_RTS Output UART request to send. MMUART_1_DTR Output Modem data terminal ready. MMUART_1_DCD Input Modem data carrier detects. MMUART_1_DSR Input Modem data set ready. MMUART_1_RI Input Modem ring indicator. Serial Peripheral Interface (SPI) Controllers SPI_0_SS0 Output SPI slave select0. SPI_0_SS1 Output SPI slave select1. SPI_0_SS2 Output SPI slave select2. SPI_0_SS3 Output SPI slave select3. SPI_0_SS4 Output SPI slave select4. SPI_0_SS5 Output SPI slave select5. SPI_0_SS6 Output SPI slave select6. SPI_0_SS7 Output SPI slave select7. SPI_0_CLK Output SPI clock. SPI_0_SDO Output SP I data output. SPI_0_SDI Input SPI data input.

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 32 Note: All the pins can also be used as Fabric I/Os as all MSS pins are muxed with Fabric I/Os.

2.13 I/O Programmable Features

SmartFusion2 devices support different I/O programmable features for MSIO, MSIOD, and DDRIO. Each I/O pair (P, N) supports the following programmable features:

  • Programmable drive strength
  • Programmable weak pull-up and pull-down
  • Configurable ODT and driver impedance
  • Programmable input delay
  • Programmable Schmitt input and receiver For more information on SmartFusion2 I/O programmable features, refer to the "SmartFusion2 I/O Features" table of the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide. SPI_1_SS0 Output SPI slave select0. SPI_1_SS1 Output SPI slave select1. SPI_1_SS2 Output SPI slave select2. SPI_1_SS3 Output SPI slave select3. SPI_1_SS4 Output SPI slave select4. SPI_1_SS5 Output SPI slave select5. SPI_1_SS6 Output SPI slave select6. SPI_1_SS7 Output SPI slave select7. SPI_1_CLK Output SPI clock. SPI_1_SDO Output SPI data output. SPI_1_SDI Input SPI data input. Table 15 • MSS Pin Names and Descriptions (continued) Name Type Description

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 33

2.14 Package Ball Information

2.14.1 FC1152

Figure 28 • FC1152 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.1.1 Pin Tables

Pin tables for the FC1152 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=132128 The following devices are available in the FC1152: M2S150(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. A1 Ballpad Corner A B C D E F G H J K L M N P R TU V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 34

2.14.2 FG896

Figure 29 • FG896 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.2.1 Pin Tables

Pin tables for the FG896 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131803 The following devices are available in the FG896: M2S050(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. 123456789101112131415161718192021222324252627282930 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK A1 Ball Pad Corner

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 35

2.14.3 FG676

Figure 30 • FG676 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.3.1 Pin Tables

Pin tables for the FG676 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=132535 The following devices are available in the FG676: M2S090(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. A1 Ball Pad Corner A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 36

2.14.4 FG484

Figure 31 • FG484 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.4.1 Pin Tables

Pin tables for the FG484 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131802 Pin tables for the FCV484 package are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=134543 The following devices are available in the FG484:

  • M2S005(S)
  • M2S010(T), (TS)
  • M2S025(T), (TS)
  • M2S050(T), (TS)
  • M2S060(T), (TS)
  • M2S090(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. A1 Ball Pad Corner 22 2120191817 161514 1312 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 37

2.14.5 VF400

Figure 32 • VF400 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.5.1 Pin Tables

Pin tables for the VF400 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=131805 The following devices are available in the VF400:

  • M2S005(S)
  • M2S010(T), (TS)
  • M2S025(T), (TS)
  • M2S050(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 87654321 A B C D E F G H J K L M O P R T U V W Y A1 Ball Pad Corner

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 38

2.14.6 FCS325

Figure 33 • FCS325 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.6.1 Pin Tables

Pin tables for the FCS325 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=132603 The following devices are available in the FCS325: M2S050(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. A1 Ball Pad Corner A B C D E F G H J K L M N P R T U V W Y AA

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 39

2.14.7 VF256

Figure 34 • VF256 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center.

2.14.7.1 Pin Tables

Pin tables for the VF256 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=133773 The following devices are available in the VF256:

  • M2S005(S)
  • M2S010(T), (TS)
  • M2S025(T), (TS) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings. $%DOO3DG&RUQHU

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 40

2.14.8 TQ144

Figure 35 • TQ144 Package Drawing Note: For Package Manufacturing and Environmental information, visit the Resource Center at Packaging Resource Center. NOTES: UNLESS OTHERWISE SPECIFIED SEE DETAIL “A” SEE DETAIL “B” O - 13 O 0.10 C 0.05 (N-4)X e

0.20 C A-B D

7.95 REF. 1.0 DIA. PIN#1 & EJECTOR PIN DP N 0.089 0.0381 Top View Side View Bottom View E/2 7.95 E 3 5 E1 E1/2 D1/2 7.50 REF. 7.50 REF. 5 7 D C Cccc SEATING PLANE D D/2 A 3 H A 1. All dimensioning and tolerances confirm to ASME Y14.5-1994. 2. Datum plane H located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and D to be determined at centerline between leads where leads exit plastic body at datum plane H. 4. To be determined at seating plane C. 5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 mm per side. Dimension D1 and E1 include mold mismatch and are determined at datum plane H. 6. N is number of terminals. DETAIL “A” DETAIL “B” DETAIL “C” e / 2 81 0 b WITH LEAD FINISH BASE METAL 0.08 O MIN. 0-7 O 0.08/0.20 R. GAUGE PLANE R. MIN. 0.20 MIN. 1.00 REF. A, B, OR D 0.05 0.25 ddd M C A-B D 7. Package top dimensions are smaller than bottom dimensions by 0.10 millimeters and top of package will not overhang bottom of package. 8. Dimension b does not include damber protrusion. Allowable damber protrusion shall be not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Damber can not be located on the lower radius or the foot. 9. All dimensions are in millimeters. 10. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 11. This drawing conforms to JEDEC registered outline m2s-026-c, variation BFB. 12. A1 is defined as the distance from the seating plane to the lowest point of the package body. GATE PIN 1.50

0.20 A-BHD4

SmartFusion2 Pin Descriptions DS0115 Datasheet Revision 12.0 41

2.14.8.1 Pin Tables

Pin tables for the TQ144 package depicted in the preceding figure are found in the Excel spreadsheet located here: http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=133134 The following devices are available in the TQ144: M2S010 and M2S005 (S) For more information on mechanical drawings, see the PD3068: Package Mechanical Drawings.