DRV8143PQDGQRQ1

DRV8143-Q1_V01 TI | Alldatasheet

Document overview

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Technical content

DRV8143-Q1 Automotive Half Bridge Driver with Integrated Current Sense and Diagnostics

1 Features

• AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA
• Documentation available to aid functional safety system design
• 4.5-V to 35-V (40-V abs. max) operating range
• SPI(S) or HW(H) variant in VQFN-HR package: RON_LS + RON_HS: 42 mΩ
• SPI(P) variant in HVSSOP package: RON_LS + RON_HS: 49 mΩ
• IOUT Max = 20 A
• PWM frequency operation up to 125 KHz with automatic dead time assertion
• Configurable slew rate and spread spectrum clocking for low electromagnetic interference (EMI)
• Integrated current sense (eliminates shunt resistor)
• Proportional load current output on IPROPI pin
• Configurable current regulation
• Protection and diagnostic features with configurable fault reaction (latched or retry) – Load diagnostics in both the off-state and on- state to detect open load and short circuit – Voltage monitoring on supply (VM) and charge pump (VCP) – Over current protection – Over temperature protection – Fault indication on nFAULT pin
• Supports 3.3-V, 5-V logic inputs
• Low sleep current - 1μA typical at 25°C
• Device family comparison table

2 Applications

• Automotive brushed DC motors, Solenoids
• Door modules and seat modules
• Body control module (BCM)
• Fuel, water, oil pumps
• On board charger

3 Description

The DRV814x-Q1 family of devices is a fully integrated half-bridge driver intended for a wide range of automotive applications. Designed in a BiCMOS high power process technology node, this monolithic family of devices in a power package offer excellent power handling and thermal capability while providing compact package size, ease of layout, EMI control, accurate current sense, robustness, and diagnostic capability. This family provides an identical pin function with scalable R ON (current capability) to support different loads. The devices integrate a N-channel half-bridge, charge pump regulator, high-side current sensing with regulation, current proportional output, and protection circuitry. A low-power sleep mode is provided to achieve low quiescent current. The devices offer voltage monitoring and load diagnostics as well as protection features against over current and over temperature. Fault conditions are indicated on nFAULT pin. DRV8143 and DRV8145 are available in three variants - hardwired interface: HW (H) and two SPI interface variants: SPI(P) and SPI(S), with SPI (P) for externally supplied logic supply and SPI (S) for internally generated logic supply. DRV8144 is available only in two variants: SPI(S) and HW(H). The SPI interface variants offer more flexibility in device configuration and fault observability. Device Information(1) PART NUMBER PACKAGE BODY SIZE (nominal) DRV8143-Q1 VQFN-HR (14) 3 mm X 4.5 mm DRV8143-Q1 HVSSOP (28) 3 mm X 7.3 mm (1) For all available packages, see the orderable addendum at the end of the data sheet DRV814X-Q1 Half Bridge Driver 4.5 - 35 V Built-in Protec on Current Regula on Current Sense Diagnos cs Controller Driver Control IPROPI nSLEEP CONFIG pins (HW variant) nFAULT SPI (SPI variant) ADC IOs Simplified Schematic DRV8143-Q1 SLVSG63 – JANUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2023 * Initial Release DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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5 Device Comparison

Table 5-1 summarizes the RON and package differences between devices in the family. Table 5-1. Device Comparison PART NUMBER(1) (LS + HS) RON IOUT MAX PACKAGE BODY SIZE (nominal) Variants DRV8143-Q1 42 mΩ 20 A VQFN-HR (14) 3 mm X 4.5 mm HW (H), SPI (S) DRV8143-Q1 49 mΩ 20 A HVSSOP (28) 3 mm X 7.3 mm SPI (P) DRV8144-Q1 23.6 mΩ 30 A VQFN-HR (16) 3 mm X 6 mm HW (H), SPI (S) DRV8145-Q1 16 mΩ 46 A VQFN-HR (16) 3.5 mm X 5.5 mm HW (H), SPI (S) DRV8145-Q1 19 mΩ 46 A HTSSOP (28) 4.4 mm X 9.7 mm SPI (P) (1) This is the product datasheet for the DRV8143-Q1. Please reference other device variant data sheets for additional information. Table 5-2 summarizes the feature differences between the SPI and HW interface variants in the DRV814X- Q1 family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback, redundant driver shutoff, improved Pin FMEA and additional features. In addition, the SPI variant has two options - SPI (S) variant and SPI (P) variant . The SPI (P) variant supports an external, low voltage 5 V supply to the device through the VDD pin for the device logic, whereas in the SPI (S) variant, this supply is internally derived from the VM pin. With this external logic supply, the SPI (P) variant avoids device brown out (reset of device) during VM under voltage transients. Table 5-2. SPI Variant vs HW Variant Comparison FUNCTION HW (H) Variant SPI (S) Variant SPI (P) Variant Bridge control Pin only Individual pin "and/or" register bit with pin status indication (Refer Register Pin control) Sleep function Available through nSLEEP pin Not available External logic supply to the device Not supported Not supported Supported through VDD pin Clear fault command Reset pulse on nSLEEP pin SPI CLR_FAULT command Slew rate 6 levels 8 levels Over current protection (OCP) Fixed at the highest setting 3 choices for thresholds, 4 choices for filter time ITRIP regulation 5 levels with disable & fixed TOFF time 7 levels with disable & indication, with programmable TOFF time Individual fault reaction configuration between retry or latched behavior Not supported, either all latched or all retry Supported Detailed fault logging and device status feedback Not supported, nFAULT pin monitoring necessary Supported, nFAULT pin monitoring optional VM over voltage Fixed 4 threshold choices On-state (Active) diagnostics Not supported Supported for high-side loads Spread spectrum clocking (SSC) Not supported Supported Table 5-3. Differentiating between devices in the family Device Package Symbolization DEVICE_ID Register DRV8143H-Q1 8143H Not applicable DRV8144H-Q1 8144H Not applicable DRV8145H-Q1 8145H Not applicable DRV8143S-Q1 8143S 0 x BA DRV8144S-Q1 8144S 0 x CA DRV8145S-Q1 8145S 0 x DA DRV8143P-Q1 8143P 0 x BE DRV8145P-Q1 8145P 0 x DE www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRV8143-Q1

6 Pin Configuration and Functions

6.1 HW Variant

6.1.1 VQFN-HR (14) package

Figure 6-1. DRV8143H-Q1 HW variant in VQFN-HR (14) package Table 6-1. Pin Functions PIN TYPE (1) DESCRIPTION NO. NAME 1 nFAULT OD Fault indication to the controller. For details, refer to nFAULT in the Device Configuration section. 2 IPROPI I/O Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration section. 3 nSLEEP I Controller input pin for SLEEP. For details, see the Bridge Control section. 4 VM P Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. 5,7 OUT P Half-bridge output. Connect this pin to the motor or load. Must combine with the other OUT pin to support device current capability.

6 GND G Ground pin

8 VCP P Charge Pump pin for storage cap. Connect a 6.3V, 1µF capacitor to VM supply. 9 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section. 10 IN I Controller input pin for bridge operation. For details, see the Bridge Control section. 11 DIAG I Device configuration pin for load type indication. For details, refer to DIAG in the Device Configuration section 12 SR I Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device Configuration section. 13 ITRIP I Device configuration pin for ITRIP level for high-side current limiting . For details, refer to ITRIP in the Device Configuration section. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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Table 6-1. Pin Functions (continued) PIN TYPE (1) DESCRIPTION NO. NAME

14 NC I No connect

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

6.2 SPI Variant

6.2.1 HVSSOP (28) package

SPI (P) variant VCP Figure 6-2. DRV8143P-Q1 SPI(P) variant in HVSSOP (28) package Table 6-2. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 SCLK I SPI - Serial Clock input. 2 nSCS I SPI - Chip Select. An active low on this pin enables the serial interface communication. 3 IN I Controller input pin for bridge operation. For details, see the Bridge Control section. 4 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section. 5 VCP P Charge Pump pin for storage cap. Connect a 6.3V, 1µF capacitor to VM supply. 6, 7, 8, 21, 22, 23 VM P Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins (6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. 9, 10, 11, 18, 19, 20 OUT P Half-bridge output. Connect this pin to the motor or load. Must combine with the rest of OUT pins (6 total) to support device current capability. 12, 13, 14, 15, 16, 17 GND G Ground pin. Must combine with the rest of GND pins (6 total) to support device current capability. 24 VDD P Logic power supply to the device. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV8143-Q1

Table 6-2. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NO. NAME 25 IPROPI I/O Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration section. 26 nFAULT OD Fault indication to the controller. For details, refer to nFAULT in the Device Configuration section. 27 SDO PP SPI - Serial Data Output. Data is updated at the rising edge of SCLK. 28 SDI I SPI - Serial Data Input. Data is captured at the falling edge of SCLK. (1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

6.2.2 VQFN-HR (14) package

GNDGNDGNDGND GND GND GND GND TOP VIEW Figure 6-3. DRV8143S-Q1 SPI(S) variant in VQFN-HR (14) package Table 6-3. Pin Functions PIN TYPE (1) DESCRIPTION NO. NAME 1 nFAULT OD Fault indication to the controller. For details, refer to nFAULT in the Device Configuration section. 2 IPROPI I/O Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration section. 3 nSLEEP I Controller input pin for SLEEP. For details, see the Bridge Control section. 4 VM P Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. 5,7 OUT P Half-bridge output. Connect this pin to the motor or load. Must combine with the other OUT pin to support device current capability. 8 VCP P Charge Pump pin for storage cap. Connect a 6.3V, 1µF capacitor to VM supply. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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Table 6-3. Pin Functions (continued) PIN TYPE (1) DESCRIPTION NO. NAME 9 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section. 10 IN I Controller input pin for bridge operation. For details, see the Bridge Control section. 11 nSCS I SPI - Chip Select. An active low on this pin enables the serial interface communication. 12 SCLK I SPI - Serial Clock input. 13 SDI I SPI - Serial Data Input. Data is captured at the falling edge of SCLK. Also VIO logic level for SDO. 14 SDO PP SPI - Serial Data Output. Data is updated at the rising edge of SCLK. (1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRV8143-Q1

7 Specifications

7.1 Absolute Maximum Ratings

Over operating temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply pin voltage VM –0.3(3) 40 V Power supply transient voltage ramp VM 2 V/µs Charge pump pin voltage VCP VVM – 0.3 VVM + 7 V Output pin voltage OUT -0.9 VVM + 0.9 V Output pin current OUT Internally limited(2) A Driver disable pin voltage DRVOFF –0.3 40 V Logic I/O voltage IN, nFAULT –0.3 5.75 V HW variant - Configuration pins voltage ITRIP, SR, DIAG –0.3 5.75 V Analog feedback pin voltage IPROPI –0.3 5.75 V Sleep pin voltage (Not applicable for SPI (P) variant) nSLEEP –0.3 40 V SPI I/O voltage - SPI variant SDI, SDO, nSCS, SCLK –0.3 5.75 V SPI (P) variant - Logic supply VDD -0.3 5.75 V SPI (P) variant - Logic supply transient voltage ramp VDD 5 V/µs Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Limited by the over current and over temperature protection functions of the device (3) With external component support, short duration violation of this limit can be tolerated during ISO 7637 transient pulse testing

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 VM, OUT, GND ±4000 V All other pins ±2000 Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B Corner pins ±750 Other pins ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted) MIN MAX UNIT VVM Power supply voltage VM 4.5 35(1) V VVDD SPI (P) variant - Logic supply voltage VDD 4.5 5.5 V VVCP Charge pump pin voltage VCP VVM VVM+5.5 V VLOGIC Logic pin voltage IN, nSLEEP, DRVOFF, nFAULT 0 5.5 V fPWM PWM frequency IN 0 125 KHz VCONFIG HW variant - Configuration pin voltage ITRIP, SR, DIAG 0 5.5 V VIPROPI Analog feedback voltage IPROPI 0 5.5 V VSPI_IOS SPI (S) variant - SPI pin voltage SDI, SDO, nSCS, SCLK 0 VnSLEEP + 0.5 V SPI (P) variant - SPI pin voltage SDI, SDO, nSCS, SCLK 0 VVDD + 0.5 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C (1) The over current protection function does not support short on OUT to VM or GND above 28 V for short inductance < 1 μH.

7.4 Thermal Information

Refer Transient thermal impedance table for application related use case. THERMAL METRIC(1) HVSSOP package VQFN-HR package UNIT RθJA Junction-to-ambient thermal resistance 31.0 48.4 °C/W RθJC(top) Junction-to-case(top) thermal resistance 29.1 22.3 °C/W RθJB Junction-to-board thermal resistance 9.3 8.1 °C/W ΨJT Junction-to-top characterization parameter 1.4 0.5 °C/W ΨJB Junction-to-board characterization parameter 9.3 7.9 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance 1.3 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

4.5 V (falling) ≤ VVM ≤ 35 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted)

For SPI (P) variant only: 4.5 V ≤ VVDD ≤ 5.5 V (unless otherwise noted)

7.5.1 Power Supply & Initialization

Refer wake up transient waveforms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVM_REV Supply pin voltage during reverse current IVM = - 5 A, device in unpowered state 1.4 V IVMQ VM current in SLEEP state VVM = 13.5 V, VnSLEEP = 0 V or VVDD < PORVDD_FALL, TA = 25°C 1 µA VVM = 13.5 V, VnSLEEP = 0 V or VVDD < PORVDD_FALL, TA = 125°C 5.8 µA IVMS VM current in STANDBY state VVM = 13.5 V 3 5 mA IVDD VDD current in ACTIVE state SPI (P) variant 10 mA tRESET RESET pulse filter time Reset signal on nSLEEP pin for HW (H) variant 5 20 µs tSLEEP SLEEP command filter time Sleep signal on nSLEEP pin for HW (H) variant 40 120 µs www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRV8143-Q1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tSLEEP_SPI SLEEP command filter time Sleep signal on nSLEEP pin for SPI (S) variant 5 20 µs tWAKEUP Wake-up command filter time Wake-up signal on nSLEEP pin for HW (H) and SPI (S) variants 10 µs tCOM Time for communication to be available after wake-up or power-up through VM or VDD supply pin Wake-up signal on nSLEEP pin or power cycle - VVM > VMPOR_RISE or VVDD > VDDPOR_RISE 400 µs tREADY Time for driver ready to be driven after wake-up through nSLEEP pin or power- up through VM or VDD supply pin Wake-up signal on nSLEEP pin or power cycle - VVM > VMPOR_RISE or VVDD > VDDPOR_RISE, 1 μF cap on VCP pin 3.5 ms VVCP Charge pump regulator voltage VVM > 7 V VVM+5 V fVCP Average Charge pump switching frequency 20 MHz

7.5.2 Logic I/Os

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL_nSLEEP Input logic low voltage nSLEEP pin 0.65 V VIH_nSLEEP Input logic high voltage nSLEEP pin 1.55 V VIHYS_nSLEE P Input hysteresis nSLEEP pin 200 mV VIL Input logic low voltage DRVOFF, IN pins 0.7 V VIH Input logic high voltage DRVOFF, IN pins 1.5 V VIHYS Input hysteresis DRVOFF, IN pins 100 mV RPD_nSLEEP Internal pull-down resistance on nSLEEP to GND Measured at min VIL level 100 400 KΩ RPU Internal pull-up resistance to VDD (reverse current blocked) on DRVOFF Measured at min VIH level 200 550 KΩ RPD Internal pull-down resistance to GND on IN Measured at max VIL level 200 500 KΩ InFAULT_PD Sink current to GND on nFAULT pin when asserted low VnFAULT = 0.3 V 5 mA

7.5.3 SPI I/Os

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPU_nSCS Internal pull-up resistance to VDD (reverse current blocked) on nSCS Measured at min VIH level 200 500 KΩ RPD_SPI Internal pull-down resistance to GND on SDI, SCLK Measured at max VIL level 150 500 KΩ VIL Input logic low voltage SDI, SCLK, nSCS pins 0.7 V VIH Input logic high voltage SDI, SCLK, nSCS pins 1.5 V VIHYS Input hysteresis SDI, SCLK, nSCS pins 100 mV VOL_SDO Output logic low voltage 0.5 mA sink into SDO 0.4 V VOH_SDO Output logic high voltage for SPI (S) variant 0.5 mA source from SDO, VnSLEEP = 5 V, VVM > 7 V 4.1 V 0.5 mA source from SDO, VnSLEEP = 3.3 V, VVM > 5 V 2.7 V Output logic high voltage for SPI (P) variant 0.5 mA source from SDO, VVDD = 5 V 4.5 V DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH_SDO_NL Output logic high voltage at no load on SDO, valid only for SPI (S) variant No current from SDO, VnSLEEP = 5 V, VVM > 7 V 5.5 V No current from SDO, VnSLEEP = 3.3 V, VVM > 5 V 3.8 V

7.5.4 Configuration Pins - HW Variant Only

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 6 level setting for ITRIP, SR and DIAG RLVL1OF6 Level 1 of 6 Connect to GND 10 Ω RLVL2OF6 Level 2 of 6 +/- 10% resistor to GND 7.4 8.2 9 KΩ RLVL3OF6 Level 3 of 6 +/- 10% resistor to GND 19.8 22 24.2 KΩ RLVL4OF6 Level 4 of 6 +/- 10% resistor to GND 42.3 47 51.7 KΩ RLVL5OF6 Level 5 of 6 +/- 10% resistor to GND 90 100 110 KΩ RLVL6OF6 Level 6 of 6 Hi-Z (no connect) 250 KΩ

7.5.5 Power FET Parameters

Measured at VVM = 13.5 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RHS_ON High-side FET on resistance, HVSSOP package IOUT = 6 A, TJ = 25°C 24.5 mΩ IOUT = 6 A, TJ = 150°C 46.6 mΩ High-side FET on resistance, VQFN-HR package IOUT = 6 A, TJ = 25°C 21 mΩ IOUT = 6 A, TJ = 150°C 39.9 mΩ RLS_ON Low-side FET on resistance, HVSSOP package IOUT = 6 A, TJ = 25°C 24.5 mΩ IOUT = 6 A, TJ = 150°C 46.6 mΩ Low-side FET on resistance, VQFN-HR package IOUT = 6 A, TJ = 25°C 21 mΩ IOUT = 6 A, TJ = 150°C 39.9 mΩ VSD Low-side & High-side FET source-drain voltage when body diode is forward biased IOUT = +/- 6 A(both directions) 0.4 0.9 1.5 V RHi-Z OUT resistance to GND in SLEEP or STANDBY state VOUTx = VVM = 13.5 V 1.4 64 KΩ

7.5.6 Switching Parameters with High-Side Recirculation

Load = 1.5mH / 4.7 Ohm, VVM = 13.5 V, refer high-side recirculation waveform PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SRLSOFF Output voltage rise time, 10% - 90% SR = 3'b000 or LVL2 1.7 V/µs SR = 3'b001 (SPI only) 4.8 V/µs SR = 3'b010 (SPI only) 8.1 V/µs SR = 3'b011 or LVL3 14 V/µs SR = 3'b100 or LVL4 19.9 V/µs SR = 3'b101 or LVL1 25.7 V/µs SR = 3'b110 or LVL6 36.4 V/µs SR = 3'b111 or LVL5 45.8 V/µs www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRV8143-Q1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPD_LSOFF Propagation time during output voltage rise SR = 3'b000 or LVL2 1.2 µs SR = 3'b001 (SPI only) 0.9 µs SR = 3'b010 (SPI only) 0.8 µs SR = 3'b011 or LVL3 0.7 µs SR = 3'b100 & 3'b101 or LVL4 & LVL1 0.5 µs SR = 3'b110 & 3'b111 or LVL6 & LVL5 0.4 µs tDEAD_LSOFF Dead time during output voltage rise All SRs 0.9 µs SRLSON Output voltage fall time, 90% - 10% SR = 3'b000 or LVL2 1.7 V/µs SR = 3'b001 (SPI only) 4.8 V/µs SR = 3'b010 (SPI only) 8.1 V/µs SR = 3'b011 or LVL3 14 V/µs SR = 3'b100 or LVL4 19.9 V/µs SR = 3'b101 or LVL1 25.7 V/µs SR = 3'b110 or LVL6 36.4 V/µs SR = 3'b111 or LVL5 45.8 V/µs tPD_LSON Propagation time during output voltage fall SR = 3'b000 or LVL2 1.5 µs SR = 3'b001 (SPI only) 0.9 µs SR = 3'b010 (SPI only) 0.6 µs SR = 3'b011 or LVL3 0.5 µs SR = 3'b100 or LVL4 0.4 µs SR = 3'b101 or LVL1 0.35 µs SR = 3'b110 & 3'b111 or LVL6 & LVL5 0.3 µs tDEAD_LSON Dead time during output voltage fall SR = 3'b000 or LVL2 2.2 µs SR = 3'b001 (SPI only) 1 µs SR = 3'b010 (SPI only) 1 µs SR = 3'b011 or LVL3 0.7 µs All other SRs 0.6 µs MatchSRLS Output voltage rise and fall slew rate matching All SRs -20 +20 % DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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7.5.7 Switching Parameters with Low-Side Recirculation

Load = 1.5 mH / 4.7 Ohm, VVM = 13.5 V, refer low-side recirculation waveform PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SRHSON Output voltage rise time, 10% - 90% SR = 3'b000 or LVL2 1.8 V/µs SR = 3'b001 (SPI only) 5.7 V/µs SR = 3'b010 (SPI only) 3.1 V/µs SR = 3'b011 or LVL3 8.7 V/µs SR = 3'b100 or LVL4 14.4 V/µs SR = 3'b101 or LVL1 20.1 V/µs SR = 3'b110 or LVL6 30.7 V/µs SR = 3'b111 or LVL5 40.3 V/µs tPD_HSON Propagation time during output voltage rise SR = 3'b000 or LVL2 3.2 µs SR = 3'b001 (SPI only) 1.7 µs SR = 3'b010 (SPI only) 1.2 µs SR = 3'b011 or LVL3 1 µs All other SRs 0.9 µs tDEAD_HSON Dead time during output voltage rise SR = 3'b000 or LVL2 2.4 µs SR = 3'b001 (SPI only) 5.1 µs SR = 3'b010 (SPI only) 1.2 µs All other SRs 0.5 µs SRHSOFF Output voltage fall time, 90% - 10% SR = 3'b000 or LVL2 2.5 V/µs SR = 3'b001 (SPI only) 5.7 V/µs SR = 3'b010 (SPI only) 8.6 V/µs SR = 3'b011 or LVL3 14.1 V/µs SR = 3'b100 or LVL4 19.7 V/µs SR = 3'b101 or LVL1 25.1 V/µs SR = 3'b110 or LVL6 35 V/µs SR = 3'b111 or LVL5 43.6 V/µs tPD_HSOFF Propagation time during output voltage fall All SRs 0.25 µs tDEAD_HSOFF Dead time during output voltage fall All SRs 0.3 µs tBLANK Current regulation blanking time after OUT slewing for current sense output to settle (Valid for only for LS recirculation) SR = 3'b000 or LVL2 10.8 µs SR = 3'b001 or 3'b010 (SPI only) 3.5 µs All other SRs 2.5 µs www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRV8143-Q1

7.5.8 IPROPI & ITRIP Regulation

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AIPROPI Current scaling factor, HVSSOP package 3040 A/A Current scaling factor, VQFN-HR package 3050 A/A AI_ERR Current scaling factor 1.6 A < IOUT < 8.6 A -5 +5 % 0.4 A < IOUT ≤ 1.6 A -20 +20 % 0.2 A < IOUT ≤ 0.4 A -50 +50 % OffsetIPROPI Offset current on IPROPI at no load current IOUT = 0 A 15 µA BWIPROPI Bandwidth of the IPROPI internal sense circuit No external capacitor on IPROPI. 400 KHz VIPROPI_LIM Internal clamping voltage on IPROPI 4.5 5.5 V VITRIP_LVL Voltage limit on VIPROPI to trigger TOFF cycle for ITRIP regulation ITRIP = 3'b001 or LVL2 1.06 1.18 1.3 V ITRIP = 3'b010 (SPI only) 1.27 1.41 1.55 V ITRIP = 3'b011 (SPI only) 1.49 1.65 1.82 V ITRIP = 3'b100 or LVL3 1.78 1.98 2.18 V ITRIP = 3'b101 or LVL4 2.08 2.31 2.54 V ITRIP = 3'b110 or LVL5 2.38 2.64 2.9 V ITRIP = 3'b111 or LVL6 2.67 2.97 3.27 V tOFF ITRIP regulation - off time TOFF = 2'b00 (SPI only) 16 20 25 µs TOFF = 2'b01 (SPI). Only choice for HW 24 30 36 µs TOFF = 2'b10 (SPI only) 33 40 48 µs TOFF = 2'b11 (SPI only) 41 50 61 µs

7.5.9 Over Current Protection (OCP)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOCP_HS Over current protection threshold on the high side OCP_SEL = 2'b00 (SPI), Only choice for HW 24 48 A OCP_SEL = 2'b10 (SPI only) 18 36 A OCP_SEL = 2'b01 (SPI only) 12 28 A IOCP_LS Over current protection threshold on the low side OCP_SEL = 2'b00 (SPI), Only choice for HW 24 48 A OCP_SEL = 2'b10 (SPI only) 18 36 A OCP_SEL = 2'b01 (SPI only) 12 28 A tOCP Over current protection deglitch time TOCP_SEL = 2'b00 (SPI), Only choice for HW 4.5 6 7.3 µs Over current protection deglitch time TOCP_SEL = 2'b01 (SPI only) 2.2 3 4.1 µs Over current protection deglitch time TOCP_SEL = 2'b10 (SPI only) 1.1 1.5 2.3 µs Over current protection deglitch time TOCP_SEL = 2'b11 (SPI only) 0.15 0.2 0.4 µs

7.5.10 Over Temperature Protection (TSD)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TTSD Thermal shutdown temperature 155 170 185 °C THYS Thermal shutdown hysteresis 30 °C tTSD Thermal shutdown deglitch time 10 12 19 µs DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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7.5.11 Voltage Monitoring

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVMOV VM over voltage threshold while rising VMOV_SEL = 2'b00 (SPI), Only choice in HW variant 33.6 37 V VMOV_SEL = 2'b01 (SPI only) 28 31 V VMOV_SEL = 2'b10 (SPI only) 18 21 V VVMOV_HYS VM over voltage hysteresis 0.6 V tVMOV VM over voltage deglitch time 10 12 19 µs VVMUV VM under voltage threshold while falling 4.2 4.5 V VVMUV_HYS VM under voltage hysteresis 200 mV tVMUV VM under voltage deglitch time 8 12 19 µs VMPOR_FALL VM voltage at which device goes into POR Applicable for HW & SPI (S) variant 3.6 V VMPOR_RISE VM voltage at which device comes out of POR Applicable for HW & SPI (S) variant 3.9 V VDDPOR_FAL L VDD voltage at which device goes into POR Applicable for SPI (P) variant 3.5 V VDDPOR_RIS E VDD voltage at which device comes out of POR Applicable for SPI (P) variant 3.8 V VCPUV Charge pump under-voltage threshold while falling VVM+2.5 V tCPUV Charge pump deglitch time 10 12 19 µs

7.5.12 Load Monitoring

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Off-state diagnostics (OLP) RS_GND Resistance on OUT to GND that will be detected as short 1 KΩ RS_VM Resistance on OUT to VM that will be detected as short 1 KΩ ROPEN_LS Resistance on OUT to GND that will be detected as open Valid for low-side load 2 KΩ ROPEN_HS Resistance on OUT to VM that will be detected as open Valid for high-side load, VVM = 13.5 V 10 KΩ VOLP_REFH OLP Comparator Reference High 2.65 V VOLP_REFL OLP Comparator Reference Low 2 V ROLP_PU Internal pull-up resistance on OUT to VDD during OLP VOUTx = VOLP_REFH + 0.1V 1 KΩ ROLP_PD Internal pull-down resistance on OUT to GND during OLP VOUTx = VOLP_REFL - 0.1V 1 KΩ SPI variant only - On-state diagnostics (OLA) IPD_OLA Internal sink current on OUT to GND during dead-time in high-side recirculation 0.1 10 mA VOLA_REF Comparator Reference with respect to VM used for OLA 0.25 V

7.5.13 Fault Retry Setting

Refer to retry setting waveform PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tRETRY Automatic driver retry time Fault reaction set to RETRY 4.1 5 6.1 ms www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV8143-Q1

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tCLEAR Fault free operation time to auto-clear from over current event Fault reaction set to RETRY 85 200 µs tCLEAR_TSD Fault free operation time to auto-clear from over temperature event Fault reaction set to RETRY 4.2 6.7 ms

7.5.14 Transient Thermal Impedance & Current Capability

Information based on thermal simulations Table 7-1. Transient Thermal Impedance (RθJA) and Current Capability - half-bridge PART NUMBER PACKA GE RθJA °C/W Current A without PWM(3) with PWM(4) 0.1 sec 1 sec 10 sec DC 0.1 sec 1 sec 10 sec DC 10 sec DC DRV8143-Q1 VQFN- (1) Based on thermal simulations using 40 mm x 40 mm x 1.6 mm 4 layer PCB – 2 oz Cu on top and bottom layers, 1 oz Cu on internal planes with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 minimum mm via pitch. (2) Estimated transient current capability at 85 °C ambient temperature for junction temperature rise up to 150°C (3) Only conduction losses (I2R) considered (4) Switching loss roughly estimated by the following equation: PSW = VVM x ILoad x fPWM x VVM/SR, where VVM = 13.5 V, fPWM = 20 KHz, SR = 23 V/µs (1)

7.6 SPI Timing Requirements

tSCLK SCLK minimum period(1) 100 ns tSCLKH SCLK minimum high time 50 ns tSCLKL SCLK minimum low time 50 ns tHI_nSCS nSCS minimum high time 300 ns tSU_nSCS nSCS input setup time 25 ns tH_nSCS nSCS input hold time 25 ns tSU_SDI SDI input data setup time 25 ns tH_SDI SDI input data hold time 25 ns tEN_SDO SDO enable delay time(1) 35 ns tDIS_SDO SDO disable delay time(1) 100 ns (1) SPI (S) variant: SDO delay times are valid only with SDO external load of 5 pF. With a 20 pF load on SDO, there is an additional delay on SDO, which results in a 25% increase in SCLK minimum time, limiting the SCLK to a maximum of 8 MHz. There is NO such limitation for the SPI (P) variant. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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tHI_nSCS tSU_nSCS tSCLK tSCLKH tSCLKL MSB LSB tH_SDItSU_SDI Z ZMSB LSB tH_nSCS tDIS_SDO X X tEN_SDO DON’T CARE HI-Z DON’T CARE HI-Z nSCS SCLK SDI SDO SDI capture point Write Command executed by device SDO propogate point Figure 7-1. SPI Peripheral-Mode Timing Definition www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRV8143-Q1

7.7 Switching Waveforms

This section illustrates the switching transients for an inductive load due to external PWM or internal ITRIP regulation.

7.7.1.1 High-Side Recirculation

8, 174, 5, 631, 2 187654321 LOAD LOAD LOAD LOAD LOAD GNDOUT E.g. High side load, OUT is switching VM tPD_LSOFF SRLSOFF tDEAD_LSOFF tPD_LSON 10% 90% tDEAD_LSON SRLSON 10% 90% VM + VD(FET BODY DIODE) High side recircula on Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF) Isense NOT OK ~SRHSON Accuracy not applicable ~SRHSOFF Accuracy not applicable “fPWM” @ duty cycle “1-D” IN Figure 7-2. Output Switching Transients with High-Side Recirculation DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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7.7.1.2 Low-Side Recirculation

4, 5, 631, 2 187654321 LOAD LOAD LOAD LOAD 8, 1 LOAD VM IN OUT E.g. Low side load, OUT is switching GND Isense OK GND - VD(FET BODY DIODE) tPD_HSOFF SRHSOFF 10% 90% SRHSON 10% 90% tDEAD_HSON ~SRLSOFF Accuracy not applicable tPD_HSON ~SRLSON Accuracy not applicable tDEAD_HSOFF tBLANK Low side recircula on Slew rate controlled by High Side Driver (SRHSON & SRHSOFF) Isense OK Isense NOT OK Figure 7-3. Output Switching Transients with Low-Side Recirculation

7.7.2 Wake-up Transients

7.7.2.1 HW Variant

Figure 7-4. Wake-up from SLEEP State to STANDBY State Transition for HW Variant Hand shake between controller and device during wake-up as follows:

• t0: Controller - nSLEEP asserted high to initiate device wake-up
• t1: Device internal state - Wake-up command registered by device (end of Sleep state)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device wake-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DRV8143-Q1

nSLEEP= 1'b1 nFAULT Internal nPOR VM VVMUV_HYST tREADY tCOM tRESET VVMUV nSLEEP RESET pulse ACK VMPOR_FALL VMPOR_RISE Figure 7-5. Power-up to STANDBY State Transition for HW Variant Hand shake between controller and device during power-up as follows:

• t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
• t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state

7.7.2.2 SPI Variant

CLR_FLT cmd ACK CLR_FLT cmd Figure 7-6. Wake-up from SLEEP State to STANDBY State Transition for SPI (S) Variant Hand shake between controller and device during a wake-up transient as follows:

• t0: Controller - nSLEEP asserted high to initiate device wake-up
• t1: Device internal state - Wake-up command registered by device (end of Sleep state)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wake-up
• t5: Device - nFAULT de-asserted as an acknowledgment of nSLEEP reset pulse. Device in STANDBY state DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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7.7.3 Fault Reaction Transients

7.7.3.1 Retry setting

Valid for both SPI and HW variants tCLEAR nFAULT I(VM) tRETRY IOCP tOCP tRETRY External short to ground fault ILOAD tOCP tOCP IVMQ Figure 7-9. Fault reaction with RETRY setting (shown for OCP occurrence on high-side when OUT is shorted to ground) Short occurrence and recovery scenario with RETRY setting:

• t1: An external short occurs.
• t2: OCP (Over Current Protection) fault confirmed after tOCP, output disabled, nFAULT asserted low to indicate fault.
• t3: Device automatically attempts retry (auto retry) after tRETRY. Each time output is briefly turned on to confirm short occurrence and then immediately disabled after tOCP. nFAULT remains asserted low through out. Cycle repeats till driver is disabled by the user or external short is removed, as illustrated further. Note that, in case of a TSD (Thermal Shut Down) event, automatic retry time depends on the cool off based on thermal hysteresis.
• t4: The external short is removed.
• t5: Device attempts auto retry. But this time, no fault occurs and device continues to keep the output enabled.
• t6: After a fault free operation for a period of tCLEAR is confirmed, nFAULT is de-asserted.
• SPI variant only – Fault status remains latched till a CLR_FLT command is issued. Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will continue to be pulled up to V IPROPI_LIM voltage to indicate this type of short, while the output is disabled. This is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other faults. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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7.7.3.2 Latch setting

Valid for both SPI and HW variants nFAULT I(VM) IOCP tOCP External short to ground fault ILOAD tOCP IVMQ CLR_FLT CMD (SPI) / nSLEEP RESET PULSE (HW) Figure 7-10. Fault reaction with Latch setting (shown for OCP occurrence on high-side when OUT is shorted to ground) Short occurrence and recovery scenario with LATCH setting:

• t1: An external short occurs.
• t2: OCP (Over Current Protection) fault confirmed after tOCP, output disabled, nFAULT asserted low to indicate fault.
• t3: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT is de-asserted and output is enabled. OCP fault is detected again and output is disabled with nFAULT asserted low.
• t4: The external short is removed.
• t5: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT is de-asserted and output is enabled. Normal operation resumes.
• SPI variant only – Fault status remains latched till a CLR_FLT command is issued. Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will continue to be pulled up to V IPROPI_LIM voltage to indicate this type of short, while the output is disabled. This is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other faults.

7.8 Typical Characteristics

Temperature [  C] FET RON [m  ] -40 -20 0 20 40 60 80 100 120 140 160 17.5 22.5 27.5 32.5 37.5 LS FET - VQFN-HR HS FET - VQFN-HR LS FET - HVSSOP HS FET - HVSSOP Figure 7-11. RHS_ON & RLS_ON vs Temperature at VVM = 13.5 V Figure 7-12. AIPROPI Gain Error vs Load Current at VVM = 13.5 V www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: DRV8143-Q1

Temperature [  C] LS OCP Threshold [A] -40 -20 0 20 40 60 80 100 120 140 160 OCP_SEL = 0 OCP_SEL = 2 OCP_SEL = 1 Figure 7-13. LS OCP Threshold vs Temperature at VVM = 13.5 V Temperature [  C] HS OCP Threshold [A] -40 -20 0 20 40 60 80 100 120 140 160 OCP_SEL = 0 OCP_SEL = 2 OCP_SEL = 1 Figure 7-14. HS OCP Threshold vs Temperature at VVM = 13.5 V Temperature [  C] Standby current [mA] -40 -20 0 20 40 60 80 100 120 140 160 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3.05 3.1 VM 5V VM 13.5V VM 25V VM 35V Figure 7-15. Current on VM in STANDBY state vs Temperature Temperature [  C] Sleep current [ A] -40 -20 0 20 40 60 80 100 120 140 160 0.5 1.5 2.5 3.5 4.5 VM 5V VM 13.5V VM 25V VM 35V Figure 7-16. Current on VM in SLEEP state vs Temperature Input duty cycle [%] on IN pin at 5 KHz PWM Measured OUT duty cycle [%] 0 10 20 30 40 50 60 70 80 90 100 100 SR = 3'b000 SR = 3'b001 SR = 3'b010 SR = 3'b011 SR = 3'b100 SR = 3'b101 SR = 3'b110 SR = 3'b111 Figure 7-17. Measured Duty Cycle vs Input Duty Cycle at PWM frequency of 5 KHz at VVM = 13.5 V for HS recirculation Figure 7-18. Measured Duty Cycle vs Input Duty Cycle at PWM frequency of 20 KHz at VVM = 13.5 V for HS recirculation DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8 Detailed Description

8.1 Overview

The DRV814x-Q1 family of devices are brushed DC motor drivers that operate from 4.5 to 35-V supporting a wide range of output load currents for various types of motors and loads. The devices integrate a charge pump regulator to support efficient high-side N-channel MOSFETs with 100% duty cycle operation. The devices operate from a single power supply input (VM) which can be directly connected to a battery or DC voltage supply. The devices also provide a low power mode to minimize current draw during system inactivity. The devices are available in two interface variants - 1. HW variant - Hardwired interface variant is available for easy device configuration. Due to the limited number of available pins in the device, this variant offers fewer configuration and fault reporting capability compared to the SPI variant. 2. SPI variant - A standard 4-wire serial peripheral interface (SPI) with daisy chain capability allows flexible device configuration and detailed fault reporting to an external controller. The feature differences of the SPI and HW variants can be found in the device comparison section. The SPI interface is available in two device variant choices, as stated below: a. SPI (S) variant - The power supply for the digital block is provided by an internal LDO regulator sourced from VM supply. The nSLEEP pin is a high impedance input pin. b. SPI (P) variant (N/A for DRV8144-Q1) - This allows for an external supply input to the digital block of the device through a VDD pin. The nSLEEP pin is replaced by this VDD supply pin. This prevents device reset (brown out) during a VM under voltage condition. The DRV814x family of devices provide a load current sense output using current mirrors on the high-side power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the high-side MOSFETs (current sourced out of the OUTx pin). This current can be converted to a proportional voltage using an external resistor (R IPROPI). Additionally, the devices also support a fixed off-time PWM chopping scheme for limiting current to the load. The current regulation level can be configured through the ITRIP function. A variety of protection features and diagnostic functions are integrated into the device. These include supply voltage monitors (VMOV & VMUV), charge pump undervoltage (CPUV) , off-state (Passive) diagnostics (OLP) , on-state (Active) diagnostics (OLA) - SPI variant only , overcurrent protection (OCP) for each power FET and over-temperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin. The SPI variant has additional communication protection features such as frame errors and lock features for configuration register bits and driver control bits. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.2 Functional Block Diagram

8.2.1 HW Variant

0.1 μF Charge Pump Internal LDO & Bias Digital CoreIN nSLEEP GND VDD Supply Monitors Oscillator DRVOFF VDD GND ISNS Impedance Estimator Digital IOs VM Thermal Shut Down (TSD) Over Current Protection (OCP) Off-state Diagnostics (OLP) VCP 1 μF ITRIP SR DIAG IPROPI ISNS RIPROPI nFAULT RnFAULT FB LOAD HS LOADLS LOAD High Side load to VM Low Side load to GND Full Bridge load (Using two DRV814X devices) DRV814X-Q1 Figure 8-1. Functional Block Diagram - HW Variant

8.2.2 SPI Variant

There are two variants for the SPI interface - SPI (S) variant and SPI (P) variant as shown below. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DRV8143-Q1

0.1 μF Charge Pump Internal LDO & Bias Digital CoreIN nSLEEP GND VDD Supply Monitors Oscillator DRVOFF VDD GND ISNS Digital IOs VM Thermal Shut Down (TSD) Over Current Protection (OCP) Load Diagnostics (OLP & OLA) VCP 1 μF nSCS SDI SCLK SDO VDD IPROPI ISNS RIPROPI nFAULT RnFAULT FB LOAD HS LOADLS LOAD High Side load to VM Low Side load to GND Full Bridge load (Using two DRV814X devices) DRV814X Figure 8-2. Functional Block Diagram - SPI (S) Variant Gate Driver LS VDD HS VVCP OUT PSMVM 0.1 μF Charge Pump Bias Digital CoreIN GND Supply Monitors Oscillator DRVOFF VDD GND ISNS Digital IOs VM Thermal Shut Down (TSD) Over Current Protection (OCP) Load Diagnostics (OLP & OLA) VCP 1 μF nSCS SDI SCLK SDO VDD IPROPI ISNS RIPROPI nFAULT RnFAULT VDD FB LOAD HS LOADLS LOAD High Side load to VM Low Side load to GND Full Bridge load (Using two DRV814X devices) DRV814X 0.1 μF Figure 8-3. Functional Block Diagram - SPI (P) variant DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.3 Feature Description

8.3.1 External Components

8.3.1.1 HW Variant

Table 8-1. External Components Table for HW Variant Component PIN Recommendation CVM1 VM 0.1 µF, low ESR ceramic capacitor to GND rated for VM CVM2 VM Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the section on bulk capacitor sizing. CVCP VCP 1µF, 6.3 V low ESR ceramic capacitor to VM RIPROPI IPROPI Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range. Pin can be shorted to GND if ITRIP and IPROPI function is not needed. CIPROPI IPROPI Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over Current Protection (OCP) section. RnFAULT nFAULT Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply. RSR SR Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer SR section. RITRIP ITRIP Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer ITRIP table. RDIAG DIAG Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer DIAG section.

8.3.1.2 SPI Variant

Table 8-2. External Components Table for SPI Variant Component PIN Recommendation CVM1 VM 0.1 µF, low ESR ceramic capacitor to GND rated for VM CVM2 VM Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the section on bulk capacitor sizing. CVCP VCP 1µF, 6.3 V low ESR ceramic capacitor to VM RIPROPI IPROPI Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range. Pin can be shorted to GND if ITRIP and IPROPI function is not needed. CIPROPI IPROPI Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over Current Protection (OCP) section. RnFAULT nFAULT Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply. If nFAULT signaling is not used, this pin can be short to GND or left open. CVDD VDD 0.1 µF, 6.3 V, low ESR ceramic capacitor to GND. This is applicable for the SPI (P) variant only.

8.3.2 Bridge Control

The DRV814x-Q1 family of devices provides a simple two pin control of the output through the pins, DRVOFF and IN. The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes. The device input pins can be powered before VM is applied. By default, the nSLEEP and DRVOFF pins have an internal pull-down and pull-up resistor respectively, to ensure the outputs are Hi-Z if no inputs are present. The IN pin also has an internal pull down resistor. The device automatically generates the optimal dead-time needed during transitioning between the high-side and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage feedback. No external timing is required. This scheme ensures minimum dead time, while guaranteeing no shoot-through current. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DRV8143-Q1

1. The SPI variant also provides additional control through the SPI_IN register bits. Refer to - Register - Pin control. 2. For the SPI (P) variant, ignore the nSLEEP column in the control table as there is no nSLEEP pin. Internally, nSLEEP = 1, always. The control table is valid when VDD > VDDPOR level. The table below shows the logic table for bridge control. For load illustration, refer the Load Summary section. Table 8-3. Control table nSLEEP DRVOFF IN OUT IPROPI Device State

0 X X Hi-Z No current SLEEP

1 1 0 Hi-Z No current STANDBY 1 1 1 Refer Off-state diagnostics table No current STANDBY 1 0 0 L No current ACTIVE 1 0 1 H(2) ISNS(1) ACTIVE (1) Current sourcing out of device (VM → OUTx → Load) (2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time

8.3.2.1 Register - Pin Control - SPI Variant Only

The SPI variant allows control of the bridge through the specific register bits, S_DRVOFF , S_IN in the SPI_IN register, provided the SPI_IN register has been unlocked. The user can unlock this register by writing the right combination to the SPI_IN_LOCK bits in the COMMAND register. Additionally, the user can configure between an AND / OR logic combination of each of external input pin with their equivalent register bit in the SPI_IN register. This logical configuration is done through the equivalent selects bits in the CONFIG4 register:

• DRVOFF_SELand IN_SEL The control of the output is similar to the truth tables described in the section before, but with these logically combined inputs. These combined inputs are listed as follows:
• Combined input = Pin input OR equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b0
• Combined input = Pin input AND equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b1 Note that external nSLEEP pin is still needed for sleep function. This logical combination offers more configurability to the user as shown in the table below. Table 8-4. Register - Pin Control Examples Example CONFIG4: xxx_SEL Bit PIN status SPI_IN Bit Status Comment DRVOFF as redundant shutoff DRVOFF_SEL = 1’b0 DRVOFF active S_DRVOFF active Either DRVOFF pin = 1 or S_DRVOFF bit = 1 will shutoff the output Pin only control DRVOFF_SEL = 1’b1 DRVOFF active S_DRVOFF = 1'b1 Only DRVOFF pin function is available Register only control IN_SEL = 1’b0 IN - short to GND or float S_IN active IN function will be controlled by the register bit alone

8.3.3 Device Configuration

This section describes the various device configurations to enable the user to configure the device to suit their use case.

8.3.3.1 Slew Rate (SR)

The SR pin (HW variant) or S_SR bits in the CONFIG3 register (SPI variant) determines the voltage slew rate of the driver output. This enables the user to optimize the PWM switching losses while meeting the EM DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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conformance requirements. For the HW variant, SR is a 6-level setting, while the SPI variant has 8 settings. For an inductive load, the slew rate control of the device depends on whether the recirculation path is through the high-side path to VM or through the low-side path to GND. Depending on the use-case, refer to the switching parameters table for either high-side recirculation or low-side recirculation in the Electrical Characteristics section for the slew rate range and values. Note The SPI variant also offers an optional spread spectrum clocking (SSC) feature that spreads the internal oscillator frequency +/- 12% around its mean with a period triangular function of ~1.3 MHz to reduce emissions at higher frequencies. There is no spread spectrum clocking (SSC) feature in the HW variant. In the HW variant, the SR pin is latched during device initialization following power-up or wake-up from sleep. Update during operation is blocked. In the SPI variant, the slew rate setting can be changed at any time when SPI communication is available by writing to the S_SR bits. This change is immediately reflected.

8.3.3.2 IPROPI

The device integrates a current sensing feature with a proportional analog current output on the IPROPI pin that can be used for load current regulation. This eliminates the need of an external sense resistor or sense circuitry reducing system size, cost, and complexity. The device senses the load current by using a shunt-less high-side current mirror topology. This way the device can only sense an uni-directional high-side current from VM → OUT → Load through the high-side FET when it is fully turned ON (linear mode). The IPROPI pin outputs an analog current proportional to this sensed current scaled by AIPROPI as follows: IIPROPI = IHS [A] / AIPROPI The IPROPI pin must be connected to an external resistor (RIPROPI) to ground in order to generate a proportional voltage VIPROPI. This allows for the load current to be measured as a voltage-drop across the R IPROPI resistor with an analog to digital converter (ADC). The R IPROPI resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized.

8.3.3.3 ITRIP Regulation

The device offers an optional internal load current regulation feature using fixed TOFF time method. This is done by comparing the voltage on the IPROPI pin against a reference voltage determined by ITRIP setting. TOFF time is fixed at 30 µsec for HW variant, while it is configurable between or 20 to 50 µsec for the SPI variant using TOFF_SEL bits in the CONFIG3 register. The ITRIP regulation, when enabled, comes into action only when the HS FET is enabled and current sensing is possible. In this scenario, when the voltage on the IPROPI pin exceeds the reference voltage set by the ITRIP setting, the internal current regulation loop forces the following action:

• OUT = L for a fixed TOFF time Note The user inputs always takes precedence over the internal control. That means that if the inputs change during the TOFF time, the remainder of the TOFF time is ignored and the outputs will follow the inputs as commanded. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: DRV8143-Q1

(HW variant) RITRIP DAC Digital Core V(ITRIP) ITRIP_CMP High Side Current Sense V(IPROPI) SPI (SPI variant) OUTx VM GND RIPROPI Figure 8-4. ITRIP Implementation Current limit is set by the following equation: ITRIP regulation level = (VITRIP / RIPROPI) X AIPROPI (2) IOUT VOUT IN ITRIP tOFF tOFF tOFF E.g. with low side load ITRIP regula on ac ve Figure 8-5. Fixed TOFF ITRIP Current Regulation The ITRIP comparator output (ITRIP_CMP) is ignored during output slewing to avoid false triggering of the comparator output due to current spikes from the load capacitance. Additionally, in the event of transition from low-side recirculation, an additional blanking time t BLANK is needed for the sense loop to stabilize before the ITRIP comparator output is valid. ITRIP is a 6-level setting for the HW variant. The SPI variant offers two more settings. This is summarized in the table below: Table 8-5. ITRIP Table ITRIP Pin S_ITRIP Register Bits VITRIP [V] RLVL1OF6 3'b000 Regulation Disabled RLVL2OF6 3'b001 1.18 Not available 3'b010 1.41 Not available 3'b011 1.65 RLVL3OF6 3'b100 1.98 RLVL4OF6 3'b101 2.31 RLVL5OF6 3'b110 2.64 RLVL6OF6 3'b111 2.97 In the HW variant of the device, the ITRIP pin changes are transparent and changes are reflected immediately. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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In the SPI variant of the device, the ITRIP setting can be changed at any time when SPI communication is available by writing to the S_ITRIP bits. This change is immediately reflected in the device behavior. SPI variant only - If the ITRIP regulation levels are reached, the ITRIP_CMP bit in the STATUS1 register is set. There is no nFAULT pin indication. This bit can be cleared with a CLR_FLT command. Note If the application requires a linear ITRIP control with multiple steps beyond the choices provided by the device, an external DAC can be used to force the voltage on the bottom side of the IPROPI resistor, instead of terminating it to GND. With this modification, the ITRIP current can be controlled by the external DAC setting as follows: ITRIP regulation level = [(VITRIP - VDAC) / RIPROPI] X AIPROPI (3)

8.3.3.4 DIAG

The DIAG is a pin (HW variant) or register (SPI variant) setting that is used in both ACTIVE and STANDBY operation of the device, as follows:

• STANDBY state – Enable or disable Off-state diagnostics (OLP), as well as select the OLP combinations when enabled. Refer to the tables in the Off-state diagnostics (OLP) section for details on this.
• ACTIVE state – Mask ITRIP regulation function if the load type is indicated as high-side load. – SPI variant only - Mask active open load detection (OLA) if the load type is indicated as low-side. load – HW variant only - Configure fault reaction between retry and latch settings

8.3.3.4.1 HW variant

For the HW variant, the DIAG pin is a 6-level setting. Depending on the mode, its configurations are summarized in the table below. Table 8-6. DIAG table for HW variant DIAG pin STANDBY state ACTIVE state Off-state diagnostics Fault reaction IPROPI / ITRIP Comment RLVL1OF6 Disabled Retry Available Use for low-side load RLVL2OF6 Enabled(1) Latch Available RLVL3OF6 Enabled(1) Latch Disabled Use for high-side load RLVL4OF6 Enabled(1) Retry Disabled RLVL5OF6 Disabled Latch Available Use for low-side load RLVL6OF6 Enabled(1) Retry Available (1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details Note HW variant only - Option to disable off-state diagnostics for a high-side load use case is not supported. In this case, setting DRVOFF pin high and IN pin low is only way to disable off-state diagnostics. In the HW variant, the DIAG pin is latched during device initialization following power-up or wake-up from sleep. Update during operation is blocked.

8.3.3.4.2 SPI variant

For the SPI variant, S_DIAG is a 2-bit setting in the CONFIG2 register. Depending on the mode, its configurations are summarized in the table below. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: DRV8143-Q1

Table 8-7. DIAG table for the SPI variant S_DIAG bits STANDBY state ACTIVE state Off-state diagnostics On-state diagnostics IPROPI / ITRIP Comment 2'b00 Disabled Disabled Available Use for low-side load 2'b01 Enabled(1) Disabled Available 2'b10 Disabled Available Disabled Use for high-side load 2'b11 Enabled(1) Available Disabled (1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details In the SPI variant of the device, the settings can be changed anytime when SPI communication is available by writing to the S_DIAG bits. This change is immediately reflected.

8.3.4 Protection and Diagnostics

The driver is protected against over-current and over-temperature events to ensure device robustness. Additionally, the device also offers load monitoring (on-state and off-state), over/ under voltage monitoring on VM pin as well as under voltage monitoring on the VCP pin to signal any unexpected voltage conditions. Fault signaling is done through a low-side open drain nFAULT pin which gets pulled to GND by I nFAULT_PD current on detection of a fault condition. Transition to SLEEP state automatically de-asserts nFAULT. Note In the SPI variant, nFAULT pin logic level is the inverted copy of the FAULT bit in the FAULT SUMMARY register. Only exception is when off-state diagnostics are enabled and SPI_IN register is locked (Refer OLP section) . For the SPI variant, whenever nFAULT is asserted low, the device logs the fault into the FAULT SUMMARY and STATUS registers. These registers can be cleared only by

• CLR FLT command or
• SLEEP command through the nSLEEP pin It is possible to get all the useful diagnostic information for periodic software monitoring in a single 16 bit SPI frame by:
• Reading the STATUS1 register during ACTIVE state
• Reading the STATUS2 register during STANDBY state All the diagnosable fault events can be uniquely identified by reading the STATUS registers.

8.3.4.1 Over Current Protection (OCP)

• Device state: ACTIVE
• Mechanism & thresholds: An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short circuit events. If the output current exceeds the overcurrent threshold, IOCP, for longer than tOCP, then an over current fault is detected.
• Action: – nFAULT pin is asserted low – OUT is Hi-Z – For a short to GND fault (over current detected on the high-side FET), the IPROPI pin continues to be pulled up to VIPROPI_LIM even if the FET has been disabled. For the HW variant, this helps differentiate a short to GND fault during ACTIVE state from other fault types, as the IPROPI pin is pulled high while the nFAULT pin is asserted low.
• Reaction configurable between latch setting and retry setting based on tRETRY and tCLEAR
• User can add a capacitor in the range of 10 nF to 100 nF on the IPROPI pin to ensure OCP detection in case of a load short condition when internal ITRIP regulation is enabled. This is especially true where there is enough inductance in the short that causes ITRIP regulation to trigger ahead of the OCP detection, resulting in the device missing the short detection. To ensure that OCP detection wins this race condition, a small capacitance added on the IPROPI pin slows down the ITRIP regulation loop enough to allow the OCP detection circuit to work as intended. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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The SPI variant offers configurable IOCP levels and tOCP filter times. Refer CONFIG4 register for these settings.

8.3.4.2 Over Temperature Protection (TSD)

• Device state: STANDBY, ACTIVE
• Mechanism & thresholds: The device has several temperature sensors spread around the die. If any of the sensors detect an over temperature event, set by TTSD for a time greater than tTSD, then an over temperature fault is detected.
• Action: – nFAULT pin is asserted low – OUT is Hi-Z – IPROPI pin is Hi-Z
• Reaction configurable between latch setting and retry setting based on THYS and tCLEAR_TSD

8.3.4.3 Off-State Diagnostics (OLP)

The user can determine the impedance on the OUT node using off-state diagnostics in the STANDBY state when the power FETs are off. With this diagnostics, it is possible to detect the following fault conditions passively in the STANDBY state:

• Output short to VM or GND < 100 Ω
• Open load > 1K Ω for low-side load
• Open load > 10K Ω for high-side load, VM = 13.5 V Note It is NOT possible to detect a load short with this diagnostic. However, the user can deduce this logically if an over current fault (OCP) occurs during ACTIVE operation, but OLP diagnostics do not report any fault in the STANDBY state. Occurrence of both OCP in the ACTIVE state and OLP in the STANDBY state would imply a terminal short (short on OUT node).
• The user can configure the following combinations – Internal pull up resistor (ROLP_PU) on OUT – Internal pull down resistor (ROLP_PD) on OUT – Comparator reference level
• This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.
• HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT pin.
• SPI variant - The off-state diagnostics comparator output (OLP_CMP) is available on OLP_CMP bit in STATUS2 register. Additionally, if the SPI_IN register has been locked, this comparator output is also available on the nFAULT pin when off-state diagnostics are enabled.
• The user is expected to toggle through all the combinations and record the comparator output after its output is settled.
• Based on the input combinations and comparator output, the user can determine if there is a fault on the output. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DRV8143-Q1

ROLP_PD ROLP_PU Internal VOLP_REFH VOLP_REFL OLP_CMP PIN / register control REF Voltage propor onal to Internal 5V Output on nFAULT pin / register Figure 8-6. Off-State (Passive) Diagnostics The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load is shown in Table 8-8. Table 8-8. Off-State Diagnostics Table for a Low-Side Load User Inputs OLP Set-Up OLP_CMP Output DIAG Pin S_DIAG Bits nSLEEP DRVOFF IN OUT CMP REF Normal Open Short LVL2, LVL6 2'b01 1 1 1 ROLP_PU VOLP_REFH L H H LVL3, LVL4 2'b11 1 1 1 ROLP_PD VOLP_REFL L L H The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load is shown in Table 8-9. Table 8-9. Off-State Diagnostics Table for a High-Side Load User Inputs OLP Set-Up OLP_CMP Output DIAG Pin S_DIAG Bits nSLEEP DRVOFF IN OUT CMP REF Normal Open Short LVL2, LVL6 2'b01 1 1 1 ROLP_PU VOLP_REFH H H L LVL3, LVL4 2'b11 1 1 1 ROLP_PD VOLP_REFL H L L

8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only

• Device state: ACTIVE - high-side recirculation
• Mechanism and threshold: On-state diagnostics (OLA) can detect an open load detection in the ACTIVE state during high-side recirculation. This includes high-side load connected directly to VM or through a high-side FET on the other half-bridge. During a PWM switching transition, the inductive load current re-circulates into VM through the HS body diode when the LS FET is turned OFF. The device looks for a voltage spike on OUTx above VM during the brief dead time, before the HS FET is turned ON. To observe the voltage spike, this load current needs to be higher than the pull down current (IPD_OLA) on the output asserted by the FET driver. Absence of this voltage spike for "3" consecutive re-circulation switching cycles indicates a loss of load inductance or increase in load resistance and is detected as an OLA fault. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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• Action: – nFAULT pin is asserted low – Output - normal function maintained – IPROPI pin - normal function maintained
• Reaction configurable between latch setting and retry setting. In retry setting, OLA fault is automatically cleared with the detection of "3" consecutive voltage spikes during re-circulation switching cycles. This monitoring is optional and can be disabled. Note 1. OLA is not supported for low-side loads (low-side recirculation). 2. CLR_FAULT command can clear this fault (recorded in the STATUS1 register) only if the direction commanded is aligned with direction during which the fault was detected. OUTx VM GND OLA_VREF OUTx_OLA_CMP IPD_OLA Figure 8-7. On-State Diagnostics

8.3.4.5 VM Over Voltage Monitor

• Device state: STANDBY, ACTIVE
• Mechanism & thresholds: If the supply voltage on the VM pin exceeds the threshold, set by VVMOV for a time greater than tVMOV, then an VM over voltage fault is detected.
• Action: – nFAULT pin is asserted low – Output - normal function maintained – IPROPI pin - normal function maintained
• Reaction configurable between retry and latch setting In the SPI variant, this monitoring is optional and can be disabled. Also the thresholds are configurable. Refer CONFIG1 register.

8.3.4.6 VM Under Voltage Monitor

• Device state: STANDBY, ACTIVE
• Mechanism & thresholds: If the supply voltage on the VM pin drops below the threshold, set by VVMUV for a time greater than tVMUV, then an VM under voltage fault is detected.
• Action: – nFAULT pin is asserted low – OUT is Hi-Z – IPROPI pin is Hi-Z
• HW and SPI (S) variant: Reaction fixed to retry setting
• Only for SPI (P) variant: Reaction configurable between retry and latch setting www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DRV8143-Q1

• Note that retry time is only dependent on recovery of VM under voltage condition and is independent of tRETRY / tCLEAR times

8.3.4.7 Charge pump under voltage monitor

• Device state: ACTIVE
• Mechanism & thresholds: If the voltage on the VCP pin falls below the threshold, set by VVCPUV for a time greater than tVCPUV, then a VCP under voltage fault is detected.
• Action: – nFAULT pin is asserted low – Output - normal function maintained. However, the high-side FET between VM and OUT becomes resistive in this charge pump under voltage condition to a point where it may even appear to Hi-Z due to lack of voltage headroom. – IPROPI pin - normal function maintained. However, current sense is affected in this charge pump voltage condition to a point where it may even appear to be Hi-Z due to lack of voltage headroom.
• Reaction fixed to retry based on VVCPUV_HYS

8.3.4.8 Power On Reset (POR)

• Device state: ALL
• Mechanism & thresholds: If logic supply drops below VDDPOR_FALL for a time greater than tPOR, then a power on reset will occur that will hard reset the device.
• Action: – nFAULT pin is de-asserted – OUT is Hi-Z – IPROPI pin is Hi-Z. – When this supply recovers above the VDDPOR_RISE level, the device will go through a wake-up initialization and nFAULT pin will be asserted low to notify the user on this reset (Refer Wake-up transients).
• HW and SPI (S) variant: These thresholds translate to VMPOR_FALL and VMPOR_RISE as the logic supply is internally derived from the VM supply
• Only for SPI (P) variant: These thresholds directly map to the VDD pin voltage (VDDPOR_FALL and VDDPOR_RISE)
• Fault reaction: Always retry, retry time depends on the external supply condition to initiate a device wake-up

8.3.4.9 Event Priority

In the ACTIVE state, in a scenario where two or more events occur simultaneously, the device assigns control of the driver based on the following priority table. Table 8-10. Event Priority Table Event Priority User SLEEP command 1 User input: DRVOFF 2 Over temperature detection (TSD) 3 Over current detection (OCP)(1) 4 VM under voltage detection (VMUV) 5 Under input: IN 6 Internal PWM control from ITRIP regulation 7 VM over voltage detection (VMOV)(2) 8 Charge pump under voltage (CPUV)(2) 9 (1) If the device is waiting for an OCP event to be confirmed (waiting for tOCP) when any of events with lower priority than OCP occur, then the device may delay servicing the other events up to a maximum time of tOCP to enable detection of the OCP event. (2) Priority is "don't care" in this case as this fault event does not cause a change in OUTx DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.4 Device Functional States

The device has three functional states:

• SLEEP
• STANDBY
• ACTIVE SLEEP nFAULT = H, No communica on ACTIVE Protec on Enabled nFAULT = fault signaling Communica on available INIT2 nFAULT = L Communica on enabled INIT1 nFAULT = H STANDBY nFAULT = H Communica on available 1. nSLEEP = 1 for t > tWAKE 2. nSLEEP = 0 for t > tSLEEP 3. Power on reset 4. End of t COM 5. CLR_FLT or HW RESET pulse from from controller & End of tREADY 6. DRVOFF = 0 7. DRVOFF = 1 543 2 2 Figure 8-8. Illustrative State Diagram These states are described in the following section.

8.4.1 SLEEP State

This state occurs when nSLEEP pin is asserted low for a time > t SLEEP or voltage on the VDD pin is < VDDPOR_FALL. This is the deep sleep low power (ISLEEP) state of the device where all functions except a wake-up command are not serviced. The drivers are in Hi-Z. The internal power supply rails (5 V and others) are powered off. nFAULT pin is de-asserted in this state. The device can enter this state from either the STANDBY or the ACTIVE state, when the nSLEEP pin is asserted low for time longer than tSLEEP (HW variant) or for tSLEEP_SPI (SPI (S) variant).

8.4.2 STANDBY State

The device is in this state when nSLEEP pin is asserted high or the voltage on the VDD pin is > VDD POR_RISE with DRVOFF = 1'b0. In this state, the device is powered up (I STANDBY), with the driver Hi-Z and nFAULT de-asserted. The device is ready to transition to ACTIVE state or SLEEP state when commanded so. Off-state diagnostics (OLP), if enabled, are done in this state.

8.4.3 Wake-up to STANDBY State

The device starts transition from SLEEP state to STANDBY state

• if the nSLEEP pin goes high for a duration longer than tWAKE, or
• if VM supply > VMPOR_RISE or VDD supply > VDDPOR_RISE such that internal POR is released to indicate a power-up. The device goes through an initialization sequence to load its internal registers and wake-up all the blocks in the following sequence:
• At a certain time, tCOM from wake-up, the device is capable of communication. This is indicated by asserting the nFAULT pin low.
• This is followed by the time tREADY, when the device wake-up is complete.
• At this point, once the device receives a nSLEEP reset pulse (HW variant) or a CLR FAULT command through SPI (SPI variant) as an acknowledgment of the wake-up from the controller, the device enters the www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DRV8143-Q1

STANDBY state. This is indicated by the de-assertion of the nFAULT pin. The driver is held in Hi-Z till this point.

• From here on, the device is ready to drive the bridge based on the truth tables. Refer to the wake-up transients waveforms for the illustration.

8.4.4 ACTIVE State

The device is fully functional in this state with the drivers controlled by other inputs as described in prior sections. All protection features are fully functional with fault signaling on nFAULT pin. SPI communication is available.The device can transition into this state only from the STANDBY state. 8.4.5 nSLEEP Reset Pulse (HW Variant Only) This is a special communication signal from the controller to the device through the nSLEEP pin available only for the HW variant. This is used to:

• Acknowledge the nFAULT asserted during the SLEEP/ Power up transition to STANDBY state
• Clear a latched fault when the fault reaction is configured to the LATCHED setting, without forcing the device into SLEEP or affecting any of the other functions (Equivalent to the CLR_FAULT command in the SPI variant) This pulse on nSLEEP must be greater than the nSLEEP deglitch time of t RESET time, but shorter than t SLEEP time, as shown in case # 3, in Table 8-11 below. Table 8-11. nSLEEP Timing (HW Variant Only) Case # Window Start Time Window End Time Command Interpretation Clear Fault Sleep 1 0 tRESET min No No 2 tRESET min tRESET max Indeterminate No 3 tRESET max tSLEEP min Yes No 4 tSLEEP min tSLEEP max Yes Indeterminate 5 tSLEEP max No limit Yes Yes Window 5Window 4Window 3Window 2Window 1 nSLEEP pulses tRESET min tRESET max tSLEEP min tSLEEP max me Case 4 Case 3 Case 5 Case 2 Case 1 Figure 8-9. nSLEEP Pulse Scenarios DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.5 Programming - SPI Variant Only

8.5.1 SPI Interface

The SPI variant has full-duplex, 4-wire synchronous communication that is used to set device configurations, operating parameters, and read out diagnostic information from the device. The SPI operates in peripheral mode and connects to a controller. The serial data input (SDI) word consists of a 16-bit word, with an 8-bit command (A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of the FAULT_SUMMARY byte (S1), followed by a report byte (R1). The report byte is either the register data being accessed by read command or null for a write command. The data sequence between the MCU and the SPI peripheral driver is shown in Figure 8-10. A1 D1 SDO SDI nSCS S1 R1 Figure 8-10. SPI Data - Standard "16-bit" Frame A valid frame must meet the following conditions:

• SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• nSCS pin should be pulled high between words.
• When nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed in the Hi-Z state.
• Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by the device on the subsequent falling edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chain frame with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction. Else, a frame error (SPI_ERR) is reported and the data is ignored if it is a WRITE operation.

8.5.2 Standard Frame

The SDI input data word is 2 bytes long and consists of the following format:

• Command byte (first byte) – MSB bit indicates frame type (bit B15 = 0 for standard frame). – Next to MSB bit, W0, indicates read or write operation (bit B14, write = 0, read = 1) – Followed by 6 address bits, A[5:0] (bits B13 through B8)
• Data byte (second byte) – Second byte indicates data, D[7:0] (bits B7 through B0). For a read operation, these bits are typically set to null values, while for a write operation, these bits have the data value for the addressed register. Table 8-12. SDI - Standard Frame Format Command Byte Data Byte Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data 0 W0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 The SDO output data word is 2 bytes long and consists of the following format:
• Status byte (first byte) www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: DRV8143-Q1

– 2 MSB bits are forced high (B15, B14 = 1) – Following 6 bits are from the FAULT SUMMARY register (B13:B8)

• Report byte (second byte) – The second byte (B7:B0) is either the data currently in the register being read for a read operation (W0 = 1), or, existing data in the register being written to for a write command (W0 = 0) Table 8-13. SDO - Standard Frame Format Status Byte Report Byte Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data 1 1 FAULT VMOV VMUV OCP TSD SPI_E RR D7 D6 D5 D4 D3 D2 D1 D0

8.5.3 SPI Interface for Multiple Peripherals

Multiple devices can be connected to the controller with and without the daisy chain. For connecting a 'n' number of devices to a controller without using a daisy chain, 'n' number of I/O resources from controller has to utilized for nSCS pins as shown in Figure 8-11. Whereas, if the daisy chain configuration is used, then a single nSCS line can be used for connecting multiple devices. Figure 8-12 DRV8x SDO SCLK SDI nSCS SPI Communication Master Controller SPI Communication CS2 CS1 MI MO MCLK DRV8x SDO SCLK SDI nSCS SPI Communication Figure 8-11. SPI Operation Without Daisy Chain DRV8x SDO SCLK SDI nSCS SPI Communication Master Controller SPI Communication CS MI MO MCLK DRV8x SDO SCLK SDI nSCS SPI Communication Figure 8-12. SPI Operation With Daisy Chain DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.5.3.1 Daisy Chain Frame for Multiple Peripherals

The device can be connected in a daisy chain configuration to save GPIO ports when multiple devices are communicating to the same MCU. Figure 8-13 shows the topology with waveforms, where, number of peripherals connected in a daisy chain "n" is set to 3. A maximum of up to 63 devices can be connected in this manner. SDI1 SDO1 SDO1 SDI2 SDI1 SDI2 SDO2 SDO2 SDI3 SDI2 SDO3 M-SDO M-SDI M-SCLK M-nSCS M-SDO HDR1 HDR2 A3 A2 A1 D3 D2 D1 S1 HDR1 HDR2 A3 A2 R1 D3 D2 S2 S1 HDR1 HDR2 A3 R2 R1 D3 S3 S2 S1 HDR1 HDR2 R3 R2 R1 Status Response Here All Address Bytes Reach Destination Reads Execute Here Writes Execute Here All Address Bytes Reach Destination SDO3 M-SDI SDO1 SDI2 SDI1 SDO2 SDI3 SDO3 nSCS Figure 8-13. Daisy Chain SPI Operation The SDI sent by the controller in this case would be in the following format (see SDI1 in Figure 8-13 ):

• 2 bytes of header (HDR1, HDR2)
• "n" bytes of command byte starting with furthest peripheral in the chain (for this example, this is A3, A2, A1)
• "n" bytes of data byte starting with furthest peripheral in the chain (for this example, this is D3, D2, D1)
• Total of 2 x "n" + 2 bytes While the data is being transmitted through the chain, the controller receives it in the following format (see SDO3 in Figure 8-13):
• 3 bytes of status byte starting with furthest peripheral in the chain (for this example, this is S3, S2, S1)
• 2 bytes of header that were transmitted before (HDR1, HDR2)
• 3 bytes of report byte starting with furthest peripheral in the chain (for this example, this is R3, R2, R1) www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: DRV8143-Q1

The Header bytes are special bytes asserted at the beginning of a daisy chain SPI communication. Header bytes must start with 1 and 0 for the two leading bits. The first header byte (HDR1) contains information of the total number of peripheral devices in the daisy chain. N5 through N0 are 6 bits dedicated to show the number of device in the chain as shown in Figure 8-14. Up to 63 devices can be connected in series per daisy chain connection. Number of peripheral = 0 is not permitted and will result in a SPI_ERR flag. The second header byte (HDR2) contains a global CLR FAULT command that will clear the fault registers of all the devices on the rising edge of the chip select (nSCS) signal. The 5 trailing bits of the HDR2 register are marked as SPARE (don’t care bits). These can be used by the MCU to determine integrity of the daisy chain connection. 1 0 N5 N4 N3 N2 N1 N0 1 0 CLR_FLT SPARE SPARE SPARE SPARE SPARE HDR2 HDR1 Don’t Care Number of Devices in the Chain (Up to 63 max) 1 = Global CLR_FAULT 0 = Don’t Care Figure 8-14. Header bytes In addition, the device recognizes bytes that start with 1 and 1 for the two leading bits as a "pass" byte. These "pass" bytes are NOT processed by the device, but they are simply transmitted out on SDO in the following byte. When data passes through a device, it determines the position of itself in the chain by counting the number of Status bytes it receives following by the first Header byte. For example, in this 3 device configuration, device 2 in the chain will receive two status bytes before receiving the two header bytes. From the two status bytes it knows that its position is second in the chain, and from HDR1 byte it knows how many devices are connected in the chain. That way it only loads the relevant address and data byte in its buffer and bypasses the other bits. This protocol allows for faster communication without adding latency to the system for up to 63 devices in the chain. The command, data, status and report bytes remain the same as described in the standard frame format. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.6 Register Map - SPI Variant Only

This section describes the user configurable registers in the device. Note While the device allows register writes at any time SPI communication is available, it is recommended to exercise caution while updating registers in the ACTIVE state while the load is being driven. This is especially important for settings such as S_DIAG which control the critical device configuration. In order to prevent accidental register writes, the device offers a locking mechanism through the REG_LOCK bits in the COMMAND register to lock the contents of all configurable registers. Best practice would be to write all the configurable registers during initialization and then lock these settings. Run-time register writes for output control are handled by the SPI_IN register, which offers its own separate locking mechanism through the SPI_IN_LOCK bits. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: DRV8143-Q1

8.6.1 User Registers

The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as "reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR. Table 8-14. User Registers Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type (2) Addr DEVICE_ID DEV_ID[5] DEV_ID[4] DEV_ID[3] DEV_ID[2] DEV_ID[1] DEV_ID[0] REV_ID[1] REV_ID[0] R 00h FAULT_SUMMARY SPI_ERR(3) POR FAULT VMOV VMUV OCP TSD VCPUV (3) R 01h STATUS1 OLA(6) OLA(6) ITRIP_CMP ACTIVE OCP_H(7) OCP_L(8) OCP_H(7) OCP_L(8) R 02h STATUS2 DRVOFF_STAT N/A(4) N/A(4) ACTIVE N/A(4) N/A(4) N/A(4) OLP_CMP R 03h COMMAND CLR_FLT N/A(4) N/A(4) SPI_IN_LOCK[1] SPI_IN_LOCK[0] (1) N/A(4) REG_LOCK[1] REG_LOCK[0] (1) R/W 08h SPI_IN N/A(4) N/A(4) N/A(4) N/A(4) S_DRVOFF (1) SPARE(5) (1) SPARE(5) S_IN R/W 09h CONFIG1 EN_OLA VMOV_SEL[1] VMOV_SEL[0] SSC_DIS(1) OCP_RETRY TSD_RETRY VMOV_RETRY OLA_RETRY R/W 0Ah CONFIG2 SPARE(5) S_DIAG[1] S_DIAG[0] N/A(4) N/A(4) S_ITRIP[2] S_ITRIP[1] S_ITRIP[0] R/W 0Bh CONFIG3 TOFF[1] TOFF[0] (1) N/A(4) S_SR[2] S_SR[1] S_SR[0] SPARE(5) SPARE(5) R/W 0Ch CONFIG4 TOCP_SEL[1] TOCP_SEL[0] N/A(4) OCP_SEL[1] OCP_SEL[0] DRVOFF_SEL(1) SPARE(5) IN_SEL R/W 0Dh (1) Defaulted to 1b on reset, others are defaulted to 0b on reset (2) R = Read Only, R/W = Read/Write (3) VCPUV replaced by SPI_ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format. (4) N/A = Not available (read back of this bit will be 0b) (5) SPARE = Don't care bits. These are available to USER as scratch bits. (6) OLA is indicated if either of the two OLA bits is set (7) OCP_L is indicated if either of the two OCP_L bits is set (8) OCP_H is indicated if either of the two OCP_H bits is set DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.6.1.1 DEVICE_ID register (Address = 00h)

Return to the User Register table. Device DEVICE_ID value DRV8143S-Q1 BAh DRV8144S-Q1 CAh DRV8145S-Q1 DAh DRV8143P-Q1 BEh DRV8145P-Q1 DEh

8.6.1.2 FAULT_SUMMARY Register (Address = 01h) [reset = 40h]

Return to the User Register table. Bit Field Type Reset Description 7 SPI_ERR R 0b 1b indicates that a SPI communication fault has occurred in the previous SPI frame. 6 POR R 1b 1b indicates that a power-on-reset has been detected.

5 FAULT R 0b Logic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD, OLA & VCPUV

4 VMOV R 0b 1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction. 3 VMUV R 0b 1b indicates that a VM under voltage has been detected.

2 OCP R 0b

1b indicates that an over current has been detected in either one or more power FETs. Refer OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure fault reaction. 1 TSD R 0b 1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure fault reaction. 0 VCPUV R 0b 1b indicates that a charge pump under voltage has been detected.

8.6.1.3 STATUS1 Register (Address = 02h) [reset = 00h]

Return to the User Register table. Bit Field Type Reset Description

7 OLA R 0b 1b indicates that an open load condition has been detected in the ACTIVE state on OUT

6 OLA R 0b 1b indicates that an open load condition has been detected in the ACTIVE state on OUT

5 ITRIP_CMP R 0b 1b indicates that load current has reached the ITRIP regulation level.

4 ACTIVE R 0b 1b indicates that the device is in the ACTIVE state

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Bit Field Type Reset Description

3 OCP_H R 0b 1b indicates that an over current has been detected on the high-side FET (short to GND) on

2 OCP_L R 0b 1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT

1 OCP_H R 0b 1b indicates that an over current has been detected on the high-side FET (short to GND) on

0 OCP_L R 0b 1b indicates that an over current has been detected on the low-side FET (short to VM) on OUT

8.6.1.4 STATUS2 Register (Address = 03h) [reset = 80h]

Return to the User Register table. Bit Field Type Reset Description 7 DRVOFF_STAT R 1b This bit shows the status of the DRVOFF pin. 1b implies the pin status is high. 6, 5 N/A R 0b Not available

4 ACTIVE R 0b 1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)

3, 2, 1 N/A R 0b Not available 0 OLP_CMP R 0b This bit is the output of the off-state diagnostics (OLP) comparator.

8.6.1.5 COMMAND Register (Address = 08h) [reset = 09h]

Return to the User Register table. Bit Field Type Reset Description 7 CLR_FLT R/W 0b Clear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert the nFAULT pin 6-5 N/A R 0b Not available 4-3 SPI_IN_LOCK R/W 01b Write 10b to unlock the SPI_IN register Write 01b or 00b or 11b to lock the SPI_IN register SPI_IN register is locked by default.

2 N/A R 0b Not available

1-0 REG_LOCK R/W 01b Write 10b to lock the CONFIG registers Write 01b or 00b or 11b to unlock the CONFIG registers CONFIG registers are unlocked by default. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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8.6.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]

Return to the User Register table. Bit Field Type Reset Description 7-4 N/A R 0b Not available 3 S_DRVOFF R/W 1b Register bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control section. 2-1 N/A R 10b Not available 0 S_IN R/W 0b Register bit equivalent of IN pin when SPI_IN is unlocked. Refer Register Pin control section

8.6.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]

Return to the User Register table. Bit Field Type Reset Description 7 EN_OLA R/W 0b Write 1b to enable open load detection in the active state. In Independent mode, OLA is always disabled for low-side load. Refer DIAG section. 6-5 VMOV_SEL R/W 0b Determines the thresholds for the VM over voltage diagnostics 00b = VM > 35 V 01b = VM > 28 V 10b = VM > 18 V 11b = VMOV disabled

4 SSC_DIS R/W 1b 0b: Enables the spread spectrum clocking feature

3 OCP_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of over current, else the fault reaction is latched 2 TSD_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of over temperature, else the fault reaction is latched

1 VMOV_RETRY R/W 0b

Write 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault reaction is latched. Note For the SPI (P) variant, this bit also controls the fault reaction for a VM under voltage detection. 0 OLA_RETRY R/W 0b Write 1b to configure fault reaction to retry setting on the detection of open load during active, else the fault reaction is latched. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DRV8143-Q1

8.6.1.8 CONFIG2 Register (Address = 0Bh) [reset = 00h]

Return to the User Register table. Bit Field Type Reset Description

7 SPARE R/W 0b Don't care

6-5 S_DIAG R/W 0b Load type indication - refer to DIAG table 4-3 N/A R 0b Not available 2-0 S_ITRIP R/W 0b ITRIP level configuration - refer ITRIP table

8.6.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]

Return to the User Register table. Bit Field Type Reset Description 7-6 TOFF R/W 1b TOFF time used for ITRIP current regulation 00b = 20 µsec 01b = 30 µsec 10b = 40 µsec 11b = 50 µsec

5 N/A R 0b Not available

4-2 S_SR R/W 0b Slew Rate configuration - refer to Section 8.3.3.1 1-0 SPARE R/W 0b Don't care

8.6.1.10 CONFIG4 Register (Address = 0Dh) [reset = 04h]

Return to the User Register table. Bit Field Type Reset Description 7-6 TOCP_SEL R/W 0b Filter time for over current detection configuration 00b = 6 µsec 01b = 3 µsec 10b = 1.5 µsec 11b = Minimum (~0.2 µsec) SLVSG63 – JANUARY 2023 www.ti.com

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Bit Field Type Reset Description 4-3 OCP_SEL R/W 0b Threshold for over current detection configuration 00b = 100% setting 01b, 11b = 50% setting 10b = 75% setting

2 DRVOFF_SEL R/W 1b

DRVOFF pin - register logic combination, when SPI_IN is unlocked 0b = OR 1b = AND

1 SPARE R/W 0b Don't care

0 IN_SEL R/W 0b

IN pin - register logic combination, when SPI_IN is unlocked 0b = OR 1b = AND www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: DRV8143-Q1

9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DRV814x-Q1 family of devices can be used in a variety of applications that require either a half-bridge or H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids, and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two half-bridge drivers.

9.1.1 Load Summary

summarizes the utility of the device features for different type of inductive loads. Table 9-1. Load Summary Table LOAD Configuration Device Feature Device Recirculation Path Slew Rate control Current sense ITRIP regulation Bi-directional motor or solenoid(1) Full-Bridge with two DRV814x High-side Full range Continuous Not useful(3) Bi-directional motor or solenoid(1) Full-Bridge with two DRV814x Low-side Full range Discontinuous(2) Useful Uni-directional motor or Low- side solenoid (one side connected to GND) DRV814x Low-side Full range Discontinuous(2) Useful High-side solenoid (one side connected to VM) DRV814x High-side Full range Not available, need external solution (1) Solenoid - clamping or quick demagnetization possible, but clamping level will be VM dependent (2) Not sensed during recirculation and during OUT voltage slew times including tblank (3) SPI variant - Controller can poll ITRIP_CMP bit for external coordination between the two Half-Bridges nSLEEP DRV814X Device 1 IN GND OUT VM IPROPI DRVOFF SPI (Opt) nFAULT to Controller ADC Controller I/Os (can be shared) to Controller I/O nSLEEP DRV814X Device 2 IN GND OUT VM IPROPI DRVOFF SPI (Opt) nFAULT Controller I/Os (can be shared) to Controller I/O LOAD BD CBDC solenoid Applicable for Figure 9-1. Illustration Showing a Full-Bridge Topology With Two DRV814X-Q1 Devices DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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SPI (Opt) nFAULT to Controller ADC Controller I/Os (can be shared) to Controller I/O LOAD BD CBDC solenoid Applicable for Figure 9-2. Illustration Showing a Half-Bridge Topology to Drive Low-side Load With DRV814X-Q1 Device nSLEEP DRV814X IN GND OUT VM IPROPI DRVOFF SPI (Opt) nFAULT Controller I/Os (can be shared) to Controller I/O Not useful HS Switch for clamping (OPT) VM to Controller I/O solenoid Figure 9-3. Illustration showing a Half-Bridge topology to drive high-side load with DRV814X-Q1 device

9.2 Typical Application

The figures below show the typical application schematic for driving a brushed DC motor or any inductive load. There are several optional connections shown in these schematics, which are listed as follows:

• nSLEEP pin – SPI (S) variant - This pin can be tied off high in the application if SLEEP function is not needed. – SPI (P) variant - N/A – HW (H) variant - Pin control is mandatory even if SLEEP function is not needed. The controller needs to issue a reset pulse (typical: 30 μsec bounded between treset max and tsleep min) during wake-up to acknowledge wake-up or power-up.
• DRVOFF pin – Both SPI (P) and SPI (S) variants - This pin can be tied off low in the application if shutoff through pin function is not needed. The equivalent register bit can be used.
• IN pin – Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is needed. www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: DRV8143-Q1

• NC pin – All variants - This pin can be left floating or tied off low.
• OUT pin – Recommend to add a PCB footprint for capacitor from OUT to GND close to the load for EMC purposes.
• IPROPI pin – All variants - Monitoring of this output is optional. Also IPROPI pin can be tied low if ITRIP feature & IPROPI function is not needed. Recommend to add a PCB footprint for a small capacitor (10 nF to 100 nF) if needed.
• nFAULT pin – Both SPI (P) and SPI (S) variants - Monitoring of this output is optional. All diagnostic information can be read from the STATUS registers.
• SPI input pins – Both SPI (P) and SPI (S) variants - Inputs (SDI, nSCS, SCLK) are compatible with 3.3 V / 5 V levels.
• SPI SDO pin – SPI (S) variant - SDO tracks the nSLEEP pin voltage. – SPI (P) variant - SDO tracks the VDD pin voltage. To interface with a 3.3 V level controller input, a level shifter or a current limiting series resistor is recommended.
• CONFIG pins – HW (H) variant - Resistor is not needed for short to GND and Hi-Z level selections
• LVL1 and LVL6 for SR, ITRIP, DIAG pins

9.2.1 HW Variant

5,7 DRVOFF9 nSLEEP3 CVCP1 VCP DIAG

13 ITRIP

5,7 LOAD I/O SR I/O IN nFAULT 1 DRVOFF 9 nSLEEP Op onal (5) 5,7 Op onal (5) Full bridge with two half-bridge devices RDIAG RITRIP RSR Op onal (7) DIAG ITRIP 12SR RDIAG RITRIP RSR Op onal (7) IN10 DIAG onal (7) LOAD HS / LS load with half bridge VM / GND Figure 9-4. Typical Application Schematic - HW Variant in VQFN-HR Package DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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9.2.2 SPI Variant

VM 6,7,8,21, 22,23 GND 12,13,14, 15,16,17 OUT DRVOFF VDD CVCP VCP S P I SDO nSCS SDI SCLK SSOP SPI Device 1 CVM1 CVM2 VCC VCC RnFAULT RIPROPI Reverse Supply Protected Input CONTROLLER I/O ADC I/O I/O IN IPROPI nFAULT26 VM 6,7,8,21, 22,23 GND 12,13,14, 15,16,17 OUT 18,19,20, 9,10,11 DRVOFF4 VDD

24 CVCP1

S P I SDO SDI SCLK SSOP SPI Device 2 IPROPI VM GND OUT CVCP2 VCP 12,13,14, 15,16,17 18,19,20, 9,10,11 LOAD 6,7,8,21, 22,23 I/O nSCS I/O I/O IN nFAULT 26 DRVOFF VDD SDO 27 SDI 28 SCLK 1 nSCS Op onal (5) Op onal (2) Op onal (3) Op onal (4) Op onal (6) Daisy Chain capable Daisy Chain capable 18,19,20, 9,10,11 LOAD Op onal (2) Op onal (3) Op onal (5) Op onal (6) Daisy Chain capable Full bridge with two half-bridge devices HS / LS load with half bridge VM / GND Logic Supply Logic Supply Logic Supply Figure 9-5. Typical Application Schematic - SPI (P) Variant in HVSSOP Package VQN-HR SPI CVM1 CVM2 VCC VCC RnFAULT RIPROPI Reverse Supply Protected Input CONTROLLER I/O ADC I/O I/O I/O IN IPROPI nFAULT VM GND OUT DRVOFF nSLEEP CVCP VCP S P I SDO nSCS SDI SCLK VQFN-HR SPI Device 1 CVM1 CVM2 VCC VCC RnFAULT RIPROPI Reverse Supply Protected Input CONTROLLER I/O ADC I/O I/O I/O IN IPROPI nFAULT1 VM GND OUT 5,7 DRVOFF9 nSLEEP3 CVCP1 VCP S P I SDO SDI SCLK VQFN-HR SPI Device 2 IPROPI VM GND OUT CVCP2 VCP 5,7 LOAD I/O nSCS I/O I/O IN nFAULT 1 DRVOFF nSLEEP SDO 14 SDI 13 SCLK 12 nSCS Op onal (5) Op onal (1) Op onal (2) Op onal (3) Op onal (4) Op onal (6) Daisy Chain capable Daisy Chain capable 5,7 Op onal (1) Op onal (2) Op onal (3) Op onal (5) Op onal (6) Daisy Chain capable Full bridge with two half-bridge devices LOAD HS / LS load with half bridge VM / GND Figure 9-6. Typical Application Schematic - SPI (S) Variant in VQFN-HR Package www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: DRV8143-Q1

10 Power Supply Recommendations

The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk capacitor must be placed on the VM pin.

10.1 Bulk Capacitance Sizing

Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The amount of local capacitance needed depends on a variety of factors including:

• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method. The inductance between the power supply and motor drive system limits the rate that current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage remains stable, and high current can be quickly supplied. The data sheet provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. Local Bulk Capacitor Parasitic Wire Inductance Motor Driver Power Supply Motor Drive System VM GND IC Bypass Capacitor Figure 10-1. Example Setup of Motor Drive System With External Power Supply The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases when the motor transfers energy to the supply. DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

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11 Layout

11.1 Layout Guidelines

Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace or ground plane connection to the device GND pin. Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current. Place a low-ESR ceramic capacitor between the VCP and VM pins. This capacitor should be 1 µF, rated for 6.3 V, and be of type X5R or X7R. For the SPI (P) device variant, VDD pin may be bypassed to ground using low-ESR ceramic 6.3 V bypass capacitor with recommended values of 0.1 μF.

11.2 Layout Example

The following figure shows a layout example for a 4 cm X 4 cm x 1.6 mm, 4 layer PCB for a leaded package device. The 4 layers uses 2 oz copper on top/ bottom signal layers and 1 oz copper on internal supply layers, with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 mm minimum via pitch. The same layout can be adopted for the non-leaded VQFN-HR package as well. The Section 7.5.14 for the 4 cm X 4 cm X 1.6 mm is based on a similar layout. Note: The layout example shown is for a full-bridge topology using DRV814xQ1 device in VQFN-HR package. Figure 11-1. Layout example: 4cm x 4 cm x 1.6mm, 4 layer PCB www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: DRV8143-Q1

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Half Bridge Driver Junction Temperature Estimator (Excel-based worksheet)
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

12.4 Trademarks

All trademarks are the property of their respective owners.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and order-able information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

13.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed DRV8143-Q1 SLVSG63 – JANUARY 2023 www.ti.com

58 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV8143-Q1

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H www.ti.com DRV8143-Q1 SLVSG63 – JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: DRV8143-Q1

www.ti.com 13-May-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV8143HQRXYRQ1 ACTIVE VQFN-HR RXY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 DRV8143H Samples DRV8143PQDGQRQ1 ACTIVE HVSSOP DGQ 28 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 8143P Samples DRV8143SQRXYRQ1 ACTIVE VQFN-HR RXY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 DRV8143S Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 13-May-2023 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-May-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DRV8143HQRXYRQ1 VQFN- HR DRV8143SQRXYRQ1 VQFN- HR Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-May-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8143HQRXYRQ1 VQFN-HR RXY 14 3000 367.0 367.0 35.0 DRV8143PQDGQRQ1 HVSSOP DGQ 28 2500 356.0 356.0 35.0 DRV8143SQRXYRQ1 VQFN-HR RXY 14 3000 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. HVSSOP - 1.1 mm max heightDGQ 28 SMALL OUTLINE PACKAGE3 x 7.1, 0.5 mm pitch 4226530/A

www.ti.com PACKAGE OUTLINE C 26X 0.5 2X 6.5 28X 0.275 0.165 5.1

4.7 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8 2X 0.45 MAX NOTE 5 4.94 4.30 1.65 1.01

1.1 MAX

B 3.1 2.9 A 7.2 7.0 NOTE 3 0.7 0.4 (0.15) TYP PowerPAD VSSOP - 1.1 mm max heightDGQ0028A SMALL OUTLINE PACKAGE 4226237/A 10/2020

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. No JEDEC registration as of September 2020. 5. Features may differ or may not be present. SEATING PLANE TM PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICALTHERMAL PAD 14 15

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND ( 0.2) TYP VIA (1.1) TYP (0.65) TYP 28X (1.45) 28X (0.3) 26X (0.5) (4.4) (R0.05) TYP (2.2) NOTE 9 (7.1) NOTE 9 (1.65) (4.94) PowerPAD VSSOP - 1.1 mm max heightDGQ0028A SMALL OUTLINE PACKAGE 4226237/A 10/2020 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 12X SYMM SYMM 14 15 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 28X (1.45) 28X (0.3) 26X (0.5) (4.4) (R0.05) TYP (4.94) BASED ON

0.125 THICK

(1.65) BASED ON PowerPAD VSSOP - 1.1 mm max heightDGQ0028A SMALL OUTLINE PACKAGE 4226237/A 10/2020 1.39 X 4.180.175 1.51 X 4.510.15 1.65 X 4.94 (SHOWN)0.125 1.84 X 5.520.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 12X SYMM SYMM 14 15 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PACKAGE OUTLINE 4226096/B 03/2022 www.ti.com VQFN-HR - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD RXY0014A A 0.08 C B PKG 3.1 2.9 4.6 4.4

1 MAX

.05 .00 C 0.05 C (0.2) TYP PIN 1 INDEX AREA 0.100 MIN (0.130) SECTION A-A TYPICAL (0.16) 2X 3.1 2.9 2X 1.475 1.275 6X (0.4) TYP 10X 0.3 0.2 1.2 1.0 10X 0.5 0.3 10X 0.3 0.2 0.05 C PIN1 ID (OPTIONAL) 1.35 0.65 0.05 0.625 1.125 1.625 0.75 0.25 PKG 14 11 (0.15) TYP

www.ti.com VQFN-HR - 1 mm max heightRXY0014A PLASTIC QUAD FLATPACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X (0) PKG NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

0.05 MIN

NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 10X (0.25) 6X (0.25) 6X (0.4) TYP 2X (3.4) (0.25) (1.3) 10X (0.6) 2X (1.575) (2.15) (1.625) (1.125) (0.625) (0.05) (0.65) (1.35) (1.8) (1.4) (0.75) (0.25) (0.9125) PKG (0) (1.4) (0.75) (0.25) (0.9125) (R0.05) TYP SOLDER MASK OPENING METAL UNDER SOLDER MASK 1114 (0.35) TYP (Ø0.2) TYP VIA 3X (1) 3X (1)

www.ti.com VQFN-HR - 1 mm max heightRXY0014A PLASTIC QUAD FLATPACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 18X NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. (0) PKG 10X (0.25) 6X (0.25) 6X (0.4) TYP (0.25) 4X (0.7) 10X (0.6) 2X (1.575) (2.15) (1.625) (1.125) (0.625) (0.05) (0.65) (1.35) (2.1) (1.4) (0.75) (0.25) (0.9125) PKG (0) (1.4) (0.75) (0.25) (0.9125) (R0.05) TYP METAL UNDER SOLDER MASK 1114 (0.35) TYP (0.2) TYP (0.9) (0.9) 4X (1.6) (0.2)

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