DRV8000QWRGZRQ1

DRV8001-Q1 TI | Alldatasheet

Document overview

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Technical content

DRV8001-Q1 Automotive Highly-Integrated, Multifunction Driver for Door Control

1 Features

• AEC-Q100 qualified for automotive applications: – Temperature grade 1: –40°C to +125°C, TA
• Functional Safety-Compliant Targeted – Developed for functional safety applications – Documentation to aid ISO26262 system design – Systematic integrity up to ASIL D – Hardware integrity up to ASIL B
• 5V to 35V (40V abs. max) operating range
• 1 Integrated half-bridge with IOUT max 8A (RDSON HS +LS FET = 155mΩ)
• 1 Integrated half-bridge with IOUT max 7A (RDSON HS +LS FET = 185mΩ)
• 2 Integrated half-bridges with IOUT max 4A (RDSON HS +LS FET = 440mΩ)
• 2 Integrated half-bridges with IOUT max 1.3A load (RDSON HS +LS FET = 1540mΩ)
• 1 Configurable integrated high-side driver as lamp or LED driver with IOUT Max 1.5/0.5A (RDSON = 0.4/1.2Ω)
• 5 Configurable integrated high-side drivers for 0.5/0.25A load (RDSON = 1.2Ω)
• 1 External MOSFET gate driver for charge of electrochromic glass
• 1 Integrated low-side FET for discharge of electrochromic glass
• Internal 10bit PWM generator for high-side drivers
• All high-side drivers support a low- or high- current threshold constant current mode to drive a wide range of LED modules
• 1 external MOSFET gate driver for heater – Offline open load detection – VDS monitoring of low RDSON MOSFET for short-circuit detection
• Integrated driver output features current regulation (ITRIP)
• Muxable sense output (IPROPI) – Internal current sensing with proportional current output (IPROPI) – Advanced die temperature monitoring with multiple thermal clusters – Motor supply voltage monitor
• Protection and diagnostic features with configurable fault behavior – Load diagnostics in both the off-state and on- state to detect open load and short-circuit – Overcurrent and over temperature protection
• Device Comparison Table

2 Applications

• Door module
• Body control modules
• Zonal module

3 Description

The DRV8001-Q1 device integrates multiple door control specific functions: driving and diagnosing motor (inductive), resistive and capacitive loads, driving a lamp or LEDs , drive MOSFETs for special loads such as heating element or electrochromic elements. These drivers include protection features for offline and active diagnostics such as under and over voltage monitors, offline open load and short-circuit diagnostics, and zone-based thermal monitoring and shutdown protection. The device features 6 integrated half-bridges (2 high-side alternate modes), 6 integrated high-side drivers, one external high-side gate driver for heater, one external high-side gate driver for electrochromic charge and one integrated low-side driver for electrochromic load discharge. The half-bridge , high-side, heater and gate drivers have PWM input control configuration, sensing, diagnostics and device system protection. There is a dedicated internal programmable PWM generators for each high-side driver. Proportional current sense pin output is available for all integrated drivers

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE (NOM)(2) DRV8001-Q1 VQFN (40) 6.00mm × 6.00mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. DRV8001-Q1 Multifunction Driver Power Stage with Motor & LED drivers VBAT Controller Protection Current Sense Current Sense PWM SPI M M Door Lock Mirror Adjust (X) Mirror Adjust (Y) LED 1…6 Mirror Heater Electrochromic Element M M Safe Lock Mirror Fold M Lamp/LED Simplified Schematic DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10.1 Receiving Notification of Documentation Updates107

11 Mechanical, Packaging, and Orderable

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4 Device Comparison

Table 4-1. Device Comparison Device Name H-Bridge Gate Driver Half-bridge Driver High-side Driver Lamp/LED HS Driver EC Gate Driver Heater HS Gate Driver Current Shunt Amp Package DRV8000-Q1 1x 6x 5x 1x 1x 1x 1x 7x7 QFN-48 Wettable Flank DRV8000E- 1x 6x 5x 1x 1x 1x 1x 7x7 QFN-48 Wettable Flank DRV8001-Q1 X 6x 5x 1x 1x 1x X 6x6 QFN-40 Wettable Flank DRV8002-Q1 1x 6x 5x 1x X X 1x 7x7 QFN-48 Wettable Flank Table 4-2. Device Orderable Information Device Pre-production Part Number Orderable Part Number EVM DRV8000-Q1 PDRV8000QWRGZRQ1 DRV8000QWRGZRQ1 DRV8000-Q1EVM P2DRV8000QWRGZRQ1 DRV8000E-Q1 PDRV8000EQWRHARQ1 DRV8000EQWRHARQ1 DRV8000-Q1EVM DRV8001-Q1 PDRV8001QWRHARQ1 DRV8001QWRHARQ1 DRV8001-Q1EVM DRV8002-Q1 PDRV8002QRGZRQ1 DRV8002QWRGZRQ1 DRV8000-Q1EVM P2DRV8002QWRGZRQ1 Selection considerations: 1. DRV8000E-Q1 is optimized for open load detection for low power brushed motors with high off state resistance and independent Half-bridge Gate Driver. 2. DRV8001-Q1 is optimized for applications without the need for an H-bridge Gate Driver in a smaller package. 3. DRV8002-Q1 is optimized for applications without sideview mirrors and pin to pin with DRV8000/E-Q1. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRV8001-Q1

5 Pin Configuration and Functions

23 DGND

32 OUT11

SH_HS GH_HS SDO Figure 5-1. VQFN (RHA) 40-Pin Package and Pin Functions Table 5-1. Pin Functions PIN I/O(1) TYPE DESCRIPTION NO. NAME 1 OUT4 O Power 440mΩ half-bridge output 4. 2 NC － － No connect. 3 NC － － No connect.

4 PVDD I

Device driver power supply input. Connect to the bridge power supply. Connect a 0.1μF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10μF between PVDD and GND pins. 5 VCP I/O Power Charge pump output. Connect a 1μF, 16V ceramic capacitor between VCP and PVDD pins.

6 PVDD I

Device driver power supply input. Connect to the bridge power supply. Connect a 0.1μF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10μF between PVDD and GND pins. 7 OUT5 O Power 155mΩ half-bridge output 5. 8 PGND I/O Ground Device ground. Connect to system ground. 9 OUT1 O Power 1.54Ω half-bridge output 1. 10 OUT2 O Power 1.54Ω half-bridge output 2.

11 PWM2 I Digital PWM input 2 for regulation of half-bridge drivers

12 PWM1 I Digital PWM input 1 for regulation of all drivers except electrochrome. 13 nSCS I Digital Serial chip select. A logic low on this pin enables serial interface communication. Internal pullup resistor. 14 SDI I Digital Serial data input. Data is captured on the falling edge of the SCLK pin. Internal pulldown resistor. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Table 5-1. Pin Functions (continued) PIN I/O(1) TYPE DESCRIPTION NO. NAME 15 SDO O Digital Serial data output. Data is shifted out on the rising edge of the SCLK pin. Push-pull output. 16 SCLK I Digital Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. Internal pulldown resistor.

17 IPROPI I/O Analog Sense output is multiplexed from any of driver load current feedback, PVDD

voltage feedback, or thermal cluster temperature feedback. 18 nSLEEP I Analog Device enable pin. Logic low to shutdown the device and enter sleep mode. Internal pulldown resistor. 19 NC － － No connect. 20 NC － － No connect. 21 DVDD I Power Device logic and digital output power supply input. Recommended to connect a 1.0µF, 6.3V ceramic capacitor between the DVDD and GND pins. 22 NC － － No connect. 23 DGND I/O Ground Device ground. Connect to system ground.

24 ECFB I/O

For EC control, pin is used as voltage monitor input and fast discharge low- side switch. If the EC drive function is not used, connect this pin to GND through 10kΩ resistor.

25 ECDRV O Analog For EC control, pin controls the gate of external MOSFET for EC voltage

26 SH_HS I Analog Source pin of high-side heater MOSFET and output to heater load. Connect to source of high-side MOSFET. 27 GH_HS O Analog Gate driver output for heater MOSFET. Connect to gate of high-side MOSFET. 28 NC － － No connect. 29 NC － － No connect. 30 NC － － No connect. 31 OUT12 O Power 1.2Ω high-side driver output 12. Connect to low-side load. 32 OUT11 O Power 1.2Ω high-side driver output 11. Configurable as SC protection switch for EC drive. Connect to low-side load. 33 OUT10 O Power 1.2Ω high-side driver output 10. Connect to low-side load. 34 OUT9 O Power 1.2Ω high-side driver output 9. Connect to low-side load. 35 OUT8 O Power 1.2Ω high-side driver output 8. Connect to low-side load. 36 OUT7 O Power High-side driver output with configurable RDSON (400 mΩ/1200 mΩ). Connect to low-side load.

37 PVDD I

Device driver power supply input. Connect to the bridge power supply. Connect a 0.1µF, PVDD-rated ceramic capacitor and local bulk capacitance greater than or equal to 10µF between PVDD and GND pins. 38 OUT6 O Power 185mΩ half-bridge output 6. 39 PGND I/O Ground Device ground. Connect to system ground. 40 OUT3 O Power 440mΩ half-bridge output 3. (1) I = Input, O = Output www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV8001-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted) (1) MIN MAX UNIT Power supply pin voltage PVDD –0.3 40 V Power supply transient voltage ramp PVDD 2 V/µs Digital Logic power supply voltage ramp DVDD 2 V/µs Voltage difference between ground pins GND, PGND –0.3 0.3 V Charge pump pin voltage VCP –0.3 PVDD + 15 V Digital regulator pin voltage DVDD –0.3 5.75 V Logic pin voltage PWM1, IPROPI, PWM2, DRVOFF, nSLEEP, SCLK, SDI, nSCS –0.3 5.75 V Output logic pin voltage SDO –0.3 VDVDD + 0.3 V Output pin voltage OUT1-OUT12 –0.3 VPVDD + 0.9 V Output current OUT1-OUT12, ECFB, ECDRV Internally Limited Internally Limited A Heater and Electrochromic MOSFET gate drive pin voltage GH_HS VSH_HS – 0.3 to VSH_HS + 13 VVCP + 0.3 V Heater and Electrochromic MOSFET source pin voltage SH_HS, ECFB, ECDRV –0.3 VPVDD + 0.3 V High-side driver and Heater MOSFET source pin maximum energy dissipation, TJ = 25°C, LLOAD < 100 µH OUT7-OUT12, SH_HS - 1 mJ Ambient temperature, TA –40 125 °C Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings Auto

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 HBM ESD(1) Classification Level 2 PVDD, OUT1 - OUT12, ECFB, GND ±4000 V All other pins ±2000 VCharged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B Corner pins ±750 Other pins ±500 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VPVDD Power supply voltage PVDD 5 35 V VDVDD Logic input voltage DVDD 3.1 5.5 V VDIN Digital input voltage PWM1, IPROPI, PWM2, SCLK, SDI 0 5.5 V IDOUT Digital output current SDO 0 5 mA fPWM Input PWM frequency PWM1, PWM2 0 25 kHz VIPROPI Analog output voltage for VPVDD > 7 V IPROPI 0 5.2 V DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VIPROPI Analog output voltage for VPVDD < 7 V IPROPI 0 VPVDD - 1.8 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C

6.4 Thermal Information RHA package

THERMAL METRIC(1) RHA Package UNIT RθJA Junction-to-ambient thermal resistance 26.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 15.8 °C/W RθJB Junction-to-board thermal resistance 9.3 °C/W ΨJT Junction-to-top characterization parameter 0.2 °C/W ΨJB Junction-to-board characterization parameter 9.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (DVDD, VCP, PVDD) IPVDDQ PVDD sleep mode current VPVDD = 13.5 V, nSLEEP = 0 V -40 ≤ TJ ≤ 85˚C 3.5 5.5 µA IDVDDQ DVDD sleep mode current VPVDD = 13.5 V, nSLEEP = 0 V -40 ≤ TJ ≤ 85˚C 3 4 µA IPVDD PVDD active mode current VPVDD = 13.5, nSLEEP = VDVDD 6.2 11.5 mA IDVDD DVDD active mode current SDO = 0 V 3.1 6.5 mA IPVDD_CP_DIS PVDD charge pump disabled mode current VPVDD = 13.5 V, DIS_CP = 1, HEAT_EN = 0, EC_ON = 0, OUTx_EN = 0 1.4 4 mA IDVDD_CP_DIS DVDD charge pump disabled mode current VPVDD = 13.5 V, DIS_CP = 1, HEAT_EN = 0, EC_ON = 0, OUTx_EN = 0 2.8 5.5 mA tSLEEP Turnoff time nSLEEP = 0 V to sleep mode 1 ms tREADY_HB_H S Turnon time for half-bridges and high- side drivers 5 ms tREADY_HEAT Turnon time for heater 10 ms fVDD Digital oscillator switching frequency Primary frequency of spread spectrum 12.83 14.25 15.68 MHz fVDD Digital oscillator spread spectrum range Center spread on primary frequency -7 7 % VVCP Charge pump regulator voltage with respect to PVDD VPVDD >7 V, IVCP ≤ 80 µA 8.5 9 12.5 V VPVDD = 5 V, IVCP ≤ 60 µA 6.8 7.5 11 V tCP_EN Charge pump turn on time after any OUTx enable. Includes initailization. 3 ms IVCP_LIM Charge pump output current limit VPVDD = 13.5 V, CVCP = 1 µF, inrush during charge pump start-up 750 µA VCP_UV Charge pump undervoltage threshold VVCP - VPVDD, VVCP falling 5 6 7 V tCP_UV_DG Charge pump undervoltage deglitch time 8 10 12.75 µs LOGIC-LEVEL INPUTS (INx, nSLEEP, SCLK, SDI, etc) www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRV8001-Q1

5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input logic low voltage PWM1, PWM2, nSLEEP, SCLK, SDI 0.3 VDVDD x 0.3 V VIH Input logic high voltage PWM1, PWM2, nSLEEP, SCLK, SDI VDVDD x 0.7 5.5 V VHYS Input hysteresis PWM1, PWM2, nSLEEP, SCLK, SDI VDVDD x 0.15 V IIL Input logic low current VDIN = 0 V, PWM1, PWM2, nSLEEP, SCLK, SDI –5 5 µA IIL Input logic low current VDIN = 0 V, nSCS 25 50 µA IIH Input logic high current VDIN = VDVDD, nSCS –5 5 µA IIH Input logic high current VDIN = VDVDD, PWM1, PWM2, nSLEEP, SCLK, SDI 25 50 µA RPD Input pulldown resistance To GND, PWM1, PWM2, nSLEEP, SCLK, SDI 140 200 260 kΩ RPU Input pullup resistance To DVDD, nSCS 140 200 265 kΩ PUSH-PULL OUTPUT SDO VOL Output logic low voltage IOD = 5 mA 0.5 V VOH Output logic high voltage IOD = –5 mA, SDO DVDD x 0.8 V HEATER MOSFET DRIVER IGH_HS_HEAT Average charge-current TJ = 25 ˚C 50 mA RGL_HEAT On-resistance (discharge stage) IGH_HS_HEAT = 25 mA; TJ = 25 ˚C 15 20 25 Ω RGL_HEAT On-resistance (discharge stage) IGH_HS_HEAT = 25 mA; TJ = 125 ˚C 28 36 Ω VGH_HS_HIGH GH_HS high level output voltage VPVDD = 5 V; ICP = 15 mA VSH_HS + 6 V VGH_HS_HIGH GH_HS high level output voltage VPVDD = 13.5 V; ICP = 15 mA VSH_HS + 7.5 VSH_HS + VSH_HS + 11.5 V IHEAT_SH_ST BY_LK SH_HS leakage current standby 25 µA RGS_HEAT Passive gate-clamp resistance 150 kΩ tPDR_GH_HS GH_HS rising propagation delay VPVDD = 13.5 V; RG = 0 Ω; CG = 2.7 nF 0.6 µs tPDF_GH_HS GH_HS falling propagation delay VPVDD = 13.5 V; VSH_HS = 0 V; RG = 0 Ω; CG = 2.7 nF 0.5 µs tRISE_GH_HS Rise time (switch mode) VPVDD = 13.5 V; VSH_HS = 0 V; RG = 0 Ω; CG = 2.7 nF 300 ns tFALL_GH_HS Fall time (switch mode) VPVDD = 13.5 V; VSH_HS = 0 V; RG = 0 Ω; CG = 2.7 nF 170 ns HEATER PROTECTION CIRCUITS DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDS_LVL_HEA T VDS overcurrent protection threshold for heater MOSFET HEAT_VDS_LVL = 0000b 0.050 0.06 0.07 V HEAT_VDS_LVL = 0001b 0.067 0.08 0.093 V HEAT_VDS_LVL = 0010b 0.085 0.10 0.115 V HEAT_VDS_LVL = 0011b 0.102 0.12 0.138 V HEAT_VDS_LVL = 0100b 0.119 0.14 0.161 V HEAT_VDS_LVL = 0101b 0.136 0.16 0.184 V HEAT_VDS_LVL = 0110b 0.153 0.18 0.207 V HEAT_VDS_LVL = 0111b 0.17 0.2 0.23 V HEAT_VDS_LVL = 1000b 0.204 0.240 0.276 V HEAT_VDS_LVL = 1001b 0.238 0.280 0.322 V HEAT_VDS_LVL = 1010b 0.272 0.320 0.368 V HEAT_VDS_LVL = 1011b 0.306 0.360 0.414 V HEAT_VDS_LVL = 1100b 0.340 0.400 0.460 V HEAT_VDS_LVL = 1101b 0.374 0.440 0.506 V HEAT_VDS_LVL = 1110b 0.476 0.560 0.644 V HEAT_VDS_LVL = 1111b 0.85 1 1.15 V tDS_HEAT_DG VDS overcurrent protection deglitch time HEAT_VDS_DG = 00b 0.75 1 1.5 µs HEAT_VDS_DG = 01b 1.5 2 2.5 µs HEAT_VDS_DG = 10b 3.25 4 4.75 µs HEAT_VDS_DG = 11b 6 8 10 µs tDS_HEAT_BLK VDS overcurrent protection blanking time HEAT_VDS_BLK = 00b 3.25 4 4.75 µs HEAT_VDS_BLK = 01b 6 8 10 µs HEAT_VDS_BLK = 10b 13 16 19 µs HEAT_VDS_BLK = 11b 27 32 37 µs VOL_HEAT Open load threshold voltage VSH_HS = 0 V 1.8 2 2.2 V IOL_HEAT Pullup current source open-load diagnosis activated VSH_HS = 0 V; VSHheater = 4.5 V 1 mA tOL_HEAT Open-load filter time for heater MOSFET 2 ms ELECTROCHROMIC DRIVER RDSON ECFB Low-side MOSFET on resistance for EC discharge VPVDD = 13.5 V; TJ = 25 ˚C; IECFB = ±0.25 A ECFB_LS_EN = 1b 1375 mΩ RDSON ECFB Low-side MOSFET on resistance for EC discharge VPVDD = 13.5 V; TJ = 150 ˚C; IECFB = ±0.125 A ECFB_LS_EN = 1b 2500 mΩ IOC_ECFB Overcurrent threshold of low-side MOSFET VPVDD = 13.5 V; IECFB current sink 0.5 1 A tDG_OC_ECFB Overcurrent shutdown deglitch time VPVDD <20 V; IECFB current sink 40 µs VPVDD >20 V; IECFB current sink 15 µs dVECFB/dt Slew rate of ECFB, low-side MOSFET VPVDD = 13.5 V, Rload = 64 Ω to PVDD 7 V/µs IOL_ECFB_LS Open load detection threshold for EC during discharge EC_OLEN = 1b, ECFB_LS_EN = 1b 10 20 32 mA tDG_OL_ECFB _LS Open load detection deglitch time EC_OLEN = 1b, ECFB_LS_EN = 1b 400 600 µs VEC_CTRLmax Maximum EC-control voltage target for ECFB ECFB_MAX = 1b 1.4 1.6 V www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRV8001-Q1

5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VEC_CTRLmax Maximum EC-control voltage target for ECFB ECFB_MAX = 0b 1.12 1.28 V VEC_res Minimum resolution for adjustable voltage of ECFB EC_ON = 1b 23.8 mV DNLECFB Differential Non Linearity EC_ON = 1b –2 2 LSB |dVECFB| Voltage deviation between target and ECFB Vtarget = 23.8 mV, dVECFB=Vtarget - VECFB; |IECDRV| < 1 µA –5% (– 1LSB) +5% (+1LSB) mV |dVECFB| Voltage deviation between target and ECFB Vtarget = 1.5V, dVECFB=Vtarget - VECFB; | IECDRV| < 1 µA –5% (– 1LSB) +5% (+1LSB) mV VECFB_HI Indicates voltage at ECFB is higher than target EC_ON = 1b Vtarget + 0.12 V VECFB_LO Indicates voltage at ECFB is lower than target EC_ON = 1b Vtarget – 0.12 V tFT_ECFB Filter time of ECFB high/low flag EC_ON = 1b 32 µs tBLK_ECFB Blanking time of EC regulation flags Any EC target voltage change 200 250 300 µs VECFB_OV_T H Threshold for overvoltage on ECFB ECFB_OV_MODE = 01b or 10b, EC_ON = 1b 3 V tECFB_OV_DG Deglitch time for overvoltage flag on ECFB ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 00b 16 20 24 µs ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 01b 40 50 60 µs ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 10b 80 100 120 µs ECFB_OV_MODE = 01b or 10b, ECFB_OV_DG = 11b 160 200 240 µs VECDRVminHI GH Output voltage range of ECDRV when EC_ON = 1 IECDRV = -10µA 4.5 6.5 V VECDRVmaxL OW Output voltage range of ECDRV when EC_ON = 0 IECDRV = 10µA 0 0.7 V IECDRV Current into ECDRV Vtarget > VECFB + 500 mV; VECDRV = 3.5 V –730 –80 µA IECDRV Current into ECDRV Vtarget < VECFB - 500 mV; VECDRV = 1.0 V; Vtarget = 1 LSB; VECFB = 0.5 V 150 350 µA RECDRV_DIS Pulldown resistance at ECDRV in fast discharge mode VECDRV = 0.7 V; EC enabled, then EC<5:0> = 0 or EC disabled 11 kΩ tDISCHARGE Auto-discharge pulse width ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b 240 300 360 ms tECFB_DISC_B LK Auto-discharge blanking time ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b 2.25 3 3.75 ms VDISC_TH PWM discharge level VECDRV ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b 335 400 465 mV VDISC_TH_DIF F PWM discharge threshold level VECDRV - VECFB ECFB_LS_PWM = 1b, ECFB_LS_EN = 1b –50 0 50 mV VECFB_OLP_T H Threshold for open load detection on ECFB EC_EN = 0b, EC_DIAG = 10b 2 V IECFB_OLP Current into ECFB during open load detection EC_EN = 0b, EC_DIAG = 10b 0.5 mA tECFB_OLP Open load filter time for ECFB EC_ON=0b, ECFB_DIAG=10b 2 3 4 ms DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VECFB_SC_TH Threshold for short-circuit detection on ECFB EC_EN = 0b, EC_DIAG = 01b, ECFB_SC_RSEL=00b 25 mV EC_EN = 0b, EC_DIAG = 01b, ECFB_SC_RSEL=01b 50 mV EC_EN = 0b, EC_DIAG = 01b, ECFB_SC_RSEL=10b 100 mV EC_EN = 0b, EC_DIAG = 01b, ECFB_SC_RSEL=11b 150 mV IECFB_SC Current into ECFB during short-circuit detection EC_EN = 0b, EC_DIAG = 01b 50 mA tECFB_SC Short-circuit diagnostics filter time for ECFB EC_ON=0b, ECFB_DIAG=01b 2 3 4 ms HALF-BRIDGE DRIVERS RON_OUT1,2_ HS High-side MOSFET on resistance IOUT = 0.325A, TJ = 25˚C 775 mΩ IOUT = 0.325A, TJ = 150˚C 1480 mΩ RON_OUT1,2_ LS Low-side MOSFET on resistance IOUT = 0.325A, TJ = 25˚C 765 mΩ IOUT = 0.325A, TJ = 150˚C 1460 mΩ RON_OUT3,4_ HS High-side MOSFET on resistance IOUT = 1A, TJ = 25˚C 220 mΩ IOUT = 1A, TJ = 150˚C 450 mΩ RON_OUT3,4_ LS Low-side MOSFET on resistance IOUT = 1A, TJ = 25˚C 220 mΩ IOUT = 1A, TJ = 150˚C 450 mΩ RON_OUT5_H S High-side MOSFET on resistance IOUT = 2A, TJ = 25˚C 80 mΩ IOUT = 2A, TJ = 150˚C 160 mΩ RON_OUT5_L S Low-side MOSFET on resistance IOUT = 2A, TJ = 25˚C 75 mΩ IOUT = 2A, TJ = 150˚C 150 mΩ RON_OUT6_H S High-side MOSFET on resistance IOUT = 1.75A, TJ = 25˚C 90 mΩ RON_OUT6_H S High-side MOSFET on resistance IOUT = 1.75A, TJ = 150˚C 180 mΩ RON_OUT6_L S Low-side MOSFET on resistance IOUT = 1.75A, TJ = 25˚C 95 mΩ RON_OUT6_L S Low-side MOSFET on resistance IOUT = 1.75A, TJ = 150˚C 190 mΩ SROUT_HB Output voltage rise/fall time for all half- bridge OUTx, 10% - 90% PVDD = 13.5 V; OUTx_SR = 00b 1.6 V/µs SROUT_HB Output voltage rise/fall time for all half- bridge OUTx, 10% - 90% PVDD = 13.5 V; OUTx_SR = 01b 13.5 V/µs SROUT_HB Output voltage rise/fall time for all half- bridge OUTx, 10% - 90% PVDD = 13.5 V; OUTx_SR = 10b 24 V/µs tPD_OUT_HB_ HS_R Propagation time during output voltage rise for HS ON command or INx (SPI last transition) to OUTx 10% voltage rise (any SR setting) 2 10 µs tPD_OUT_HB_ HS_F Propagation time during output voltage fall for HS ON command or INx (SPI last transition) to OUTx 10% voltage fall (any SR setting) 1.5 11 µs tPD_OUT_HB_ LS_R Propagation time during output voltage rise for LS ON command or INx (SPI last transition) to OUTx 10% voltage rise (any SR setting) 1.5 10 µs tPD_OUT_HB_ LS_F Propagation time during output voltage fall for LS ON command or INx (SPI last transition) to OUTx 10% voltage fall (any SR setting) 1.5 10 µs www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRV8001-Q1

5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDEAD_HS_ON Dead time during output voltage rise for HS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1 6 µs tDEAD_HS_OF F Dead time during output voltage fall for HS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1 6 µs tDEAD_LS_ON Dead time during output voltage rise for LS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1 7 µs tDEAD_LS_OF F Dead time during output voltage fall for LS PVDD = 13.5 V; OUTx_ITRIP_LVL = 00b, All SRs 1.7 14 µs HALF-BRIDGE PROTECTION CIRCUITS IOCP_OUT1,2 Overcurrent protection threshold 1.2 2.2 A IOCP_OUT3,4 Overcurrent protection threshold 4 8 A IOCP_OUT5 Overcurrent protection threshold 8 16 A IOCP_OUT6 Overcurrent protection threshold 7 13 A tDG_OCP_HB Overcurrent protection deglitch time in half-bridge drivers OUTX_OCP_DG = 00b 4.5 6 7.3 µs OUTX_OCP_DG = 01b 8 10 12 µs OUTX_OCP_DG = 10b 12 15 18 µs OUTX_OCP_DG = 11b 48 60 72 µs IITRIP_OUT1,2 Current threshold to trigger ITRIP regulation for OUT1 and OUT2 OUT1_ITRIP_LVL = 1b and OUT2_ITRIP_LVL = 1b 0.65 1.1 A OUT1_ITRIP_LVL = 0b and OUT2_ITRIP_LVL = 0b 0.5 0.9 A IITRIP_OUT3,4 Current threshold to trigger ITRIP regulation for OUT3 and OUT4 OUT3_ITRIP_LVL = 10b and OUT4_ITRIP_LVL = 10b 2.9 4.1 A OUT3_ITRIP_LVL = 01b and OUT4_ITRIP_LVL = 01b 1.6 3.25 A OUT3_ITRIP_LVL = 00b and OUT4_ITRIP_LVL = 00b 1 1.6 A IITRIP_OUT5 Current threshold to trigger ITRIP regulation for OUT5 OUT5_ITRIP_LVL = 10b 6.65 8.95 A OUT5_ITRIP_LVL = 01b 5.65 7.8 A OUT5_ITRIP_LVL = 00b 2.5 3.4 A IITRIP_OUT6 Current threshold to trigger ITRIP regulation for OUT6 OUT6_ITRIP_LVL = 10b 5.35 7.35 A IITRIP_OUT6 Current threshold to trigger ITRIP regulation for OUT6 OUT6_ITRIP_LVL = 01b 4.65 6.4 A IITRIP_OUT6 Current threshold to trigger ITRIP regulation for OUT6 OUT6_ITRIP_LVL = 00b 1.75 2.75 A fITRIP_HB Fixed frequency of ITRIP regulation for half-bridge drivers OUTX_ITRIP_FREQ = 00b 17 20 23 kHz OUTX_ITRIP_FREQ = 01b 8 10 12 kHz OUTX_ITRIP_FREQ = 10b 4 5 6 kHz OUTX_ITRIP_FREQ = 11b 2 2.5 3 kHz tDG_ITRIP_HB ITRIP regulation deglitch time for half- bridge drivers OUTX_ITRIP_DG = 00b 1.5 2 2.5 µs OUTX_ITRIP_DG = 01b 4 5 6 µs OUTX_ITRIP_DG = 10b 8 10 12 µs OUTX_ITRIP_DG = 11b 16 20 24 µs IOLA_OUT1,2 Under-current threshold for half-bridges 1 and 2 6 20 30 mA IOLA_OUT3,4 Under-current threshold for half-bridges 3 and 4 15 50 90 mA DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOLA_OUT5 Under-current threshold for half-bridges 5 40 150 300 mA IOLA_OUT6 Under-current threshold for half-bridges 6 30 120 240 mA tOLA_HB Filter time of open-load signal for half- bridges Duration of open-load condition to set the status bit 10 ms AIPROPI1,2 Current scaling factor for OUT1-2 650 A/A AIPROPI3,4 Current scaling factor for OUT3-4 1940 A/A AIPROPI5 Current scaling factor for OUT5 4000 A/A AIPROPI6 Current scaling factor for OUT6 3500 A/A IACC_1,2 Current sense output accuracy for OUT1-2 0.1 A < IOUT1,2 < 0.25 A -15 15 % 0.25 A < IOUT1,2 < 0.5 A -10 10 %

0.5 A < IOUT1,2 < 1 A, TJ < 125C -8 8 %

0.5 A < IOUT1,2 < 1 A, TJ > 125C -12 12 %

IACC_3,4 Current sense output accuracy for OUT3-4 0.1 A < IOUT3,4 < 0.5 A -15 15 %

0.5 A < IOUT3,4 < 1 A -12 12 %

1 A < IOUT3,4 < 2 A -10 10 %

2 A < IOUT3,4 < 4 A, TJ < 125C -8 8 %

2 A < IOUT3,4 < 4 A, TJ > 125C -10 10 %

IACC_5 Current sense output accuracy for OUT5 0.1 A < IOUT5 < 0.8 A -40 40 % IACC_5 0.8 A < IOUT5 < 2 A -12 12 % IACC_5 2 A < IOUT5 < 4 A -10 10 % IACC_5 4 A < IOUT5 < 8 A -8 8 % IACC_6 Current sense output error for OUT6 0.1 A < IOUT6 < 0.8 A -40 40 % IACC_6 0.8 A < IOUT6 < 2 A -12 12 % IACC_6 2 A < IOUT6 < 4 A -10 10 % IACC_6 4 A < IOUT6 < 8 A -8 8 % RS_GND Resistance threshold on OUTx to GND detected as a short during OLP VDVDD = 5 V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 0.8 3 kΩ RS_PVDD Resistance threshold on OUTx to PVDD detected as a short during OLP VPVDD = 13.5 V, VDVDD = 5 V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 3 15 kΩ RS_PVDD Resistance threshold on OUTx to PVDD detected as a short during OLP

5 V ≤ VPVDD ≤ 35 V, VDVDD = 5

V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1 40 kΩ ROPEN_HB Resistance on OUTx detected as an open VDVDD = 5 V, VOLP_REF = 2.65 V, OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 320 1500 Ω VOLP_REFH OLP comparator Reference High OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 2.85 V VOLP_REFL OLP comparator Reference Low OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1.7 V ROLP_PU Internal pullup resistance on OUTx to VDD during OLP OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1 kΩ www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRV8001-Q1

5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ROLP_PD Internal pulldown resistance on OUTx to VDD during OLP OUTX_CNFG = 0b, HB_OLP_CNFG > 0b and HB_OLP_SEL > 0b 1 kΩ HIGH-SIDE DRIVERS RDSON OUT7 (low RDSON mode) High-side MOSFET on resistance in low resistance mode TJ = 25˚C; IOUT7 = ±0.375A 400 mΩ TJ = 150˚C; IOUT7 = ±0.375A 730 mΩ RDSON OUT7 (high RDSON mode) High-side MOSFET on resistance in high resistance mode TJ = 25˚C; IOUT7 = ±0.125A 1200 mΩ TJ = 150 ˚C; IOUT7 = ±0.125 A 2200 mΩ RDSON OUT8 High-side MOSFET on resistance TJ = 25˚C; IOUT8 = ±0.125A 1200 mΩ TJ = 150˚C; IOUT8 = ±0.125A 2200 mΩ RDSON OUT9 High-side MOSFET on resistance TJ = 25˚C; IOUT9 = ±0.125A 1200 mΩ TJ = 150˚C; IOUT9 = ±0.125A 2200 mΩ RDSON OUT10 High-side MOSFET on resistance TJ = 25˚C; IOUT10 = ±0.125A 1200 mΩ TJ = 150˚C; IOUT10 = ±0.125A 2200 mΩ RDSON OUT11 High-side MOSFET on resistance TJ = 25˚C; IOUT11 = ±0.125A 1200 mΩ TJ = 150˚C; IOUT11 = ±0.125A 2200 mΩ RDSON OUT12 High-side MOSFET on resistance TJ = 25˚C; IOUT12 = ±0.125A 1200 mΩ TJ = 150˚C; IOUT12 = ±0.125A 2200 mΩ SRHS_OUT7_ HI Slew rate for OUT7 High RDSON mode (10 to 90% of the final OUT value) OUT7_RDSON_MODE = 0b, PVDD = 13.5V, Rload = 64 Ω 0.3 V/µs SRHS_OUT7_ LO Slew rate for OUT7 Low RDSON mode (10 to 90% of the final OUT value) OUT7_RDSON_MODE = 1b, PVDD = 13.5V, Rload = 16 Ω 0.24 V/µs SRHS Slew rate for OUT8 – OUT12 (10 to 90% of the final OUT value) PVDD = 13.5V, Rload 64 Ω 1.4 V/µs tPD_OUT7_HI_ ON Rise propagation delay time driver for OUT7 High RDSON mode (Delay between High-side ON command (SPI last transition) to 10% of final OUT7 value) OUT7_RDSON_MODE = 0b, PVDD=13.5V, Rload = 64 Ω 16 µs tPD_OUT7_HI_ OFF Fall propagation delay time driver for OUT7 High RDSON mode (Delay between High-side OFF command (SPI last transition) to 90% of final OUT7 value) OUT7_RDSON_MODE = 0b, PVDD=13.5V, Rload = 64 Ω 16 µs tPD_OUT7_LO _ON Rise propagation delay time driver for OUT7 Low RDSON mode (Delay between High-side ON command (SPI last transition) to 10% of final OUT7 value) OUT7_RDSON_MODE = 1b, PVDD=13.5V, Rload =16 Ω 19 µs tPD_OUT7_LO _OFF Fall propagation delay time driver for OUT7 Low RDSON mode (Delay between High-side OFF command (SPI last transition) to 90% of final OUT7 value) OUT7_RDSON_MODE = 1b, PVDD=13.5V, Rload =16 Ω 19 µs tPD_HS_ON Rising propagation delay time driver for high-side drivers OUT8 – OUT12 (Delay between High-side ON command (SPI last transition) to 10% of final OUTx value) PVDD=13.5V, Rload = 64 Ω 4 µs DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPD_HS_OFF Falling propagation delay time driver for high-side drivers OUT8 – OUT12 (Delay between High-side OFF command (SPI last transition) to 90% of final OUTx value) PVDD=13.5V, Rload = 64 Ω 4 µs fPWMx(00) PWM switching frequency PWM_OUTX_FREQ = 00b 78 108 138 Hz fPWMx(01) PWM switching frequency PWM_OUTX_FREQ = 01b 157 217 277 Hz fPWMx(10) PWM switching frequency PWM_OUTX_FREQ = 10b 229 289 359 Hz fPWMx(11) PWM switching frequency PWM_OUTX_FREQ = 11b 374 434 494 Hz ILEAK_H Switched-off output current high-side drivers of OUT7-12 VOUT = 0 V; standby mode –10 µA HIGH-SIDE DRIVER PROTECTION CIRCUITS IOC7 Overcurrent threshold in high RDSON mode OUT7_RDSON_MODE = 0b 500 1000 mA Overcurrent threshold in low RDSON mode OUT7_RDSON_MODE = 1b 1500 3000 mA IOC8, IOC9, IOC10, IOC11,IOC12 Overcurrent threshold OUT8 - OUT12 OUTX_OC_TH = 0b 250 500 mA OUTX_OC_TH = 1b 500 1000 mA ICCM_OUT7 Constant current level for high-side driver OUT7 High RDSON OUT7_RDSON_MODE = 0b, OUT7_CCM_EN = 1b, OUT7_CCM_TO = 0b 180 250 330 mA OUT7_RDSON_MODE = 0b, OUT7_CCM_EN = 1b, OUT7_CCM_TO = 1b 240 330 420 mA ICCM_OUT7 Constant current level for high-side driver OUT7 Low RDSON OUT7_RDSON_MODE = 1b, OUT7_CCM_EN = 1b, OUT7_CCM_TO = 0b 210 360 530 mA ICCM_OUT7 OUT7_RDSON_MODE = 1b, OUT7_CCM_EN = 1b, OUT7_CCM_TO = 1b 250 450 650 mA ICCM Constant current level for high-side drivers OUT8-12 OUTX_CCM_EN = 1b, OUTX_CCM_TO = 0b 240 350 450 mA OUTX_CCM_EN = 1b, OUTX_CCM_TO = 1b 320 450 580 mA tCCMto Constant current mode time expiration OUTX_CCM_EN = 1b 8 10 12 ms VSC_DET Short-circuit detection Voltage on OUT7-12 2 V tSC_BLK Blank time for short-circuit detection, ITRIP regulation and overcurrent protection in OUT7-12 40 µs t_HS_DG_OUT Degltich time for short circuit detection , ITRIP regulation and overcurrent protection in OUT7 OUT7_ITRIP_DG = 00b , PVDD ≤ 20V 39 48 59 µs OUT7_ITRIP_DG = 01b , PVDD ≤ 20V 32 40 48 µs OUT7_ITRIP_DG = 10b , PVDD ≤ 20V 26 32 38 µs OUT7_ITRIP_DG = 11b , PVDD ≤ 20V 19 24 29 µs PVDD > 20V 9 12 14 µs fITRIP_HS_OU ITRIP frequency for high-side driver OUT7 OUT7_ITRIP_FREQ = 00b 1.7 kHz OUT7_ITRIP_FREQ = 01b 2.2 kHz OUT7_ITRIP_FREQ = 10b 3 kHz OUT7_ITRIP_FREQ = 11b 4.4 kHz www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV8001-Q1

5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t_HS_DG_OUT x Degltich time for short-circuit detection , ITRIP regulation and overcurrent protection in OUT8-12 OUTX_ITRIP_DG = 00b , PVDD ≤ 20V 39 48 59 µs OUTX_ITRIP_DG = 01b , PVDD ≤ 20V 32 40 48 µs OUTX_ITRIP_DG = 10b , PVDD ≤ 20V 26 32 38 µs OUTX_ITRIP_DG = 11b , PVDD ≤ 20V 19 24 29 µs PVDD > 20V 9 12 14 µs fITRIP_HS_OU TX ITRIP frequency for high-side driver OUT8-12 HS_OUT_ITRIP_FREQ=00b 1.7 kHz HS_OUT_ITRIP_FREQ=01b 2.2 kHz HS_OUT_ITRIP_FREQ=10b 3 kHz HS_OUT_ITRIP_FREQ=11b 4.4 kHz IOLD7 Open-load threshold for OUT7 OUT7_RDSON_MODE = 1b 15 30 mA Open-load threshold for OUT7 OUT7_RDSON_MODE = 0b 5 10 mA IOLD8, IOLD9, IOLD10, IOLD11, IOLD1 Open-load threshold for OUT8 - OUT12 OUTX_OLA_TH = 0b 1.3 3.3 mA OUTX_OLA_TH = 1b 4 12 mA tOLD_HS Filter time of open-load signal for high- side drivers Duration of open-load condition to set the status bit 200 250 µs AIPROPI7_HI Current scaling factor for OUT7 in high on-resistance mode OUT7_RDSON_MODE = 0b 250 A/A AIPROPI7_LO Current scaling factor for OUT7 in low on-resistance mode OUT7_RDSON_MODE = 1b 750 A/A AIPROPI8, AIPROPI9, AIPROPI10, AIPROPI11, AIPROPI12, Current scaling factor for OUT8-12 250 A/A IACC_7_HI_RD SON Current sense output accuracy for OUT7 in high RDSON mode 0.1 A < IOUT7 < 0.5 A -18 18 % IACC_7_HI_RD SON Current sense output accuracy for OUT7 in high RDSON mode IOUT7 = 0.25 A -10 10 % IACC_7_LOW_ RDSON Current sense output accuracy for OUT7 in low RDSON mode 0.5 A < IOUT7 < 1.5 A -14 14 % IACC_7_LOW_ RDSON Current sense output accuracy for OUT7 in low RDSON mode IOUT7 = 1 A -8 8 % IACC_8-12_LO Current sense output accuracy for low current OUT8-12 0.05 A < IOUT8-12 < 0.1 A -28 28 % IACC_8-12_LO Current sense output accuracy for low current OUT8-12 IOUT8-12 < 0.075 A -20 20 % IACC_8-12_LO Current sense output accuracy for low current OUT8-12 IOUT8-12 < 0.1 A -18 18 % IACC_8-12_HI Current sense output accuracy for high current OUT8-12 0.1 A < IOUT8-12 < 0.5 A -18 18 % IACC_8-12_HI Current sense output accuracy for high current OUT8-12 IOUT8-12 = 0.25 A -10 10 % IACC_8-12_HI Current sense output accuracy for high current OUT8-12 IOUT8-12 = 0.5 A -6 6 % tIPROPI_BLK IPROPI blanking time OUT7-12 goes high to IPROPI ready, only applicable when monitoring High- side driver current 60 µs IPROPI mux switching to IPROPI ready 5 µs PROTECTION CIRCUITS DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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5 V ≤ VPVDD ≤ 35 V, 3.1 V ≤ VDVDD ≤ 5.5 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted). Typical limits apply for VPVDD = 13.5 V, VDVDD = 5 V and TJ = 25˚C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VPVDD_UV PVDD undervoltage threshold VPVDD rising 4.425 4.725 5 V VPVDD falling 4.225 4.525 4.8 V VPVDD_UV_H YS PVDD undervoltage hysteresis Rising to falling threshold 250 mV tPVDD_UV_DG PVDD undervoltage deglitch time 8 10 12.75 µs VPVDD_OV PVDD overvoltage threshold VPVDD rising, PVDD_OV_LVL = 0b 20 21 22 V VPVDD falling, PVDD_OV_LVL = 0b 19 20 21 V VPVDD rising, PVDD_OV_LVL = 1b 25.75 26.8 28 V VPVDD falling, PVDD_OV_LVL = 1b 24.75 25.8 27 V VPVDD_OV_H YS PVDD overvoltage hysteresis Rising to falling threshold 1 V tPVDD_OV_DG PVDD overvoltage deglitch time PVDD_OV_DG = 00b 0.75 1 1.5 µs PVDD_OV_DG = 01b 1.5 2 2.5 µs PVDD_OV_DG = 10b 3.25 4 4.75 µs PVDD_OV_DG = 11b 7 8 9 µs VDVDD_POR DVDD supply POR threshold DVDD falling 2.5 2.7 2.9 V DVDD rising 2.6 2.8 3 V VDVDD_POR_ HYS DVDD POR hysteresis Rising to falling threshold 100 mV tDVDD_POR_D G DVDD POR deglitch time 5 12 25 µs tWD Watchdog window min WD_WIN = 0b 3.4 4 4.6 ms WD_WIN = 1b 8.5 10 11.5 ms Watchdog window max WD_WIN = 0b 10.5 12 13.5 ms WD_WIN = 1b 85 100 115 ms AIPROPI_PVD D_VOUT IPROPI PVDD Voltage Sense Output Scaling Factor (VPVDD / IIPROPI ) IPROPI_SEL = 10000b (5V-22V sense range) 9 11 13 V/mA AIPROPI_PVD D_VOUT IPROPI PVDD Voltage Sense Output Scaling Factor (VPVDD / IIPROPI ) IPROPI_SEL = 101010b (20V - 32V sense range) 13.5 16.5 19.5 V/mA VIPROPI_TEM P_VOUT IPROPI Temperature Sense Output –20 +20 °C TOTW1 Low Thermal warning temperature TJ rising 105 120 135 °C TOTW2 High Thermal warning temperature TJ rising 125 140 155 °C THYS Thermal warning hysteresis 20 °C TOTSD Thermal shutdown temperature TJ rising 155 170 185 °C THYS Thermal shutdown hysteresis 20 °C tOTSD_DG Thermal shutdown deglitch time 10 µs

6.6 Timing Requirements

fSPI SPI supported clock frequency(1) (2) 5 MHz tREADY_SPI SPI ready after power up 1 ms tCLK SCLK minimum period 200 ns tCLKH SCLK minimum high time 100 ns tCLKL SCLK minimum low time 100 ns tHI_nSCS nSCS minimum high time 300 ns www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRV8001-Q1

tSU_nSCS nSCS input setup time 25 ns tH_nSCS nSCS input hold time 25 ns tSU_SDI SDI input data setup time 25 ns tH_SDI SDI input data hold time 25 ns tD_SDO SDO output data delay time, CL = 20 pF(1) 60 ns tEN_nSCS Enable delay time, nSCS low to SDO active 50 ns tDIS_nSCS Disable delay time, nSCS high to SDO Hi-Z 50 ns (1) SDO delay times are valid only with SDO external load (CL) of 20 pF. Increasing load on SDO add an additional delay on SDO limiting the SCLK maximum. (2) Refer to SPI Timing diagram for parameters. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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7 Detailed Description

7.1 Overview

The DRV8001-Q1 device integrates multiple types of drivers intended for multiple functions: driving and diagnosing motor (inductive), resistive and capacitive loads. The devices features 6 integrated half-bridges, 6 integrated high-side drivers, one high-side external MOSFET gate driver for heater, one high-side gate driver for electrochromic charge and one integrated low-side driver for electrochromic load discharge. Each driver features current sensing, protection and diagnostics along with system protection and diagnostics, which increases system integration and reduces total system size and cost. The half-bridge drivers can be controlled through SPI register or PWM pins PWM1 and PWM2. The half-bridges have configurable current chopping scheme called ITRIP. Protection circuits include short-circuit protection, active and passive open load detection. The high-side drivers can be controlled through SPI register, external PWM pin (PWM1), or with a dedicated PWM generator which enables load regulation during operation. All High-side drivers also have optional constant current mode, ITRIP regulation for LED or lamp module loads. One high-side driver is configurable to drive either a lamp or LED load. Protection circuits include short-circuit protection and open load detection. The device also has an external MOSFET drivers for resistive heating element. The heater MOSFET driver can be controlled with SPI register or with PWM pin (PWM1) and feature both short-circuit and open load detection. There is also an electrochromic (EC) mirror driver. The EC driver is controlled only through SPI register. For EC drive, the driver control loop regulates the EC voltage to a 6-bit target voltage. To discharge the EC element or change target voltage, there is an integrated low-side MOSFET to discharge the EC element in either two discharge modes, a PWM discharge and fast discharge options. The EC driver protection includes LS overcurrent and open load detection. IPROPI pin is an output pin that can provide proportional current sense from any of the integrated drivers, PVDD motor supply monitor or one of four internal temperature clusters. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DRV8001-Q1

7.2 Functional Block Diagram

OUT1 1.54 OUT2 1.54 OUT3 440 m OUT4 440 m HS Driver OUT8...12 1.2 GH_HS Gate Driver Electrochromic Glass Driver ECDRV Current Monitor MUX IOUTX IOUTX, VPVDD, TZONEIPROPI Power Supplies VCP Charge Pump DVDD DGND VCP GND VDVDD PWM2 OUT5 155 m OUT6 185 m ECFB SH_HS HS Driver OUT7 0.4 /1.2 VPVDD Monitor VCP Monitor PWM GeneratorPWM GeneratorPWM GeneratorPWM GeneratorPWM GeneratorPWM Generator VDVDD nSLEEP Figure 7-1. Block Diagram for DRV8001-Q1

7.3 External Components

Table 7-1 lists the recommended external components for the device. Refer to Section 9.2 for example of component placement. Table 7-1. Recommended External Components COMPONENT PIN 1 PIN 2 RECOMMENDED CPVDD1 PVDD GND 0.1µF, low ESR ceramic capacitor, PVDD-rated. CPVDD2 PVDD GND Local bulk capacitance greater than or equal to 10µF, PVDD-rated. CDVDD DVDD GND 1μF 6.3V, low ESR ceramic capacitor CVCP VCP PVDD 1μF 16V, low ESR ceramic capacitor RIPROPI IPROPI GND Typically up to 2.35kΩ 0.063W resistor with 1% tolerance, depending on the controller supply voltage rail. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Table 7-1. Recommended External Components (continued) COMPONENT PIN 1 PIN 2 RECOMMENDED RFILT RIPROPI CFILT Optional resistor part of RC filter depending on the controller input. CFILT RFILT GND Optional low ESR ceramic capacitor part of RC filter depending on controller input. RECDRV ECDRV GND Typically 220Ω series resistance between ECDRV pin and gate of external MOSFET to stabilize control loop (only for ESD purposes). RECDRV is placed close to gate of external MOSFET after CECDRV. CECDRV ECDRV GND 4.7nF, low ESR ceramic capacitor. CECDRV is placed on the ECDRV pin side of the series resistor RECDRV. Note Voltage rating for this capacitor is based on short to battery assumptions for ECFB. CECFB ECFB GND 220nF, low ESR ceramic capacitor Note Voltage rating for this capacitor is based on short to battery assumptions for ECFB. RGH_HS GH_HS MOSFET Gate Optional 0Ω, can be used for Heater slew rate control. RSH_HS SH_HS MOSFET Source Optional 0Ω, can be used for Heater short to battery assumptions. Note External diode with appropriate current rating recommended in case of inductive shorts.

7.4 Feature Description

The table below provides links to all feature descriptions of key blocks of the device. Table 7-2. Table of Device Features by Section Device Block Heater MOSFET Driver Electrochromic Glass Driver High-side Drivers Half-bridge Drivers IPROPI Protection Circuits Thermal Clusters Fault Table www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DRV8001-Q1

7.4.1 Heater MOSFET Driver

Table 7-3. Heater Driver Section Table of Contents Heater Section Link to Section Back to Top of Feature Section Section 7.4 Heater Driver Control Section 7.4.1.1 Heater Driver Protection Section 7.4.1.2 This is an external high-side MOSFET gate driver that can be used for driving resistive heating elements. The driver is controlled through SPI or PWM, and has programmable active short detection and off-state open-load detection.

7.4.1.1 Heater MOSFET Driver Control

The heater MOSFET driver control mode is configured with HEAT_CNFG bits in register HS_HEAT_OUT_CNFG. The heater configuration bits enable or disable control of the heater output, and configures the control source. For the heater driver, the control sources are SPI register control and PWM pin control. When in SPI register control mode ( HEAT_CNFG = 01b), the heater MOSFET gate drive is enabled and disabled by setting bit HEAT_EN in the register HS_EC_HEAT_CTRL. When in PWM control mode ( HEAT_CNFG = 10b), the gate driver is controlled with an external PWM signal on pin PWM1. If the heater driver is in PWM control mode, then HEAT_EN is ignored. The table below summarizes the heater driver configuration and control options: Table 7-4. Heater Configuration HEAT_CNFG bits Configuration Description 00b Disabled Heater control disabled 01b SPI register control Heater SPI control enabled 10b PWM1 control Heater control by PWM1 pin 11b Reserved Reserved Below is the block diagram for the heater driver block: Digital Core GH_HS SH_HS Heater Load Overcurrent Detection Open Load Detection + VCP PVDD VOL_HEAT IOL_HEAT PVDD Figure 7-2. Heater MOSFET Driver Block Diagram DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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The timing waveform below shows the expected timing for the heater driver: 80% 20% 50% tPDR_GH_HS tPDF_GH_HS VnSCS,PWM1 VGS(GH_HS) Figure 7-3. Heater Timing Diagram

7.4.1.2 Heater MOSFET Driver Protection

The heater driver has an active short-circuit detection and an off-state open-load detection.

7.4.1.2.1 Heater SH_HS Internal Diode

Only a limited amount of energy (<1mJ) can be dissipated by the internal ESD diodes on SH_HS pin. TI recommends adding an external diode from ground to SH_HS pin in case of a load short condition. During a heater load short condition, the current is limited only by the saturation current of the external heater MOSFET. If the heater output is configured to shut off due to short-circuit detection, this same current dissipates through the internal ESD diode from ground to SH_HS, which is larger than the what the internal ESD diode can dissipate.

7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)

If the voltage across the heater driver V DS overcurrent comparator exceeds the V DS_LVL_HEAT for longer than the tDS_HEAT_DG time, a heater overcurrent condition is detected. The voltage threshold and deglitch time can be adjusted through the HEAT_CNFG register settings. Table 7-5. Heater VDS Levels HEAT_VDS_LVL VDS Voltage Level 0000b 0.06V 0001b 0.08V 0010b 0.10V 0011b 0.12V 0100b 0.14V 0101b 0.16V 0110b 0.18V 0111b 0.2V 1000b 0.24V 1001b 0.28V 1010b 0.32V 1011b 0.36V 1100b 0.4V 1101b 0.44V www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: DRV8001-Q1

Table 7-5. Heater VDS Levels (continued) HEAT_VDS_LVL VDS Voltage Level 1110b 0.56V 1111b 1V Table 7-6. Heater VDS Deglitch Times HEAT_VDS_DG Time 00b 1μs 01b 2μs 10b 4μs 11b 8μs There is also a heater MOSFET VDS monitor blanking period that is configured in bit HEAT_VDS_BLK in register HEAT_CNFG. There are four blanking time options: Table 7-7. Heater VDS Blanking Times HEAT_VDS_BLK Time 00b 4μs 01b 8μs 10b 16μs 11b 32μs The heater overcurrent monitor can respond and recover in four different modes set through the HEAT_VDS_MODE register setting.

• Latched Fault Mode: After detecting the overcurrent event, the gate driver pulldown is enabled, HEAT_VDS and EC_HEAT bits are asserted. After the overcurrent event is removed, the fault state remains latched until CLR_FLT is issued.
• Cycle by Cycle Mode: After detecting the overcurrent event, the gate driver pulldown is enabled and HEAT_VDS, EC_HEAT and FAULT bits are asserted. EC_HEAT and FAULT status bit in register IC_STAT1 remains asserted until driver control input changes (SPI or PWM). To clear HEAT_VDS bit, a CLR_FLT command must be sent after an input change. If CLR_FLT is issued before an input change, all the status bits remain asserted and driver pulldown stays enabled.
• Warning Report Only Mode: The heater overcurrent event is reported in the WARN and HEAT_VDS bits. The device takes no action. The warning remains latched until CLR_FLT is issued.
• Disabled Mode: The heater VDS overcurrent monitors are disabled and do not respond or report.

7.4.1.2.3 Heater MOSFET Open Load Detection

Off-state open-load monitoring is done by comparing the voltage difference SH_HS node when pulled up by current source against open-load threshold voltage VOL_HEAT. If SH_HS voltage exceeds the open-load threshold VOL_HEAT for longer than filter time t OL_HEAT, the open-load bit HEAT_OL is set. Open-load monitor is controlled by bit HEAT_OLP_EN. Note The heater open load diagnostics only works when the heater configuration is disabled, where bits HEAT_CNFG must be 00b. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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7.4.2 High-Side Drivers

Table 7-8. High-Side Driver Section Table of Contents Half-Bridge Section Link to Section Back to Top of Feature Section Section 7.4 High-side Driver Control Section 7.4.2.1 High-side Driver Regulation Section 7.4.2.1.3 High-side Driver Protection Section 7.4.2.2 The device integrates 6 high-side drivers, OUT7 - OUT12, that can be programmed to drive several load types. Each high-side driver has selectable high or low overcurrent protection and open-load current thresholds. OUT7 can be configured to drive lamps, bulbs, or LEDs. All high-side drivers also have a fixed-time constant current mode intended for driving high capacitance LED modules. Every high-side driver has open-load detection, overcurrent protection and short-circuit protection . OUT7 in both low R DSON and high R DSON mode has an optional ITRIP regulation for lamp or bulb loads. OUT8 - OUT12 also have optional ITRIP regulation which is activated if the respective overcurrent threshold (high or low) is exceeded. This feature can be used for driving larger LED modules or other load types with OUT8 - OUT12. If the electrochromic driver is used, OUT11 can be used to provide protected battery voltage for the EC element. Below is a block diagram of the high-side drivers: Digital Core OUTx LED/Lamp IOUTX IOCP PVDD Figure 7-4. High-Side Driver Block Diagram summarizes all the device high-side drivers with the corresponding feature sets: Table 7-9. High-Side Drivers and Features High-Side Driver RDSON (Ω) OL Detect Overcurrent/ Short-circuit Protection ITRIP CCM Used for EC Supply OUT7 0.4/1.2 Yes Yes Yes Yes No OUT8 1.2 Yes Yes Yes Yes No OUT9 1.2 Yes Yes Yes Yes No OUT10 1.2 Yes Yes Yes Yes No OUT11 1.2 Yes Yes Yes Yes Yes OUT12 1.2 Yes Yes Yes Yes No www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DRV8001-Q1

7.4.2.1 High-side Driver Control

The high-side drivers can be configured for control by SPI register, an internally generated PWM signal from 10-bit PWM generator or an external PWM signal from PWM1 pin. This configuration is done by setting OUTx_CNFG (OUT7-OUT12) bits in register HS_HEAT_OUT_CNFG. In SPI register control mode, ( OUTx_CNFG = 01b), the high-side output follows the enable bits for each output in HS_EC_HEAT_CNFG (ON/OFF). The table below summarizes the high-side driver configuration options: Table 7-10. High-side Driver Configuration OUTx_CNFG bits Configuration Description

00 OFF High-side driver control disabled

01 SPI register control High-side driver SPI control enabled

10 PWM1 pin control High-side driver control by PWM1 pin

11 PWM Generator High-side driver control with dedicated internal

7.4.2.1.1 High-side Driver PWM Generator

Each high-side driver has a dedicated PWM generator with 10-bit duty cycle resolution. The frequency and duty of each PWM generator can be controlled independently. When configuring the high-side driver duty cycle a value up to 1022 (99.8%) can be selected. Required Register Configuration Sequence: 1. Configure the high-side driver PWM frequency value in register HS_PWM_FREQ_CNFG 2. Set the duty cycle in register OUTx_DC with a value from 0 to 1022 (0% - 99.8% duty cycle) 3. Configure the driver mode of operation in register HS_HEAT_OUT_CNFG The frequency of the PWM generator is controlled by bits PWM_OUTX_FREQ from register HS_PWM_FREQ_CNFG as shown in the table below: Table 7-11. PWM Frequency PWM_OUTX_FREQ PWM Frequency (Hz) 00b 108 01b 217 10b 289 11b 434

7.4.2.1.2 Constant Current Mode

All high-side drivers have a timed Constant Current Mode feature (CCM), which can be used to provide a constant current for a short duration to the desired output. This mode is enabled with bit OUTx_CCM_EN in register HS_REG_CNFG2. When enabled, the current from the high-side driver is limited to the configured limit for a short duration of 10ms. There are two current limit options for constant current mode. This is configured with bit OUTx_CCM_EN in register HS_REG_CNFG2, summarized in the table below: Table 7-12. Constant Current Mode Options High-side Output OUTX_CCM_TO Current Limit (ICCM) Timeout (tCCMto) OUT7 (RDSON High) 0b 250mA 10ms 1b 330mA 10ms OUT7 (RDSON Low) 0b 360mA 10ms 1b 450mA 10ms DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Table 7-12. Constant Current Mode Options (continued) High-side Output OUTX_CCM_TO Current Limit (ICCM) Timeout (tCCMto) OUT8-12 0b 350mA 10ms 1b 450mA 10ms This constant current mode feature is enabled only if the OUTx_CCM_EN bit is configured prior to enabling the configured output and when the output is in the disabled state. CCM automatically expires after expiration time tCCMto. After timeout, the driver remains enabled per bits OUTx_EN in register HS_EC_HEAT_CTRL and configured based on OUTx_CNFG bits in register HS_HEAT_OUT_CNFG. Required Register Configuration Sequence: 1. Configure the high-side driver CCM mode in register HS_REG_CNFG2 2. Configure the high-side driver operation in register HS_HEAT_OUT_CNFG Once CCM mode is set and the driver configuration is done, the CCM timer begins when the corresponding OUTx_CNFG bits are set in register HS_HEAT_OUT_CNFG. Only SPI control or external PWM generator control (OUTx_CNFG = 01b or 10b) is supported after CCM timer expires. Internal PWM generator control does not support CCM mode. If constant current mode is configured after configuring the high-side driver, the CCM mode does not activate. For OUTx_CCM_EN bit:

• If OUTx_CCM_EN is cleared by the controller before constant current mode timeout, the driver follows the command and is switched to the mode corresponding to OUTx_CNFG bits
• If OUTx_CCM_EN is set after the driver has already been enabled, the OUTx_CCM_EN bit is ignored; in this case OUTx_CCM_EN remains off The short-circuit and overcurrent detection are active/enabled when the driver is ON, PWM driven, but NOT in constant current mode. Open load detection is always active.

7.4.2.1.3 OUTx HS ITRIP Behavior

For all high-side drivers, a fixed frequency current regulation feature called HS ITRIP is available. This function restarts the driver when an overcurrent condition occurs while driving certain loads. The overcurrent detection is based on sensed load current. This feature is intended to be used to drive loads with large inrush currents that exceed the overcurrent threshold of the driver, loads such as a lamp, bulb, or large LED module. High side drivers can be configured to enable ITRIP regulation by setting the OUT7_ITRIP_EN in the HS_REG_CNFG1 register for OUT7 and the HS_OUTx_ITRIP_EN for OUT8-12 in HS_REG_CNFG3 register. By default, ITRIP regulation is disabled for all High-side drivers. If ITRIP regulation is disabled and after the blank time if the driver current exceeds overcurrent threshold (IOCx) for deglitch time, the output is disabled. ITRIP regulation enabled: When ITRIP regulation is enabled and after blank time if driver current exceeds overcurrent threshold I OCx for deglitch time, the output turns OFF. It automatically turns ON again after the end of ITRIP cycle. Overcurrent thresholds (high or low) are configured by setting OUT7_RDSON_MODE bit for OUT7 and OUTx_OC_TH bits for OUT8-12 in HS_OC_CNFG register. Blank time for ITRIP regulation is 40 μs for all high-side driver outputs. Blank time starts when OUTx is enabled. OUT7 has dedicated ITRIP frequency and deglitch time settings, configurable via bits OUT7_ITRIP_FREQ and OUT7_ITRIP_DG in the HS_REG_CNFG1 register. For OUT8-12, ITRIP frequency and deglitch time settings are shared, configurable via bits HS_OUT_ITRIP_FREQ and HS_OUT_ITRIP_DG in the HS_REG_CNFG3 register. For VPVDD < 20V, all deglitch options (24, 32, 40, and 48μs) are available. For VPVDD > 20V the deglitch time is automatically reduced to 10μs. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DRV8001-Q1

When ITRIP regulation is enabled and if an overcurrent detection is detected, OUT7_ITRIP_STAT bit in EC_HEAT_ITRIP_STAT register for OUT7 driver or OUTx_ITRIP_STAT bit in HS_ITRIP_STAT register for OUT8-12 drivers is set and latched. The fault bit remains set until the CLR_FLT bit is asserted. Table 7-13. High-Side ITRIP Frequency Option Summary Frequency (fITRIP_HS) HS_OUT_ITRIP_FREQ/OUT7_ITRIP_FREQ 1.7 kHz 00b 2.2 kHz 01b 3 kHz 10b 4.4 kHz 11b Table 7-14. High-Side ITRIP Deglitch Option Summary Deglitch Time (tITRIP_HS_DG) HS_OUT_ITRIP_DG/OUT7_ITRIP_DG 48 μs 00b 40 μs 01b 32 μs 10b 24 μs 11b The ITRIP deglitch timer starts when the OUTx ITRIP blank time expires. The minimum OUTx ITRIP ON time is the sum of blanking and deglitch times, and total period is determined by the OUTx ITRIP frequency. The diagram below shows the ITRIP behavior. IOUTx IOCx t Unlimited Inrush Current Current during OUTx ITRIP mode tOUT7_ITRIP_DG TOUT7_ITRIP_FREQtSC_BLK THS_OUT_ITRIP_FREQ tHS_OUT_ITRIP_DG Figure 7-5. OUTx HS ITRIP Behavior with Incandescent Bulb The blanking time t SC_BLK is 40 μs, after which the overcurrent condition can be detected. t OUT7_ITRIP_DG or t HS_OUT_ITRIP_DG is the time OUTx remains on after overcurrent protection threshold is exceeded. TOUT7_ITRIP_FREQ or T HS_OUT_ITRIP_FREQ is the time period of the ITRIP loop, inverse of t OUT7_ITRIP_FREQ or tHS_OUT_ITRIP_FREQ. ITRIP faults for OUT7-12 are reported in bits OUT7_ITRIP_STAT and OUTx_ITRIP_STAT. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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7.4.2.1.4 High-side Drivers - Parallel Outputs

The high-side drivers OUT8 through OUT12 can be connected in parallel combinations to support even higher current loads. For example, OUT8 and OUT9 can be connected in parallel as a 600m Ω driver effectively, or OUT9, OUT10, and OUT12 can be connected in parallel as a 400mΩ driver effectively. However, there are limitations with this mode of operation:

• Internal PWM control does not work for parallel high-side drivers and must not be configured for this mode of operation.
• Constant current mode is not be possible and must be disabled.
• ITRIP regulation is not supported.
• Overcurrent protection, short-circuit protection and active open load detection is supported. If operating in parallel, the high-side drivers must be configured for ON/OFF SPI register control or external PWM signal control through pin.

7.4.2.2 High-side Driver Protection Circuits

7.4.2.2.1 High-side Drivers Internal Diode

Each high-side driver has an internal diode from ground to the high-side OUTx node for ESD protection. If either of the following occurs, this diode can be subjected to high energy dissipation:

• Both a loss of ground connection and short to ground on a high-side output.
• There is an inductive load on the high-side output. Only a limited amount of energy (<1mJ) can be dissipated by the internal ESD diodes during freewheeling. For inductive loads greater than 100 μH, a connection to an external freewheeling diode between PGND and the corresponding output is required

7.4.2.2.2 High-side Driver Short-circuit Protection

Short-circuit protection monitors each high-side output (OUT7-12) using a 2V comparator on the OUTx node. After the blank time If OUTx voltage does exceed the 2V short-circuit threshold for deglitch time, a short to ground fault is detected and the output is disabled. The 2V comparator blank time (t SC_BLK) is 40 μs for all high side driver outputs. Blank time starts when OUTx is enabled. OUT7 has dedicated deglitch time settings, configurable via bits OUT7_ITRIP_DG in the HS_REG_CNFG1 register. For OUT8-12 deglitch time settings are shared, configurable via bits HS_OUT_ITRIP_DG in the HS_REG_CNFG3 register. For V PVDD < 20V, all deglitch options (24, 32, 40, and 48μs) are available. For VPVDD > 20V the deglitch time is automatically reduced to 10μs. Upon short-circuit detection, the corresponding OUTx_OCP fault status bit in the HS_STAT register is latched and the corresponding output is shutoff. The fault bit remains set until the CLR_FLT bit is asserted. The diagram below shows the short circuit behavior for high-side drivers: www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DRV8001-Q1

t OCP Status bit goes high (Disable Output) tSC_BLK CLR_FLT bit set tHS_DG_OUTx Figure 7-6. High-side Drivers Short-circuit Protection

7.4.2.2.3 High-side Driver Overcurrent Protection

Overcurrent protection is available when ITRIP regulation is disabled. The output current for all drivers (OUT7- OUT12) is monitored, and after the blank time if current exceed the overcurrent threshold after for deglitch time, the output is disabled. Disable ITRIP for OUT7 by configuring OUT7_ITRIP_EN = 0b in HS_REG_CNFG1 and for OUT8-12 by configuring HS_OUTx_ITRIP_EN = 0b in HS_REG_CNFG3 register. Overcurrent thresholds are configured (high or low) by setting OUT7_RDSON_MODE bit for OUT7 and OUTx_OC_TH bits for OUT8-12 in HS_OC_CNFG register. Blank time for overcurrent protection is 40 μs for all high-side driver outputs. Blank time starts when OUTx is enabled. OUT7 has dedicated deglitch time settings, configurable via bits OUT7_ITRIP_DG in the HS_REG_CNFG1 register. For OUT8-12 deglitch time settings are shared, configurable via bits HS_OUT_ITRIP_DG in the HS_REG_CNFG3 register. For V PVDD < 20V, all deglitch options (24, 32, 40, and 48 μs) are available. For V PVDD > 20V the deglitch time is automatically reduced to 10 μs. When overcurrent detection is detected, OUT7_ITRIP_STAT bit in EC_HEAT_ITRIP_STAT register for OUT7 driver or OUTx_ITRIP_STAT bit in HS_ITRIP_STAT register for OUT8-12 drivers is latched and the corresponding output is shutoff. The fault bit remains set until the CLR_FLT bit is asserted.

7.4.2.2.4 High-side Driver Open Load Detection

The high-side drivers have open-load detection. Similar to the half-bridge drivers OLA detection scheme of the DRV800x-Q1, the high-side drivers open-load detection scheme sequences through each driver checking if the load current is below the open-load current threshold. The open-load current threshold I OLDx is configurable between high and low-current thresholds with bits OUTx_OLA_TH in register HS_OL_CNFG for OUT8-12. The thresholds are automatically adjusted only for high-side driver OUT7 based on OUT7_RDSON_MODE. Open-load detection must be enabled with bit OUTx_OLA_EN in register HS_OL_CNFG for OUT7-12 high-side drivers. If the load current I OUTX is below the open-load threshold (I OLD_HS) for t > t OLD_HS, then the corresponding high-side open load status bit OUTx_OLA is set in the status register. The driver detected with open-load is not switched off. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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t IOUTx IOLDx Load Current (ILOAD) Nominal LED/Lamp Current Load Open Load Re-connected LED/Lamp Opera on OL Status bit goes high tOLD Figure 7-7. Open-Load Detection for High-side Drivers The open-load detection test time for each high-side driver is 200 μs. The timer does not start until the output is enabled. Once all enabled drivers have been cycled through, the detection cycle restarts. When the OLA bit is flagged for an OUTx, the status is latched and the OUTx is excluded from the detection cycle. CLR_FLT is required to restart the OLA check for the OUTx. The high-side driver must be ON for minimum 200 μs for the OLA detection to complete. Otherwise, the device waits until the next PWM cycle. The OFF counter for the OLA detection starts when the high-side driver turns OFF and ends OLA detection if the driver is detected OFF for more than 10ms. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: DRV8001-Q1

7.4.3 Electrochromic Glass Driver

Table 7-15. EC Driver Section Table of Contents EC Driver Section Link to Section Back to Top of Feature Section Section 7.4 EC Driver Control Section 7.4.3.1 EC Driver Protection Section 7.4.3.2 The device features an integrated electrochromic driver block that can be used to charge or discharge an electrochromic element of a mirror. The electrochromic driver block charges an external MOSFET to control the charging and discharge voltage of the element. The driver configuration operates with either high-side driver OUT11 as protected supply to the element or without OUT11 (independent OUT11 control).

7.4.3.1 Electrochromic Driver Control

Below is the block diagram for the electrochromic driver: EC Control 6-bit DAC Digital Core Electrochromic ECDRV ECFB OUT11 1.2 1.2 PVDD PVDD RECDRV Figure 7-8. Electrochromic Driver Block Diagram - Default Configuration Depending on the system implementation, the device electrochrome driver supports configuration where the drain of electrochrome high-side charge MOSFET can be supplied from either high-side driver OUT11, or directly from the supply voltage (PVDD). The EC control block can operate independently of the OUT11 or external FET supply (PVDD), with independent protection circuits in either configuration. This can be useful if an extra high-side driver is needed to drive another load. The main limitation in this configuration is that if the charge MOSFET fails short, the connection to supply cannot be shut off as when OUT11 is used as EC supply. A short, over voltage and open-load condition can still be detected when EC supplied with PVDD directly (OUT11 is configured as independent). DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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OUT11 for EC supply: This configuration is set in register HS_OC_CNFG, bit OUT11_EC_MODE. By default, OUT11_EC_MODE = 1b, which is configured as the supply for EC drive as shown in the block diagram Electrochromic Driver Block Diagram - Default Configuration . When in this configuration, bits OUT11_CNFG in register HS_HEAT_OUT_CNFG are ignored (ON/OFF, SPI/PWM). Both OUT11 and the 1.2 Ω ECFB low-side discharge MOSFET have overcurrent, over voltage and passive open load detection active during EC charge and discharge states, respectfully. PVDD for EC supply, independent OUT11: To use OUT11 as an independent high-side driver (independent of EC control) to drive a separate load, where the drain of the EC charge MOSFET is connected directly to supply voltage, set OUT11_EC_MODE = 0b in register HS_OC_CNFG. Independent mode ITRIP regulation is valid for OUT11 when the pin is not used as EC. When OUT11 is in EC mode, no current regulation is performed even if the regulation mode is configured. As before, the ECFB low-side discharge MOSFET protection circuits are active during EC discharge state. The diagram below shows this configuration: Digital Core Electrochromic ECDRV ECFB 1.2 PVDD ECFB_OV Over Voltage Detection Filter EC_OL_TH Open Load Detection Filter IOLX PVDD EC Control RECDRV Figure 7-9. Electrochrome with direct PVDD supply (OUT11 independent) To enable the EC driver: Set bits EC_ON and EC_V_TAR to the desired target voltage in register HS_EC_HEAT_CTRL to enable the EC driver control loop. Once these bits are set, EC driver control loop is enabled. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: DRV8001-Q1

For EC element voltage control: Once the EC driver is enabled, the feedback loop of the driver is activated, and regulates ECFB pin voltage to the target voltage set in bits EC_V_TAR in register HS_EC_HEAT_CTRL. The target voltage on ECFB pin is binary coded with a full-scale range of either 1.5V or 1.2V, depending if bit ECFB_MAX in register EC_CNFG is set to 1 or 0, respectively. ECFB_MAX = 0b is the default value (1.2V). Whenever a new value for the EC voltage is set, there is a blanking time t BLK_ECFB of 250 μs for ECFB_HI or ECFB_LO status indication of ECFB once the control loop begins regulation to the new target value. The device provides two discharge modes: fast discharge and PWM discharge. Fast discharge of the EC element: To fully discharge the EC element with fast discharge ECFB_LS_PWM must be set to 0b. The target output voltage EC_V_TAR must also be set to 0b, and bits ECFB_LS_EN, and EC_ON must be set to 1b in EC_CNFG. When these four conditions are met, the voltage at pin ECFB is discharged by pulling the internal 1.2Ω low-side MOSFET on ECFB pin to ground. 1. Configure ECFB_LS_PWM = 0b in register EC_CNFG 2. Set bits ECFB_LS_EN = 1b, EC_ON = 1b and EC_V_TAR = 0b in register HS_EC_HEAT_CTRL. 3. ECFB LS MOSFET is enabled and performs fast discharge of EC mirror. PWM discharge of the EC element: The steps below outline the PWM discharge cycle of electrochrome driver: 1. Configure ECFB_LS_PWM = 1b in register EC_CNFG 2. Set bits ECFB_LS_EN = 1b, EC_ON = 1b in register HS_EC_HEAT_CTRL. 3. If the regulation loop detects VECDRV is less than VECFB and VECDRV is less than 400mV for longer than tRECHARGE or 3ms, the ECDRV regulator is switched off and the LS MOSFET on ECFB is activated for approximately 300ms (tDISCHARGE). During this discharge, the ECDRV output is pulled low to prevent shoot- thru currents. 4. At the end of the discharge pulse tDISCHARGE, the discharge MOSFET is switched off and the regulation loop is activated again with the new lower value. The regulation loop goes back to step 2, and out of regulation is again observed (VECDRV < 400mV or VECDRV < VECFB). If out of regulation condition is not met the loop goes back to normal operation state. The diagram below shows the PWM discharge cycle of the electrochrome driver: EC_ON ECDRV_LOW ECFB LS nSCS VTARGET VECFB VECDRV EC enabled EC disabled (5k to GND) 2. Regulation Status: Out of Regulation VECDRV < VECFB tRECHARGE 1. New EC target voltage requested tRECHARGE tDISCHARGE tDISCHARGEtDISCHARGE ECDRV – ECFB Sample 3. End of discharge Figure 7-10. Electrochrome Discharge with PWM DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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The status of the voltage control loop is reported through SPI, and TI recommends to observe the report to determine the EC charge and discharge control timing. If the voltage at pin ECFB is higher than the target value by greater than 120mV, then bit ECFB_HI is set. If the voltage at pin ECFB is lower than the target value by 120mV , ECFB_LO is set. Both ECFB status bits ECFB_HI and ECFB_LO are valid if stable for at least the filter time tFT_ECFB. The bits are not latched, and are not designated as global faults. Exit discharge mode: To exit discharge mode set EC_V_TAR to a non-zero value. There is no need to change ECFB_LS_EN bit when a new target voltage is programmed, the control loop internal logic prevents both OUT11 and ECFB LS from being simultaneously on. A capacitor of at least 4.7nF has to be added to pin ECDRV, and 220nF capacitor between ECFB and ground to increase control loop stability. For noise immunity reasons, TI recommends to place the loop capacitors as close as possible to the respective pins. If the EC driver is not used, connect ECFB pin to ground.

7.4.3.2 Electrochromic Driver Protection

The electrochromic driver block has multiple protection and detection circuits for both charge and discharge states. There are the comparator-based detection circuits, protection circuits of OUT11 which are active during EC charge state (when configured with OUT11 as supply), and protection circuits on ECFB low-side discharge MOSFET. EC supplied by OUT11: When the electrochrome drive is configured to be supplied by integrated high-side driver OUT11, the same protection and diagnostic functions as the other high-side drivers are available (e.g. during an overcurrent detection, the control loop is switched off). These high-side driver protections are active when the electrochrome is in the charge state (voltage ramp up). When in OUT11 EC mode ( OUT11_EC_MODE = 1b), OUT11 cannot be controlled in PWM mode and EC_CNFG is used to configure diagnostics. For EC_OUT11_OCP_DG when VPVDD < 20V, deglitch options (6μs, 10μs, 15μs, and 60μs) are available. For VPVDD > 20V the deglitch time is automatically reduced to 10μs. Fault on OUT11 during EC charge: In case of an overtemperature shutdown fault (zone 3 or 4) or overcurrent fault on OUT11 while EC_ON = 1b (EC control enabled):

• OUT11 is shut off (status register set)
• ECDRV pin is pulled to ground
• EC_ON remains '1'
• ECFB_LS_EN remains as programmed To restart EC control after OUT11 failure, the controller must read and clear the corresponding fault. The driver reverts to the previous value of EC_V_TAR when restart occurs. If an open load is detected on OUT11 during EC charge, the OUT11_OLA bit in register HS_STAT is set. Discharge overcurrent protection LS FET: During discharge of ECFB via low-side FET(LSFET), overcurrent fault is detected if load current on ECFB pin exceeds the overcurrent threshold (I OC_ECFB). Overcurrent fault response is configurable with EC_FLT_MODE bit in register EC_CNFG. EC_FLT_MODE = 0b: If the current through EC LSFET crosses the OCP threshold (I OC_ECFB) after deglitch time, LSFET is disabled. The deglitch times for the EC LSFET depend on V PVDD. For VPVDD < 20V, the deglitch time is 40μs. For VPVDD > 20V, the deglitch time is automatically reduced to 15μs. EC_FLT_MODE = 1b: If the current through EC LSFET after blank time crosses the OCP threshold (I OC_ECFB) for deglitch time, the driver enters overcurrent recovery mode (OCR), similar to ITRIP regulation of HS drivers OUT7-12. Deglitch time and ITRIP frequency are taken from the OUT7 ITRIP settings. If ECFB_OV bit is high due to short from ECFB to V PVDD, the driver is shutoff regardless of ECFB_OV_MODE. The ECFB_OV deglitch time is 20μs regardless of the ECFB_OV_DG configuration settings. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DRV8001-Q1

Table 7-16. Discharge Overcurrent Protection EC_FLT_MODE Fault Response 0b Latch (Hi-Z) 1b Overcurrent Recovery (OUT7 ITRIP settings) Discharge open load detection: While discharging the EC, open-load can also be detected. Bit EC_OLEN in register EC_CNFG must be set. If the load current on ECFB is below I OL_ECFB_LS for longer than tDG_OL_ECFB_LS, then the open load status bit ECFB_OL is set, and WARN bit is set in register IC_STAT1. Short to battery/OV detection: ECFB overvoltage or short to battery is detected when ECFB voltage exceeds threshold V ECFB_OV_TH, for longer than the deglitch time t ECFB_OV_DG while EC_ON = 1. Bit ECFB_OV_MODE determines the driver ECFB overvoltage fault response. The EC overvoltage deglitch time is configured with bit ECFB_OV_DG in register EC_CNFG. For over voltage fault response control, bit ECFB_OV_MODE can be configured in register EC_CNFG. If ECFB_OV_MODE = 00b, then no action is taken during this fault. For ECFB_OV_MODE = 01b, when ECFB voltage exceeds 3V for longer than programmed deglitch time t ECFB_OV_DG, then the ECFB_OV bit is set in EC_HEAT_ITRIP_STAT register, and EC_HEAT fault bit is set in register IC_STAT1. For ECFB_OV_MODE = 10b, when OV on ECFB occurs, the ECDRV pin is pulled down, and the ECFB LS FET is Hi-Z. Faults are reported in the same registers as for when ECFB_OV_MODE = 01b. The fault responses and bit values are summarized in the table below: Table 7-17. Electrochrome Overvoltage Fault Response ECFB_OV_MODE Fault Response 00b No action 01b Report fault in register 10b Pulldown ECDRV and ECFB LS FET, report fault in register 11b No action Table 7-18. EC Overvoltage Deglitch Times ECFB_OV_DG Deglitch Time 00b 20μs 01b 50μs 10b 100μs 11b 200μs Short-circuit or open-load detection: The EC diagnostics can be configured to report either a short-circuit or an open load. This mode is selected by setting the ECFB_DIAG bits in the EC_CNFG register, with the requirement that the EC_ON bit must be 0b. Note Short-circuit and open-load detection is available for EC supply with PVDD. Short-circuit testing must pass prior to running open load detection to ensure external FET is not damaged. Table 7-19. ECFB Diagnostic Detection Options ECFB_DIAG Detection Setting 00b Disabled 01b Short-circuit 10b Open Load DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Short-circuit detection: The short-circuit detection can detect a low-impedance condition across ECFB to GND. The bits ECFB_SC_RSEL select the impedance under which a short-circuit is detected from 0.5 Ω to 3 Ω. The voltage VECFB_SC_TH is compared to I ECFB_SC * ECFB_SC_RSEL. The short-circuit detection below runs when the EC amplifier is off, ECFB_DIAG = 01b, and EC_ON = 0b:

• Run IECFB_SC current into the ECFB pin and wait an initial 3ms blanking time
• If the ECFB voltage is less than IECFB_SC * ECFB_SC_RSEL after enabling the short-circuit detection, register a short-circuit (ECFB_SC) by setting ECFB_DIAG_STAT = 1b.
• The IECFB_SC continues to run through ECFB pin as long as short-circuit detection is active. Table 7-20. ECFB Diagnostic Detection Options ECFB_SC_RSEL Impedance Threshold 00b 0.5Ω 01b 1.0Ω 10b 2.0Ω 11b 3.0Ω Open-load detection: The passive open load detection is active when ECFB_DIAG = 10b, EC_ON = 0b, the EC amplifier is off. An open load is detected when the output impedance is greater than 4k Ω, resulting in an ECFB voltage threshold of IECFB_OLP * 4kΩ which is VECFB_OLP_TH. The procedure for open load detection is:
• Run IECFB_OLP current into the ECFB pin and wait an initial 3ms blanking time
• If the ECFB voltage detected is greater than VECFB_OLP_TH, register an open-load condition (ECFB_OLP) by setting ECFB_DIAG_STAT = 1b.
• The IECFB_OLP continues to run through ECFB pin as long as open-load detection is active. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DRV8001-Q1

7.4.4 Half-bridge Drivers

Table 7-21. Half-bridge Section Table of Contents Half-bridge Section Link to Section Back to Top of Feature Section Section 7.4 Half-bridge Control Section 7.4.4.1 Half-bridge Regulation Section 7.4.4.4 Half-bridge Protection Half-bridge Protection and Diagnostics The device integrates six total half-bridge high-side and low-side FETs, supporting bidirectional drive for up to five motors; two 1.54 Ω half-bridges, two 440m Ω half-bridges, one 185m Ω half-bridge, and one 155m Ω half-bridge. All of these drivers can be controlled with SPI register, PWM signal that can be sourced from the PWM1 pin or PWM2 pin. Each driver also has configurable current regulation feature called ITRIP. Half-bridge protection circuits include overcurrent protection, off-state and active open-load diagnostics. The diagrams below show common configurations for the integrated half-bridges to support up to five mirror and lock motors, and all mirror motors: M X-adj Y-adj Lock Safe LockMirror Fold M M MM VVM OUT1 1540 m IOUT1 OUT2 1540 m IOUT2 OUT3 440 m IOUT3 OUT4 440 m IOUT4 OUT5 155 m IOUT5 OUT6 185 m IOUT6 Figure 7-11. Half-bridge Configuration for up to Five Motors (Mirror and Lock) The diagram below shows a configuration for mirror only loads: DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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M Y-adj Mirror Telescope M MM VPVDD OUT1 1540 m IOUT1 OUT2 1540 m IOUT2 OUT3 440 m IOUT3 OUT4 440 m IOUT4 OUT5 155 m IOUT5 IOUT6 Figure 7-12. Half-bridge Configuration for up to Four Motors (Mirrors only)

7.4.4.1 Half-bridge Control

The half-bridge drivers can be controlled in two modes to support control schemes with either PWM input pins or SPI register control. The half-bridge drivers also have configuration registers ( HB_OUT_CNFG1 and HB_OUT_CNFG2) to enable half-bridge control and to set up control mode (PWM or SPI). The half-bridges can be configured for control by input signal from either PWM1 or PWM2 pins. The signal to PWM1 pin can be multiplexed internally to half-bridges, high-side drivers, and heater driver. PWM2 control from PWM2 pin is only available for half-bridges. Each half-bridge driver's slew rate can be configured in the HB_SR_CNFG. The configuration table is shown below. Note that OUT5 and OUT6 are configured in HB_OUT_CNFG1 and OUT1 through OUT4 are configured in HB_OUT_CNFG2: Table 7-22. OUTX_CNFG Half-bridge Configuration OUTX_CNFG[2] OUTX_CNFG[1] OUTX_CNFG[0] OUTx HS ON LS ON 0 0 0 OFF OFF OFF 0 0 1 SPI Register Control OUTX_CTRL OUTX_CTRL 0 1 0 PWM 1 Complementary Control ~PWM1 PWM1 0 1 1 PWM 1 LS Control OFF PWM1 1 0 0 PWM 1 HS Control PWM1 OFF 1 0 1 PWM 2 Complementary Control ~PWM2 PWM2 1 1 0 PWM 2 LS Control OFF PWM2 1 1 1 PWM 2 HS Control PWM2 OFF When the half-bridges are configured for SPI register control ( OUTx_CNFG = 01b), the half-bridges high- and low-side MOSFETs can be individually controlled in register HB_CTRL with bits OUTx_CTRL. The control truth table for the half-bridge outputs is shown below: www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DRV8001-Q1

Table 7-23. Half-bridge Driver Controls OUTx_CTRL (OUT1-6) bits Configuration Description

00 OFF Half-bridge control OFF

01 HS ON High-side MOSFET ON

10 LS ON Low-side MOSFET ON

11 RSVD Reserved. The half-bridge control mode can be changed anytime SPI communication is available by writing to the bits. This change is immediately reflected. When the half-bridges are configured for PWM operation ( OUTx_CNFG = 01xb, 10xb or 11xb), the inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes. The device automatically generates the dead-time needed during transitioning between the high-side and low- side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage. No external timing is required. This scheme provides minimum dead time while preventing shoot-through current.

7.4.4.2 OUT1 and OUT2 High-side Driver Mode

OUT1 and OUT2 2 half bridges can be configured as high side drivers by setting the OUT1_MODE and OUT2_MODE bits in the HB_OUT_CNFG2 register. When OUTx_MODE is set to 1b the corresponding output operates in high-side mode. In high side driver configuration, OUT1 and OUT2 outputs are controlled only by internal PWM generator. This control is enabled by configuring OUT1_CNFG and OUT2_CNFG to xx1b. Setting these bits to xx0b disables the outputs OUT1 and OUT2. When configured in high-side mode, the PWM frequency for OUT1 and OUT2 can be programmed using PWM_OUT1_FREQ and PWM_OUT2_FREQ bits in the HB_ITRIP_FREQ register. The bits OUT1_DC and OUT2_DC configure the duty cycle control from internal PWM generator up to a value of 1022 (99.8% duty cycle). Table 7-24. OUT1 or OUT2 PWM Frequency in High-side Driver Mode PWM_OUTx_FREQ PWM Frequency (Hz) 00b 108 01b 217 10b 289 11b 434 The same protections and diagnostic features as half-bridge mode apply to OUT1 and OUT2 in high-side mode.

7.4.4.3 Half-bridge Register Control

The half-bridges are disabled by default, once configured to operate in SPI register control mode any high-side or low-side can be enabled by configuring the individual enable bits for high-side ( HS_ON) and low-side (LS_ON) in bits OUTx_CTRL in HB_CTRL register. An example can be used when connecting two half-bridges (OUT1/OUT2, OUT3/OUT4, OUT5/OUT6) as half- bridge X (OUTX) and half-bridge Y (OUTY). The high-side and low-side enable bits of a particular half-bridge are configured to drive the motor in forward mode, reverse mode, brake mode and coast mode as shown below: Table 7-25. Motor Operation (Motor Connected between OUTX and OUTY) nSLEEP Half-Bridge X HS Half-Bridge X LS Half-Bridge Y HS Half-Bridge Y LS OUTX OUTY

0 X X X X Z Z Sleep

1 HS_ON = 1 LS_ON = 0 HS_ON = 0 LS_ON = 1 H L Forward

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Table 7-25. Motor Operation (Motor Connected between OUTX and OUTY) (continued) nSLEEP Half-Bridge X HS Half-Bridge X LS Half-Bridge Y HS Half-Bridge Y LS OUTX OUTY

1 HS_ON = 0 LS_ON = 1 HS_ON = 1 LS_ON = 0 L H Reverse

1 HS_ON = 0 LS_ON = 1 HS_ON = 0 LS_ON = 1 L L Brake (low-

side)

1 HS_ON = 1 LS_ON = 0 HS_ON = 1 LS_ON = 0 H H Brake (high-

side)

7.4.4.4 Half-Bridge ITRIP Regulation

The device half-bridges have optional fixed-frequency load current regulation called ITRIP. This is done by comparing the active output current against configured current thresholds determined by OUTx_ITRIP_LVL. OUT1-2 has two possible ITRIP current thresholds, and OUT3-6 also have three current threshold options. ITRIP thresholds, enables, and timing settings are set individually for each half-bridge in the HB_ITRIP_CONFIG, HB_ITRIP_FREQ and HB_ITRIP_DG. As this device has multiple integrated drivers which are enabled at any given time, there is freewheeling configuration intended to reduce power dissipation during ITRIP half-bridge regulation. Power dissipation is lower with synchronous rectification (MOSFETs) compared with asynchronous rectification (diodes). The half-bridge freewheeling is configurable between non-synchronous (passive freewheeling) and synchronous rectification (active freewheeling). The synchronous rectification for half-bridges during ITRIP regulation is enabled by setting bits NSR_OUTx_DIS in configuration register HB_OUT_CNFG1. ITRIP detection is done on both high- and low-side MOSFETs of each half-bridge with blanking controlled internally. The configurable ITRIP timing parameters are frequency and deglitch. The tables below summarize the ITRIP configuration options. Table 7-26. Half-bridge ITRIP Synchronous Rectification Settings NSR_OUTx_DIS ITRIP Half-bridge Off-time Response 0b Hi-Z 1b complementary MOSFET ON Table 7-27. ITRIP Current Thresholds for Half-bridges Half-bridges Typ ITRIP Current Thresholds OUTx_ITRIP_LVL OUT6 6.2 A 10b

5.4 A 01b

2.3 A 00b

OUT5 7.6 A 10b

6.6 A 01b

2.9 A 00b

OUT3 & OUT4 3.4 A 10b

2.5 A 01b

1.3 A 00b

OUT1 & OUT2 0.875 A 1b

0.7 A 0b

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Table 7-28. ITRIP Timing - Deglitch Options Deglitch Time OUTx_ITRIP_DG 2 μs 00b 5 μs 01b 10 μs 10b 20 μs 11b Table 7-29. ITRIP Timing - Frequency Options ITRIP Frequency OUTx_ITRIP_FREQ 20 kHz 00b 10 kHz 01b 5 kHz 10b 2.5 kHz 11b Note If 20kHz ITRIP frequency is desired, the fastest deglitch time is recommended (2μs). ITRIP regulation follows these steps:

• The low- or high-side of a half-bridge is enabled. The first ITRIP clock edge occurs when half-bridge enabled.
• If ITRIP limit is exceeded on either low- or high-side, the device waits for longer than deglitch time tDG_ITRIP_HB.
• If ITRIP limit is still exceeded after the deglitch time, then either the half-bridge enters the Hi-Z state or turns on the opposite MOSFET for the remainder of the ITRIP cycle, depending on NSR_OUTx_DIS bit setting. ITRIP status bit is set, and the regulation loop restarts.
• If NSR_OUTx_DIS = 1b (synchronous rectification enabled), the current through the enabled MOSFET is monitored for current reversal. If current reversal is detected, the half-bridge output is Hi-Z for the remainder of the ITRIP cycle. The synchronous rectification or freewheeling feature is enabled by setting bits NSR_OUTx_DIS in configuration register HB_OUT_CNFG1. When NSR_OUTx_DIS = 0b, if ITRIP occurs on either MOSFET, the half-bridge goes Hi-Z. If NSR_OUTx_DIS = 1b, if ITRIP occurs on either MOSFET, the opposite MOSFET is enabled. For example, NSR_OUTx_DIS = 1b and OUTx_CNFG = 101b and 010b for complementary mode. If the PWM input sets HS MOSFET ON, and ITRIP is reached on HS MOSFET, the LS MOSFET turns on for the remainder of the ITRIP cycle. The HS MOSFET is turned ON at the end of the cycle. If the PWM input changes within the ITRIP period, the ITRIP counter is reset and ITRIP regulation is active while the LS MOSFET is ON. If synchronous rectification is enabled and MOSFET turns on when ITRIP occurs, current is monitored for a current reversal, or zero-crossing detection. There is zero-crossing detection on both high-side and low-side MOSFETs. If the detected load current reaches 0A during ITRIP regulation for longer than the deglitch time, then the half-bridge output goes Hi-Z for the remainder of the ITRIP cycle. The zero-crossing deglitch time is the same ITRIP deglitch time. The diagram below shows the ITRIP behavior for a half-bridge after configuring the OUTx_ITRIP_LVL, NSR_OUTx_DIS, HB_ITRIP_FREQ, HB_TOFF_SEL, and HB_ITRIP_DG: DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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HS_ON LS_ON Current ITRIP level ITRIP Fixed Freq Pulse tBLANK tPERIODtPERIOD tPERIOD tPERIOD tPERIOD tDG_ITRIP_HB tON tOFF tBLANK tOFF = Period - tON tON tOFF tDG_ITRIP_HB tBLANK tDG_ITRIP_HB tOFF tBLANK tOFF tDG_ITRIP_HB Figure 7-13. Fixed Frequency ITRIP Current Regulation for Half-bridges The ITRIP setting can be changed at any time when SPI communication is available by writing to the OUTx_ITRIP_LVL bits. The change is immediately reflected in device behavior. If a half-bridge is configured for PWM control and ITRIP, when ITRIP is reached, the behavior is the same as for SPI register control, but the input now comes from the configured PWM pin. There is a minimum t OFF time enforced based on the HB_TOFF_SEL bits in the HB_ITRIP_FREQ register. With this setting enabled,where Period = 1/f PWM, tOFF = (Period - t ON) if (Period - t ON) > tOFF_MIN or tOFF = tOFF_MIN if (Period - tON) < tOFF_MIN . For example, in the case of HB_TOFF_SEL = 01b and minimum tOFF insertion of T/2. 1. If ITRIP occurs beyond 50% of duty cycle minimum fixed T/2 off time is inserted after ITRIP. The behavior is tOFF = T/2. 2. If ITRIP occurs within 50% duty cycle then behavior is tOFF = (Period - tON). Table 7-30. Minimum tOFF Time Options HB_TOFF_SEL Minimum tOFF Enforced 00b disabled, Zero 01b TOFF= T/2, 50% T 10b TOFF= T/4, 25% T 11b TOFF= T

7.4.4.5 Half-bridge Protection and Diagnostics

The half-bridge drivers are protected against overcurrent. The device also offers on-state and off-state load monitoring. Fault signaling is done through register HB_STATX. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: DRV8001-Q1

7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)

The user can determine the impedance on a pair of half-bridges using off-state diagnostics while the half-bridges are disabled in register HB_OUT_CNFGx. With this diagnostic, detecting the following fault conditions passively is possible:

• Output short to VM or GND < 1000 Ω
• Open load > (min ROPEN_HB) for high-side load, VM = 13.5 V Table 7-31. Off-state Open Load Threholds Device Min ROPEN_HB DRV8000-Q1 35 Ω DRV8000E-Q1 320 Ω DRV8001-Q1 320 Ω DRV8002-Q1 35 Ω Note Detecting a load short with this diagnostic is NOT possible. However, the user can deduce this logically if an overcurrent fault (OCP) occurs when an output is actively driven, but OLP diagnostics do not report any fault when the output is disabled. Occurrence of both OCP when an output is actively drive and OLP when the output is disabled implies a terminal short (short on selected output node).
• The user can configure the following combinations – Internal pullup resistor (ROLP_PU) on OUTx – Internal pulldown resistor (ROLP_PD) on OUTx – Comparator reference level
• This combination is determined by the HB_OLP_CNFG bits in the HB_OL_CNFG1 register.
• The half-bridge pairs to be diagnosed are determined by the HB_OLP_SEL bits in the HB_OL_CNFG1 register.
• The off-state diagnostics comparator output is available on HB_OLP_STAT bit in HB_STAT2 register. The output is not latched.
• The user is expected to toggle through all the combinations and record the status bit output after the output is settled.
• Based on the input combinations and status register, the user can determine if there is a fault on the output. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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ROLP_PD ROLP_PU Internal VOLP_REFH VOLP_REFL OUTx_OLP Register control REF Voltage proporonal to Internal 5V Output in register Filter Register control PVDD RHIZ ROLP_PD ROLP_PU Internal PGND OUTy Figure 7-14. Off-State (Passive) Diagnostics The following output, pulldown/pullup and VREF combinations are shown below: Table 7-32. Off-state Output Pullup/pulldown and VREF Options HB_OLP_CNFG Description 00b OLP Off 01b Output X Pullup enabled, Output Y pulldown enabled, Output Y selected, VREF Low 10b Output X Pullup enabled, Output Y pulldown enabled, Output X selected, VREF High 11b Output X Pulldown enabled, Output Y pullup enabled, Output Y selected, VREF Low The OLP combinations and truth table for a no fault scenario vs. fault scenario is shown in Table 7-33 For the diagnostics to be active and valid, all half-bridge configurations in bits OUTx_CNFG in registers HB_OUT_CNFGx must be zero (disabled). Table 7-33. Off-State Diagnostics Control Table User Inputs OLP Set-Up HB_OLP_STAT HB_OLP_C NFG nSLEEP OUTX OUTY CMP REF Output Selected Normal Open GND Short VM Short 01b 1 ROLP_PU ROLP_PD VOLP_REFL OUTY 1b 0b 0b 1b 10b 1 ROLP_PU ROLP_PD VOLP_REFH OUTX 0b 1b 0b 1b 11b 1 ROLP_PD ROLP_PU VOLP_REFL OUTY 1b 1b 0b 1b The following half-bridge pair off-state combinations and selection values are shown below. Note If any half-bridge is enabled, then all half-bridge OLP bits are automatically disabled and device ends off-state diagnostics. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: DRV8001-Q1

Table 7-34. OUTx and OUTy Configurations HB_OLP_SEL OUTX & OUTY Pairs Selected 0000b No output 0001b OUT1 & OUT2 0010b OUT1 & OUT3 0011b OUT1 & OUT4 0100b OUT1 & OUT5 0101b OUT1 & OUT6 0110b OUT2 & OUT3 0111b OUT2 & OUT4 1000b OUT2 & OUT5 1001b OUT2 & OUT6 1010b OUT3 & OUT4 1011b OUT3 & OUT5 1100b OUT3 & OUT6 1101b OUT4 & OUT5 1110b OUT4 & OUT6 1111b OUT5 & OUT6

7.4.4.5.2 Half-bridge Open Load Detection

When the device is active and waiting for drive commands, there is an open-load detection loop for half-bridges OUT1 - OUT6. The detection scheme sequentially checks the open-load status for each high- and low-side of each half-bridge output and reports the status in bit OUTx_xx_OLA in register HB_STAT2 and WARN bit in register IC_STAT1. From standby or sleep mode, starting with OUT1, the control loop begins checking the open-load status by comparing the current to the under-current threshold for that half-bridge after completing the open-load filter time. When running in PWM mode, this delay can be configured for 32, 128, 512, or 1024 PWM cycles with bit OUTx_OLA_TH in register HB_OL_CNFG2. The readback takes one extra cycle for example if OUTx_OLA_TH is configured for 32 cycles the value to read back is available at the end of the 33rd cycle. If an output is driven with EN/DIS only (no PWM switching) then the open-load detection delay is 10ms. Table 7-35. Open Load Detection Cycle Delay OUTx_OLA_TH Delay Cycle Count 00b 32 01b 128 10b 512 11b 1024 If open-load is detected at the end of the cycle count threshold or 10ms timeout occurs, then bit OUTx_HS_OLA/ OUTx_LS_OLA is reported. If no open-load is detected after configured delay cycle count, then the loop moves to the next half-bridge. The loop continues checking each output through OUT6, then goes back to OUT1 to restart the OLA loop. For the open-load check to be valid, the half-bridge open-load detection must be enabled (OUTx_OLA = 1b) and the output OUTx_CNFG must not be disabled. The diagram below shows the OLA scheme: DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Figure 7-15. Half-bridge Open-Load Active Detection Any given half-bridge is skipped if any of the following three conditions are met: 1. OUTx is disabled (OUTx_CNFG = 00b). 2. Open-load detect is not enabled (OUTx_OLA = 0b) for the half-bridge. 3. OUTx is OFF for more than 10ms 4. Both HS_OLA and LS_OLA have already been detected and flagged, or other fault condition on OUTx (overcurrent, over temperature) With all half-bridge OUTx enabled without PWM, the total loop time can take up to 60ms to cycle through all half-bridges. When a half-bridge is driven individually or sequentially, the loop detects open load within 10ms or more (depending on EN or PWM control frequency). If a half-bridge is driven with a low frequency external PWM signal, the OFF time of the output can exceed the open-load detection window of 10ms, and so the half-bridge reports the status at end of timeout or number of PWM cycles less than 10ms and continue.

7.4.4.5.3 Half-Bridge Overcurrent Protection

When a half-bridge is active, an analog current protection circuit on each MOSFET shuts off the MOSFET during hard short-circuit events. If the output current exceeds the overcurrent threshold I OCP_OUTX for longer than t DG_OCP_HB, an overcurrent fault is detected. The corresponding output is Hi-Z (latch behavior) and the fault is latched in register ( HB_STAT1). The half-bridge is disabled if V PVDD > V PVDD_OV configured in the PVDD_OV_MODE. For overcurrent deglitch time t DG_OCP_HB of half-bridge drivers, there are four overcurrent deglitch options summarized in the table below. Table 7-36. Half-bridge Overcurrent Deglitch OUTx_OCP_DG Voltage Limitation Deglitch time 00b VPVDD < VPVDD_OV 6 μs 01b VPVDD < VPVDD_OV 10 μs 10b VPVDD < VPVDD_OV 15 μs 11b VPVDD < 20V 60 μs VPVDD > 20V 15 μs To re-activate the driver, the fault must first be cleared in register by the MCU by reading the status register. The diagram below shows the overcurrent behavior of a half-bridge: www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: DRV8001-Q1

IOCP_HB_OUTx,y tDG_OCP_HB VOUTx HBX_STAT Fault Latched Fault Cleared, CLR_FLT set Normal Operation Figure 7-16. Overcurrent Behavior for Half-bridges

7.4.5 Sense Output (IPROPI)

The device features an output for current sensing, V PVDD monitoring, and die temperature on the IPROPI pin. This information can be used for status or regulation of loads (on OUTx), check die temperature, or to provide local motor suppy voltage. These integrated features eliminate the need for multiple external sense resistors or sense circuitry, reducing system size, cost and complexity. The load currents are sensed by using a shunt-less high-side current mirror topology. The IPROPI output current is a fixed ratio A IPROPI of the instantaneous current of the enabled driver (OUTx). The thermal cluster outputs come from the corresponding zones temperature sensing circuits. The local motor supply PVDD sense and temperature sense is converted to a current output on IPROPI pin through the IPROPI resistor allowing scalable output voltage for 5V and 3.3V ADC pins. For any IPROPI sense output, the maximum value of the selected scale (load current, voltage, or temperature) is represented by the maximum IPROPI output current of 2mA. For example, if OUT5 IPROPI is selected while driving an 8A load (the minimum driver OCP), the expected IPROPI output current is 2mA. If the load current is slightly higher than the minimum driver OCP, the IPROPI output current cannot be verified to follow the IPROPI current sense ratio, and in some cases OCP shutdown can occur. Bit IPROPI_SEL defines which of the outputs is multiplexed to the IPROPI pin, the control values shown in the table below: Table 7-37. IPROPI_SEL Options IPROPI_SEL Output 00000b No output 00001b OUT1 Current Sense 00010b OUT2 Current Sense 00011b OUT3 Current Sense 00100b OUT4 Current Sense 00101b OUT5 Current Sense 00110b OUT6 Current Sense 00111b OUT7 Current Sense 01000b OUT8 Current Sense 01001b OUT9 Current Sense 01010b OUT10 Current Sense 01011b OUT11 Current Sense 01100b OUT12 Current Sense 01101b RSVD DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Table 7-37. IPROPI_SEL Options (continued) IPROPI_SEL Output 01110b RSVD 01111b RSVD 10000b VPVDD Sense Nominal Range (5V - 22V) 10001b Thermal Cluster 1

10010 Thermal Cluster 2

10011 Thermal Cluster 3

10100 Thermal Cluster 4

10101 VPVDD Sense High Range (20V - 32V)

The diagram below shows the simple block diagram for the selectable IPROPI output: IOUTX IPROPI_SEL IPROPI RIPROPI To MCU ADC VTHERMX_OUT VPVDD_OUT Figure 7-17. IPROPI Output Circuit IPROPI Reset, Blank and Settling Times: When selecting between IPROPI output options from the above table, using the IPROPI_SEL bit, the IPROPI output first resets to 0V within 5.5 μs. This reset occurs for any IPROPI output selection or transition. To prevent false readouts, the signal on IPROPI is blanked after switching on any driver or sense output until the circuitry settles, roughly 60μs for High-side driver. Current (IOUTx) Sense: For current output, the IPROPI output analog current is scaled by AIPROPI as follows: IIPROPI = IOUTX / AIPROPI (1) PVDD Sense: For PVDD voltage sense output, there are two ranges:

• Nominal Range: 5V - 22V, where IPROPI output current is VPVDD/11,000
• High Range: 20V - 32V, where IPROPI output current is VPVDD/16,500 For example:
• IPROPI_SEL is selected for Nominal PVDD Range 1 (IPROPI_SEL = 10000b)
• VPVDD is 13.5V
• IIPROPI = 1.2mA PVDD Sense Fault Behavior: The IPROPI PVDD voltage sense output is valid and available when V PVDD is above the PVDD UV threshold, and when VDVDD is above the minimum recommended operating voltage. If VPVDD is above the PVDD OV threshold, PVDD sense output is still supported. However, the nominal range (5V-22V) IPROPI PVDD sense output cannot be verified above V PVDD > 22V. The High range IPROPI PVDD sense output ratio of 1/16,500 is valid within 20V to 32V, but cannot be verified above VPVDD of 32V. The faults where PVDD sense is unavailable:
• Charge Pump Undervoltage (VCP_UV)
• Thermal Shutdown when configured for global shutdown (default) Temperature Sense Output: The IPROPI output also provides current representation of any single of the four thermal cluster temperature. This is intended for use in testing and evaluation, but not during device run-time. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DRV8001-Q1

The maximum internal temperature at which IPROPI output current is available is 195°C, at which point the IPROPI output current is 1.94mA. The IPROPI current output is scaled according to the temperature range -40°C to 195°C. The equation for the IPROPI output current is: IIPROPI = α + β×t where α is offset roughly equal to 1.49mA, β is 2.24μA/°C, and 't' is temperature. To convert back to temperature, solving for temperature yields: t = (IIPROPI - α)/β In terms of the voltage generated on RIPROPI: t = ([VIPROPI/RIPROPI] - α)/β For example, when the cluster temperature is 0°C, the IPROPI output current is 1.49mA. At 145°C, the IPROPI output current is 1.81mA. The IPROPI pin must connect to ground through an external resistor (R IPROPI) generate the proportional voltage VIPROPI. This allows for the IPROPI current to be measured as a voltage-drop across the R IPROPI resistor in the application so that the full range of the controller ADC is utilized. When selecting the IPROPI resistance value, note the maximum operating IPROPI output voltage of 4.7V. This value considers a 10% output error of IPROPI drives the IPROPI output voltage to 5.3V at a maximum sense value (maximum load current of a driver, for example). To stay below this voltage, use a resistance value of less below the MCU absolute maximum voltage, considering this 10% output error of IPROPI.

7.4.6 Protection Circuits

7.4.6.1 Fault Reset (CLR_FLT)

The DRV8001-Q1 provides a specific sequence to clear fault conditions from the driver and resume operation. This function is provided through the CLR_FLT register bit. To clear fault reporting the CLR_FLT register bit must be asserted after the fault condition is removed. After being asserted, the driver clears the fault and reset the CLR_FLT register bit.

7.4.6.2 DVDD Logic Supply Power on Reset (DVDD_POR)

If at any time the input logic supply voltage on the DVDD pin falls below the V DVDD_POR threshold for longer than the tDVDD_POR_DG time or the nSLEEP pin is asserted low, the device enters the inactive state disabling the gate drivers, charge pump, OUTx outputs and protection monitors. Normal operation resumes when the DVDD undervoltage condition is removed or the nSLEEP pin is asserted high. After a DVDD power on reset (POR), the POR register bit is asserted until CLR_FLT is issued.

7.4.6.3 PVDD Supply Undervoltage Monitor (PVDD_UV)

If at any time the power supply voltage on the PVDD pin falls below the V PVDD_UV threshold for longer than the tPVDD_UV_DG time, the DRV8001-Q1 detects a PVDD undervoltage condition. After detecting the undervoltage condition, the gate driver pulldowns are enabled, charge pump disabled, all OUTx disabled, FAULT bit and PVDD_UV register bit are asserted. The PVDD undervoltage monitor can recover in two different modes set through the PVDD_UV_MODE register setting.

• Latched Fault Mode: After the undervoltage condition is removed, the fault state remains latched and all outputs disabled until CLR_FLT is issued.
• Automatic Recovery Mode: After the undervoltage condition is removed, the FAULT register bit is automatically cleared and the outputs are re-enabled. The PVDD_UV register bit remains latched until CLR_FLT is issued. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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7.4.6.4 PVDD Supply Overvoltage Monitor (PVDD_OV)

In the DRV8001-Q1, there are two V PVDD_OV thresholds, a low and high threshold. The overvoltage response options are dependent on the driver outputs configured (High-side, EC, Heater driver, Half-bridge drivers). There are two fault status bits available PVDD_OV_22V and PVDD_OV_28V in IC_STAT1. The PVDD overvoltage monitor can respond and recover in two different modes set through the PVDD_OV_MODE register setting.

• Latched Fault Mode (0b): After detecting the overvoltage condition, all drivers are disabled and FAULT register bit, and PVDD_OV_22V or PVDD_OV_28V register bit are asserted. After the overvoltage condition is removed, the fault state remains latched until CLR_FLT is issued.
• Automatic Recovery Mode (1b): After detecting the overvoltage condition, all drivers are disabled and FAULT register bit, and PVDD_OV_22V or PVDD_OV_28V register bit asserted. After the overvoltage condition is removed, the FAULT register bit is automatically cleared and the driver automatically reenabled. The PVDD_OV_22V or PVDD_OV_28V register bit remains latched until CLR_FLT is issued. High-side, EC and heater drivers overvoltage fault (PVDD_OV_22V):
• High-side, EC and heater drivers shutoff when VPVDD > low VPVDD threshold voltage (22V).
• PVDD_OV_22V fault status is defined in High-side, EC and heater drivers PVDD Overvoltage Behavior table.
• No PVDD_OV_LVL setting available for High-side, EC and heater drivers outputs
• PVDD_OV_MODE can be set to fault response Latched Fault or Automatic Recovery modes. Table 7-38. High-side, EC and Heater Drivers PVDD Overvoltage Behavior PVDD Voltage High-side, EC and Heater Drivers PVDD_OV_22V Status PVDD_OV_28V FAULT VPVDD < 22 V Normal Operation 0b Not Applicable 0b VPVDD > 22 V Shutdown 1b Not Applicable 1b Half-bridges overvoltage fault (PVDD_OV_22V or PVDD_OV_28V):
• Half-bridges support warning or shutoff when VPVDD > low VPVDD threshold voltage (22V) or shutoff for high VPVDD threshold voltage (28V).
• PVDD_OV_22V has a configurable warning or fault condition using register PVDD_OV_LVL setting available for these driver outputs as defined in Half-bridges and Gate driver PVDD Overvoltage Behavior table.
• The deglitch time for PVDD_OV_22V can be adjusted through the PVDD_OV_DG register settings.
• PVDD_OV_MODE can be set to fault response Latched Fault or Automatic Recovery modes. Table 7-39. Half-Bridges and Gate Driver PVDD Overvoltage Behavior PVDD_OV_LVL PVDD Voltage Half-Bridges and Gate Drivers High-Side, EC and Heater Drivers PVDD_OV_22V PVDD_OV_28V FAULT 0b VPVDD < 22 V Normal Operation Normal Operation 0b 0b 0b 0b VPVDD > 22 V Shutdown Shutdown 1b 0b 1b 1b VPVDD < 22 V Normal Operation Normal Operation 0b 0b 0b 1b 28 V> VPVDD > 22 V Normal Operation with Warning Shutdown 1b 0b 1b 1b VPVDD > 28 V Shutdown Shutdown 1b 1b 1b

7.4.6.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)

If at any time the voltage on the VCP pin falls below the V VCP_UV threshold for longer than the t VCP_UV_DG time, the DRV8001-Q1 detects a VCP undervoltage condition. After detecting the undervoltage condition, all outputs are disabled and FAULT register bit, and VCP_UV register bit is asserted. The VCP undervoltage monitor can recover in two different modes set through the VCP_UV_MODE register setting. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: DRV8001-Q1

• Latched Fault Mode: Additionally the charge pump is disabled in latched fault mode. After the undervoltage condition is removed, the fault state remains latched and charge pump disabled until CLR_FLT is issued.
• Automatic Recovery Mode: After the undervoltage condition is removed, the FAULT register bit is cleared and the driver automatically reenabled. The VCP_UV register bit remains latched until CLR_FLT is issued.

7.4.6.6 Thermal Clusters

As there are multiple drivers and types of drivers on this device, there are multiple dedicated thermal sensors located on chip to monitor key block temperatures on the chip. Each of these sensors, called thermal clusters, measure local die temperature for specific device blocks. These measurements are converted to a current for output on IPROPI pin, used to trigger temperature warnings or to shutdown a specific cluster which is exceeding acceptable temperature range or the entire device. The device response to thermal cluster warnings can be configured with bit OTSD_MODE in the IC_CNFG1 register:

• Default mode (OTSD_MODE = 0b): if any cluster reaches thermal shutdown threshold for longer than tOTSD_DG, the entire device is shutoff.
• Cluster mode (OTSD_MODE = 1b): if a cluster reaches thermal shutdown threshold for longer than tOTSD_DG, only that cluster is shutoff. There are four zones defined with thermal clusters, shown in the table and diagram below: Zone 1 Zone 2 Zone 4 Zone 3 OUT5 7 OUT4 1 nSCS 13 SDI 14 SCLK IPROPI Thermal Pad PVDD 4 NC 2 NC 3 OUT12 VCP 5 PGND 8 PVDD 6 nSLEEP NC NC PWM2 NC ECFB

SH_HS GH_HS SDO Figure 7-18. Thermal Sensor Zones Table 7-40. Thermal Cluster Locations Thermal Cluster 1 Thermal Cluster 2 Thermal Cluster 3 Thermal Cluster 4 OUT5, OUT1 and OUT2 OUT3, OUT4 and OUT6 High-side drivers Global and remaining drivers For each zone, there are comparator-based warnings for two temperature points, 120°C for low and 140°C for high. Bit ZONEX_OTW_X (L or H) is latched in register IC_STAT2. Each warning can be individually disabled DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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with bit ZONEX_OTW_X_DIS in register IC_CNFG2. If overtemperature shutdown occurs, ZONEX_OTSD bit is latched in register IC_STAT2.

7.4.6.7 Watchdog Timer

The device integrates a programmable window type SPI watchdog timer to verify that the external controller is operating and the SPI bus integrity is monitored. The SPI watchdog timer can be enabled by through the WD_EN SPI register bit. The watchdog timer is disabled by default. When the watchdog timer is enabled, an internal timer starts to count up. The watchdog timer is reset by inverting the WD_RST SPI register. This WD_RST must be issued between the lower window time and the upper window time. If a watchdog timer fault is detected, the device response can be configured to either report only a warning or report a fault and disable all drivers. The watchdog fault can be cleared with a CLR_FLT command. If the watchdog is set to disable all drivers, the drivers are enabled after a CLR_FLT command is sent to remove the watchdog fault condition. To restart the watchdog after clear fault, disable and re-enable watchdog using WD_EN bit.

7.4.6.8 Fault Detection and Response Summary Table

FAULT EVENT CONDITION MODE DIGITAL CORE CHARGE PUMP DRIVERS STATUS BIT FAULT/ WARN FUNCTIONAL RECOVERY STATUS BIT RECOVERY SPI Clock Fault Invalid SPI Clock Frame Latched Active Active Active SPI_OK, SCLK_FLT, Reject Frame SPI_ERR on SDO frame NA Valid SPI frame CLR_FLT SPI Address Fault Address out of range Latched Active Active Active SPI_ERR in SDO frame NA Valid SPI frame NA DVDD Power-on- Reset DVDD < VDVDD_POR NA Reset Disabled Semi-Active Pulldown POR NA DVDD > VDVDD_POR CLR_FLT PVDD Undervoltage PVDD < VPVDD_UV Latched Active Disabled Pulldown PVDD_UV OV/UV on SDO frame FAULT PVDD > VPVDD_UV and CLR_FLT CLR_FLT Automatic Active Disabled Pulldown PVDD_UV OV/UV on SDO frame FAULT PVDD > VPVDD_UV CLR_FLT VCP Undervoltage VCP < VVCP_UV Latched Active Disabled Pulldown VCP_UV OV/UV on SDO frame FAULT VCP > VVCP_UV and CLR_FLT CLR_FLT Automatic Active Active Pulldown VCP_UV OV/UV on SDO frame FAULT VCP > VVCP_UV CLR_FLT PVDD Overvoltage PVDD_OV_LVL =

0 PVDD > 22V

Latched Active Active Pulldown PVDD_OV_22V OV/UV on SDO frame FAULT PVDD <VPVDD_OV_LO and CLR_FLT CLR_FLT Automatic Active Active Pulldown PVDD_OV_22V OV/UV on SDO frame FAULT PVDD <VPVDD_OV_LO CLR_FLT PVDD_OV_LVL = 1 28V > PVDD > 22V Latched Active Active EC, Heater and HS are Pulldown PVDD_OV_22V OV/UV on SDO frame FAULT PVDD <VPVDD_OV_LO and CLR_FLT CLR_FLT Automatic Active Active EC, Heater and HS are Pulldown PVDD_OV_22V OV/UV on SDO frame FAULT PVDD <VPVDD_OV_LO CLR_FLT PVDD_OV_LVL =

1 PVDD > 28V

Latched Active Active Pulldown PVDD_OV_22V, PVDD_OV_28V OV/UV on SDO frame FAULT PVDD <VPVDD_OV_LO and CLR_FLT CLR_FLT Automatic Active Active Pulldown PVDD_OV_22V, PVDD_OV_28V OV/UV on SDO frame FAULT PVDD <VPVDD_OV_LO CLR_FLT Half-bridge Overcurrent Fault (OUT1-OUT6) IOUTx > IOCPx Latched Active Active Affected driver Hi-Z HB, OUTx_HS_OCP, OUTx_LS_OCP FAULT IOUTx < IOCPx and CLR_FLT CLR_FLT Half-bridge active open load Fault (OUT1-OUT6) IOUTx < IOLA_OUTx Latched Active Active Active HB, OUTx_HS_OLA,O UTx_LS_OLA WARN IOUTx > IOLA_OUTx and CLR_FLT CLR_FLT www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: DRV8001-Q1

FAULT EVENT CONDITION MODE DIGITAL CORE CHARGE PUMP DRIVERS STATUS BIT FAULT/ WARN FUNCTIONAL RECOVERY STATUS BIT RECOVERY High-side Driver overcurrent Fault (OUT7-OUT12) OUTx_ITRIP_EN =0 IOUTx > IOCx Latched Active Active Affected driver Hi-Z HS, ITRIP, OUTx_ITRIP_STA T FAULT IOUTx < IOCx and CLR_FLT CLR_FLT High-side Driver OUTx ITRIP (OUT7-OUT12) OUTx_ITRIP_EN =1 IOUTx > IOCx Latched Active Active Active HS, ITRIP, OUTx_ITRIP_STA T NA IOUTx < IOCx CLR_FLT High Side driver short circuit fault (OUT7-12) VOUTx<VSC_DE T Latched Active Active Affected driver Hi-Z HS, OUTx_OCP FAULT VOUTx > VSC_DET and CLR_FLT CLR_FLT High-side Driver open load Fault (OUT7-OUT12) IOUTx < IOLDx Latched Active Active Active HS, OUTx_OLA WARN IOUTx > IOLDx and CLR_FLT CLR_FLT ECFB Overvoltage ECFB_OV_MOD E=00b or 11b VECFB>VECFB_ OV_TH Disabled Active Active Active NA NA NA NA ECFB_OV_MOD E=01b VECFB>VECFB_ OV_TH Latched Active Active Active EC_HEAT, ECFB_OV NA NA CLR_FLT ECFB_OV_MOD E=10b VECFB>VECFB_ OV_TH Latched Active Active EC driver Hiz EC_HEAT, ECFB_OV FAULT VECFB<VECFB_O V_TH and CLR_FLT CLR_FLT ECFB short circuit (passive) ECFB_DIAG=01b VECFB<VECFB_ SC_TH Automatic Active Active NA EC_HEAT, ECFB_DIAG_STA T NA VECFB > VECFB_SC_TH NA ECFB open load (passive) ECFB_DIAG=10b VECFB >VECFB_OLP_T H Automatic Active Active NA EC_HEAT, ECFB_DIAG_STA T NA VECFB <VECFB_OLP_TH NA ECFB Above Target Voltage VECFB>VECFB_ HI Automatic Active Active Active EC_HEAT, ECFB_HI NA VECFB<VECFB_HI NA ECFB Below Target Voltage VECFB<VECFB_ LO Automatic Active Active Active EC_HEAT, ECFB_LO NA VECFB>VECFB_L O NA ECFB Overcurrent (discharge) EC_FLT_MODE= 0b IECFB> IOC_ECFB Latched Active Active ECFB Hi-Z EC_HEAT, ECFB_OC FAULT IECFB< IOC_ECFB and CLR_FLT CLR_FLT ECFB Open load active (discharge) IECFB< IOL_ECFB_LS Latched Active Active Active EC_HEAT, ECFB_OL WARN IECFB> IOL_ECFB_LS and CLR_FLT CLR_FLT Heater VDS Overcurrent Fault VHEAT_VDS > VDS_LVL_HEAT Latched Active Active Heater is Pulldown EC_HEAT,HEAT_ VDS FAULT VHEAT_VDS < VDS_LVL_HEAT and CLR_FLT CLR_FLT Cycle Active Active Heater is Pulldown EC_HEAT,HEAT_ VDS FAULT VHEAT_VDS < VDS_LVL_HEAT and (CLR_FLT or PWM) CLR_FLT Warning Active Active Active EC_HEAT,HEAT_ VDS WARN NA CLR_FLT Disabled Active Active Active NA NA NA NA Heater VDS Open load Fault VSH_HS > VOL_HEAT Latched Active Active Heater is Pulldown EC_HEAT,HEAT_ OL FAULT VSH_HS < VOL_HEAT and CLR_FLT CLR_FLT Zone X Thermal Warning TJ > TOTW1,TOTW2 Automatic Active Active Active OTW, ZONEx_OTW_L, ZONEx_OTW_H NA TJ < TOTW1,TOTW2 NA Zone X Thermal Shutdown TJ > TOTSD Latched Active Disabled Semi-Active Pulldown, Hi- Z OTSD, ZONEx_OTSD FAULT TJ < TOTSD and CLR_FLT CLR_FLT Watchdog WD_FLT_M=0b , Invalid Access or Expiration Warning Active Active Active WD_FLT WARN CLR_FLT and WD_EN disable and re-enable CLR_FLT DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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FAULT EVENT CONDITION MODE DIGITAL CORE CHARGE PUMP DRIVERS STATUS BIT FAULT/ WARN FUNCTIONAL RECOVERY STATUS BIT RECOVERY Watchdog WD_FLT_M=1b , Invalid Access or Expiration Latched Active Active Pulldown WD_FLT FAULT CLR_FLT and WD_EN disable and re-enable CLR_FLT

7.5 Programming

7.5.1 Serial Peripheral Interface (SPI)

An SPI bus is used to set device configurations, operating parameters, and read out diagnostic information on the DRV8001-Q1 device. The SPI operates in peripheral mode and connects to a controller. The SPI input data (SDI) word consists of a 24 bit word, with an 8 bit command and 16 bits of data. The SPI output data (SDO) word for read commands consists of the fault status indication bits and then the register data being accessed for read commands. The SDO word for write commands consists of the fault status followed by the existing data in the written register. The data sequence between the MCU and the SPI peripheral driver is shown in Figure 7-19. A1 D1 SDO SDI nSCS S1 R1 Figure 7-19. SPI Data Frame A valid frame must meet the following conditions:

• The SCLK pin is pulled low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin is pulled high between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed in the Hi-Z state.
• Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 24 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is less than or more than 24 bits, a frame error (SCLK_FLT) occurs and the data word is ignored.
• For a write command, following the 16-bit command data, the existing data in the register being written to is shifted out on the SDO pin starting with fault status byte then 16-bit data . www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: DRV8001-Q1

Figure 7-20. SPI peripheral Timing Diagram

7.5.2 SPI Format

The SDI input data word is 24 bits long and consists of the following format:

• MSB bit indicates frame type (bit B23 = 0 for standard frame)
• 1 read or write bit, W (bit B22, write = 0, read = 1)
• 6 address bits, A (bits B21 through B16)
• 16 data bits, D (bits B15 through B0). For a read operation, these bits are typically set to null values, while for a write operation, these bits have the data value for the addressed register. Table 7-41. SDI Input Data Word Format R/W Address Data Bit B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Dat a 0 W0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 The SDO output data word is 24 bits long and the first 8 bits makes up the IC status register. The report word is the content of the register being accessed. For a write command (W0 = 0), the response word consists of the fault status indication bits followed by the existing data in the register being written to. For a read command (W0 = 1), the response word consists of the fault status indications bits followed by the data currently in the register being read. Table 7-42. SDO Output Data Word Format IC Status Report Bit B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data 1 1 FAULT WARN OV_U V DRV OTSD SPI_E RR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
• FAULT - 'OR' of any device fault (global or driver)
• WARN - 'OR' of any device warnings
• OV_UV - 'OR' of PVDD, VCP overvoltage and undervoltage status DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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• DRV - 'OR' of any driver fault
• OTSD - Set when over temperature shutdown occurs
• SPI_ERR - Set when incorrect number of SCLKs received

7.5.3 Timing Diagrams

tHI_nSCS tSU_nSCS tCLK tCLKH tCLKL MSB LSB tH_SDItSU_SDI Z ZMSB LSB tH_nSCS tDIS_nSCS X X tD_SDO nSCS SCLK SDI SDO Figure 7-21. SPI Timing Diagram www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: DRV8001-Q1

8 DRV8001-Q1 Register Map

Table 8-2 lists the memory-mapped registers for the DRV8001-Q1. All register addresses not listed are considered as reserved locations and the register contents are not modified. Descriptions of reserved locations are provided for reference only. The device ID table summarizes the device IDs for DRV800x devices. Table 8-1. Device ID Summary Device Device ID DRV8000-Q1 Reg Address 0x8h, DEVICE_ID=0x02 DRV8001-Q1 Reg Address 0x8h, DEVICE_ID=0x12 DRV8002-Q1 Reg Address 0x8h, DEVICE_ID=0x22 Table 8-2. DRV8001-Q1 Register Map Name 15 14 13 12 11 10 9 8 Type Addr 7 6 5 4 3 2 1 0 IC_ STAT1 SPI_OK POR FAULT WARN RSVD HB EC_HEAT HS R 00h PVDD_UV PVDD_OV_22V VCP_UV OTW OTSD WD_FLT ITRIP PVDD_OV_28V IC_STAT2 DEVICE_ERR RSVD SCLK_FLT RSVD ZONE4_OTSD ZONE3_OTSD ZONE2_OTSD ZONE1_OTSD R 01h ZONE4_OTW_H ZONE3_OTW_H ZONE2_OTW_H ZONE1_OTW_H ZONE4_OTW_L ZONE3_OTW_L ZONE2_OTW_L ZONE1_OTW_L RSVD R 02h HB_STAT1 RSVD OUT6_LS_OCP OUT5_LS_OCP OUT4_LS_OCP OUT3_LS_OCP OUT2_LS_OCP OUT1_LS_OCP R 03h RSVD OUT6_HS_OCP OUT5_HS_OCP OUT4_HS_OCP OUT3_HS_OCP OUT2_HS_OCP OUT1_HS_OCP HB_STAT2 RSVD HB_OLP_STAT OUT6_LS_OLA OUT5_LS_OLA OUT4_LS_OLA OUT3_LS_OLA R 04h OUT2_LS_OLA OUT1_LS_OLA OUT6_HS_OLA OUT5_HS_OLA OUT4_HS_OLA OUT3_HS_OLA OUT2_HS_OLA OUT1_HS_OLA EC_HEAT_ITRIP_ STAT ECFB_DIAG_ST AT ECFB_OV ECFB_HI ECFB_LO ECFB_OC ECFB_OL HEAT_OL HEAT_VDS R 05h RSVD OUT7_ITRIP_ST AT OUT6_ITRIP_ST AT OUT5_ITRIP_ST AT OUT4_ITRIP_ST AT OUT3_ITRIP_ST AT OUT2_ITRIP_ST AT OUT1_ITRIP_ST AT HS_STAT RSVD OUT12_OLA OUT11_OLA OUT10_OLA OUT9_OLA OUT8_OLA OUT7_OLA R 06h RSVD OUT12_OCP OUT11_OCP OUT10_OCP OUT9_OCP OUT8_OCP OUT7_OCP HS_ITRIP_STAT RSVD R 07h RSVD ECFB_LS_ITRIP _STAT RSVD OUT12_ITRIP_S TAT OUT11_ITRIP_S TAT OUT10_ITRIP_S TAT OUT9_ITRIP_ST AT OUT8_ITRIP_ST AT SPARE_STAT2 RSVD R 08h DEV_ID IC_CNFG1 OTSD_MODE DIS_CP RSVD PVDD_OV_MOD E PVDD_OV_DG PVDD_OV_LVL RSVD R/W 09h RSVD VCP_UV_MODE PVDD_UV_MOD E WD_EN WD_FLT_M WD_WIN EN_SSC IC_CNFG2 RSVD R/W 0AhZONE4_OTW_H _DIS ZONE3_OTW_H _DIS ZONE2_OTW_H _DIS ZONE1_OTW_H _DIS ZONE4_OTW_L _DIS ZONE3_OTW_L _DIS ZONE2_OTW_L _DIS ZONE1_OTW_L _DIS RSVD RSVD R 0Bh - 13h HB_ITRIP_DG RSVD OUT6_ITRIP_DG OUT5_ITRIP_DG R/W 14h OUT4_ITRIP_DG OUT3_ITRIP_DG OUT2_ITRIP_DG OUT1_ITRIP_DG HB_OUT_CNFG1 RSVD NSR_OUT6_DIS NSR_OUT5_DIS NSR_OUT4_DIS NSR_OUT3_DIS NSR_OUT2_DIS NSR_OUT1_DIS IPROPI_SH_EN R/W 15h RSVD OUT6_CNFG OUT5_CNFG HB_OUT_CNFG2 RSVD OUT4_CNFG OUT3_CNFG R/W 16h OUT2_MODE OUT1_MODE OUT2_CNFG OUT1_CNFG HB_OCP_CNFG RSVD OUT6_OCP_DG OUT5_OCP_DG R/W 17h OUT4_OCP_DG OUT3_OCP_DG OUT2_OCP_DG OUT1_OCP_DG HB_OL_CNFG1 RSVD HB_OLP_CNFG HB_OLP_SEL R/W 18h RSVD OUT6_OLA_EN OUT5_OLA_EN OUT4_OLA_EN OUT3_OLA_EN OUT2_OLA_EN OUT1_OLA_EN HB_OL_CNFG2 RSVD OUT6_OLA_TH OUT5_OLA_TH R/W 19h OUT4_OLA_TH OUT3_OLA_TH OUT2_OLA_TH OUT1_OLA_TH HB_SR_CNFG RSVD OUT6_SR OUT5_SR R/W 1Ah OUT4_SR OUT3_SR OUT2_SR OUT1_SR DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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Table 8-2. DRV8001-Q1 Register Map (continued) Name 15 14 13 12 11 10 9 8 Type Addr 7 6 5 4 3 2 1 0 HB_ITRIP_CNFG OUT6_ITRIP_E N OUT5_ITRIP_E N OUT4_ITRIP_E N OUT3_ITRIP_E N OUT2_ITRIP_E N OUT1_ITRIP_E N OUT6_ITRIP_LVL R/W 1Bh OUT5_ITRIP_LVL OUT4_ITRIP_LVL OUT3_ITRIP_LVL OUT2_ITRIP_LV L OUT1_ITRIP_LV L HB_ITRIP_FREQ RSVD HB_TOFF_SEL OUT6_ITRIP_FREQ OUT5_ITRIP_FREQ R/W 1Ch OUT4_ITRIP_FREQ OUT3_ITRIP_FREQ OUT2_ITRIP_PWM_FREQ/ PWM_OUT2_FREQ OUT1_ITRIP_PWM_FREQ/ PWM_OUT1_FREQ HS_HEAT_OUT_ CNFG HEAT_CNFG RSVD OUT12_CNFG OUT11_CNFG R/W 1Dh OUT10_CNFG OUT9_CNFG OUT8_CNFG OUT7_CNFG HS_OC_CNFG RSVD OUT11_EC_MO DE RSVD R/W 1Eh RSVD OUT12_OC_TH OUT11_OC_TH OUT10_OC_TH OUT9_OC_TH OUT8_OC_TH OUT7_RDSON_ MODE HS_OL_CNFG RSVD OUT12_OLA_TH OUT11_OLA_TH OUT10_OLA_TH OUT9_OLA_TH OUT8_OLA_TH RSVD R/W 1Fh RSVD OUT12_OLA_E N OUT11_OLA_EN OUT10_OLA_E N OUT9_OLA_EN OUT8_OLA_EN OUT7_OLA_EN HS_REG_CNFG1 RSVD R/W 20hOUT7_ITRIP_E N RSVD OUT7_ITRIP_FREQ OUT7_ITRIP_DG HS_REG_CNFG2 RSVD OUT12_CCM_T O OUT11_CCM_T O OUT10_CCM_T O OUT9_CCM_TO OUT8_CCM_TO OUT7_CCM_TO R/W 21h RSVD OUT12_CCM_E N OUT11_CCM_E N OUT10_CCM_E N OUT9_CCM_EN OUT8_CCM_EN OUT7_CCM_EN HS_PWM_FREQ _CNFG RSVD PWM_OUT12_FREQ PWM_OUT11_FREQ R/W 22h PWM_OUT10_FREQ PWM_OUT9_FREQ PWM_OUT8_FREQ PWM_OUT7_FREQ HEAT_CNFG RSVD HEAT_VDS_LVL R/W 23h HEAT_VDS_MODE HEAT_VDS_BLK HEAT_VDS_DG HEAT_OLP_EN RSVD EC_CNFG ECFB_DIAG EC_OUT11_OCP_DG ECFB_SC_RSEL ECFB_OV_DG R/W 24h RSVD ECFB_OV_MODE EC_FLT_MODE ECFB_LS_PWM EC_OLEN ECFB_MAX HS_REG_CNFG3 RSVD HS_OUT_ITRIP_FREQ HS_OUT_ITRIP_DG R/W 25h RSVD HS_OUT12_ITRI P_EN HS_OUT11_ITRI P_EN HS_OUT10_ITRI P_EN HS_OUT9_ITRI P_EN HS_OUT8_ITRI P_EN SPARE_CNFG2 RSVD R/W 26h OUT1_HS_MODE _DC RSVD OUT1_DC R/W 27h OUT1_DC OUT2_HS_MODE _DC RSVD OUT2_DC R/W 28h OUT2_DC IC_CTRL RSVD IPROPI_SEL R/W 29h CTRL_LOCK CNFG_LOCK WD_RST CLR_FLT HB_CTRL RSVD OUT6_CTRL OUT5_CTRL R/W 2Ah OUT4_CTRL OUT3_CTRL OUT2_CTRL OUT1_CTRL HS_EC_HEAT_C TRL ECFB_LS_EN EC_ON EC_V_TAR R/W 2Bh HEAT_EN RSVD OUT12_EN OUT11_EN OUT10_EN OUT9_EN OUT8_EN OUT7_EN OUT7_PWM_DC RSVD OUT7_DC R/W 2Ch OUT7_DC OUT8_PWM_DC RSVD OUT8_DC R/W 2Dh OUT8_DC OUT9_PWM_DC RSVD OUT9_DC R/W 2Eh OUT9_DC OUT10_PWM_DC RSVD OUT10_DC R/W 2Fh OUT10_DC OUT11_PWM_DC RSVD OUT11_DC R/W 30h OUT11_DC OUT12_PWM_DC RSVD OUT12_DC R/W 31h OUT12_DC www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: DRV8001-Q1

8.1 DRV8000-Q1_STATUS Registers

Table 8-3 lists the memory-mapped registers for the DRV8000-Q1_STATUS registers. All register offset addresses not listed in Table 8-3 should be considered as reserved locations and the register contents should not be modified. Table 8-3. DRV8000-Q1_STATUS Registers Offset Acronym Register Name Section 0h IC_STAT1 Device status summary 1. Section 8.1.1 1h IC_STAT2 Device status summary 2. Section 8.1.2 3h HB_STAT1 Half-bridge overcurrent status. Section 8.1.3 4h HB_STAT2 Half-bridge open-load status. Section 8.1.4 5h EC_HEAT_ITRIP_STAT Electrochrome, Heater, and ITRIP status. Section 8.1.5 6h HS_STAT High-side driver status. Section 8.1.6 7h HS_ITRIP_STAT Electrochrome and High-side ITRIP status Section 8.1.7 8h SPARE_STAT2 Spare status 2. Section 8.1.8 Complex bit access types are encoded to fit into small table cells. Table 8-4 shows the codes that are used for access types in this section. Table 8-4. DRV8000-Q1_STATUS Access Type Codes Access Type Code Description Read Type R R Read Reset or Default Value -n Value after reset or the default value DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.1.1 IC_STAT1 Register (Offset = 0h) [Reset = C000h]

IC_STAT1 is shown in Table 8-5. Return to the Summary Table. Main device status register for driver, supply and over temperature fault status. Also includes watchdog and ITRIP regulation fault status. Table 8-5. IC_STAT1 Register Field Descriptions Bit Field Type Reset Description 15 SPI_OK R 1h Indicates if a SPI communications fault has been detected. 0b = One or multiple of SCLK_FLT in the prior frames. 1b = No SPI fault has been detected. 14 POR R 1h Indicates power-on-reset condition. 0b = No power-on-reset condition detected. 1b = Power-on reset condition detected. 13 FAULT R 0h General Fault indicator. Indicates a device or driver fault has occurred. 0b = No fault. 1b = Fault detected. 12 WARN R 0h General warning indicator. Indicates a warning is present. 0b = No warning. 1b = Warning is present.

11 RESERVED R 0h Reserved

10 HB R 0h Logic OR of overcurrent and open load fault indicators for half-

bridges.

9 EC_HEAT R 0h Logic OR of EC OV, overcurrent, open load fault indicators for EC

and heater.

8 HS R 0h Logic OR of overcurrent, short-circuit and open load fault indicators

for integrated high-side drivers. 7 PVDD_UV R 0h Indicates undervoltage fault on PVDD pin. 6 PVDD_OV_22V R 0h Indicates overvoltage fault on PVDD pin greater than 22 V. 5 VCP_UV R 0h Indicates undervoltage fault on VCP pin. 4 OTW R 0h Indicates overtemperature warning.

3 OTSD R 0h Indicates overtemperature shutdown

2 WD_FLT R 0h Indicates watchdog timer fault. 1 ITRIP R 0h Indicates ITRIP regulation warning when any OUTx entered ITRIP. 0 PVDD_OV_28V R 0h Indicates overvoltage fault on PVDD pin greater than 28 V. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: DRV8001-Q1

8.1.2 IC_STAT2 Register (Offset = 1h) [Reset = 0000h]

IC_STAT2 is shown in Table 8-6. Return to the Summary Table. Second device status register with SPI faults and specific thermal cluster fault/warning status. Table 8-6. IC_STAT2 Register Field Descriptions Bit Field Type Reset Description 15 DEVICE_ERR R 0h Indicates device OTP memory error has occurred.

14 RESERVED R 0h Reserved

13 SCLK_FLT R 0h Indicates SPI clock (frame) fault when the number of SCLK pulses in

a transaction frame are not equal to 24 bits, 1 byte address and two bytes data. Reported on bit SPI_ERR.

12 RESERVED R 0h Reserved

11 ZONE4_OTSD R 0h Indicates overtemperature shutdown has occurred in zone 4. 10 ZONE3_OTSD R 0h Indicates overtemperature shutdown has occurred in zone 3. 9 ZONE2_OTSD R 0h Indicates overtemperature shutdown has occurred in zone 2. 8 ZONE1_OTSD R 0h Indicates overtemperature shutdown has occurred in zone 1.

7 ZONE4_OTW_H R 0h Indicates high temperature warning (above 145°C) has occurred in

zone 4.

6 ZONE3_OTW_H R 0h Indicates high temperature warning (above 145°C) has occurred in

zone 3.

5 ZONE2_OTW_H R 0h Indicates high temperature warning (above 145°C) has occurred in

zone 2.

4 ZONE1_OTW_H R 0h Indicates high temperature warning (above 145°C) has occurred in

zone 1.

3 ZONE4_OTW_L R 0h Indicates low temperature warning (above 125°C) has occurred in

zone 4.

2 ZONE3_OTW_L R 0h Indicates low temperature warning (above 125°C) has occurred in

zone 3.

1 ZONE2_OTW_L R 0h Indicates low temperature warning (above 125°C) has occurred in

zone 2.

0 ZONE1_OTW_L R 0h Indicates low temperature warning (above 125°C) has occurred in

zone 1. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.1.3 HB_STAT1 Register (Offset = 3h) [Reset = 0000h]

HB_STAT1 is shown in Table 8-7. Return to the Summary Table. Half-bridge overcurrent faults for either high- or low-side of each half-bridge. Table 8-7. HB_STAT1 Register Field Descriptions Bit Field Type Reset Description

15 RESERVED R 0h Reserved

13 OUT6_LS_OCP R 0h Indicates overcurrent fault on low-side of half-bridge OUT6. 12 OUT5_LS_OCP R 0h Indicates overcurrent fault on low-side of half-bridge OUT5. 11 OUT4_LS_OCP R 0h Indicates overcurrent fault on low-side of half-bridge OUT4. 10 OUT3_LS_OCP R 0h Indicates overcurrent fault on low-side of half-bridge OUT3. 9 OUT2_LS_OCP R 0h Indicates overcurrent fault on low-side of half-bridge OUT2. 8 OUT1_LS_OCP R 0h Indicates overcurrent fault on low-side of half-bridge OUT1.

7 RESERVED R 0h Reserved

6 RESERVED R 0h Reserved

5 OUT6_HS_OCP R 0h Indicates overcurrent fault on high-side of half-bridge OUT6. 4 OUT5_HS_OCP R 0h Indicates overcurrent fault on high-side of half-bridge OUT5. 3 OUT4_HS_OCP R 0h Indicates overcurrent fault on high-side of half-bridge OUT4. 2 OUT3_HS_OCP R 0h Indicates overcurrent fault on high-side of half-bridge OUT3. 1 OUT2_HS_OCP R 0h Indicates overcurrent fault on high-side of half-bridge OUT2. 0 OUT1_HS_OCP R 0h Indicates overcurrent fault on high-side of half-bridge OUT1. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: DRV8001-Q1

8.1.4 HB_STAT2 Register (Offset = 4h) [Reset = 0000h]

HB_STAT2 is shown in Table 8-8. Return to the Summary Table. Half-bridge active and off-state open load faults. Table 8-8. HB_STAT2 Register Field Descriptions Bit Field Type Reset Description

13 RESERVED R 0h Reserved

12 HB_OLP_STAT R 0h Indicates integrated half-bridge OLP status. 11 OUT6_LS_OLA R 0h Indicates active open load fault on low-side of half-bridge OUT6. 10 OUT5_LS_OLA R 0h Indicates active open load fault on low-side of half-bridge OUT5. 9 OUT4_LS_OLA R 0h Indicates active open load fault on low-side of half-bridge OUT4. 8 OUT3_LS_OLA R 0h Indicates active open load fault on low-side of half-bridge OUT3. 7 OUT2_LS_OLA R 0h Indicates active open load fault on low-side of half-bridge OUT2. 6 OUT1_LS_OLA R 0h Indicates active open load fault on low-side of half-bridge OUT1. 5 OUT6_HS_OLA R 0h Indicates active open load fault on high-side of half-bridge OUT6. 4 OUT5_HS_OLA R 0h Indicates active open load fault on high-side of half-bridge OUT5. 3 OUT4_HS_OLA R 0h Indicates active open load fault on high-side of half-bridge OUT4. 2 OUT3_HS_OLA R 0h Indicates active open load fault on high-side of half-bridge OUT3. 1 OUT2_HS_OLA R 0h Indicates active open load fault on high-side of half-bridge OUT2. 0 OUT1_HS_OLA R 0h Indicates active open load fault on high-side of half-bridge OUT1. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.1.5 EC_HEAT_ITRIP_STAT Register (Offset = 5h) [Reset = 0000h]

EC_HEAT_ITRIP_STAT is shown in Table 8-9. Return to the Summary Table. Includes all electrochrome and heater driver faults and warnings. Also includes ITRIP regulation status warnings. Table 8-9. EC_HEAT_ITRIP_STAT Register Field Descriptions Bit Field Type Reset Description 15 ECFB_DIAG_STAT R 0h Indicates ECFB_SC fault is present when ECFB_DIAG=0x01. Indicates ECFB OLP fault when ECFB_DIAG=10b. 14 ECFB_OV R 0h Indicates overvoltage (short to battery) fault on ECFB pin. 13 ECFB_HI R 0h Indicates regulation overvoltage fault on ECFB pin. 12 ECFB_LO R 0h Indicates regulation undervoltage fault on ECFB pin. 11 ECFB_OC R 0h Indicates overcurrent fault on ECFB pin. 10 ECFB_OL R 0h Indicates open load fault on ECFB pin. 9 HEAT_OL R 0h Indicates open load fault on SH_HS pin. 8 HEAT_VDS R 0h Indicates overcurrent fault on heater MOSFET. 6 OUT7_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT7. 5 OUT6_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT6. 4 OUT5_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT5. 3 OUT4_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT4. 2 OUT3_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT3. 1 OUT2_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT2. 0 OUT1_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT1. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: DRV8001-Q1

8.1.6 HS_STAT Register (Offset = 6h) [Reset = 0000h]

HS_STAT is shown in Table 8-10. Return to the Summary Table. High-side driver overcurrent and open load fault status. Table 8-10. HS_STAT Register Field Descriptions Bit Field Type Reset Description 13 OUT12_OLA R 0h Indicates open load fault on OUT12. 12 OUT11_OLA R 0h Indicates open load fault on OUT11. 11 OUT10_OLA R 0h Indicates open load fault on OUT10. 10 OUT9_OLA R 0h Indicates open load fault on OUT9. 9 OUT8_OLA R 0h Indicates open load fault on OUT8. 8 OUT7_OLA R 0h Indicates open load fault on OUT7. 5 OUT12_OCP R 0h Indicates overcurrent fault on OUT12. 4 OUT11_OCP R 0h Indicates overcurrent fault on OUT11. 3 OUT10_OCP R 0h Indicates overcurrent fault on OUT10. 2 OUT9_OCP R 0h Indicates overcurrent fault on OUT9. 1 OUT8_OCP R 0h Indicates overcurrent fault on OUT8. 0 OUT7_OCP R 0h Indicates overcurrent fault on OUT7. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.1.7 HS_ITRIP_STAT Register (Offset = 7h) [Reset = 0000h]

HS_ITRIP_STAT is shown in Table 8-11. Return to the Summary Table. Includes electrochrome and High-side ITRIP status register. Table 8-11. HS_ITRIP_STAT Register Field Descriptions Bit Field Type Reset Description

10 RESERVED R 0h Reserved

9 RESERVED R 0h Reserved

8 RESERVED R 0h Reserved

6 ECFB_LS_ITRIP_STAT R 0h Indicates if ECFB_LS_ITRIP has occurred. Cleared only with CLR_FLT.

5 RESERVED R 0h Reserved

4 OUT12_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT12. 3 OUT11_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT11. 2 OUT10_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT10. 1 OUT9_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT9. 0 OUT8_ITRIP_STAT R 0h Indicates ITRIP regulation warning on OUT8. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: DRV8001-Q1

8.1.8 SPARE_STAT2 Register (Offset = 8h) [Reset = 0000h]

SPARE_STAT2 is shown in Table 8-12. Return to the Summary Table. Spare status register. Table 8-12. SPARE_STAT2 Register Field Descriptions Bit Field Type Reset Description 7-0 DEV_ID R 0h 0x02= DRV8000 0x21= DRV8001 0x22= DRV8002 DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2 DRV8000-Q1_CNFG Registers

Table 8-13 lists the memory-mapped registers for the DRV8000-Q1_CNFG registers. All register offset addresses not listed in Table 8-13 should be considered as reserved locations and the register contents should not be modified. Table 8-13. DRV8000-Q1_CNFG Registers Offset Acronym Register Name Section 9h IC_CNFG1 IC configuration register 1. Section 8.2.1 Ah IC_CNFG2 IC configuration register 2. Section 8.2.2 14h HB_ITRIP_DG Half-bridge ITRIP deglitch configuration register 2. Section 8.2.3 15h HB_OUT_CNFG1 Half-bridge output 5 and 6 configuration register. Section 8.2.4 16h HB_OUT_CNFG2 Half-bridge output 1-4 configuration register. Section 8.2.5 17h HB_OCP_CNFG Half-bridge overcurrent deglitch configuration register. Section 8.2.6 18h HB_OL_CNFG1 Half-bridge active and passive open-load enable register Section 8.2.7 19h HB_OL_CNFG2 Half-bridge active open-load threshold select register. Section 8.2.8 1Ah HB_SR_CNFG Half-bridge slew rate configuration register. Section 8.2.9 1Bh HB_ITRIP_CNFG Half-bridge ITRIP configuration register 1. Section 8.2.10 1Ch HB_ITRIP_FREQ Half-bridge ITRIP frequency configuration register 2. Section 8.2.11 1Dh HS_HEAT_OUT_CNFG High-side and heater driver output configuration register. Section 8.2.12 1Eh HS_OC_CNFG High-side driver overcurrent threshold configuration register. Section 8.2.13 1Fh HS_OL_CNFG High-side driver open load threshold configuration register. Section 8.2.14 20h HS_REG_CNFG1 High-side driver regulation configuration register. Section 8.2.15 21h HS_REG_CNFG2 High-side driver regulation configuration register. Section 8.2.16 22h HS_PWM_FREQ_CNFG High-side driver PWM generator frequency configuration register. Section 8.2.17 23h HEAT_CNFG Heater configuration register. Section 8.2.18 24h EC_CNFG Electrochrome configuration register. Section 8.2.19 25h HS_REG_CNFG3 High-side driver regulation configuration register. Section 8.2.20 26h SPARE_CNFG2 Spare configuration Section 8.2.21 27h OUT1_HS_MODE_DC Duty cycle configuration for OUT1. Section 8.2.22 28h OUT2_HS_MODE_DC Duty cycle configuration for OUT2. Section 8.2.23 Complex bit access types are encoded to fit into small table cells. Table 8-14 shows the codes that are used for access types in this section. Table 8-14. DRV8000-Q1_CNFG Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: DRV8001-Q1

8.2.1 IC_CNFG1 Register (Offset = 9h) [Reset = 0002h]

IC_CNFG1 is shown in Table 8-15. Return to the Summary Table. Includes configurations charge pump and watchdog, and fault levels and reactions for supply, charge pump, thermal, and watch dog faults. Table 8-15. IC_CNFG1 Register Field Descriptions Bit Field Type Reset Description 15 OTSD_MODE R/W 0h Sets overtemperature shutdown behavior. If any thermal cluster reaches OT, the device shuts down all drivers or affected drivers only (drivers in zone 3, for example). 0b = Global shutdown. 1b = Affected driver shutdown only.

14 RESERVED R/W 0h Reserved

13 RSVD R 0h Reserved. 12 PVDD_OV_MODE R/W 0h PVDD supply overvoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery. 11-10 PVDD_OV_DG R/W 0h PVDD supply overvoltage monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs 9 PVDD_OV_LVL R/W 0h PVDD supply overvoltage monitor threshold. 0b = 22 V 1b = 28 V

8 RESERVED R/W 0h Reserved

7-6 CP_MODE R/W 0h Charge pump operating mode. 00b = Automatic switch between tripler and doubler mode. 01b = Always doubler mode. 10b = Always tripler mode. 11b = RSVD 5 VCP_UV_MODE R/W 0h VCP charge pump undervoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery. 4 PVDD_UV_MODE R/W 0h PVDD supply undervoltage monitor mode. 0b = Latched fault. 1b = Automatic recovery. 3 WD_EN R/W 0h Watchdog timer enable. 0b = Watchdog timer disabled. 1b = Watchdog timer enabled. 2 WD_FLT_M R/W 0h Watchdog fault mode. Watchdog fault is cleared by CLR_FLT. 0b = Watchdog fault is reported to WD_FLT and WARN register bits. Drivers remain enabled and FAULT bit is not asserted. 1b = Watchdog fault is reported to WD_FLT and FAULT register bits. All drivers are disabled in response to watchdog fault. 1 WD_WIN R/W 1h Watchdog timer window. 0b = 4 to 12 ms 1b = 10 to 100 ms 0 EN_SSC R/W 0h Spread spectrum clocking. 0b = Disabled. 1b = Enabled. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.2 IC_CNFG2 Register (Offset = Ah) [Reset = 0000h]

IC_CNFG2 is shown in Table 8-16. Return to the Summary Table. Includes thermal cluster warning disable bits. Table 8-16. IC_CNFG2 Register Field Descriptions Bit Field Type Reset Description

15 RESERVED R/W 0h Reserved

13 RESERVED R/W 0h Reserved

12 RESERVED R/W 0h Reserved

11 RESERVED R/W 0h Reserved

10 RESERVED R/W 0h Reserved

9 RESERVED R/W 0h Reserved

7 ZONE4_OTW_H_DIS R/W 0h Disables the high overtemperature warning for zone 4. Enabled = 0b Disabled = 1b 6 ZONE3_OTW_H_DIS R/W 0h Disables the high overtemperature warning for zone 3. Enabled = 0b Disabled = 1b 5 ZONE2_OTW_H_DIS R/W 0h Disables the high overtemperature warning for zone 2. Enabled = 0b Disabled = 1b 4 ZONE1_OTW_H_DIS R/W 0h Disables the high overtemperature warning for zone 1. Enabled = 0b Disabled = 1b 3 ZONE4_OTW_L_DIS R/W 0h Disables the low overtemperature warning for zone 4. Enabled = 0b Disabled = 1b 2 ZONE3_OTW_L_DIS R/W 0h Disables the low overtemperature warning for zone 3. Enabled = 0b Disabled = 1b 1 ZONE2_OTW_L_DIS R/W 0h Disables the low overtemperature warning for zone 2. Enabled = 0b Disabled = 1b 0 ZONE1_OTW_L_DIS R/W 0h Disables the low overtemperature warning for zone 1. Enabled = 0b Disabled = 1b www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: DRV8001-Q1

8.2.3 HB_ITRIP_DG Register (Offset = 14h) [Reset = 0000h]

HB_ITRIP_DG is shown in Table 8-17. Return to the Summary Table. Configures ITRIP deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs. Table 8-17. HB_ITRIP_DG Register Field Descriptions Bit Field Type Reset Description 11-10 OUT6_ITRIP_DG R/W 0h Configures ITRIP deglitch time for half-bridge 6. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs 9-8 OUT5_ITRIP_DG R/W 0h Configures ITRIP deglitch time for half-bridge 5. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs 7-6 OUT4_ITRIP_DG R/W 0h Configures ITRIP deglitch time for half-bridge 4. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs 5-4 OUT3_ITRIP_DG R/W 0h Configures ITRIP deglitch time for half-bridge 3. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs 3-2 OUT2_ITRIP_DG R/W 0h Configures ITRIP deglitch time for half-bridge 2. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs 1-0 OUT1_ITRIP_DG R/W 0h Configures ITRIP deglitch time for half-bridge 1. 00b = 2 µs 01b = 5 µs 10b = 10 µs 11b = 20 µs DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.4 HB_OUT_CNFG1 Register (Offset = 15h) [Reset = 0000h]

HB_OUT_CNFG1 is shown in Table 8-18. Return to the Summary Table. Configures the output mode for each half-bridge, sets IPROPI sample and hold circuit, and half-bridge pair freewheeling. Table 8-18. HB_OUT_CNFG1 Register Field Descriptions Bit Field Type Reset Description

14 NSR_OUT6_DIS R/W 0h Disables non-synchronous rectification during ITRIP regulation (sets

active freewheeling) for half-bridge 6. Passive freewheeling = 0b Active freewheeling = 1b

13 NSR_OUT5_DIS R/W 0h Disables non-synchronous rectification during ITRIP regulation (sets

active freewheeling) for half-bridge 5. Passive freewheeling = 0b Active freewheeling = 1b

12 NSR_OUT4_DIS R/W 0h Disables non-synchronous rectification during ITRIP regulation (sets

active freewheeling) for half-bridge 4. Passive freewheeling = 0b Active freewheeling = 1b

11 NSR_OUT3_DIS R/W 0h Disables non-synchronous rectification during ITRIP regulation (sets

active freewheeling) for half-bridges 3. Passive freewheeling = 0b Active freewheeling = 1b

10 NSR_OUT2_DIS R/W 0h Disables non-synchronous rectification during ITRIP regulation (sets

active freewheeling) for half-bridge 2. Passive freewheeling = 0b Active freewheeling = 1b

9 NSR_OUT1_DIS R/W 0h Disables non-synchronous rectification during ITRIP regulation (sets

active freewheeling) for half-bridge 1. Passive freewheeling = 0b Active freewheeling = 1b 8 IPROPI_SH_EN R/W 0h Enables IPROPI sample and hold circuit.

7 RESERVED R/W 0h Reserved

6 RESERVED R/W 0h Reserved

5-3 OUT6_CNFG R/W 0h Configuration for half-bridge 6. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control 2-0 OUT5_CNFG R/W 0h Configuration for half-bridge 5. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: DRV8001-Q1

8.2.5 HB_OUT_CNFG2 Register (Offset = 16h) [Reset = 0000h]

HB_OUT_CNFG2 is shown in Table 8-19. Return to the Summary Table. Configures the output mode for each half-bridge. Table 8-19. HB_OUT_CNFG2 Register Field Descriptions Bit Field Type Reset Description 13-11 OUT4_CNFG R/W 0h Configuration for half-bridge 4. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control 10-8 OUT3_CNFG R/W 0h Configuration for half-bridge 3. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control 7 OUT2_MODE R/W 0h Bit to enable OUT2 as High Side driver with internal PWM. OUT2_CNFG used for enabling and disabling the driver PWM settings - Freq: PWM_OUT2_FREQ, DC: OUT2_DC. 6 OUT1_MODE R/W 0h Bit to enable OUT1 as High Side driver with internal PWM. OUT1_CNFG used for enabling and disabling the driver PWM settings - Freq: PWM_OUT1_FREQ, DC: OUT1_DC. 5-3 OUT2_CNFG R/W 0h Configuration for half-bridge 2. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control 2-0 OUT1_CNFG R/W 0h Configuration for half-bridge 1. Enables or disables control of half-bridge, and sets control mode between PWM or SPI. 000b = Disabled 001b = Enabled (SPI register control) 010b = PWM1 Complementary Control 011b = PWM1 LS Control 100b = PWM1 HS Control 101b = PWM2 Complementary Control 110b = PWM2 LS Control 111b = PWM2 HS Control DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.6 HB_OCP_CNFG Register (Offset = 17h) [Reset = 0000h]

HB_OCP_CNFG is shown in Table 8-20. Return to the Summary Table. Overcurrent deglitch for half-bridges configuration register. Table 8-20. HB_OCP_CNFG Register Field Descriptions Bit Field Type Reset Description 11-10 OUT6_OCP_DG R/W 0h Overcurrent deglitch time for half-bridge 6. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs 9-8 OUT5_OCP_DG R/W 0h Overcurrent deglitch time for half-bridge 5. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs 7-6 OUT4_OCP_DG R/W 0h Overcurrent deglitch time for half-bridge 4. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs 5-4 OUT3_OCP_DG R/W 0h Overcurrent deglitch time for half-bridge 3. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs 3-2 OUT2_OCP_DG R/W 0h Overcurrent deglitch time for half-bridge 2. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs 1-0 OUT1_OCP_DG R/W 0h Overcurrent deglitch time for half-bridge 1. 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: DRV8001-Q1

8.2.7 HB_OL_CNFG1 Register (Offset = 18h) [Reset = 0000h]

HB_OL_CNFG1 is shown in Table 8-21. Return to the Summary Table. Configures active and off-state open load detection circuits for half-bridges. Table 8-21. HB_OL_CNFG1 Register Field Descriptions Bit Field Type Reset Description 13-12 HB_OLP_CNFG R/W 0h Off-state diagnostics configuration. 00b = Off-state disabled 01b = OUT X Pullup enabled, OUT Y pulldown enabled, OUT Y selected, VREF Low 10b = OUT X Pullup enabled, OUT Y pulldown enabled, OUT X selected, VREF High 11b = OUT X Pulldown enabled, OUT Y pullup enabled, OUT Y selected, VREF Low 11-8 HB_OLP_SEL R/W 0h Off-state open load diagnostics enable for half-bridges. 0000b = Disabled 0001b = OUT1 and OUT2 0010b = OUT1 and OUT3 0011b = OUT1 and OUT4 0100b = OUT1 and OUT5 0101b = OUT1 and OUT6 0110b = OUT2 and OUT3 0111b = OUT2 and OUT4 1000b = OUT2 and OUT5 1001b = OUT2 and OUT6 1010b = OUT3 and OUT4 1011b = OUT3 and OUT5 1100b = OUT3 and OUT6 1101b = OUT4 and OUT5 1110b = OUT4 and OUT6 1111b = OUT5 and OUT6 5 OUT6_OLA_EN R/W 0h Active open load diagnostics enable for half-bridge 6. 0b = Disabled 1b = Enabled 4 OUT5_OLA_EN R/W 0h Active open load diagnostics enable for half-bridge 5. 0b = Disabled 1b = Enabled 3 OUT4_OLA_EN R/W 0h Active open load diagnostics enable for half-bridge 4. 0b = Disabled 1b = Enabled 2 OUT3_OLA_EN R/W 0h Active open load diagnostics enable for half-bridge 3. 0b = Disabled 1b = Enabled 1 OUT2_OLA_EN R/W 0h Active open load diagnostics enable for half-bridge 2. 0b = Disabled 1b = Enabled 0 OUT1_OLA_EN R/W 0h Active open load diagnostics enable for half-bridge 1. 0b = Disabled 1b = Enabled DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.8 HB_OL_CNFG2 Register (Offset = 19h) [Reset = 0000h]

HB_OL_CNFG2 is shown in Table 8-22. Return to the Summary Table. Configures cycle count threshold for active open load detection circuits of half-bridges. Table 8-22. HB_OL_CNFG2 Register Field Descriptions Bit Field Type Reset Description 11-10 OUT6_OLA_TH R/W 0h Sets the half-bridge 6 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles 9-8 OUT5_OLA_TH R/W 0h Sets the half-bridge 5 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles 7-6 OUT4_OLA_TH R/W 0h Sets the half-bridge 4 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles 5-4 OUT3_OLA_TH R/W 0h Sets the half-bridge 3 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles 3-2 OUT2_OLA_TH R/W 0h Sets the half-bridge 2 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles 1-0 OUT1_OLA_TH R/W 0h Sets the half-bridge 1 active open load cycle count threshold. 0b = 32 cycles 1b = 128 cycles 10b - 512 cycles 11b - 1024 cycles www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: DRV8001-Q1

8.2.9 HB_SR_CNFG Register (Offset = 1Ah) [Reset = 0000h]

HB_SR_CNFG is shown in Table 8-23. Return to the Summary Table. Configures slew rate timing for each half-bridge. Table 8-23. HB_SR_CNFG Register Field Descriptions Bit Field Type Reset Description 11-10 OUT6_SR R/W 0h Configures slew rate for half-bridge 6. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs 9-8 OUT5_SR R/W 0h Configures slew rate for half-bridge 5. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs 7-6 OUT4_SR R/W 0h Configures slew rate for half-bridge 4. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs 5-4 OUT3_SR R/W 0h Configures slew rate for half-bridge 3. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs 3-2 OUT2_SR R/W 0h Configures slew rate for half-bridge 2. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs 1-0 OUT1_SR R/W 0h Configures slew rate for half-bridge 1. 00b = 1.6 V/µs 01b = 13.5 V/µs 10b = 24 V/µs DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.10 HB_ITRIP_CNFG Register (Offset = 1Bh) [Reset = 0000h]

HB_ITRIP_CNFG is shown in Table 8-24. Return to the Summary Table. Configures ITRIP levels and enables ITRIP for each half-bridge. ITRIP levels are shared between half-bridge pairs. Table 8-24. HB_ITRIP_CNFG Register Field Descriptions Bit Field Type Reset Description 15 OUT6_ITRIP_EN R/W 0h Enables ITRIP regulation for half-bridge 6. 14 OUT5_ITRIP_EN R/W 0h Enables ITRIP regulation for half-bridge 5. 13 OUT4_ITRIP_EN R/W 0h Enables ITRIP regulation for half-bridge 4. 12 OUT3_ITRIP_EN R/W 0h Enables ITRIP regulation for half-bridge 3. 11 OUT2_ITRIP_EN R/W 0h Enables ITRIP regulation for half-bridge 2. 10 OUT1_ITRIP_EN R/W 0h Enables ITRIP regulation for half-bridge 1. 9-8 OUT6_ITRIP_LVL R/W 0h Configures ITRIP current threshold level for half-bridge 6. 00b = 2.3 A. 01b = 5.4 A 10b = 6.2 A 11b = Reserved. 7-6 OUT5_ITRIP_LVL R/W 0h Configures ITRIP current threshold level for half-bridge 5. 00b = 2.9 A 01b = 6.6 A 10b = 7.6 A 11b = Reserved. 5-4 OUT4_ITRIP_LVL R/W 0h Configures ITRIP current threshold level for half-bridge 4. 00b = 1.3 A 01b = 2.5 A 10b = 3.4 A 11b = Reserved. 3-2 OUT3_ITRIP_LVL R/W 0h Configures ITRIP current threshold level for half-bridge 3. 00b = 1.3 A 01b = 2.5 A 10b = 3.4 A 11b = Reserved. 1 OUT2_ITRIP_LVL R/W 0h Configures ITRIP current threshold level for half-bridge 2. 0b = 0.7 A 1b = 0.875 A 0 OUT1_ITRIP_LVL R/W 0h Configures ITRIP current threshold level for half-bridge 1. 0b = 0.7 A 1b = 0.875 A www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: DRV8001-Q1

8.2.11 HB_ITRIP_FREQ Register (Offset = 1Ch) [Reset = 0000h]

HB_ITRIP_FREQ is shown in Table 8-25. Return to the Summary Table. Configures ITRIP frequency and deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs. Table 8-25. HB_ITRIP_FREQ Register Field Descriptions Bit Field Type Reset Description 13-12 HB_TOFF_SEL R/W 0h Toff selection for OUT1-6 half bridge drivers. Here T is decided by OUTx_ITRIP_FREQ. 00b - Zero, disabled 01b - Toff = T/2 10b - Toff=T/4 11b - Toff=T 11-10 OUT6_ITRIP_FREQ R/W 0h Configures ITRIP regulation frequency for half-bridge 6. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz 9-8 OUT5_ITRIP_FREQ R/W 0h Configures ITRIP regulation frequency for half-bridge 5. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz 7-6 OUT4_ITRIP_FREQ R/W 0h Configures ITRIP regulation frequency for half-bridge 4. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz 5-4 OUT3_ITRIP_FREQ R/W 0h Configures ITRIP regulation frequency for half-bridge 3. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz 3-2 OUT2_ITRIP_FREQ/ PWM_OUT2_FREQ R/W 0h Configures ITRIP regulation frequency for half-bridge 2. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz When OUT2_MODE = 1. Used for PWM FREQ settings PWM_OUT2_FREQ: 00b - 108Hz 01b - 217Hz 10b - 289Hz 11b - 434Hz 1-0 OUT1_ITRIP_FREQ/ PWM_OUT1_FREQ R/W 0h Configures ITRIP regulation frequency for half-bridge 1. 00b = 20 kHz 01b = 10 kHz 10b = 5 kHz 11b = 2.5 kHz When OUT1_MODE = 1. Used for PWM FREQ settings PWM_OUT1_FREQ: 00b - 108Hz 01b - 217Hz 10b - 289Hz 11b - 434Hz DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.12 HS_HEAT_OUT_CNFG Register (Offset = 1Dh) [Reset = 0000h]

HS_HEAT_OUT_CNFG is shown in Table 8-26. Return to the Summary Table. Configures the output mode for each high-side driver and heater. Table 8-26. HS_HEAT_OUT_CNFG Register Field Descriptions Bit Field Type Reset Description 15-14 HEAT_CNFG R/W 0h Configuration for heater driver. Enables or disables control of heater, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM1 pin control 11b = Reserved 11-10 OUT12_CNFG R/W 0h Configuration for high-side driver 12. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator 9-8 OUT11_CNFG R/W 0h Configuration for high-side driver 11. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator 7-6 OUT10_CNFG R/W 0h Configuration for high-side driver 10. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator 5-4 OUT9_CNFG R/W 0h Configuration for high-side driver 9. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator 3-2 OUT8_CNFG R/W 0h Configuration for high-side driver 8. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator 1-0 OUT7_CNFG R/W 0h Configuration for high-side driver 7. Enables or disables control of high-side driver, and sets control mode between PWM or SPI. 00b = Disabled 01b = SPI control enabled 10b = PWM pin control 11b = PWM Generator www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: DRV8001-Q1

8.2.13 HS_OC_CNFG Register (Offset = 1Eh) [Reset = 1000h]

HS_OC_CNFG is shown in Table 8-27. Return to the Summary Table. Configures overcurrent threshold for each high-side driver. Table 8-27. HS_OC_CNFG Register Field Descriptions Bit Field Type Reset Description

12 OUT11_EC_MODE R/W 1h Bit sets high-side OUT11 for independent control through

OUT11_CNFG bits or for supply for Electrochromic dirver. 0b = OUT11 is configured as independent high-side driver. Drain of EC FET is connected to PVDD 1b = OUT11 is configured as supply for EC FET

5 OUT12_OC_TH R/W 0h Configures overcurrent threshold between high or low for high-side

driver 12. 0b = Low current threshold 1b = High current threshold

4 OUT11_OC_TH R/W 0h Configures overcurrent threshold between high or low for high-side

driver 11. 0b = Low current threshold 1b = High current threshold

3 OUT10_OC_TH R/W 0h Configures overcurrent threshold between high or low for high-side

driver 10. 0b = Low current threshold 1b = High current threshold

2 OUT9_OC_TH R/W 0h Configures overcurrent threshold between high or low for high-side

driver 9. 0b = Low current threshold 1b = High current threshold

1 OUT8_OC_TH R/W 0h Configures overcurrent threshold between high or low for high-side

driver 8. 0b = Low current threshold 1b = High current threshold

0 OUT7_RDSON_MODE R/W 0h Configures high-side driver 7 between high RDSON mode and low

RDSON mode (for bulb/lamp load). 0b = High RDSON mode (LED driver mode) 1b = Low RDSON mode (bulb/lamp driver mode) DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.14 HS_OL_CNFG Register (Offset = 1Fh) [Reset = 0000h]

HS_OL_CNFG is shown in Table 8-28. Return to the Summary Table. Configures open load threshold for each high-side driver. Table 8-28. HS_OL_CNFG Register Field Descriptions Bit Field Type Reset Description 13 OUT12_OLA_TH R/W 0h Configures high-side driver 12 open load threshold. 0b = Low threshold 1b = High threshold 12 OUT11_OLA_TH R/W 0h Configures high-side driver 11 open load threshold. 0b = Low threshold 1b = High threshold 11 OUT10_OLA_TH R/W 0h Configures high-side driver 10 open load threshold. 0b = Low threshold 1b = High threshold 10 OUT9_OLA_TH R/W 0h Configures high-side driver 9 open load threshold. 0b = Low threshold 1b = High threshold 9 OUT8_OLA_TH R/W 0h Configures high-side driver 8 open load threshold. 0b = Low threshold 1b = High threshold 5 OUT12_OLA_EN R/W 0h Enables open load detection circuit for high-side driver 12. 4 OUT11_OLA_EN R/W 0h Enables open load detection circuit for high-side driver 11. 3 OUT10_OLA_EN R/W 0h Enables open load detection circuit for high-side driver 10. 2 OUT9_OLA_EN R/W 0h Enables open load detection circuit for high-side driver 9. 1 OUT8_OLA_EN R/W 0h Enables open load detection circuit for high-side driver 8. 0 OUT7_OLA_EN R/W 0h Enables open load detection circuit for high-side driver 7. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: DRV8001-Q1

8.2.15 HS_REG_CNFG1 Register (Offset = 20h) [Reset = 0000h]

HS_REG_CNFG1 is shown in Table 8-29. Return to the Summary Table. Configures OUT7 ITRIP settings. Table 8-29. HS_REG_CNFG1 Register Field Descriptions Bit Field Type Reset Description 7 OUT7_ITRIP_EN R/W 0h Enables ITRIP for high-side driver 7.

5 RESERVED R/W 0h Reserved

4 RESERVED R/W 0h Reserved

3-2 OUT7_ITRIP_FREQ R/W 0h Configures OUT7 ITRIP regulation frequency. 00b = 1.7 kHz 01b = 2.2 kHz 10b = 3 kHz 11b = 4.4 kHz 1-0 OUT7_ITRIP_DG R/W 0h Configures OUT7 ITRIP deglitch time. 00b = 48 µs 01b = 40 µs 10b = 32 µs 11b = 24 µs DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.16 HS_REG_CNFG2 Register (Offset = 21h) [Reset = 0000h]

HS_REG_CNFG2 is shown in Table 8-30. Return to the Summary Table. Configures constant current mode for each high-side driver. Table 8-30. HS_REG_CNFG2 Register Field Descriptions Bit Field Type Reset Description

13 OUT12_CCM_TO R/W 0h Configures the constant current mode current limit option of high-

side output 12. 0b = 350 mA 1b = 450 mA

12 OUT11_CCM_TO R/W 0h Configures the constant current mode current limit option of high-

side output 11. 0b = 350 mA 1b = 450 mA

11 OUT10_CCM_TO R/W 0h Configures the constant current mode current limit option of high-

side output 10. 0b = 350 mA 1b = 450 mA

10 OUT9_CCM_TO R/W 0h Configures the constant current mode current limit option of high-

side output 9. 0b = 350 mA 1b = 450 mA

9 OUT8_CCM_TO R/W 0h Configures the constant current mode current limit option of high-

side output 8. 0b = 350 mA 1b = 450 mA

8 OUT7_CCM_TO R/W 0h Configures the constant current mode current limit option of high-

side output 7. CCM values are based on OUT7_RDSON_MODE. If OUT7_RDSON_MODE = 0b: 0b = 250 mA 1b = 330 mA IF OUT7_RDSON_MODE = 1b: 0b = 360 mA 1b = 450 mA 5 OUT12_CCM_EN R/W 0h Enables constant current mode circuit for high-side driver 12. 4 OUT11_CCM_EN R/W 0h Enables constant current mode circuit for high-side driver 11. 3 OUT10_CCM_EN R/W 0h Enables constant current mode circuit for high-side driver 10. 2 OUT9_CCM_EN R/W 0h Enables constant current mode circuit for high-side driver 9. 1 OUT8_CCM_EN R/W 0h Enables constant current mode circuit for high-side driver 8. 0 OUT7_CCM_EN R/W 0h Enables constant current mode circuit for high-side driver 7. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: DRV8001-Q1

8.2.17 HS_PWM_FREQ_CNFG Register (Offset = 22h) [Reset = 0000h]

HS_PWM_FREQ_CNFG is shown in Table 8-31. Return to the Summary Table. Configures the frequency for each dedicated PWM generator. Table 8-31. HS_PWM_FREQ_CNFG Register Field Descriptions Bit Field Type Reset Description 11-10 PWM_OUT12_FREQ R/W 0h Configures frequency output of dedicated PWM generator for high- side driver 12. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz 9-8 PWM_OUT11_FREQ R/W 0h Configures frequency output of dedicated PWM generator for high- side driver 11. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz 7-6 PWM_OUT10_FREQ R/W 0h Configures frequency output of dedicated PWM generator for high- side driver 10. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz 5-4 PWM_OUT9_FREQ R/W 0h Configures frequency output of dedicated PWM generator for high- side driver 9. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz 3-2 PWM_OUT8_FREQ R/W 0h Configures frequency output of dedicated PWM generator for high- side driver 8. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz 1-0 PWM_OUT7_FREQ R/W 0h Configures frequency output of dedicated PWM generator for high- side driver 7. 00b = 108 Hz 01b = 217 Hz 10b = 289 Hz 11b = 434 Hz DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.18 HEAT_CNFG Register (Offset = 23h) [Reset = 0A3Ch]

HEAT_CNFG is shown in Table 8-32. Return to the Summary Table. Configures heater driver and fault responses. Table 8-32. HEAT_CNFG Register Field Descriptions Bit Field Type Reset Description 11-8 HEAT_VDS_LVL R/W Ah Heater MOSFET VDS monitor protection threshold. 0000b = 0.06 V 00001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.24 V 1001b = 0.28 V 1010b = 0.32 V 1011b = 0.36 V 1100b = 0.4 V 1101b = 0.44 V 1110b = 0.56 V 1111b = 1 V 7-6 HEAT_VDS_MODE R/W 0h Heater MOSFET VDS overcurrent monitor fault mode. 00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled. 5-4 HEAT_VDS_BLK R/W 3h Heater MOSFET VDS monitor blanking time. 00b = 4 µs 01b = 8 µs 10b = 16 µs 11b = 32 µs 3-2 HEAT_VDS_DG R/W 3h Heater MOSFET VDS overcurrent monitor deglitch time. 00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs 1 HEAT_OLP_EN R/W 0h Enables heater offline open load detection circuit.

0 RESERVED R/W 0h Reserved

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8.2.19 EC_CNFG Register (Offset = 24h) [Reset = 0000h]

EC_CNFG is shown in Table 8-33. Return to the Summary Table. Configures electrochrome driver and fault responses. Table 8-33. EC_CNFG Register Field Descriptions Bit Field Type Reset Description 15-14 ECFB_DIAG R/W 0h Enables open-load detection circuit on ECFB. 00b = disable 01b = SC 10b = OLP 11b = disable/reserved 13-12 EC_OUT11_OCP_DG R/W 0h OUT11 OCP Deglitch setting when EC_MODE=1 00b = 6 µs 01b = 10 µs 10b = 15 µs 11b = 60 µs 11-10 ECFB_SC_RSEL R/W 0h ECFB Diagnostic short-circuit detection options. 00b = 0.5 Ω 01b = 1.0 Ω 10b = 2.0 Ω 11b = 3.0 Ω 9-8 ECFB_OV_DG R/W 0h Configures overvoltage fault deglitch time. 00b = 20 µs 01b = 50 µs 10b = 100 µs 11b = 200 µs 5-4 ECFB_OV_MODE R/W 0h Configures ECFB OV fault response for EC driver. 0b = No action 01b = Report ECFB_OV if voltage > 3V longer than EFB_OV_DG time. 10b = Report ECFB_OV if voltage > 3V longer than EFB_OV_DG time, drive ECDRV low with pulldown. 3 EC_FLT_MODE R/W 0h Configures overcurrent fault response for EC driver. 0b = Hi-Z EC Driver 1b = Retry with OUT7 ITRIP settings 2 ECFB_LS_PWM R/W 0h Enables LS PWM discharge for EC load. 0b = No PWM discharge (Fast discharge) 1b = PWM discharge enabled 1 EC_OLEN R/W 0h This bit enables the open load detection circuit during EC discharge. 0b = Open load detection disabled during EC discharge 1b = Open load detection enabled during EC discharge 0 ECFB_MAX R/W 0h Configures the maximum target voltage for EC. 0b = 1.2 V 1b = 1.5 V DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.2.20 HS_REG_CNFG3 Register (Offset = 25h) [Reset = 0000h]

HS_REG_CNFG3 is shown in Table 8-34. Return to the Summary Table. Configures HS ITRIP settings. Table 8-34. HS_REG_CNFG3 Register Field Descriptions Bit Field Type Reset Description 11-10 HS_OUT_ITRIP_FREQ R/W 0h ITRIP FREQ settings for OUT8-12 00b - 1.7KHz 01b - 2.2KHz 10b - 3KHz 11b - 4.4KHz 9-8 HS_OUT_ITRIP_DG R/W 0h Common ITRIP deglitch settings for OUT8-12 drivers 00b - 48 µs 01b - 40 µs 10b - 32 µs 11b - 24 µs 4 HS_OUT12_ITRIP_EN R/W 0h Enables ITRIP for high-side driver 12. 3 HS_OUT11_ITRIP_EN R/W 0h Enables ITRIP for high-side driver 11. 2 HS_OUT10_ITRIP_EN R/W 0h Enables ITRIP for high-side driver 10. 1 HS_OUT9_ITRIP_EN R/W 0h Enables ITRIP for high-side driver 9. 0 HS_OUT8_ITRIP_EN R/W 0h Enables ITRIP for high-side driver 8. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: DRV8001-Q1

8.2.21 SPARE_CNFG2 Register (Offset = 26h) [Reset = 0000h]

SPARE_CNFG2 is shown in Table 8-35. Return to the Summary Table. Spare configuration register. Table 8-35. SPARE_CNFG2 Register Field Descriptions Bit Field Type Reset Description

3 RESERVED R/W 0h Reserved

2 RESERVED R/W 0h Reserved

1 RESERVED R/W 0h Reserved

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8.2.22 OUT1_HS_MODE_DC Register (Offset = 27h) [Reset = 0000h]

OUT1_HS_MODE_DC is shown in Table 8-36. Return to the Summary Table. Configures 10 bits for duty cycle Table 8-36. OUT1_HS_MODE_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT1_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for OUT1 with max value of 1022 when OUT1_MODE=1. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: DRV8001-Q1

8.2.23 OUT2_HS_MODE_DC Register (Offset = 28h) [Reset = 0000h]

OUT2_HS_MODE_DC is shown in Table 8-37. Return to the Summary Table. Configures 10 bits for duty cycle Table 8-37. OUT2_HS_MODE_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT2_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for OUT2 with max value of 1022 when OUT2_MODE=1. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.3 DRV8000-Q1_CTRL Registers

Table 8-38 lists the memory-mapped registers for the DRV8000-Q1_CTRL registers. All register offset addresses not listed in Table 8-38 should be considered as reserved locations and the register contents should not be modified. Table 8-38. DRV8000-Q1_CTRL Registers Offset Acronym Register Name Section 29h IC_CTRL IC control register. Section 8.3.1 2Ah HB_CTRL Gate driver and half-bridge control register. Section 8.3.2 2Bh HS_EC_HEAT_CTRL High-side driver, EC, and heater driver control register. Section 8.3.3 2Ch OUT7_PWM_DC OUT7 PWM Duty cycle control register. Section 8.3.4 2Dh OUT8_PWM_DC OUT8 PWM Duty cycle control register. Section 8.3.5 2Eh OUT9_PWM_DC OUT9 PWM Duty cycle control register. Section 8.3.6 2Fh OUT10_PWM_DC OUT10 PWM Duty cycle control register. Section 8.3.7 30h OUT11_PWM_DC OUT11 PWM Duty cycle control register. Section 8.3.8 31h OUT12_PWM_DC OUT12 PWM Duty cycle control register. Section 8.3.9 Complex bit access types are encoded to fit into small table cells. Table 8-39 shows the codes that are used for access types in this section. Table 8-39. DRV8000-Q1_CTRL Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: DRV8001-Q1

8.3.1 IC_CTRL Register (Offset = 29h) [Reset = 006Ch]

IC_CTRL is shown in Table 8-40. Return to the Summary Table. Control register to lock and unlock configuration or control registers, and clear faults. Table 8-40. IC_CTRL Register Field Descriptions Bit Field Type Reset Description 13 IPROPI_MODE R/W 0h Selects IPROPI/PWM2 pin mode between input and output modes. 0b = Output (IPROPI mode) 1b = Input (PWM mode) 12-8 IPROPI_SEL R/W 0h Controls IPROPI MUX output between current, voltage, and temperature sense output. 00000b = No output 00001b = OUT1 current sense output 00010b = OUT2 current sense output 00011b = OUT3 current sense output 00100b = OUT4 current sense output 00101b = OUT5 current sense output 00110b = OUT6 current sense output 00111b = OUT7 current sense output 01000b = OUT8 current sense output 01001b = OUT9 current sense output 01010b = OUT10 current sense output 01011b = OUT11 current sense output 01100b = OUT12 current sense output 01101b = Reserved. 01110b = Reserved. 01111b = Reserved. 10000b = VPVDD Sense Nominal Range (5V -22V) 10001b = Thermal cluster 1 output 10010b = Thermal cluster 2 output 10011b = Thermal cluster 3 output 10100b = Thermal cluster 4 output 10101b = VPVDD Sense High Range (20V - 32V) 7-5 CTRL_LOCK R/W 3h Lock and unlock the control registers. Bit settings not listed have no effect. 011b = Unlock all control registers. 110b = Lock the control registers by ignoring further writes except to the IC_CTRL register. 4-2 CNFG_LOCK R/W 3h Lock and unlock the configuration registers. Bit settings not listed have no effect. 011b = Unlock all configuration registers. 110b = Lock the configuration registers by ignoring further writes. 1 WD_RST R/W 0h Watchdog restart. 0b by default after power up. Invert this bit to restart the watchdog timer. After written, the bit reflects the new inverted value. 0 CLR_FLT R/W 0h Clear latched fault status information. 0b = Default state. 1b = Clear latched fault bits, resets to 0b after completion. It also clears SPI fault and watchdog fault status. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.3.2 HB_CTRL Register (Offset = 2Ah) [Reset = 0000h]

HB_CTRL is shown in Table 8-41. Return to the Summary Table. Half-bridge output control register. Table 8-41. HB_CTRL Register Field Descriptions Bit Field Type Reset Description 11-10 OUT6_CTRL R/W 0h Integrated half-bridge output 6 control. 00b = OFF 01b = HS ON 10b = LS ON 11b = RSVD 9-8 OUT5_CTRL R/W 0h Integrated half-bridge output 5 control. 00b = OFF 01b = HS ON 10b = LS ON 11b = RSVD 7-6 OUT4_CTRL R/W 0h Integrated half-bridge output 4 control. 00b = OFF 01b = HS ON 10b = LS ON 11b = RSVD 5-4 OUT3_CTRL R/W 0h Integrated half-bridge output 3 control. 00b = OFF 01b = HS ON 10b = LS ON 11b = RSVD 3-2 OUT2_CTRL R/W 0h Integrated half-bridge output 2 control. 00b = OFF 01b = HS ON 10b = LS ON 11b = RSVD 1-0 OUT1_CTRL R/W 0h Integrated half-bridge output 1 control. 00b = OFF 01b = HS ON 10b = LS ON 11b = RSVD www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: DRV8001-Q1

8.3.3 HS_EC_HEAT_CTRL Register (Offset = 2Bh) [Reset = 0000h]

HS_EC_HEAT_CTRL is shown in Table 8-42. Return to the Summary Table. High-side driver, EC, and heater driver output control register. Table 8-42. HS_EC_HEAT_CTRL Register Field Descriptions Bit Field Type Reset Description

15 ECFB_LS_EN R/W 0h Enables EC discharge with LS MOSFET on ECFB while the EC

regulation is active. 14 EC_ON R/W 0h Enables the EC output. 13-8 EC_V_TAR R/W 0h 6-bits of resolution to control the target voltage on ECFB. 0 V to ECFB max (1.2 or 1.5V). 7 HEAT_EN R/W 0h Enables heater output. 5 OUT12_EN R/W 0h Enables high-side driver 12. 4 OUT11_EN R/W 0h Enables high-side driver 11. 3 OUT10_EN R/W 0h Enables high-side driver 10. 2 OUT9_EN R/W 0h Enables high-side driver 9. 1 OUT8_EN R/W 0h Enables high-side driver 8. 0 OUT7_EN R/W 0h Enables high-side driver 7. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.3.4 OUT7_PWM_DC Register (Offset = 2Ch) [Reset = 0000h]

OUT7_PWM_DC is shown in Table 8-43. Return to the Summary Table. 10-bit duty cycle control for high-side driver 7. Table 8-43. OUT7_PWM_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT7_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 7 with max value of 1022. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: DRV8001-Q1

8.3.5 OUT8_PWM_DC Register (Offset = 2Dh) [Reset = 0000h]

OUT8_PWM_DC is shown in Table 8-44. Return to the Summary Table. 10-bit duty cycle control for high-side driver 8. Table 8-44. OUT8_PWM_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT8_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 8 with max value of 1022. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.3.6 OUT9_PWM_DC Register (Offset = 2Eh) [Reset = 0000h]

OUT9_PWM_DC is shown in Table 8-45. Return to the Summary Table. 10-bit duty cycle control for high-side driver 9. Table 8-45. OUT9_PWM_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT9_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 9 with max value of 1022. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: DRV8001-Q1

8.3.7 OUT10_PWM_DC Register (Offset = 2Fh) [Reset = 0000h]

OUT10_PWM_DC is shown in Table 8-46. Return to the Summary Table. 10-bit duty cycle control for high-side driver 10. Table 8-46. OUT10_PWM_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT10_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 10 with max value of 1022. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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8.3.8 OUT11_PWM_DC Register (Offset = 30h) [Reset = 0000h]

OUT11_PWM_DC is shown in Table 8-47. Return to the Summary Table. 10-bit duty cycle control for high-side driver 11. Table 8-47. OUT11_PWM_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT11_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 11 with max value of 1022. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: DRV8001-Q1

8.3.9 OUT12_PWM_DC Register (Offset = 31h) [Reset = 0000h]

OUT12_PWM_DC is shown in Table 8-48. Return to the Summary Table. 10-bit duty cycle control for high-side driver 12. Table 8-48. OUT12_PWM_DC Register Field Descriptions Bit Field Type Reset Description 9-0 OUT12_DC R/W 0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 12 with max value of 1022. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The DRV800x-Q1 is a highly configurable multichannel integrated half-bridge and half-bridge MOSFET gate driver than can be used to drive a variety of different output loads. The design examples below highlight how to use and configure the device for different application use cases.

9.2 Typical Application

The typical application for the DRV8001-Q1 is to control multiple loads in a typical automotive door. These include multiple integrated half-bridges and high-side drivers, an electrochromic mirror driver and external high- side MOSFET driver for a heating element. A high-level schematic example is shown in Figure 9-1 below. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: DRV8001-Q1

PGNDx (1,2) DRV8001-Q1 1 μF VCP PVDDDVDD DGND nSLEEP PAD Power and Charge Pump 1 μF Interface (SPI) VDVDD VCC nSCS SCLK MDO MDI GP-O Microcontroller Reverse Polarity Protection VPVDD VBATT CBULK CBULKVPVDD 0.1 μF Half-Bridges & High-side Drivers PWM1 IPROPI PWM ADC OUT1 M M Lock X Y M M Safe Lock M OUT2 OUT3 OUT4 OUT5 OUT6 OUT8 OUT9 OUT10 OUT12 GH_HS SH_HS OUT11 Fold RGH_HS VPVDD ECDRV ECFB 10 μF CECDRV CECFB EC Glass RECDRV RIPROPI OUT7 Heater **Recommended protection in case of inductive short Heater EC Driver PWM2PWM Lamp/LED LED Figure 9-1. DRV8001-Q1 Typical Application

9.2.1 Design Requirements

Table 9-1 lists a set of example input parameters for the system design. Table 9-1. Design Parameters PARAMETER VALUE PVDD Supply Voltage Range 9 to 18V PVDD Nominal Supply Voltage 13.5V DVDD Logic Supply Voltage Range 3.3V IPROPI Resistance 2.35kΩ PWM Frequency 20kHz DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

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9.3 Initialization Setup

9.4 Power Supply Recommendations

9.4.1 Bulk Capacitance Sizing

Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size. The amount of local capacitance depends on a variety of factors including:

• The highest current required by the motor system
• The type of power supply, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor start-up and braking methods The inductance between the power supply and motor drive system can limit the current rate from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet provides a recommended minimum value, but system level testing is required to determine the appropriate sized bulk capacitor. Local Bulk Capacitor IC Bypass Capacitor Parasitic Wire Inductance Motor Driver Power Supply Motor Driver System PVDD GND Figure 9-2. Motor Driver Supply Parasitics Example

9.5 Layout

9.5.1 Layout Guidelines

Bypass the PVDD pin to the GND pin using a low-ESR ceramic bypass capacitor CPVDD1. Place this capacitor as close to the PVDD pin as possible with a thick trace or ground plane connected to the GND pin. Additionally, bypass the PVDD pin using a bulk capacitor C PVDD2 rated for PVDD. This component can be electrolytic. This capacitance must be at least 10µF. Having the capacitance shared with the bulk capacitance for the external power MOSFETs is acceptable. Bypass the DVDD pin to the DGND pin with CDVDD. Place this capacitor as close to the pin as possible and minimize the path from the capacitor to the DGND pin. If local bypass capacitors are already present on these power supplies in close proximity of the device to minimize noise, these additional components for DVDD are not required. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: DRV8001-Q1

For the EC driver, place both the CECDRV and CECFB bypass capacitors to GND as close to the respective pins as possible.

9.5.2 Layout Example

Figure 9-3. DRV8001-Q1 Component Placement and Layout The layout screen shot above shows the device component and layout relative to the device. This layout screen shot comes from the device evaluation module. Note that all power supply decoupling capacitors, especially smaller values, and charge pump capacitors are placed as closed to the pins as possible and are placed on the same layer of the device. All general guidelines outlined in the previous section were followed in the evaluation module layout design when possible. DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 www.ti.com

106 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated

Product Folder Links: DRV8001-Q1

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop designs are listed below.

10.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com DRV8001-Q1 SLVSHD9A – MARCH 2025 – REVISED DECEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: DRV8001-Q1

www.ti.com 16-Dec-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV8001QWRHARQ1 Active Production VQFN (RHA) | 40 2500 | LARGE T&R - NIPDAU Level-2-260C-1 YEAR -40 to 125 DRV8001 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8001QWRHARQ1 VQFN RHA 40 2500 360.0 360.0 36.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHA 40 PLASTIC QUAD FLATPACK - NO LEAD6 x 6, 0.5 mm pitch 4225870/A

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