DRV632 TI | Alldatasheet
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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV632 SLOS681C –JANUARY 2011–REVISED AUGUST 2019 DRV632DirectPath™,2-VRMSAudioLineDriverWithAdjustableGain
1 Features
1• Stereo DirectPath™ Audio Line Driver – 2 Vrms Into 10 kΩ With 3.3-V Supply
- Low THD+N < 0.01% at 2 Vrms Into 10 kΩ
- High SNR, >90 dB
- 600-Ω Output Load Compliant
- Differential Input and Single-Ended Output
- Adjustable Gain by External Gain-Setting Resistors
- Low DC Offset, <1 mV
- Ground-Referenced Outputs Eliminate DC- Blocking Capacitors – Reduce Board Area – Reduce Component Cost – Improve THD+N Performance – No Degradation of Low-Frequency Response Due to Output Capacitors
- Short-Circuit Protection
- Click- and Pop-Reduction Circuitry
- External Undervoltage Mute
- Active Mute Control for Pop-Free Audio On/Off Control
- Space-Saving TSSOP Package
2 Applications
- Set-Top Boxes
- Blu-ray Disc™ , DVD Players
- LCD and PDP TV
- Mini/Micro Combo Systems
- Sound Cards
- Laptops
3 Description
The DRV632 is a 2-VRMS pop-free stereo line driver designed to allow the removal of the output dc- blocking capacitors for reduced component count and cost. The device is ideal for single-supply electronics where size and cost are critical design parameters. Designed using TI’s patented DirectPath™ technology, The DRV632 is capable of driving 2 VRMS into a 10-kΩ load with 3.3-V supply voltage. The device has differential inputs and uses external gain- setting resistors to support a gain range of ±1 V/V to ±10 V/V, and gain can be configured individually for each channel. Line outputs have ±8-kV IEC ESD protection, requiring just a simple resistor-capacitor ESD protection circuit. The DRV632 has built-in active-mute control for pop-free audio on/off control. The DRV632 has an external undervoltage detector that mutes the output when the power supply is removed, ensuring a pop-free shutdown. Using the DRV632 in audio products can reduce component count considerably compared to traditional methods of generating a 2-VRMS output. The DRV632 does not require a power supply greater than 3.3 V to generate its 5.6-Vpp output, nor does it require a split-rail power supply. The DRV632 integrates its own charge pump to generate a negative supply rail that provides a clean, pop-free ground-biased 2-VRMS output. The DRV632 is available in a 14-pin TSSOP. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV632 TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Diagram
SLOS681C –JANUARY 2011–REVISED AUGUST 2019 www.ti.com Product Folder Links: DRV632 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated Table of Contents
14 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (August 2015) to Revision C Page Changes from Revision A (June 2013) to Revision B Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Original (January 2011) to Revision A Page
www.ti.com SLOS681C –JANUARY 2011–REVISED AUGUST 2019 Product Folder Links: DRV632 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated
5 Device Comparison Table
DEVICE INPUT OFFSET (±µV) OUTPUT VOLTAGE (TYP) (VRMS) MINIMUM LOAD IMPEDANCE (Ω) DRV632 1000 2.4 600 DRV612 1000 2.2 600 DRV604 500 2.1 1000 (line output) / 8 (headphone output) DRV603 1000 2.05 (VSS = 3.3 V) / 3.01 (VDD = 5 V) 600 DRV602 5000 2.05 (VSS = 3.3 V) / 3.01 (VDD = 5 V) 600 DRV601 8000 2.1 (VSS = 3.3 V) / 2.7 (VDD = 4.5 V) 100 DRV600 8000 2.1 (VSS = 3.3 V) / 2.7 (VDD = 4.5 V) 100
–INR OUTR GND 7 8 Mute VSS CN CP VDD GND OUTL –INL +INL Charge Pump UVP External Under- Voltage Detector DRV632 SLOS681C –JANUARY 2011–REVISED AUGUST 2019 www.ti.com Product Folder Links: DRV632 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) I = input, O = output, P = power
6 Pin Configuration and Functions
(Top View) Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. CN 7 I/O Charge-pump flying capacitor negative connection CP 8 I/O Charge-pump flying capacitor positive connection GND 4, 10 P Ground –INL 13 I Left-channel OPAMP negative input +INL 14 I Left-channel OPAMP positive input –INR 2 I Right-channel OPAMP negative input +INR 1 I Right-channel OPAMP positive input Mute 5 I Mute, active-low OUTL 12 O Left-channel OPAMP output OUTR 3 O Right-channel OPAMP output UVP 11 I Undervoltage protection, internal pullup; unconnected if UVP function is unused. VDD 9 P Positive supply VSS 6 P Supply voltage (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (1) MIN MAX UNIT Supply voltage, VDD to GND –0.3 4 V VI Input voltage VSS – 0.3 VDD + 0.3 V RL Minimum load impedance – line outputs – OUTL, OUTR 600 Ω Mute to GND, UVP to GND –0.3 VDD + 0.3 V TJ Maximum operating junction temperature –40 150 °C Tstg Storage temperature –40 150 °C
www.ti.com SLOS681C –JANUARY 2011–REVISED AUGUST 2019 Product Folder Links: DRV632 Submit Documentation FeedbackCopyright © 2011–2019, Texas Instruments Incorporated (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) ±4000
7.3 Recommended Operating Conditions
VDD Supply voltage DC supply voltage 3 3.3 3.6 V RL Load impedance 0.6 10 kΩ VIL Low-level input voltage Mute 40 % of VDD VIH High-level input voltage Mute 60 % of VDD TA Operating free-air temperature –40 25 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
7.4 Thermal Information
THERMAL METRIC(1) DRV632 UNITPW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 130 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49 °C/W RθJB Junction-to-board thermal resistance 63 °C/W ψJT Junction-to-top characterization parameter 3.6 °C/W ψJB Junction-to-board characterization parameter 62 °C/W
7.5 Electrical Characteristics
TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOS| Output offset voltage VDD = 3.3 V 0.5 1 mV PSRR Power-supply rejection ratio 80 dB VOH High-level output voltage VDD = 3.3 V 3.1 V VOL Low-level output voltage VDD = 3.3 V –3.0 V VUVP_EX External UVP detect voltage 1.25 V VUVP_EX_HYSTERESIS External UVP detect hysteresis current 5 µA fCP Charge pump switching frequency 200 300 400 kHz |IIH| High-level input current, Mute VDD = 3.3 V, VIH = VDD 1 µA |IIL| Low-level input current, Mute VDD = 3.3 V, VIL = 0 V 1 µA IDD Supply current VDD = 3.3 V, no load, Mute = VDD 5 14 25 mAVDD = 3.3 V, no load, Mute = GND, disabled
SLOS681C –JANUARY 2011–REVISED AUGUST 2019 www.ti.com Product Folder Links: DRV632 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated (1) SNR is calculated relative to 2-Vrms output.
7.6 Operating Characteristics
VDD = 3.3 V, RDL = 10 kΩ, RFB = 30 kΩ, RIN = 15 kΩ, TA = 25°C, Charge pump: CP = 1 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Output voltage, outputs in phase THD+N = 1%, VDD = 3.3 V, f = 1 kHz, RL = 10 kΩ 2 2.4 Vrms THD+N Total harmonic distortion plus noise VO = 2 VRMS, f = 1 kHz 0.002% SNR Signal-to-noise ratio(1) A-weighted 105 dB DNR Dynamic range A-weighted 105 dB VN Noise voltage A-weighted 11 μV ZO Output Impedance when muted Mute = GND 110 mΩ Input-to-output attenuation when muted Mute = GND 80 dB Crosstalk— L to R, R to L VO = 1 Vrms –110 dB ILIMIT Current limit 25 mA
7.7 Typical Characteristics
Figure 1. Total Harmonic Distortion and Noise vs Output Figure 2. Total Harmonic Distortion and Noise vs Output Figure 3. Total Harmonic Distortion and Noise vs Frequency Figure 4. Total Harmonic Distortion and Noise vs Frequency Figure 5. Crosstalk vs Frequency
8 Parameter Measurement Information
All parameters are measured according to the conditions described in Specifications.
–INR +INR OUTL –INL OUTR +INL Mute GND UVP Line Driver Line Driver DRV632 SLOS681C –JANUARY 2011–REVISED AUGUST 2019 www.ti.com Product Folder Links: DRV632 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated
9 Detailed Description
9.1 Overview
Combining the TI's patented DirectPath technology with the built-in click and pop reduction circuit, the DRV632 is a 2-VRMS pop-free stereo line driver designed to avoid the use of the output DC-blocking capacitors, resulting in reduced component count and cost. The DRV632 is capable of driving 2-VRMS into a line load of 600 Ω to 10 kΩ with a 3.3-V supply voltage. The use of charge-pump flying, PVSS, and decoupling capacitors ensure the performance of the amplifier. The device has two channels with differential inputs that require DC input-blocking capacitors to block the DC portion of the audio source. These allow the DRV632 inputs to be properly biased to provide maximum performance. The DRV632 allows external gain-setting resistors to support a gain range of ±1 V/V to ±10 V/V. The gain can be configured individually for each channel. Additionally, both channels can be used as a second-order filter when the removal of out-of-band noise is required. The DRV632 has a built-in active-mute control for pop-free audio on/off, and avoids the click and pop generation by using external undervoltage detection. The device does not generate a pop or click when the power supply is removed or placed.
9.2 Functional Block Diagram
9 V–12 V
9.3 Feature Description
9.3.1 Line Driver Amplifiers
(CO), and the cutoff frequency (fC). CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known. increase cost of assembly, and can reduce the fidelity of the audio output signal. Figure 6. Conventional and DirectPath Line Drivers
9.3.2 Charge-Pump Flying Capacitor and PVSS Capacitor
The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
9.3.3 Decoupling Capacitors
required in most applications because of the high PSRR of this device.
9.3.4 Gain-Setting Resistor Ranges
DRV632 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN. Table 1. Recommended Resistor Values
9.3.5 Input-Blocking Capacitors
biased to provide maximum performance. commonly seen in ceramic capacitors and can increase low-frequency audio distortion.
9.3.6 DRV632 UVP Operation
9.3.7 External Undervoltage Detection
For example, to obtain VUVP = 3.8 V and 1-V hysteresis, use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.
Figure 7. UVP Resistor Divider
9.4 Device Functional Modes
9.4.1 Using the DRV632 as a Second-Order Filter
single-ended input are shown. the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum. To calculate the component values, use the TI WEBENCH® Filter Designer (www.ti.com/filterdesigner). Figure 8. Second-Order Active Low-Pass Filter dynamic range (DYR) of 106 dB can be achieved with a 1-μF input ac-coupling capacitor.
9.4.2 Mute Mode
ensures that when the mute mode is used, it does not generate an additional click or pop.
validate and test their design implementation to confirm system functionality.
10.1 Application Information
DRV632 product page for information on ordering the EVM.
10.2 Typical Application
Figure 9. Typical Application Schematic
10.2.1 Design Requirements
In this design example, use the parameters listed in Table 2. Table 2. Design Parameters
10.2.2 Detailed Design Procedure
10.2.2.1 Charge-Pump Flying, PVSS and Decoupling Capacitors
10.2.2.2 Second-Order Active Low-Pass Filters
differential-input and a single-ended output. See Using the DRV632 as a Second-Order Filter for details.
10.2.2.3 UVP Resistor Divider
External Undervoltage Detection for details.
10.2.3 Application Curves
Figure 10. Total Harmonic Distortion and Noise vs Output Figure 11. Total Harmonic Distortion and Noise vs Output
Figure 12. Total Harmonic Distortion and Noise vs Figure 13. Total Harmonic Distortion and Noise vs Figure 14. Crosstalk vs Frequency
11 Power Supply Recommendations
value of 47 µF is a typical choice. equivalent-series-resistance (ESR) ceramic capacitor with a value of 1 µF is a typical choice.
12 Layout
12.1 Layout Guidelines
12.1.1 Gain-Setting Resistors
PCB layout, see the DRV632EVM User's Guide.
12.2 Layout Example
Figure 15. DRV632 Layout Example
SLOS681C –JANUARY 2011–REVISED AUGUST 2019 www.ti.com Product Folder Links: DRV632 Submit Documentation Feedback Copyright © 2011–2019, Texas Instruments Incorporated
13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For the DRV632EVM and Gerber files, go to www.ti.com/tool/DRV632EVM.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
13.3 Trademarks
DirectPath, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV632PW Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632 DRV632PW.A Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632 DRV632PWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632 DRV632PWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV632PWR TSSOP PW 14 2000 350.0 350.0 43.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DRV632PW PW TSSOP 14 90 530 10.2 3600 3.5 DRV632PW.A PW TSSOP 14 90 530 10.2 3600 3.5 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6
6.2 TYP
1.2 MAX
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8
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