DRV612_16 TI1 | Alldatasheet

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-1x to -10x DRV612 www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011 2-VrmsDirectPath™LineDriverWithProgrammable-FixedGain Check forSamples: DRV612 1FEATURES DESCRIPTION The DRV612 isa single-ended,2-Vrms stereoline 2• DirectPath™ driverdesigned to reduce component count,board– EliminatesPops/Clicks space and cost. It is ideal for single-supply – EliminatesOutput DC-Blocking Capacitors electronicswhere sizeand cost are criticaldesign parameters.– 3-V to3.6-VSupply Voltage

  • Low Noise and THD The DRV612 does notrequirea power supplygreater than3.3V togenerateits5.6-VPP output,nor does it– SNR > 105 dB at–1× Gain requirea split-railpower supply.– TypicalVn < 12 μVms 20 Hz–20 kHz Designed usingTI’s patentedDirectPathtechnology,at–1× Gain which integratesa charge pump to generate a– THD+N < 0.003% at10-kΩ Load negativesupplyrailthatprovidesa clean,pop-freeand –1× Gain ground-biasedoutput.The DRV612 is capable of
  • 2-Vrms Output VoltageInto600-Ω Load driving2 Vms into a 600-Ω load. DirectPath technologyalso allowsthe removal of the costly• Single-EndedInputand Output outputdc-blockingcapacitors.• Programmable Gain SelectReduces Component Count The devicehas fixed-gainsingle-endedinputswitha gain-selectpin.Usinga singleresistoron thispin,the– 13× Gain Values designercan choose from 13 internalprogrammable• ActiveMute With More Than 80 dB Attenuation gainsettingsto match the linedriverwiththe codec
  • ShortCircuitand Thermal Protection outputlevel.Italsoreducesthecomponent countand boardspace.• ±8-kV HBM ESD-ProtectedOutputs Line outputs have ±8 kV HBM ESD protection, APPLICATIONS enabling a simple ESD protectioncircuit.The DRV612 has built-inactivemute controlwithmore• PDP /LCD TV that 80 dB attenuationfor pop-freemute on/off• DVD Players control.
  • Mini/MicroCombo Systems The DRV612 is availablein a 14-pinTSSOP and• Soundcards 16-pin QFN. For a footprint-compatiblestereo headphone driver,see TPA6139A2 (SLOS700 ). Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2DirectPathisa trademarkofTexas Instruments. UNLESS OTHERWISE NOTED this document contains Copyright© 2010–2011,Texas InstrumentsIncorporatedPRODUCTION DATA informationcurrentas of publicationdate. Products conform to specificationsper the terms of Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

-IN_L OUT_L MUTE -IN_R OUT_R 13141516 8765 OUT_L MUTE -IN_L NC NC -IN_R GND GAIN VDD OUT_R VSS CN NC CP RGT PACKAGE QFN (TOP VIEW) PW PACKAGE TSSOP (TOP VIEW) DRV612 SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. GENERAL INFORMATION TERMINAL ASSIGNMENT The DRV612 isavailableinpackage:

  • 14-pinTSSOP package (PW) or16-pinQFN package (RGT) PIN FUNCTIONS PIN FUNCTION (1) DESCRIPTION NAME PW NO. RGT NO. -IN_L 1 16 I Negativeinput,leftchannel OUT_L 2 1 O Output,leftchannel GND 3,11 2,3,10 P Ground MUTE 4 4 I MUTE, activelow VSS 5 5 O Change Pump negativesupplyvoltage CN 6 6 I/O Charge Pump flyingcapacitornegativeconnection NC 7,8 7.14,15 No internalconnection CP 9 8 I/O Charge Pump flyingcapacitorpositiveconnection VDD 10 9 P Supplyvoltage,connecttopositivesupply Gain setprogrammingpin;connecta resistortoground.GAIN 12 11 I See Table1 forrecommended resistorvalues OUT_R 13 12 O Output,rightchannel -IN_R 14 13 I Negativeinput,rightchannel ThermalPad n/a ThermalPad P Connecttoground (1) I= input,O = output,P = power

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www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011 SYSTEM BLOCK DIAGRAM ORDERING INFORMATION (1) TA PACKAGE DESCRIPTION DRV612PW 14-pinTSSOP –40°C to85°C DRV612RGT 16-pinQFN (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI Web siteatwww.ti.com. THERMAL INFORMATION DRV612 DRV612 THERMAL METRIC (1) UNITS RGT (16-Pin) PW (14-Pin) θJA Junction-to-ambientthermalresistance 52 130 θJCtop Junction-to-case(top)thermalresistance 71 49 θJB Junction-to-boardthermalresistance 26 63 °C/W ψJT Junction-to-topcharacterizationparameter 3.0 3.6 ψJB Junction-to-boardcharacterizationparameter 26 62 θJCbot Junction-to-case(bottom)thermalresistance n/a n/a (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . Copyright© 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):DRV612

SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT MIN MAX VDD toGND –0.3 4 Voltagerange VI,Inputvoltage VSS – 0.3 VDD + 0.3 V MUTE toGND –0.3 VDD + 0.3 Maximum operatingjunctiontemperaturerange,TJ –40 150 Temperature °C Storagetemperature –65 150 OUT_L, OUT_R 8Electrostaticdischarge(HBM) QSS kV009-105(JESD22-A114A) Allotherpins 2 (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended Operating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerangeunlessotherwisenoted MIN NOM MAX UNIT VDD Supplyvoltage DC supplyvoltage 3.0 3.3 3.6 V R L 600 10k Ω VIL Low-levelinputvoltage MUTE 38 40 43 %VDD VIH High-levelinputvoltage MUTE 57 60 66 %VDD TA Free-airtemperature –0 25 85 °C

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www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011

ELECTRICAL CHARACTERISTICS

VDD = 3.3V,R LD = 5 kΩ,TA = 25°C, Charge pump: C CP = 1 μF,unlessotherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT |VOS | Outputoffsetvoltage VDD = 3.3V,inputac-coupled 0.5 1 mV PSRR Power-supplyrejectionratio 70 80 dB VOH High-leveloutputvoltage VDD = 3.3V 3.1 V VOL Low-leveloutputvoltage VDD = 3.3V –3.05 V Vuvp_on VDD, undervoltagedetection 2.8 V Vuvp_hysteresisVDD, undervoltagedetection,hysteresis 200 mV FCP Charge-pump switchingfrequency 350 kHz |IIH| High-levelinputcurrent,MUTE VDD = 3.3V,VIH = VDD 1 µA |IIL| Low-levelinputcurrent,MUTE VDD = 3.3V,VIL= 0 V 1 µA I(VDD) Supplycurrent,no load VDD, MUTE = 3.3V 18 mA Supplycurrent,MUTED VDD = 3.3V,MUTE = GND 18 mA TSD Thermalshutdown 150 °C Thermalshutdownhysteresis 15 °C ELECTRICAL CHARACTERISTICS, LINE DRIVER VDD = 3.3V,R LOAD = 10 kΩ,TA = 25°C, Charge pump: C CP = 1 µF,1× gainselect(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO Outputvoltage,outputsinphase 1% THD+N, f= 1 kHz,10 -kΩ load 2.2 Vrms THD+N Totalharmonicdistortionplusnoise f= 1 kHz,10-kΩ load,VO = 2 Vrms 0.007% SNR Signal-to-noiseratio A-weighted,AES17 filter,2 Vrms ref 105 dB DNR Dynamic range A-weighted,AES17 filter,2 Vrms ref 105 dB Vn Noisevoltage A-weighted,AES17 filter 12 μV Zo Outputimpedance when muted MUTE = GND 0.07 1 Ω Input-to-outputattenuationwhen 1 Vrms,1-kHzinput 80 dBmuted Slew rate 4.5 V/μs G BW Unity-gainbandwidth 8 MHz Crosstalk– LineL-R and R-L 10-kΩ load,VO = 2 Vrms –91 dB Ilimit Currentlimit VDD = 3.3V 25 mA Copyright© 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):DRV612

SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com PROGRAMMABLE GAIN SETTINGS (1)(2) VDD = 3.3V,R load= 10 kΩ,TA = 25°C, Charge pump: C CP = 1 μF,1× gainselect,unlessotherwisenoted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT R_Tol Gain programmingresistortolerance 2% ΔAV Gain matching Between leftand rightchannels 0.25 dB Gain steptolerance 0.1 dB Gain resistor2% tolerance A 249k orhigher –2 82k5 –1 51k1 –1.5 34k8 –2.3 27k4 –2.5 20k5 –3Gain steps V/V15k4 –3.5 11k5 –4 9k09 –5 7k50 –5.6 6k19 –6.4 5k11 –8.3 4k22 –10 Gain resistor2% tolerance A 249k orhigher 37 82k5 55 51k1 44 34k8 33 27k4 31 20k5 28Inputimpedance kΩ15k4 24 11k5 22 9k09 18 7k50 17 6k19 15 5k11 12 4k22 10 (1) IftheGAIN pinisleftfloating,an internalpullupsetsthegainto–2×. (2) Gain settingislatchedduringpower up.

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V -□Output□Voltage□-□VrmsO 0.001 0.005 0.01 0.1 0.5 THD+N□-□Total□Harmonic□Distortion□+□Noise□-□% 0.001 0.005 0.01 0.1 0.5 40m 4100m 200m 500m 1 2 THD+N□-□Total□Harmonic□Distortion□+□Noise□-□% V -□Output□Voltage□-□VrmsO 20 20k50 100 200 500 1k 2k 5k V -□Output□Voltage□-□VrmsO 0.001 0.005 0.01 0.1 0.5 THD+N□-□Total□Harmonic□Distortion□+□Noise□-□% -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k50 100 200 500 1k 2k 5k 10k f□-□Frequency□-□Hz Attenuation□-□dBr Left□to□Right Right□to□Left 3.3□V,□5□k ,□2Vrms/c87 DRV612 www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011 TYPICAL CHARACTERISTICS, LINE DRIVER VDD = 3.3V,TA = 25°C, R L = 2.5kΩ,C PUMP = C (VSS) = 1 µF,Gain = -2V/V(unlessotherwisenoted) THD+N vs OUTPUT VOLTAGE THD+N vs OUTPUT VOLTAGE 3.3V,10 kΩ,1 kHz 3.3V,600 Ω load,1 kHz Figure1. Figure2. THD+N vs FREQUENCY CHANNEL SEPARATION 3.3V,10 kΩ load,2 Vrms 3.3V,5 kΩ load,2 Vrms, Blue L toR, Red R toL Blue:10-µF ceramicac-couplingcapacitor. Red: 10-µF electrolyticac-couplingcapacitor Figure3. Figure4. Copyright© 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):DRV612

+22 +10 +12 +14 +16 +18 +20 20 200k50 100 200 500 1k 2k 5k 10k 20k 50k f□-□Frequency□-□Hz Gain□-□dBr DRV612 SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS, LINE DRIVER (continued) VDD = 3.3V,TA = 25°C, R L = 2.5kΩ,C PUMP = C (VSS) = 1 µF,Gain = -2V/V(unlessotherwisenoted) Gain vs Frequency For theDifferentGain Settings Mute toPlay Figure5. Figure6. PlaytoMute Figure7.

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Mute□Circuit Output MUTE 9-12V Conventional□solution DRV612 Output MUTE 3.3V DRV612 Solution VDD VSS GND VDD VDD/2 GND DirectPath DRV612 www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011

APPLICATION INFORMATION

Single-supplyline-driveramplifierstypicallyrequiredc-blockingcapacitors.The topdrawinginFigure8 illustrates theconventionalline-driveramplifierconnectiontotheloadand outputsignal. DC blockingcapacitorsareoftenlargeinvalue,and a mute circuitisneeded duringpower up tominimizeclick and pop. The outputcapacitorand mute circuitconsume PCB area and increasecostof assembly,and can reducethefidelityoftheaudiooutputsignal. Figure8. Conventionaland DirectPathLineDriver The DirectPathamplifierarchitectureoperatesfroma singlesupplybutmakes use ofan internalchargepump to providea negativevoltagerail. Combiningtheuser-providedpositiverailand thenegativerailgeneratedby theIC,thedeviceoperatesinwhat iseffectivelya splitsupplymode. The outputvoltagesarenow centeredatzerovoltswiththecapabilitytoswingtothepositiverailornegativerail. Combining thiswiththe built-inclick-and pop-reductioncircuit,the DirectPathamplifierrequiresno output dc-blockingcapacitors. The bottomblockdiagramand waveform ofFigure8 illustratetheground-referencedline-driverarchitecture.This isthearchitectureoftheDRV612. Copyright© 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):DRV612

1.25 V Bandgap Comparator DRV612 SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com COMPONENT SELECTION Charge Pump FlyingCapacitorand VSS Capacitor The charge-pumpflyingcapacitorservestotransferchargeduringthegenerationofthenegativesupplyvoltage. The VSS capacitormust be at leastequalto the charge pump capacitorinorderto allowmaximum charge transfer.Low-ESR capacitorsarean idealselection,and a valueof1 μF istypical. Decoupling Capacitors The DRV612 isa DirectPathline-driveramplifierthatrequiresadequatepower-supplydecouplingtoensurethat the noiseand totalharmonicdistortion(THD) are low.A good low equivalent-series-resistance(ESR) ceramic capacitor,typically1 μF,placedas closeas possibletothedeviceVDD leadworks best.Placingthisdecoupling capacitorcloseto the DRV612 isimportantforthe performanceof the amplifier.For filteringlower-frequency noisesignals,a 10-μF orgreatercapacitorplacedneartheaudiopower amplifieralsohelps,butitisnotrequired inmost applicationsbecause ofthehighPSRR ofthisdevice. Gain-Setting The gainsettingisprogrammed withtheGAIN pin.Gain settingislatcheddurningpower on.Table1 liststhe gainsettings. NOTE: Ifgainpinisleftunconnected(open)defaultgainof–2× isselected. Table1.Gain Settings Gain_setRESISTOR GAIN GAIN (dB) INPUT RESISTANCE 249 kΩ(1) –2× 6 37 kΩ 82k5 –1× 0.0 55 kΩ 51k1 –1.5× 3.5 44 kΩ 34k8 –2.3× 7.2 33 kΩ 27k4 –2.5× 8 31 kΩ 20k5 –3× 9.5 28 kΩ 15k4 –3.5× 10.9 24 kΩ 11k5 –4.0× 12 22 kΩ 9k09 –5× 14 18 kΩ 7k5 –5.6× 15 17 kΩ 6k19 –6.4× 16.1 15 kΩ 5k11 –8.3× 18.4 12 kΩ 4k22 –10× 20 10 kΩ (1) orhigher InternalUndervoltageDetection The DRV612 containsan internalprecisionband-gap referencevoltageand a comparatorused tomonitorthe supplyvoltage,VDD. The internalVDD monitorissetat2.8V with200-mV hysteresis.

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MUTE_ Time for ac -coupling capasitors to charge DRV612 www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011 Input-BlockingCapacitors DC input-blockingcapacitorsare requiredtobe added inserieswiththeaudiosignalintotheinputpinsofthe DRV612. These capacitorsblockthedc portionoftheaudiosourceand allowtheDRV612 inputstobe properly biasedtoprovidemaximum performance.The inputblockingcapacitorsalsolimitthedc gainto1,limitingthe dc-offsetvoltageattheoutput. These capacitorsform a high-passfilterwiththe inputresistor,R IN. The cutofffrequencyiscalculatedusing Equation1.For thiscalculation,thecapacitanceused istheinput-blockingcapacitorand theresistanceisthe inputresistorchosen fromTable2.Then thefrequencyand/orcapacitancecan be determinedwhen one ofthe two valuesisgiven. (1) For a fixedcutofffrequencyof2 Hz, thesizeoftheinputcapacitanceisshown inTable2 withthecapacitors roundedup tonearestE6 values.For 20-Hz cutoff,simplydividethecapacitorvalueswith10;e.g.,for1× gain, 150 nF isneeded. Table2.InputCapacitorforDifferentGain and Cutoff Gain_set Gain INPUT 2 HzGAINRESISTOR (dB) RESISTANCE Cutoff 249 kΩ –2 × 6 37 kΩ 2.2µF 82k5 –1 × 0.0 55 kΩ 1.5µF 51k1 –1.5× 3.5 44 kΩ 2.2µF 34k8 –2.3× 7.2 33 kΩ 3.3µF 27k4 –2.5× 8 31 kΩ 3.3µF 20k5 –3× 9.5 28 kΩ 3.3µF 15k4 –3.5× 10.9 24 kΩ 3.3µF 11k5 –4× 12 22 kΩ 4.7µF 9k09 –5× 14 18 kΩ 4.7µF 7k5 –5.6× 15 17 kΩ 4.7µF 6k19 –6.4× 16.1 15 kΩ 6.8µF 5k11 –8.3× 18.4 12 kΩ 6.8µF 4k22 –10× 20 10 kΩ 10 µF Pop-Free Power Up Pop-freepower up isensuredby keepingtheMUTE pinlow duringpower-supplyramp-up and -down.The pins shouldbe keptlow untiltheinputac-couplingcapacitorsare fullychargedbeforeassertingtheMUTE pinhigh, thisway properpre-chargeof the ac-couplingis performedand pop-lesspower up is achieved.Figure9 illustratesthepreferredsequence. Figure9. Power-Up/Down Sequence Copyright© 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):DRV612

SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com CAPACITIVE LOAD The DRV612 has theabilitytodrivea highcapacitiveloadup to220 pF directly.Highercapacitiveloadscan be acceptedby addinga seriesresistorof47 Ω orlargerforthelinedriveroutput. LAYOUT RECOMMENDATIONS A proposedlayoutfortheDRV612 can be seen intheDRV612EVM User'sGuide (SLOU248 ),and theGerber filescan be downloaded from http://focus.ti.com/docs/toolsw/folders/print/DRV612evm.html. To access this information,open theDRV612 productfolderand lookintheToolsand Softwarefolder. Ground tracesare recommended to be routedas a starground to minimizehum interference.VDD, VSS decouplingcapacitorsand thecharge-pumpcapacitorsshouldbe connectedwithshorttraces.

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21 C24

OUT_LEFT MUTE IN_LEFT R21 1 2 OUT_RIGHT +3.3 V IN_RIGHT U21 DRV612RGT OUT_L GND2 GND MUTE VSS CN CP GAIN 11 OUT_R -IN_R nc nc VDD GND nc -IN_L GND GND GND C15 GND C11 2.2 F/c109 2 1 C12 2 1 GND U11 DRV612PW -IN_L OUT_L GND MUTE VSS5 CN NC GND GAIN OUT_R -IN_R NC CP VDD 10 C13 1 F/c109 C14 2 1 MUTE IN_LEFT OUT_LEFT R11 49 k/c87 1 2 +3.3 V IN_RIGHT OUT_RIGHT

2.2 F/c109

1 F/c109

www.ti.com SLOS690B –DECEMBER 2010–REVISED APRIL 2011 FOOTPRINT COMPATIBLE WITH TPA6139A2 The DRV612 stereolinedriverispincompatiblewiththeheadphone amplifierTPA6139A2. Therefore,a single PCB layoutcan be used withstuffingoptionsfordifferentboardconfigurations. APPLICATION CIRCUIT Figure10. Single-EndedInputand Output,Gain Set to–1.5× Copyright© 2010–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):DRV612

SLOS690B –DECEMBER 2010–REVISED APRIL 2011 www.ti.com

REVISION HISTORY

Changes from Original(December 2010)toRevisionA Page

  • Changed theGain resistor2% tolerancevaluesintheProgrammable Gain SettingstableForGain Stepsand Input
  • Changed Note 1 ofthePROGRAMMABLE GAIN SETTINGS tableFrom:Ifpin12,GAIN, isleftfloatingTo:Ifthe Changes from RevisionA (February2011)toRevisionB Page

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www.ti.com 29-Apr-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV612PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV612 DRV612PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV612 DRV612RGTR ACTIVE QFN RGT 16 3000 TBD Call TI Call TI -40 to 85 D612 DRV612RGTT ACTIVE QFN RGT 16 250 TBD Call TI Call TI -40 to 85 D612 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 29-Apr-2016 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV612PWR TSSOP PW 14 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 28-Apr-2016 Pack Materials-Page 2

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