DRV5013ADQLPG

DRV5013_V02 TI | Alldatasheet

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Technical content

DRV5013 Digital-Latch Hall Effect Sensor

1 Features

• Digital bipolar-latch Hall sensor
• Superior temperature stability – BOP ±10% over temperature
• Multiple sensitivity options (BOP / BRP) – ±1.3mT (FA, see Device Nomenclature) – ±2.7mT (AD, ND, see Device Nomenclature) – ±6mT (AG, see Device Nomenclature) – ±12mT (BC, see Device Nomenclature)
• Supports a wide voltage range – 2.5V to 38V – No external regulator required
• Wide operating temperature range – TA = –40 to +125°C (Q, see Device Nomenclature) – TA = –40 to +150°C (E, see Device Nomenclature)
• Open-drain output (30mA sink)
• Fast 35µs power-on time
• Small package and footprint – Surface mount 3-pin SOT-23 (DBZ)
• 2.92mm × 2.37mm – Through-hole 3-pin TO-92 (LPG, LPE)
• 4mm × 3.15mm
• Protection features: – Reverse supply protection (up to –22V) – Supports up to 40V load dump – Output short-circuit protection – Output current limitation +B (mT) OUT BOP (South) BRP (North) 0mT BHYS Output State (FA, AD, AG, BC Versions) +B (mT) OUT BOP (South) BRP (North) 0mT BHYS Inverted Output State (ND Version)

2 Applications

• Power tools
• Flow meters
• Valve and solenoid status
• Brushless dc motors
• Proximity sensing
• Tachometers

3 Description

The DRV5013 device is a chopper-stabilized Hall effect sensor that offers a magnetic sensing solution with superior sensitivity stability over temperature and integrated protection features. The magnetic field is indicated through a digital bipolar latch output. The IC has an open-drain output stage with 30-mA current sink capability. A wide operating voltage range from 2.5 V to 38 V with reverse polarity protection up to –22 V makes the device suitable for a wide range of industrial applications. Internal protection functions are provided for reverse supply conditions, load dump, and output short circuit or overcurrent. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV5013 SOT-23 (3) 2.92 mm × 1.30 mm TO-92 (3) 4.00 mm × 3.15 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Device Packages DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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4 Pin Configuration and Functions

For additional configuration information, see Device Markings and Mechanical, Packaging, and Orderable Information. GND OUT

1 VCC

Figure 4-1. DBZ Package 3-Pin SOT-23 Top View 1 2 3 VCC GND OUT Figure 4-2. LPG and LPE Packages 3-Pin TO-92 Top View Table 4-1. Pin Functions PIN TYPE DESCRIPTION NAME DBZ LPG, LPE GND 3 2 Ground Ground pin OUT 2 3 Output Hall sensor open-drain output. The open drain requires a resistor pullup. VCC 1 1 Power 2.5 V to 38 V power supply. Bypass this pin to the GND pin with a 0.01-µF (minimum) ceramic capacitor rated for VCC. www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRV5013

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Power supply voltage VCC –22 (2) 40 V Voltage ramp rate (VCC), VCC < 5V Unlimited V/µs Voltage ramp rate (VCC), VCC > 5V 0 2 Output pin voltage –0.5 40 V Output pin reverse current during reverse supply condition 0 100 mA Magnetic flux density, BMAX Unlimited Operating junction temperature, TJ Q, see Figure 8-1 –40 150 E, see Figure 8-1 –40 175 Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Specified by design. Only tested to –20 V.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2500 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Power supply voltage 2.5 38 V VO Output pin voltage (OUT) 0 38 V ISINK Output pin current sink (OUT)(1) 0 30 mA TA Operating ambient temperature Q, see Figure 8-1 –40 125 E, see Figure 8-1 –40 150 (1) Power dissipation and thermal limits must be observed.

5.4 Thermal Information

THERMAL METRIC(1) DRV5013 UNITDBZ (SOT-23) LPG, LPE (TO-92)

3 PINS 3 PINS

RθJA Junction-to-ambient thermal resistance 333.2 180 °C/W RθJC(top) Junction-to-case (top) thermal resistance 99.9 98.6 °C/W RθJB Junction-to-board thermal resistance 66.9 154.9 °C/W ψJT Junction-to-top characterization parameter 4.9 40 °C/W DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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THERMAL METRIC(1) DRV5013 UNITDBZ (SOT-23) LPG, LPE (TO-92) ψJB Junction-to-board characterization parameter 65.2 154.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VCC) VCC VCC operating voltage 2.5 38 V ICC Operating supply current ND Version VCC = 2.5V to 38V, TA = 25°C 1.5 mA ND Version VCC = 2.5V to 38V, TA = TA, MAX (1) 1.5 3.2 AD, AG, BC, FA Versions VCC = 2.5V to 38V, TA = 25°C 2.7 AD, AG, BC, FA Versions VCC = 2.5V to 38V, TA = TA, MAX (1) 3 3.5 ton Power-on time AD, AG, BC, ND versions 35 50 µs FA version 35 70 OPEN DRAIN OUTPUT (OUT) rDS(on) FET on-resistance VCC = 3.3V, IO = 10mA, TA = 25°C 22 Ω VCC = 3.3V, IO = 10mA, TA = TA,MAX (1) 36 50 Ilkg(off) Off-state leakage current Output Hi-Z 1 µA PROTECTION CIRCUITS VCCR Reverse supply voltage –22 V IOCP Overcurrent protection level OUT shorted VCC 15 30 45 mA (1) TA, MAX is 125°C for Q devices and 150°C for E devices (see Figure 8-1).

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN-DRAIN OUTPUT (OUT) td Output delay time B = BRP – 10mT to BOP + 10mT in 1µs 13 25 µs tr Output rise time (10% to 90%) R1 = 1kΩ, CO = 50pF, VCC = 3.3V 200 ns tf Output fall time (90% to 10%) R1 = 1kΩ, CO = 50pF, VCC = 3.3V 31 ns

5.7 Magnetic Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1) fBW Bandwidth(2) 20 30 kHz DRV5013FA: ±1.3 mT BOP Operate point; see Figure 6-2 TA = –40°C to TA,MAX (3) –0.6 1.3 3.4 mT BRP Release point; see Figure 6-2 –3.4 –1.3 0.6 Bhys Hysteresis; Bhys = (BOP – BRP) 1.2 2.6 BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV5013

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT(1) DRV5013AD: ±2.7 mT BOP Operate point; see Figure 6-2 TA = –40°C to TA,MAX (3) 1 2.7 5 mT BRP Release point; see Figure 6-2 –5 –2.7 –1 Bhys Hysteresis; Bhys = (BOP – BRP) 5.4 BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 DRV5013ND: ±2.7 mT BOP Operate point; see Figure 6-3 TA = 25°C 2 2.7 3.3 mT TA = –40°C to TA,MAX (3) 1.5 2.7 3.6 BRP Release point; see Figure 6-3 TA = –40°C to TA,MAX (3) –3.6 –2.7 –1.5 Bhys Hysteresis; Bhys = (BOP – BRP) TA = 25°C 4.3 5.4 TA = –40°C to TA,MAX (3) 3 5.4 BO Magnetic offset; BO = (BOP + BRP) / 2 TA = 25°C –0.5 0 0.5 TA = –40°C to TA,MAX (3) –1 0 1 DRV5013AG: ±6 mT BOP Operate point; see Figure 6-2 TA = –40°C to TA,MAX (3) 3 6 9 mT BRP Release point; see Figure 6-2 –9 –6 –3 Bhys Hysteresis; Bhys = (BOP – BRP) 12 BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 DRV5013BC: ±12 mT BOP Operate point; see Figure 6-2 TA = –40°C to TA,MAX (3) 6 12 18 mT BRP Release point; see Figure 6-2 –18 –12 –6 Bhys Hysteresis; Bhys = (BOP – BRP) 24 BO Magnetic offset; BO = (BOP + BRP) / 2 –1.5 0 1.5 (1) 1 mT = 10 Gauss. (2) Bandwidth describes the fastest changing magnetic field that can be detected and translated to the output. (3) TA, MAX is 125°C for Q devices and 150°C for E devices (see Figure 8-1). DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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5.8 Typical Characteristics

TA > 125°C data is valid for devices with the "E" temperature range designator only, (see Device Nomenclature) Supply Voltage (V) Supply Current (mA) 0 10 20 30 40 2.5 3.5 D009 TA ±ƒ& TA = 25°C TA = 75°C TA = 125°C TA = 150°C Versions: DRV5013AD, DRV5013AG, DRV5013BC, DRV5013FA Figure 5-1. ICC vs VCC Ambient Temperature (qC) Supply Current (mA) -50 -25 0 25 50 75 100 125 150 2.5 3.5 D010 VCC = 2.5 V VCC = 3.3 V VCC = 13.2 V VCC = 38 V Versions: DRV5013AD, DRV5013AG, DRV5013BC, DRV5013FA Figure 5-2. ICC vs Temperature Supply Voltage (V) Supply Current (mA) 0 10 20 30 40 1.5 2.5 T A = − 40°C T A = 25°C T A = 75°C T A = 125°C T A = 150°C Version: DRV5013ND Figure 5-3. ICC vs VCC Ambient Temperature (°C) Supply Current (mA) -50 -25 0 25 50 75 100 125 150 1.5 2.5 V CC = 2.5V V CC = 3.3V V CC = 13.2V V CC = 38V Version: DRV5013ND Figure 5-4. ICC vs Temperature Supply Voltage (V) Magnetic Field Operate Point BOP (mT) 0 10 20 30 40 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA TA = 25°C Figure 5-5. BOP vs VCC Ambient Temperature (°C) Magnetic Field Operate Point BOP (mT) -50 -25 0 25 50 75 100 125 150 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA VCC = 3.3 V Figure 5-6. BOP vs Temperature www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRV5013

5.8 Typical Characteristics (continued)

TA > 125°C data is valid for devices with the "E" temperature range designator only, (see Device Nomenclature) Supply Voltage (V) Magnetic Field Release Point BRP (mT) 0 10 20 30 40 -14 -12 -10 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA TA = 25°C Figure 5-7. BRP vs VCC Ambient Temperature (°C) Magnetic Field Release Point BRP (mT) -50 -25 0 25 50 75 100 125 150 -14 -12 -10 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA VCC = 3.3 V Figure 5-8. BRP vs Temperature Supply Voltage (V) Hysteresis (mT) 0 10 20 30 40 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA TA = 25°C Figure 5-9. Hysteresis vs VCC Ambient Temperature (°C) Hysteresis (mT) -50 -25 0 25 50 75 100 125 150 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA VCC = 3.3 V Figure 5-10. Hysteresis vs Temperature Supply Voltage (V) Offset (mT) 0 10 20 30 40 -0.25 -0.125 0.125 0.25 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA TA = 25°C Figure 5-11. Offset vs VCC Ambient Temperature (°C) Offset (mT) -50 -25 0 25 50 75 100 125 150 -0.25 -0.125 0.125 0.25 DRV5013AD/ND DRV5013AG DRV5013BC DRV5013FA VCC = 3.3 V Figure 5-12. Offset vs Temperature DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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6 Detailed Description

6.1 Overview

The DRV5013 device is a chopper-stabilized Hall sensor with a digital latched output for magnetic sensing applications. The DRV5013 device can be powered with a supply voltage ranging from 2.5 V to 38 V, and continuously withstand –22 V reverse-battery conditions. The DRV5013 device does not operate when –22 V to 2.4 V is applied to the VCC pin (with respect to the GND pin). In addition, the device can withstand voltages up to 40 V for transient durations. The field polarity is defined as follows: a south pole near the marked side of the package induces a positive magnetic flux density on the sensor, while a north pole near the marked side of the package induces a negative magnetic flux density on the sensor. The output state is dependent on the magnetic flux density perpendicular to the package. A positive magnetic flux density greater than the operate point threshold, B OP, causes the output to pull low for the AD, AG, BC and FA device versions (release high for the inverted ND device version). A negative magnetic flux density less than the release point threshold, B RP, causes the output to release high for the AD, AG, BC and FA device versions (pull low for the inverted ND device version). Hysteresis is included in between the operate point and the release point to help prevent magnetic noise from accidentally tripping the output. An external pullup resistor is required on the OUT pin. The OUT pin can be pulled up to V CC, or to a different voltage supply. This allows for easier interfacing with controller circuits.

6.2 Functional Block Diagram

2.5 to 38 V (Optional) Hall Element www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRV5013

6.3 Feature Description

6.3.1 Field Direction Definition

Figure 6-1 illustrates that a positive magnetic flux density is defined as the presence of a south pole near the marked side of the package. 1 2 3 S N B > 0 mT S N B < 0 mT S N B > 0 mT S N B < 0 mT (Bottom view) SOT-23 (DBZ) TO-92 (LPG, LPE) 1 2 3 N = North pole, S = South pole Figure 6-1. Field Direction Definition

6.3.2 Device Output

If the device is powered on with a magnetic flux density between B RP and B OP, then the device output is indeterminate and can either be Hi-Z or Low. If the magnetic flux density is greater than B OP, then the output is pulled low (released high for the inverted ND version) . If the magnetic flux density is less than B RP, then the output is released high according to the output reference voltage and pullup resistor (pulled low for the inverted ND version). +B (mT) OUT BOP (South) BRP (North) 0mT BHYS Figure 6-2. Output State (FA, AD, AG, BC Versions) +B (mT) OUT BOP (South) BRP (North) 0mT BHYS Figure 6-3. Inverted Output State (ND Version) DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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6.3.3 Power-On Time

After applying V CC to the DRV5013 device, t on must elapse before the OUT pin is valid. During the power-up sequence, the output is Hi-Z. A pulse as shown in Figure 6-4 and Figure 6-5 occurs at the end of t on. This pulse can allow the host processor to determine when the DRV5013 output is valid after start-up. The power-up sequence, including the pulse, is the same for all device output versions (AD, AG, BC, FA, ND). Case 1, 2, 3 and 4 below show examples of valid outputs for the non-inverted output versions (AD, AG, BC, FA). In Case 1 (Figure 6-4) and Case 2 ( Figure 6-5), the output is defined assuming a constant magnetic flux density B > B OP and B < BRP. VCC BOP BRP t (s) B (mT) t (s) t (s) OUT Valid Output ton Figure 6-4. Case 1: Power On When B > BOP VCC BOP BRP t (s) B (mT) t (s) OUT t (s) Valid Output ton Figure 6-5. Case 2: Power On When B < BRP www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRV5013

If the device is powered on with the magnetic flux density BRP < B < BOP, then the device output is indeterminate and can either be Hi-Z or pulled low. During the power-up sequence, the output is held Hi-Z until ton has elapsed. At the end of t on, a pulse is given on the OUT pin to indicate that t on has elapsed. After t on, if the magnetic flux density changes such that B OP < B, the output is released. Case 3 ( Figure 6-6) and Case 4 ( Figure 6-7) show examples of this behavior. VCC BOP BRP t (s) B (mT) t (s) t (s) OUT Valid Output tdton Figure 6-6. Case 3: Power On When BRP < B < BOP, Followed by B > BOP VCC BOP BRP t (s) B (mT) t (s) t (s) OUT Valid Output tdton Figure 6-7. Case 4: Power On When BRP < B < BOP, Followed by B < BRP DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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6.3.4 Output Stage

Figure 6-8 shows the DRV5013 open-drain NMOS output structure, rated to sink up to 30 mA of current. For proper operation, use Equation 1 to calculate the value of pullup resistor R1. ref refV max V minR 1 30 mA 100 µAd d (1) The size of R1 is a tradeoff between the OUT rise time and the current when OUT is pulled low. A lower current is generally better, however faster transitions and bandwidth require a smaller resistor for faster switching. In addition, make sure that the value of R1 > 500 Ω so that the output driver can pull the OUT pin close to GND. Note Vref is not restricted to V CC. The allowable voltage range of this pin is specified in the Absolute Maximum Ratings. Gate Drive OCP OUT GND Vref ISINK Figure 6-8. NMOS Open-Drain Output Select a value for C2 based on the system bandwidth specifications as shown in Equation 2. BW 1 ¦

2 R 1 C2u S u u

(2) Most applications do not require this C2 filtering capacitor. www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRV5013

6.3.5 Protection Circuits

The DRV5013 device is fully protected against overcurrent and reverse-supply conditions. Table 6-1 lists a summary of the protection circuits. Table 6-1. Protection Circuit Summary FAULT CONDITION DEVICE DESCRIPTION RECOVERY FET overload (OCP) ISINK ≥ IOCP Operating Output current is clamped to IOCP IO < IOCP Load dump 38 V < VCC < 40 V Operating Device will operate for a transient duration VCC ≤ 38 V Reverse supply –22 V < VCC < 0 V Disabled Device will survive this condition VCC ≥ 2.5 V

6.3.5.1 Overcurrent Protection (OCP)

An analog current-limit circuit limits the current through the FET. The driver current is clamped to I OCP. During this clamping, the rDS(on) of the output FET is increased from the nominal value.

6.3.5.2 Load Dump Protection

The DRV5013 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand V CC = 40 V. No current-limiting series resistor is required for this protection.

6.3.5.3 Reverse Supply Protection

The DRV5013 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V). Note In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings specified in the Absolute Maximum Ratings.

6.4 Device Functional Modes

The DRV5013 device is active only when VCC is between 2.5 V and 38 V. When a reverse supply condition exists, the device is inactive. DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Application Information

The DRV5013 device is used in magnetic-field sensing applications.

7.2 Typical Applications

7.2.1 Standard Circuit

0.01 µF (minimum) OUT VCC 10 kŸ 680 pF (Optional) VCC Figure 7-1. Typical Application Circuit

7.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 7-1 as the input parameters. Table 7-1. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Supply voltage VCC 3.2 to 3.4 V System bandwidth ƒBW 10 kHz

7.2.1.2 Detailed Design Procedure

Table 7-2. External Components COMPONENT PIN 1 PIN 2 RECOMMENDED C1 VCC GND A 0.01-µF (minimum) ceramic capacitor rated for VCC C2 OUT GND Optional: Place a ceramic capacitor to GND R1 OUT REF(1) Requires a resistor pullup (1) REF is not a pin on the DRV5013 device, but a REF supply-voltage pullup is required for the OUT pin; the OUT pin may be pulled up to VCC. www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV5013

7.2.1.2.1 Configuration Example

ref refV max V minR 1 30 mA 100 µAd d (3) For this design example, use Equation 4 to calculate the allowable range of R1. 3.4 V 3.2 VR130 mA 100 µAd d (4) Therefore: 113 Ω ≤ R1 ≤ 32 kΩ (5) After finding the allowable range of R1 (Equation 5), select a value between 500 Ω and 32 kΩ for R1. Assuming a system bandwidth of 10 kHz, use Equation 6 to calculate the value of C2. BW 1 ¦ (6) For this design example, use Equation 7 to calculate the value of C2. 12 10 kHz 2 R 1 C2u S u u (7) An R1 value of 10 kΩ and a C2 value less than 820 pF satisfy the requirement for a 10-kHz system bandwidth. A selection of R1 = 10 kΩ and C2 = 680 pF would cause a low-pass filter with a corner frequency of 23.4 kHz.

7.2.1.3 Application Curves

R1 = 10 kΩ pull-up No C2 Figure 7-2. 10-kHz Switching Magnetic Field OUT R1 = 10-kΩ pull-up C2 = 680 pF Figure 7-3. 10-kHz Switching Magnetic Field DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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Frequency (Hz) Magnitude (dB) 100 1000 10000 100000 -14 -12 -10 D011 R1 = 10-kΩ pull-up C2 = 680 pF Figure 7-4. Low-Pass Filtering

7.2.2 Alternative Two-Wire Application

For systems that require minimal wire count, the device output can be connected to V CC through a resistor, and the total supplied current can be sensed near the controller. OUT VCC GND 3 2 1 Controller Current sense Figure 7-5. 2-Wire Application Current can be sensed using a shunt resistor or other circuitry.

7.2.2.1 Design Requirements

Table 7-3 lists the related design parameters. Table 7-3. Design Parameters DESIGN PARAMETER REFERENCE EXAMPLE VALUE Supply voltage VCC 12 V OUT resistor R1 1 kΩ Bypass capacitor C1 0.1 µF Current when B < BRP IRELEASE About 3 mA Current when B > BOP IOPERATE About 15 mA www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRV5013

7.2.2.2 Detailed Design Procedure

When the open-drain output of the device is high-impedance, current through the path equals the I CC of the device (approximately 3 mA). When the output pulls low, a parallel current path is added, equal to V CC / (R1 + r DS(on)). Using 12 V and 1 k Ω, the parallel current is approximately 12 mA, making the total current approximately 15 mA. The local bypass capacitor C1 should be at least 0.1 µF, and a larger value if there is high inductance in the power line interconnect.

7.3 Power Supply Recommendations

The DRV5013 device is designed to operate from an input voltage supply (VM) range between 2.5 V and 38 V. A 0.01-µF (minimum) ceramic capacitor rated for V CC must be placed as close to the DRV5013 device as possible. Larger values of the bypass capacitor may be needed to attenuate any significant high-frequency ripple and noise components generated by the power source. TI recommends limiting the supply voltage variation to less than 50 mVPP.

7.4 Layout

7.4.1 Layout Guidelines

The bypass capacitor should be placed near the DRV5013 device for efficient power delivery with minimal inductance. The external pullup resistor should be placed near the microcontroller input to provide the most stable voltage at the input; alternatively, an integrated pullup resistor within the GPIO of the microcontroller can be used. Generally, using PCB copper planes underneath the DRV5013 device has no effect on magnetic flux, and does not interfere with device performance. This is because copper is not a ferromagnetic material. However, If nearby system components contain iron or nickel, they may redirect magnetic flux in unpredictable ways.

7.4.2 Layout Example

Figure 7-6. DRV5013 Layout Example DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Device Nomenclature

Figure 8-1 shows a legend for reading the complete orderable part numbers for the DRV5013. (DBZ)(AD)DRV5013 Prefix DRV5013: Digital latch Hall sensor (Q) (R) () AEC-Q100 Q1: Automotive qualification Blank: Non-auto Package DBZ: 3-pin SOT-23 LPG: 3-pin TO-92 LPE: 3-pin TO-92 Temperature Range Q: –40 to 125°C E: –40 to 150°C BOP/BRP FA: 1.3/–1.3 mT AD: 2.7/–2.7 mT ND: 2.7/–2.7 mT, Inverted Output State AG: 6/–6 mT BC: 12/–12 mT Tape and Reel R: 3000 pcs/reel T: 250 pcs/reel M: 3000 pcs/box (ammo) Blank: 1000 pcs/bag (bulk) Figure 8-1. Device Nomenclature

8.1.2 Device Markings

Figure 8-2. SOT-23 (DBZ) Package (Bottom view) 1 2 3 Marked Side Front Marked Side 1 2 3 Figure 8-3. TO-92 (LPG, LPE) Package

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DRV5013

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision L (February 2023) to Revision M (June 2024) Page

• Added graphs to the Typical Characteristics section to include the DRV5013ND and DRV5013FA
• Added text to the Overview section to highlight the differences between the inverted and non-inverted output
• Added text to the Device Output section to highlight the differences between the inverted and non-inverted
• Added text to the Power-On Time section to highlight the differences between the inverted and non-inverted Changes from Revision K (August 2019) to Revision L (February 2023) Page
• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation Changes from Revision J (June 2019) to Revision K (August 2019) Page
• Changed TA to show existing range is for Q version device in the Recommended Operating Conditions table4
• Changed ICC test condition for TA from 125 to TA,MAX to highlight the differences between the E and Q DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV5013

• Changed rDS(on) test condition for TA from 125 to TA,MAX to highlight the difference between the E and Q
• Changed all test conditions for TA max from 125 to TA,MAX to highlight difference between the E and Changes from Revision I (August 2018) to Revision J (June 2019) Page Changes from Revision H (September 2016) to Revision I (August 2018) Page Changes from Revision G (August 2016) to Revision H (September 2016) Page Changes from Revision F (May 2016) to Revision G (August 2016) Page
• Changed the maximum BOP and the minimum BRP for the FA version in the Magnetic Characteristics table... 5 Changes from Revision E (February 2016) to Revision F (May 2016) Page Changes from Revision D (December 2015) to Revision E (February 2016) Page Changes from Revision C (September 2014) to Revision D (June 2015) Page Changes from Revision B (July 2014) to Revision C (September 2014) Page
• Updated the output rise and fall time typical values and removed max values in Switching Characteristics ....5 www.ti.com DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DRV5013

Changes from Revision A (March 2014) to Revision B (June 2014) Page

• Changed IOCP MIN and MAX values from 20 and 40 to 15 and 45, respectively, in the Electrical
• Changed the MIN value for the ±2.3 mT BRP parameter from –4 to –5 in the Magnetic Characteristics table...5 Changes from Revision * (March 2014) to Revision A (March 2014) Page
• Deleted Output pin current and changed VCCmax to VCC after the voltage ramp rate for the supply voltage....4
• Changed the MIN value for the ±2.3 mt BRP parameter from +2.3 to –2.3 in the Magnetic Characteristics table
• Deleted condition statement from the Typical Characteristics and changed all TJ to TA in the graph
• Deleted Number from the Power-On Time case names; added conditions to captions of case timing
• Added the C2 not required for most applications text after the second equation in the Output Stage section.13
• Changed IO to ISINK in condition statement of FET overload fault condition in Reverse Supply Protection

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DRV5013 SLIS150M – MARCH 2014 – REVISED JUNE 2024 www.ti.com

22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV5013

www.ti.com 27-Jun-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV5013ADQDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 (+NLAD, 13AD, 1J52 Samples DRV5013ADQLPG ACTIVE TO-92 LPG 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 125 +NLAD Samples DRV5013ADQLPGM ACTIVE TO-92 LPG 3 3000 RoHS & Green SN N / A for Pkg Type -40 to 125 +NLAD Samples DRV5013AGQDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 (+NLAG, 13AG, 1IW2 Samples DRV5013AGQLPG ACTIVE TO-92 LPG 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 125 +NLAG Samples DRV5013AGQLPGM ACTIVE TO-92 LPG 3 3000 RoHS & Green SN N / A for Pkg Type -40 to 125 +NLAG Samples DRV5013BCELPE ACTIVE TO-92 LPE 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 150 1UVJ Samples DRV5013BCELPEM ACTIVE TO-92 LPE 3 3000 RoHS & Green SN N / A for Pkg Type -40 to 150 1UVJ Samples DRV5013BCQDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green NIPDAUAG | SN Level-1-260C-UNLIM -40 to 125 (+NLBC, 1IX2) Samples DRV5013BCQLPG ACTIVE TO-92 LPG 3 1000 RoHS & Green SN N / A for Pkg Type -40 to 125 +NLBC Samples DRV5013BCQLPGM ACTIVE TO-92 LPG 3 3000 RoHS & Green SN N / A for Pkg Type -40 to 125 +NLBC Samples DRV5013FAQDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 (+NLFA, 1IZ2) Samples DRV5013NDQDBZR ACTIVE SOT-23 DBZ 3 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 13ND Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

www.ti.com 27-Jun-2024 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DRV5013 :

• Automotive : DRV5013-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Feb-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV5013ADQDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013AGQDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013BCQDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 DRV5013FAQDBZR SOT-23 DBZ 3 3000 180.0 180.0 18.0 DRV5013FAQDBZR SOT-23 DBZ 3 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.20

0.08 TYP

0.25 2.64 2.10

1.12 MAX

0.10

0.01 TYP

3X 0.5 0.3 0.6

0.2 TYP

1.9 0.95 0 -8 TYP A 3.04 2.80 B1.4 1.2 (0.95) (0.15) (0.125) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/E 06/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length. 4. Support pin may differ or may not be present. 5. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side

0.2 C A B

0.1 C SCALE 4.000 ALTERNATIVE PACKAGE SINGULATION VIEW

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/E 06/2024 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/E 06/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG

www.ti.com PACKAGE OUTLINE 4.1 3.9 16.0 15.6 3X 0.48 0.33 2X 1.27 0.05 3.25 3.05 3X 0.51 0.33 3X 0.51 0.40 2X (45 ) 0.86 0.66 1.62 1.42 2.64 2.44 2.68 2.28 5.05 MAX (0.55) 3X (0.8) 4224358/A 06/2018 TO-92 - 5.05 mm max heightLPE0003A TRANSISTOR OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 3 1 2 3 SCALE 1.300

www.ti.com EXAMPLE BOARD LAYOUT TYP ALL AROUND

0.05 MAX

TYP(1.07) (1.7) (1.27) (2.54) 2X (1.7) 3X ( 0.75) VIA 4224358/A 06/2018 TO-92 - 5.05 mm max heightLPE0003A TRANSISTOR OUTLINE LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE:20X METAL TYP OPENING SOLDER MASK 1 32 METAL2X SOLDER MASK OPENING

www.ti.com TAPE SPECIFICATIONS 0 1 0 1 12.9 12.5 6.55 6.15 13.0 12.4 2.5 MIN 6.5 5.5 3.8-4.2 TYP 9.5 8.5 19.0 17.5

1 MAX21

0.45 0.35 0.25 0.15 TO-92 - 5.05 mm max heightLPE0003A TRANSISTOR OUTLINE 4224358/A 06/2018

www.ti.com PACKAGE OUTLINE 4.1 3.9 15.5 15.1 3X 0.48 0.35 2X 1.27 0.05 3.25 3.05 3X 0.51 0.36 3X 0.55 0.40 2X (45 ) 0.86 0.66 1.62 1.42 2.64 2.44 2.68 2.28 5.05 MAX (0.5425) 3X (0.8) 4221343/C 01/2018 TO-92 - 5.05 mm max heightLPG0003A TRANSISTOR OUTLINE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 1 3 1 2 3 SCALE 1.300

www.ti.com EXAMPLE BOARD LAYOUT TYP ALL AROUND TYP(1.07) (1.7) (1.27) (2.54) 2X (1.7) 3X ( 0.75) VIA 4221343/C 01/2018 TO-92 - 5.05 mm max heightLPG0003A TRANSISTOR OUTLINE LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE:20X METAL TYP OPENING SOLDER MASK 1 32 METAL2X SOLDER MASK OPENING

www.ti.com TAPE SPECIFICATIONS 0 1 0 1 12.9 12.5 6.55 6.15 13.0 12.4

2.5 MIN

6.5 5.5 3.8-4.2 TYP 9.5 8.5 19.0 17.5 0.45 0.35 0.25 0.15 TO-92 - 5.05 mm max heightLPG0003A TRANSISTOR OUTLINE 4221343/C 01/2018

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