DRV401AMDWPREP

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www.ti.com SBVS104 JANUARY 2008 SENSOR SIGNAL CONDITIONING IC FOR CLOSED-LOOP MAGNETIC CURRENT SENSOR AND MEDICAL (VAC) One Assembly/Test Site Single Supply: V One Fabrication Site Power Output: H-Bridge Available in Military C/125 Designed For Driving Inductive Loads Temperature Range (1) Excellent DC Precision Extended Product Life Cycle Wide System Bandwidth Extended Product-Change Notification High-Resolution, Low-Temperature Drift Product Traceability Built-In Degauss System Extensive Fault Detection External High-Power Driver Option Generator/Alternator Monitoring and Control Frequency and Voltage Inverters Motor Drive Controllers System Power Consumption Photovoltaic Systems (1) Custom temperature ranges available The DRV401 is designed to control and process signals from specific magnetic current sensors made by VACUUMSCHMELZE GmbH Co. KG (VAC). A variety of current ranges and mechanical configurations are available. Combined with a VAC sensor, the DRV401 monitors both ac and dc currents to high accuracy. Provided functions include: probe excitation, signal conditioning of the probe signal, signal loop amplifier, an H-bridge driver for the compensation coil, and an analog signal output stage that provides an output voltage proportional to the primary current. It offers overload and fault detection, as well as transient noise suppression. The DRV401 can directly drive the compensation coil or connect to external power drivers. Therefore, the DRV401 combines with sensors to measure small to very large currents. To maintain the highest accuracy, the DRV401 can demagnetize (degauss) the sensor at power-up and on demand. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

H−Bridge Driver VOUT REF IN ICOMP2 R S ICOMP1 Compensation Patents Pending. Diff Amp Timing, Error Detection, and Power Control Degauss VREF VREF GND+5V IS2 IS1 DRV401 IP Compensation Winding Magnetic Core Primary Winding Field Probe PWM PWM ABSOLUTE MAXIMUM RATINGS (1) DRV401-EP SBVS104 JANUARY 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR (2) PACKAGE MARKING DRV401 SO-20 DWP DRV401M (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage V Voltage (2) 0.5 V DD 0.5 V Differential amplifier (3) +10 V Signal Input terminals: Current at IS1 and IS2 mA Current (pins other than IS1 and IS2) (2) mA I COMP short circuit (4) +250 mA Operating junction temperature +150 C Storage temperature +150 C Pins IA IN1 and IA IN2 only kV Human body model ESD rating (HBM) All other pins kV (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current limited, except for the differential amplifier input pins. (3) These inputs are not internally protected against over voltage. The differential amplifier input pins must be limited to mA, max or max. (4) Power-limited; observe maximum junction temperature. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

(1) DRV401-EP www.ti.com SBVS104 JANUARY 2008 Boldface limits apply over the specified temperature range: T J C to +125 At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, and zero output current I COMP unless otherwise noted. DRV401 PARAMETER CONDITIONS UNITS MIN TYP MAX R L k Ω to 2.5 DIFFERENTIAL AMPLIFIER V REFIN 2.5 V OFFSET VOLTAGE V OS Offset voltage, RTO (2) (3) Gain V/V 0.01 0.1 mV dV OS /dT Drift, RTO (3) 0.1 µ C V OS Offset voltage, RTO (2) (3) Gain V/V 0.17 mV CMRR vs common-mode, RTO V to V REF 2.5 V 280 µ V/V PSRR vs power-supply, RTO V REF not included µ V/V SIGNAL INPUT Common-mode voltage range DD V SIGNAL OUTPUT Signal over-range indication V IN V step (3) (4) 2.5 to 3.5 µ s (OVER-RANGE), Delay (3) Voltage output swing from negative rail (3) I +2.5 mA, CMP trip level +48 +85 mV OVER-RANGE trip level Voltage putput swing from positive rail (3) I 2.5 mA, CMP trip level V DD V DD mV OVER-RANGE trip level I SC Short-circuit current (3) V OUT connected to GND mA V OUT connected to V DD +20 mA Gain, V OUT IN_DIFF V/V Gain error 0.02 0.3 Gain error drift 0.1 ppm/ C Linearity error R L k Ω ppm (1) For Electromigration derating curves, please refer to http://focus.ti.com/pdfs/hirel/mltry/EP_Reliability_Information.pdf. (2) Parameter value referred to output (RTO). (3) See Typical Characteristics curves. (4) Total input resistance and comparator threshold current are inversely related. See Figure 2a. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range: T J C to +125 At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, and zero output current I COMP unless otherwise noted. DRV401 PARAMETER CONDITIONS UNITS MIN TYP MAX FREQUENCY RESPONSE BW 3dB Bandwidth (5) MHz SR Slew rate (5) CMVR V to V 6.5 µ s dV V to 1%, Settling time, large-signal (5) 0.9 µ s No external filter Settling time (5) dV 0.4 V to 0.01% µ s INPUT RESISTANCE Differential 16.5 23.5 k Ω Common-mode k Ω External reference input k Ω NOISE Output voltage noise density, f kHz, e n Compensation loop disabled 170 nV/ Hz RTO (5) COMPENSATION LOOP Probe f 250 kHz, DC STABILITY R LOAD Ω Deviation from 50% PWM, Offset error (6) 0.03 Pin gain L Deviation from 50% PWM, Offset error drift (5) 7.5 ppm/ C Pin gain L Gain, pin gain L (5) ICOMP1 ICOMP2 200 200 ppm/V PSRR Power-supply rejection ratio Probe loop f 250 kHz 500 ppm/V FREQUENCY RESPONSE Open-loop gain, two modes, 7.8 kHz Pin gain H/L dB PROBE COIL LOOP Input voltage clamp range Field probe current mA 0.7 0.7 to V DD V Internal resistor, IS1 or IS2 to V DD1 (5) Ω R HIGH Internal resistor, IS1 or IS2 to GND1 (5) Ω Resistance mismatch between IS1 and R LOW ppm of R HIGH R LOW 300 1500 ppm IS2 (5) Total input resistance (7) 134 200 Ω Comparator threshold current (7) mA Minimum probe loop half-cycle (5) 250 280 310 ns Probe loop minimum frequency 250 kHz No oscillation detect (error) suppression µ s COMPENSATION COIL DRIVER, H-BRIDGE Peak current (5) V ICOMP1 V ICOMP2 4.0V PP 250 mA Voltage swing Ω load 4.2 V PP Output common-mode voltage V DD2 V Wire break detect, threshold current (8) I COMP1 and I COMP2 railed mA VOLTAGE REFERENCE Voltage (5) No load 2.495 2.5 2.505 V Drift (5) No load ppm/ C (5) See Typical Characteristics curves. (6) For VAC sensors, 0.2% of PWM offset approximately corresponds to mA primary current offset per winding. (7) Total input resistance and comparator threshold current are inversely related. See Figure 2a. (8) See Compensation Driver section in Information. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

www.ti.com SBVS104 JANUARY 2008 ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range: T J C to +125 At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, and zero output current I COMP unless otherwise noted. DRV401 PARAMETER CONDITIONS UNITS MIN TYP MAX Drift (5) No load 2.491 2.509 V PSRR (5) 200 µ V/V Load to GND/V DD Load regulation (5) 0.15 mV/mA dl mA to mA I SC Short-circuit current REF OUT connected to V DD +20 mA REF OUT connected to GND mA DEMAGNETIZATION Duration See Timing Diagram 106 130 (7) ms DIGITAL I/O LOGIC INPUTS (DEMAG, GAIN, and CMOS Type Levels CCdiag Pins) Pull-up high current (CCdiag) 3.5 V IN V DD 160 µ A Pull-up low current (CCdiag) V IN 1.5 µ A Logic input leakage current V IN V DD 0.01 µ A Logic level, input: L/H 2.1/2.8 V Hysteresis 0.7 V OUTPUTS (ERROR AND OVER-RANGE Pins) Logic level, output: L mA sink 0.3 V Logic level, output: H No Internal Pull-Up OUTPUTS (PWM and PWM Pins) Push-pull type Logic level L mA sink 0.2 V Logic level H mA source DD 0.4 V POWER SUPPLY V DD Specified voltage range 4.5 5.5 V V RST Power-on reset threshold 1.8 V I COMP mA, I Q Quiescent current [I(V DD1 I(V DD2 6.8 mA Sensor not connected Brownout voltage level (9) V Brownout indication delay 135 µ s TEMPERATURE RANGE T J Specified range +125 C T J Operating range +150 C SO PowerPAD θ JA Package thermal resistance C/W surface-mount (10) (9) See Typical Characteristics curves. (10) See dissipation, layout considerations, and proper PCB soldering and heat-sinking technique. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

V DD1 OVER- RANGE CCdiag V DD2 ICOMP1 ICOMP2 GND2 1 2 Wide- Body SO- 20 Exposed Thermal Pad on Underside, Connect to GND1 DRV401-EP SBVS104 JANUARY 2008 www.ti.com PIN ASSIGNMENTS TERMINAL

DESCRIPTION

NO. ERROR Error flag: open-drain output, see the Error Conditions section. DMAG Control input, see the Demagnetization section. GAIN Control input for open-loop gain: low normal, high dB. REF OUT Output for internal 2.5 V reference voltage. REF IN Input for zero reference to differential amplifier. V OUT Output for differential amplifier. IA IN2 Noninverting input of differential amplifier. IA IN1 Inverting input of differential amplifier. GND2 Ground connection. Connect to GND1. I COMP2 Output of compensation coil driver. I COMP1 Output of compensation coil driver. V DD2 Supply voltage. Connect to V DD1 CCdiag Control input for wire-break detection: high enable. OVER-RANGE Open-drain output for over-range indication: low over-range. V DD1 Supply voltage. IS2 Probe connection GND1 Ground connection. IS1 Probe connection PWM PWM output from probe circuit (inverted). PWM PWM output from probe circuit. Exposed Thermal Pad Connect to GND1. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

0.04 0.03 0.02 0.01 −0.01 −0.02 −0.03 −0.04 4.34.1 IPRIM (A) DRV401 AND SENSOR: OFFSET vs SUPPL Y VOLTAGE VDD (V) M4645−X211M4645−X211 M4645−X080 100 0.1 0.1 VN (mV/√Hz) 1 10 100 1k 10k 100k DRV401 AND SENSOR: OUTPUT VOLTAGE NOISE DENSITY (Sensor M4645− X080, RSHUNT = 10W, Mode = Low) Frequency (Hz) 60Hz Line Frequency and Multiples (measured in a 60Hz environment) Divided Field Probe Frequency 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 Normalized Gain 100 1k 10k 100k 1M GAIN FLATNESS vs FREQUENCY (Measurements by Vacuumschmelze GmbH) Frequency (Hz) DRV401 with M4645−X600 Sensor DRV401 with M4645−X211 Sensor DRV401 with M4645−X080 Sensor DRV401 AND SENSOR: ABSOLUTE ERROR (Soldered DWP−20 with 1 Square−Inch Copper Pad) (Measurements by Vacuumschmelza GmbH) 0.3 0.2 0.1 -0.1 -0.2 -0.3 300200100-300 -200 -100 Primary Current (A) Absolute Error (A) TC (RSHUNT )±25ppm//C0095C. T =-50/C0095C T = +25/C0095C T = +85/C0095C T = +125/C0095C 20 60 1000 2V/div 2000A/div IPRIM 40 80 120 140 160 180 200 3A ICOMP OVERLOAD RECOVERY (Measurements by Vacuumschmelze GmbH) Time (µs) IPRIM Over−Range ERROR ERROR VOUT Over−Range VOUT NOTE: IPRIM = 3000A corresponds to ICOMP = 3A. −50 −45 −40 −35 −30 −25 −20 −15 −10 Population DIFFERENTIAL AMPLIFIER: VOLTAGE OFFSET PRODUCTION DISTRIBUTION Voltage Offset (µV) RTO DRV401-EP www.ti.com SBVS104 JANUARY 2008 At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, unless otherwise noted. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

−10 −15 −20 Gain (dB) 100 1k 10k 100k 1M 10M DIFFERENTIAL AMPLIFIER: GAIN vs FREQUENCY Frequency (Hz) −12 −16 −20 −25 25 75−50 Input VOS (µV) 0 50 100 125 150 DIFFERENTIAL AMPLIFIER: OFFSET VOLTAGE vs TEMPERATURE, RTO T emperature (/C0095C) Sample Average DIFFERENTIAL AMPLIFIER: OUTPUT VOLTAGE vs OUTPUT CURRENT 5.0 4.9 4.8 4.7 0.3 0.2 0.1 0 1 2 3 4 5 6 7 8 9 10 Load Current (mA) Output Voltage (V) −40/C0095C +85/C0095C +125/C0095C −40/C0095C+25/C0095C +85/C0095C+125/C0095C +25/C0095C 120 100 10 100 1k 10k 100k 1M PSRR and CMRR (dB) Frequency (Hz) CMRR PSRR DIFFERENTIAL AMPLIFIER: PSRR AND CMRR vs FREQUENCY 1000 100 100 Noise Density (nV/√Hz) 1k 10k 100k 1M DIFFERENTIAL AMPLIFIER: OUTPUT NOISE DENSITY Frequency (Hz) Autozero Frequency = 69kHz Sensor Not Running e n = 162nV/√Hz (average over 250Hz to 50kHz) −10 −15 −20 −25 −25−50 Short−Circuit Current (mA) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: SHORT−CIRCUIT CURRENT vs TEMPERATURE T emperature (/C0095C) VOUT Shorted to 0V VOUT Shorted to 5V DRV401-EP SBVS104 JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, unless otherwise noted. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 Voltage (V) 1µs/div DIFFERENTIAL AMPLIFIER: TA = −50/C0095C LARGE−SIGNAL STEP RESPONSE 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 Voltage (V) 1µs/div DIFFERENTIAL AMPLIFIER: TA = +25/C0095C LARGE−SIGNAL STEP RESPONSE 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 Voltage (V) 1µs/div DIFFERENTIAL AMPLIFIER: TA = +150/C0095C LARGE−SIGNAL STEP RESPONSE 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 -25-50 Over−Range Delay (ms) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: OVER−RANGE DELAY vs TEMPERATURE Temperature (/C0095C) At 5.0V V IN Step 0V to±1V Positive Over−Range Negative Over−Range 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 −25−50 Slew Rate (V/µs) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: POSITIVE SLEW RATE vs TEMPERATURE Temperature (/C0095C) At 5.0V −6.5 −6.6 −6.7 −6.8 −6.9 −7.0 −7.1 −7.2 −7.3 −7.4 −7.5 −25−50 Slew Rate (V/µs) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: NEGATIVE SLEW RATE vs TEMPERATURE T emperature (/C0095C) At 5.0V DRV401-EP www.ti.com SBVS104 JANUARY 2008 TYPICAL CHARACTERISTICS (continued) At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, unless otherwise noted. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

50.250 50.125 50.000 49.875 49.750 49.625 −25−50 R REF IN (kΩ ) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: REF IN RESISTANCE vs TEMPERATURE T emperature (/C0095C) 1k100 Gain VPWM AVERAGE /(VICOMP1 , VICOMP2 ) (dB) 10k 100k COMPENSATION LOOP: SMALL−SIGNAL GAIN Frequency (Hz) Pin Gain = Low Pin Gain = High 2000 1500 1000 500 −500 −1000 −1500 −2000 −25−50 Duty Cycle Error (ppm) 0 25 50 75 100 125 150 COMPENSATION LOOP: DUTY CYCLE ERROR vs TEMPERATURE Temperature (/C0095C) At 400kHz, 5.0V At 250kHz, 5.0V −200 −180 −160 −140 −120 −100 −80 −60 −40 −20 100 120 140 160 180 200 Population COMPENSATION LOOP: DC GAIN: DUTY CYCLE ERROR CHANGE Gain (ppm/V) VICOMP1 − VICOMP2 = 4.2V ILOAD = 210mA Gain Pin Low 35.0 32.5 30.0 27.5 25.0 −25−50 Probe Comparator Threshold Current (mA) 0 25 50 75 100 125 150 PROBE COMPARATOR THRESHOLD CURRENT vs TEMPERATURE Temperature (/C0095C) ICOMP OUTPUT SWING TO RAIL vs OUTPUT CURRENT 5.00 4.75 4.50 4.25 4.00 1.00 0.75 0.50 0.25 0 50 100 150 200 250 300 Output Current (mA) Output Swing (V) −50/C0095C+25/C0095C+125/C0095C −50/C0095C+25/C0095C+125/C0095C DRV401-EP SBVS104 JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, unless otherwise noted. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

−25−50 Resistance (Ω) 0 25 50 75 100 125 150 PROBE DRIVER: INTERNAL RESISTOR vs TEMPERATURE Temperature (/C0095C) Driver L Driver H 0.10 0.08 0.06 0.04 0.02 −25−50 Output Impedance Mismatch (Ω ) 0 25 50 75 100 125 150 OUTPUT IMPEDANCE MISMATCH OF IS1 AND IS2 vs TEMPERATURE T emperature (/C0095C) 2.5010 2.5008 2.5006 2.5004 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 −4−6 VREF (V) −2 0 2 4 6 VOLTAGE REFERENCE vs LOAD CURRENT ILOAD (mA) 2.4950 2.4955 2.4960 2.4965 2.4970 2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.5025 2.5030 2.5035 2.5040 2.5045 2.5050 Population VOLTAGE REFERENCE PRODUCTION DISTRIBUTION VREF (V) 2.525 2.520 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 −25−50 VREF (V) 0 25 50 75 100 125 150 VOLTAGE REFERENCE vs TEMPERATURE T emperature (/C0095C) 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0 42.5 45.0 47.5 50.0 Population VOLTAGE REFERENCE DRIFT PRODUCTION DISTRIBUTION Voltage Reference Drift (ppm//C0095C) DRV401-EP www.ti.com SBVS104 JANUARY 2008 TYPICAL CHARACTERISTICS (continued) At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, unless otherwise noted. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

OSCILLATOR PRODUCTION DISTRIBUTION Minimum Probe Loop Half− Cycle (ns) −200 −175 −150 −125 −100 −75 −50 −25 100 125 150 175 200 Population VOLTAGE REFERENCE POWER−SUPPL Y REJECTION PRODUCTION DISTRIBUTION PSR (µV/V) 310 305 300 295 290 285 280 275 270 265 260 255 250 −25−50 Minimum Probe Loop Half−Cycle (ns) 0 25 50 75 100 125 150 OSCILLATOR vs TEMPERATURE T emperature (/C0095C) 310 305 300 295 290 285 280 275 270 265 260 255 250 4.6 5.2 5.84.3 Minimum Probe Loop Half−Cycle (ns) 4.9 5.5 6.0 OSCILLATOR vs SUPPL Y VOLTAGE VDD (V) 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 −25−50 Brown−Out Voltage (V) 0 25 50 75 100 125 150 BROWN−OUT VOLTAGE vs TEMPERATURE Temperature (/C0095C) DRV401-EP SBVS104 JANUARY 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 C and V DD1 V DD2 V with external 100 kHz filter BW, unless otherwise noted. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

H−Bridge Driver VOUT REF IN ICOMP2 R S ICOMP1 Compensation Diff Amp Timing, Error Detection, and Power Control Degauss VREF VREF GND+5V IS1 IS2 DRV401 IP Compensation Winding Magnetic Core Primary Winding Field Probe FUNCTIONAL www.ti.com SBVS104 JANUARY 2008 USING THE DRV401 Closed-loop current sensors measure current over wide frequency ranges, including dc. These types of devices offer a contact-free method as well as excellent galvanic isolation performance combined with high resolution, accuracy, and reliability. At dc and in low-frequency ranges, the magnetic field induced from the current in the primary winding is compensated by a current flowing through a compensation winding. A magnetic field probe, located in the magnetic core loop, detects the magnetic flux. This probe delivers the signal to the amplifier that drives the current through the compensation coil, bringing the magnetic flux back to zero. This compensation current is proportional to the primary current, relative to the winding ratio. In higher frequency ranges, the compensation winding acts as the secondary winding in the current transformer, while the H-bridge compensation driver is rolled off and provides low output impedance. A difference amplifier senses the voltage across a small shunt resistor that is connected to the compensation loop. This difference amplifier generates the output voltage that is referenced to REFIN and is proportional to the primary current. Figure shows the DRV401 used as a compensation current sensor. Figure Principle of Compensation Current Sensor With the DRV401 The DRV401 operates from a single V supply. It is a complete sensor signal conditioning circuit that directly connects to the current sensor, providing all necessary functions for the sensor operation. The DRV401 provides magnetic field probe excitation, signal conditioning, and compensation coil driver amplification. In addition, it detects error conditions and handles overload situations. A precise differential amplifier allows translation of the compensation current into an output voltage using a small shunt resistor. A buffered voltage reference can be used for comparator, analog-to-digital converter (ADC), or bipolar zero reference voltages. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

(SENSOR) INTERFACE DRV401-EP SBVS104 JANUARY 2008 www.ti.com Dynamic error correction ensures high dc precision over temperature and long-term accuracy. The DRV401 uses analog signal conditioning; the internal loop filter and integrator are switched capacitor-based circuits. Therefore, the DRV401 allows combination with high-precision sensors for exceptional accuracy and resolution. The typical characteristic curve, DRV401 and Sensor Linearity, shows an example of the linearity and temperature stability achieved by the device. A demagnetization cycle can be initiated on demand or on power-up. This cycle reduces offset and restores high performance after a strong overload condition. An internal clock and counter logic generate the degauss function. The same clock controls power-up, overload detection and recovery, error, and time-out conditions. The DRV401 is built on a highly reliable CMOS process. Unique protection cells at critical connections enable the design to handle inductive energy. The magnetic field probe consists of an inductor wound on a soft magnetic core. The probe is connected between pins IS1 and IS2 of the probe driver that applies approximately V (the supply voltage) through resistors across the probe coil (see Figure 2a). The probe core reaches saturation at a current of typically mA (see Figure 2a). The comparator is connected to V REF by approximately 0.5 A current comparator detects the saturation and inverts the excitation voltage polarity, causing the probe circuit to oscillate in a frequency range of 250 kHz to 550 kHz. The oscillating frequency is a function of the magnetic properties of the probe core and its coil. The current rise rate is a function of the coil inductance: dI L V dT. However, the inductance of the field probe is low while its core material is in saturation (the horizontal part of the hysteresis curve) and is high at the vertical part of the hysteresis curve. The resulting inductance and the series resistance determine the output voltage and current versus time performance characteristic. Without external magnetic influence, the duty cycle is exactly 50% because of the inherent symmetry of the magnetic hysteresis; the probe inductor is driven from B saturation through the high inductance range to saturation and back again in a time-symmetric manner (see Figure 2b). If the core material is magnetized in one direction, a long and a short charge time result because the probe current through the inductors generates a field that either subtracts or adds to the flux in the probe core, either driving the probe core out of saturation or further into saturation (see Figure 2c). The current into the probe is limited by the voltage drops across the probe driver resistors. The DRV401 continuously monitors the logic magnetic flux polarity state. In the case of distortion noise and excessive overload that could fully saturate the probe, the overload control circuit recovers the probe loop. During an overload condition, the probe oscillation frequency increases to approximately 1.6 MHz until limited by the internal timing control. In an overload condition, the compensation current COMP driver cannot deliver enough current into the sensor secondary winding, and the magnetic flux in the sensor main core becomes uncompensated. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

a) Simplified probe interface circuit. The probe is connected between S1 and S2. b) Without an external magnetic field, the hysteresis curve is symmetrical and the probe loop generates 50% duty cycle. c) An external magnetic flux (H) generated from the primary current (IPRIM ) shifts the hysteresis curve of the magnetic field probe in the H-axis and the probe loop generates a nonsymmetrical duty cycle. B H 500ns/div 2V/div500mV/div V (IS1) V (PWM)/10 B H 500ns/div 2V/div500mV/div V (IS1) V (PWM)/10 55Ω IS2 IS1 Probe VDD1 PWMCMP18Ω VREF = 0.5V NOTE: MOS components function as switches only. 55Ω DRV401-EP www.ti.com SBVS104 JANUARY 2008 Figure Magnetic Probe, Hysteresis, and Duty Cycle Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

Sensor: 4 x 100 R SH = 10W Step Response 2kHz In V(Gain) = Low Channel 1: 2V/div Channels 2−4: 500mV/div V(1W× IPRIM /10) ICOMP1 ICOMP2 VOUT A current pulse of 0A to 18A (Ch 1) generates the two ICOMP signals (Ch 3 and Ch 4). Ch 2 shows the resulting output signal, VOUT . This test uses the M4645-X030 sensor, no bandwidth limitation, but a 20-sample average. DRV401-EP SBVS104 JANUARY 2008 www.ti.com The transition from normal operation to overload happens relatively slowly, because the inherent sensor transformer characteristics induce the initial primary current step, as shown in Figure As the transformer-induced secondary current starts to decay, the compensation feedback driver increases its output voltage to maintain the sensor core flux compensation at zero. When the system compensation loop reaches its driving limit, the rising magnetic flux causes one of the probe PWM half-periods to become shorter. The minimum half-period of the probe oscillation is limited by the internal timing to 280 ns, based on the properties of the VAC magnetic sensors. After three consecutive cycles of the same half-period being shorter than 280 ns, the DRV401 goes into overload-latch mode. The device stores the ICOMP driver output signal polarity and continues producing the skewed-duty cycle PWM signal. This action prevents the loss of compensation signal polarity information during very strong overloads. In this case, both PWM half-periods are short and approximately equal, because the field probe stays completely in one of the saturated regions. The overload-latch condition is removed after the primary current goes low enough for the I COMP driver to compensate, and both half-periods of the probe driver oscillation become longer than 280ns (the field probe comes out of the saturated region). Peak voltages and currents can be generated during normal operations as well as overload conditions. Therefore, both probe connection pins are internally protected against coupled energy from the magnetic core. Wiring between probe and IC inputs should be short and guarded against interference; see Layout Considerations .For reliable operation, error detection circuits monitor the probe operation: If the probe driver comparator (CMP) output stays low longer than µ the ERROR flag asserts active, and the compensation current COMP is set to zero. If the probe driver period is less than 275 ns on three consecutive pulses, the ERROR flag asserts active. See the Error Conditions section for more details. The outputs PWM and PWM represent the probe output signal as a differential PWM signal. It can drive external circuitry or be used for synchronous ripple reduction. The PWM signal from the probe excitation and sense stage is internally connected to a high-performance, switched-capacitor integrator followed by an integrating-differentiating filter. This filter converts the PWM signal into a filtered delta signal and prepares it for driving the analog compensation coil driver. The gain roll-off frequency of the filter stage is set to provide high dc gain and loop stability. If additional gain is added from external circuitry, the internal gain can be reduced by dB, asserting the GAIN pin high (see the External Compensation Coil Driver section). Figure Primary Current Step Response Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

www.ti.com SBVS104 JANUARY 2008 The compensation coil driver provides the driving current for the compensation coil. A fully differential driver stage offers high signal voltages to overcome the wire resistance of the coil with only V supply. The compensation coil is connected between I COMP1 and I COMP2 both generating an analog voltage across the coil (see Figure that turns into current from the wire resistance (and eventually from the inductance). The compensation current represents the primary current transformed by the turns ratio. A shunt resistor is connected in this loop and the high-precision difference amplifier translates the voltage from this shunt to an output voltage. Both compensation driver outputs provide low impedance over a wide frequency range to ensure smooth transitions between the closed-loop compensation frequency range and the high-frequency range, where the primary winding directly couples the primary current into the compensation coil at a rate set by the winding ratio. The two compensation driver outputs are designed with protection circuitry to handle inductive energy. However, additional external protection diodes might be necessary for high current sensors. For reliable operation, a wire break in the compensation circuit can be detected. If the feedback loop is broken, the integrating filter drives the outputs I COMP1 and I COMP2 to the opposite rails. With one of these pins coming within 300 mV to ground, a comparator tests for a minimum current flowing between I COMP1 and I COMP2 If this current stays below the threshold current level for at least 100 µ the ERROR pin is asserted active (low). The threshold current level for this test is less than mA at C and mA at if the I COMP pins are fully railed (see the Typical Characteristics). For sensors with high winding resistance (compensation coil resistance R SHUNT or connected to an external compensation driver, this function should be disabled by pulling the CCdiag pin low. Where: V OUT equals the peak voltage between I COMP1 and I COMP2 at a 65mA drive current. R MAX equals the sum of the coil and the shunt resistance. An external driver for the compensation coil can be connected to the I COMP1 and I COMP2 outputs. To prevent a wire break indication, CCdiag has to be asserted low. An external driver can provide both a higher drive voltage and more drive current. It also moves the power dissipation to the external transistors, thereby allowing a higher winding resistance in the compensation coil and more current. Figure shows a block diagram of an external compensation coil driver. To drive the buffer, either one or both I COMP outputs can be used. Note, however, that the additional voltage gain could cause instability of the loop. Therefore, the internal gain can be reduced by approximately dB by asserting the GAIN pin high. R SHUNT is connected to GND to allow for a single-ended external compensation driver. The differential amplifier can continue to sense the voltage, and used for the gain and over-range comparator or ERROR flag. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

R SHUNT ICOMP1 ICOMP2 SHUNT SENSE AMPLIFIER 4 /C0043R 2 R 1 /C0043R 4 /C0041R 5 R SHUNT /C0041R 3 DRV401-EP SBVS104 JANUARY 2008 www.ti.com Figure DRV401 With External Compensation Coil Driver and R SHUNT Connected to GND The differential (H-bridge) driver arrangement for the compensation coil requires a differential sense amplifier for the shunt voltage. This differential amplifier offers wide bandwidth and a high slew rate for fast current sensors. Excellent dc stability and accuracy result from an auto-zero technique. The voltage gain is V/V, set by precisely matched and stable internal SiCr resistors. Both inputs of the differential amplifier are normally connected to the current shunt resistor. This resistor adds to the internal (10 k Ω resistor, slightly reducing the gain in this leg. For best common-mode rejection (CMR), a dummy shunt resistor is placed in series with the REF IN pin to restore matching of both resistor dividers, as shown in Figure 5a. For gains of V/V: With R R R R SHUNT Typically, the gain error resulting from the resistance of R SHUNT is negligible; for dB of common-mode rejection, however, the match of both divider ratios needs to be better than 1/3000. The amplifier output can drive close to the supply rails, and is designed to drive the input of a SAR-type ADC; adding an RC low-pass filter stage between the DRV401 and the ADC is recommended. This filter not only limits the signal bandwidth but also decouples the high-frequency component of the converter input sampling noise from the amplifier output. For R F and C F values, refer to the specific converter recommendations in the specific product data sheet. Empirical evaluation may be necessary to obtain optimum results. The output can drive 100 pF directly and shows 50% overshoot with approximately nF capacitance. Adding R F allows much larger capacitive loads, as shown in Figure and Figure 5c. Note that with R F of only Ω the load capacitor should be either smaller than nF or larger than nF to avoid overshoot; with R F of Ω this transient area is avoided. The reference input (REF IN is the reference node for the exact output signal OUT Connecting REF IN to the reference output (REF OUT results in a live zero reference voltage of 2.5 Using the same reference for REF IN and the ADC avoids mismatch errors that exist between two reference sources. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

a) Internal difference amplifier with an example of a decoupling filter. 10µs/div 20mV/div b) VOUT of Figure 5a with R5 = 20Ω and CD = 100nF. 10µs/div 20mV/div c) VOUT of Figure 5a with R5 = 50Ω and CD = 10nF. R 2 40kΩ R 1 10kΩ R 4 40kΩ R 3 10kΩ R 5 Dummy Shunt Differential Amplifier R F 50Ω Decoupling, Low−Pass Filter REF IN Compensated REF IN ADC VOUT C F 10nF R SHUNT ICOMP2 DRV401 Differential Amplifier Section NOTE: R 5 is a dummy shunt resistor equal to 4x RSHUNT to compensate for RSHUNT and provide best CMR. OVER-RANGE COMPARATOR DRV401-EP www.ti.com SBVS104 JANUARY 2008 Figure Internal Difference Amplifier With Example of a Decoupling Filter High peak current can overload the differential amplifier connected to the shunt. The OVER-RANGE pin, an open-drain output, indicates an over-voltage condition for the differential amplifier by pulling low. The output of this flag is suppressed for µ preventing unwanted triggering from transients and noise. This pin returns to high as soon as the overload condition is removed (external pull-up required to return the pin high). This ERROR flag not only provides a warning about a signal clipping condition, but is also a window comparator output for actively shutting off circuits in the system. The value of the shunt resistor defines the operating window for the current. It sets the ratio between the nominal signal and the trip level of the Over-Range flag. The trip current of this window comparator is calculated using the following example: With a V supply, the output voltage swing is approximately 2.45 V (load and supply voltage-dependent). The gain of V/V allows an input swing of 0.6125 Thus, the clipping current is I MAX 0.6125 V/R SHUNT See the differential amplifier curve of the Typical Characteristics, Output Voltage vs Output Current The over-range condition is internally detected as soon as the amplifier exceeds its linear operating range, not just a set voltage level. Therefore, the error or the over-range comparator level is reliably indicated in fault conditions such as output shorts, low load or low supply conditions. As soon as the output cannot drive the voltage higher, the flag is activated. This configuration is a safety improvement over a voltage level comparator. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

2.5ms/div 10mV/div 10kW 1nF ±5V +2.5V REF OUT Test Circuit: DEMAGNETIZATION DRV401-EP SBVS104 JANUARY 2008 www.ti.com NOTE: The internal resistance of the compensation coil may prevent high compensation current from flowing because of I COMP driver overload. Therefore, the differential amplifier may not overload with this current. However, a fast rate of change of the primary current would be transmitted through transformer action and safely trigger the overload flag. The precision 2.5 V reference circuit offers low drift (typically ppm/K) and is used for internal biasing; it is also connected to the REF OUT pin. The circuit is intended as the reference point of the output signal to allow a bipolar signal around it. This output is buffered for low impedance and tolerates sink and source currents of mA. Capacitive loads can be directly connected, but generate ringing on fast load transients. A small series resistor of a few ohms improves the response, especially for a capacitive load in the range of µ Figure shows the transient load regulation with nF direct load. The reference source is part of the integrated circuit and referenced to GND2. Large current pulses driving the compensation coil can generate a voltage drop in the GND connection that would add on to the reference voltage. Therefore, a low impedance GND layout is critical to handle the currents and the high bandwidth of this IC. Figure Pulse Response Test Circuit and Scope Shot of Reference Iron cores are not immune to residual (remanence) magnetism. The residual remanence can produce a signal offset error, especially after strong current overload, which goes along with high magnetic field density. Therefore, the DRV401 includes a signal generator for a demagnetization cycle. The digital control pin, DEMAG, starts this cycle on demand after this pin is held high for at least 25.6 µ Shorter pulses are ignored. The cycle lasts for approximately 110 ms. During this time, the Error flag is asserted low to indicate that the output is not valid. When DEMAG is high during power-on, a demagnetization cycle immediately initiates (12 µ after power-on DD V). Holding DEMAG low avoids this cycle at power-up (see the Power-On and Brownout section). The probe circuit is in normal operation and oscillates during the demagnetization cycle. The outputs PWM and PWM are active accordingly. A demagnetization cycle can be aborted by pulling DEMAG low, filtered by µ s to ignore glitches (see Figure In a typical circuit, the DEMAG pin may be connected to the positive supply, which enables a degauss cycle every time the unit is powered on. The degauss cycle is based on an internal clock and counter logic. The maximum current is limited by the resistance of the connected coil in series with the shunt resistor. The DEMAG logic input requires a V CMOS-compatible signal. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

www.ti.com SBVS104 JANUARY 2008 Power-on is detected with the supply voltage going higher than V at V DD1 When DEMAG is high, a degauss cycle is started (see Figure 7a). During this time the ERROR flag remains low, indicating the not ready condition. Maintaining DEMAG low prevents this cycle, and the DRV401 starts operation approximately µ s after power-up. If no probe error conditions are detected within four full cycles (that is, the probe half-periods are shorter than µ s and longer than 280 ns), the compensation driver starts and the ERROR pin indicates the ready condition by going high, typically about µ s after power-up. NOTE: An external pull-up resistor is required to pull the ERROR pin high. Both supply pins DD1 and V DD2 should not differ by more than 100 mV for proper device operation. They are normally connected together or separately filtered (see Layout Considerations The DRV401 tests for low supply voltage with a brown-out voltage level of proper power conditions must be supplied. Good power-supply and low ESR bypass capacitors are required to maintain the supply voltage during the large current pulses that the DRV401 can drive. A critical voltage level is derived from the proper operation of the probe driver. The probe interface relies on a peak current flowing through the probe to trip the comparator. The probe resistance plus the internal resistance of the driver (see Electrical Characteristics specification, Probe Coil Loop, Internal Resistor sets the lower limit for the acceptable supply voltage. Voltage drops lasting less than ms are ignored. The probe error detection activates the ERROR pin as soon as proper oscillation fails for more than µ A low supply voltage condition, or brown-out, is detected at Short and light voltage drops of less than 100 µ s are ignored, provided the probe circuit continues to operate. If the probe no longer operates, the ERROR pin goes active. Signal overload recovery is only provided if the probe loop was not discontinued. A supply drop lasting longer than 100 µ s generates power-on reset. A voltage dip down to +1.8 V (for V DD1 also initiates a power-on reset. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

a) Demagnetization cycle on power-up. With power-up, the VOUT across the compensation coil centers around half the supply and then starts the cycle after the 4V threshold is exceeded. The ERROR flag resets to H after the cycle is completed. d) Abort of demagnetization cycle. The ERROR flag resets to H (as shown) and the output settles back to normal operation. b) Power-up without demagnetization. The probe oscillation V(IS1) starts just before ERROR resets — 15µs after the supply voltage crosses the 4V threshold. c) Demagnetization cycle on command. 20ms/div 5V/div 2V/div R SH = 10Ω VDD1 V(ICOMP2 ) VOUT V(ERROR)106ms 20ms/div 5V/div 2V/div VDD1 V(ERROR) V(IS1) V(ICOMP2 ) 42µs Initial setting upon closing of feedback loop. 20ms/div 5V/div 2V/div V(DEMAG) V(ICOMP2 ) VOUT V(ERROR)106ms R SH = 10Ω 500µs/div 5V/div 2V/div R SH = 10Ω V(DEMAG) V(ICOMP2 ) VOUT V(ERROR) 3.4ms DRV401-EP SBVS104 JANUARY 2008 www.ti.com Figure Demagnetization and Power-On Timing Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

www.ti.com SBVS104 JANUARY 2008 In addition to the Over-Range flag that indicates signal clipping in the output amplifier (differential amplifier), a system error flag is provided. The ERROR flag indicates conditions when the output voltage does not represent the primary current. It is active during a demagnetization cycle, during a power-fail or brown-out. It also goes active with an open or short-circuit in the probe loop. As soon as the error condition is no longer present and the circuit has returned to normal operation, the flag resets. Both the ERROR and Over-Range flags are open-drain logic outputs. They can be connected together for a wired-OR and require an external pull-up resistor for proper operation. The following conditions result in ERROR flag activation (ERROR asserts low): The probe comparator stays low for more than µ This condition occurs either if the probe coil connection is open or if the supply voltage dips to the level where the required saturation current cannot be reached. During the µ s timeout, the I COMP driver remains active but goes inactive thereafter. In case of recovery, ERROR is low and the ICOMP driver remains in reset for another 3.3 ms. The probe driver pulse-width is less than 280 ns for three consecutive periods. This condition indicates either a shorted field probe coil or a fully-saturated sensor at start-up. If this condition persists longer than µ s and then recovers, the ERROR flag remains low and ICOMP is in reset for another 3.3 ms. If the condition lasts less than µ the ERROR flag recovers immediately and the I COMP driver is not interrupted. During demagnetization, if the cycle is aborted early by pulling DEMAG low, the ERROR flag stays low for another 3.3 ms COMP is disabled during this time). An open compensation coil is detected (longer than 100 µ s). Note: the probe driver, the PWM signal filter and the I COMP driver continue to function in normal mode only the ERROR flag is asserted in this case. This condition indicates that not enough current is flowing in the I COMP driver output; this condition might be the result of a high-resistance compensation coil or the connection of an external driver. Detection of this condition can be disabled by setting the CCdiag pin low. At power-on after V DD1 crosses the V threshold, the ERROR flag is low for approximately µ A supply voltage low (brown-out) condition lasts longer than 100 µ Recovery is the same as power-up, either with or without a demag cycle. The inputs IA IN1 and IA IN2 require external protection to limit the voltage swing beyond V of the supply voltage. The driver outputs I COMP1 and I COMP2 can handle high current pulses protected by internal clamp circuits to the supply voltage. If repeated over-currents of large magnitudes are expected, connect external Schottky diodes to the supply rails. This external protection prevents current flowing into the die. The probe connections IS1 and IS2 are protected with diode clamps to the supply rails. In normal applications, no external protection is required. The maximum current must be limited to mA. All other pins offer standard protection-see the Absolute Maximum Ratings table. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

H−Bridge Driver CCdiag Amp V = 4 Logic: Timing, Error Detection, and Demagnetize Power Valid Bandgap Reference VDD2 GND2 VDD1 GND1 DRV401 VOUT REF IN OVER−RANGE REF OUT Probe Coil Driver and Comparator R 7 R 3 R 4 ERROR +5V DEMAG +5V C 2 C 3 C 4 IS1 IS2 PWM PWM VSW (PWM is in phase with IS1.) GAIN +5V ICOMP1 ICOMP2 IAIN2 IAIN1 R 1R 2 +5V +5V D 1 D 2 R 6 2.5V VSW Oscillator Reset 10MHz C 4 +5V IS2 S2S1 ICOMP IP Probe Coil K2K1 Compensation Coil Primary Winding Current Sensor Module Main CoreProbe Core R 5 DRV401-EP SBVS104 JANUARY 2008 www.ti.com The circuit shown in Figure offers an axample of a fully-connected current sensor system. Figure Basic Connection Circuit Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

www.ti.com SBVS104 JANUARY 2008 The connection example in Figure illustrates the few external components required for optimal performance. Each component is described in the following list: I P is the primary current to be measured; K and K connect to the compensation coil. and connect to the magnetic field probe. The dots indicate the winding direction on the sensor main core. R and R form the shunt resistor R SHUNT This resistance is split into two to allow for adjustments to the required R SHUNT value. The accuracy and temperature stability of these resistors are part of the final system performance. R and R together with C and C form a network that reduces the remaining probe oscillator ripple in the output signal. The component values depend on the sensor type and are tailored for best results. This network is not required for normal operation. R is the dummy shunt D resistor used to restore the symmetry of both differential amplifier inputs. R R SHUNT but the accuracy is less important. R and R are pull-up resistors connected to the logic outputs. C and C are decoupling capacitors. Use low ESR-type capacitors connected close to the pins. Use low impedance printed circuit board (PCB) traces, either avoiding vias (plated-through holes) or using multiple vias. A combination of a large( µ and a small 4.7 nF) capacitor are suggested. When selecting capacitors, make sure to consider the large pulse currents handled from the DRV401. D and D are protection diodes for the differential amplifier input. They are needed only if the voltage drop at R SHUNT exceeds V at the maximum possible peak current. The DRV401 operates with relatively large currents and fast current pulses, and offers wide-bandwidth performance. It is often exposed to large distortion energy from both the primary signal and the operating environment. Therefore, the wiring layout must provide shielding and low-impedance connections between critical points. Use low ESR capacitors for power-supply decoupling. Use a combination of a small capacitor and a large capacitor of µ F or larger. Use low-impedance tracks to connect the capacitors to the pins. Both grounds should be connected to a local ground plane. Both supplies can be connected together; however, best results are achieved with separate decoupling (to the local GND plane) and ferrite beads in series with the main supply. The ferrite beads decouple the DRV401, reducing interaction with other circuits powered from the same supply voltage source. The reference output is referred to GND2. A low-impedance, star-type connection is required to avoid the driver current and the probe current modulating the voltage drop on the ground track. The connection wires of the difference amplifier to the shunt must be low resistance and of equal length. For best accuracy, avoid current in this connection. Consider using a Kelvin Contact -type connection. The required resistance value can be set using two resistors. Wires and PCB traces for and should be very close or twisted. I COMP1 and I COMP2 should also be wired close together. To avoid capacitive coupling, run a ground shield between the S1/S2 and ICOMP wire pair or keep them distant from each other. The compensation driver outputs COMP are low frequency only; however, the primary signal (with high-frequency content present) is coupled into the compensation winding, the shunt, and the difference amplifier. Therefore, careful layout is recommended. The output of REF OUT and V OUT can drive some capacitive loads, but avoid large direct capacitive loads; these loads increase internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate any large capacitive load with a small series resistor. A small capacitor in the pF range can improve the transient response on a high resistive load. The exposed thermal pad on the bottom of the package must be soldered to GND because it is internally connected to the substrate, which must be connected to the most negative potential. It is also necessary to solder the exposed pad to the PCB to provide structural integrity and long-term reliability. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

www.ti.com Using the thermally-enhanced PowerPAD SO package dramatically reduces the thermal impedance from junction to case. This package is constructed using a down-set lead frame upon which the die is mounted, as shown in Figure and Figure 9b. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package. Figure shows the SO-20 package as an example. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The two outputs I COMP1 and I COMP2 are linear outputs. Therefore, the power dissipation on each output is proportional to the current multiplied by the internal voltage drop on the active transistor. For I COMP1 and I COMP2 this internal voltage drop is the voltage drop to V DD2 or GND, according to the current-conducting side of the output. Output short-circuits are particularly critical for the driver because the full supply voltage can be seen across the conducting transistor, and the current is not limited by anything other than the current density limitation of the FET. Permanent damage to the device can occur. The DRV401 does not include temperature protection or thermal shut-down. Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but board layout greatly influences overall heat dissipation. Table shows the thermal resistance JA for the two packages with the exposed thermal pad soldered to a normal PCB, as described in Technical Brief SLMA002, PowerPAD Thermally-Enhanced Package Documents are available for download at www.ti.com Table θ JA/JP Estimations According to EIA/JED51-7 SO θ JP (1) θ JA (2) Still Air θ JA with Forced Airflow (150lfm (3) (1) θ JP junction-to-pad thermal resistance, (2) θ JA junction-to-ambient thermal resistance, (3) lfm linear foot per minute. NOTE: All thermal models have an accuracy 20%. Measuring the temperature as close as possible to the exposed thermal pad is recommended. The relatively low thermal impedance, θ JP of less than C/W (with some additional C/W to the temperature test point on the PCB) allows good estimation of the junction temperature in the application. The thermal pad on the PCB should contain nine or more vias for the SO package, where the solder pad on the PCB can be larger than the exposed pad (for example, 6.6 mm mm) as recommended in the application literature noted previously. Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature well below +125 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): DRV401-EP

Bottom View (c) Side View (a) DIE DIE End View (b) Exposed Thermal Pad DRV401-EP www.ti.com SBVS104 JANUARY 2008 Figure SO-20 Package Example of Thermally Enhanced PowerPAD Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DRV401-EP

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DRV401AMDWPREP ACTIVE SO Power PAD DWP 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/08630-01XE ACTIVE SO Power PAD DWP 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DRV401AMDWPREP SO Power PAD PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV401AMDWPREP SO PowerPAD DWP 20 1000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2008 Pack Materials-Page 2

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