DRV401AIDWPG4

DRV401 BURR-BROWN | Alldatasheet

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Technical content

FEATURES

/C0068DESIGNED FOR SENSORS FROM VACUUMSCHMELZE (VAC) /C0068SINGLE SUPPLY: 5V /C0068POWER OUTPUT: H-Bridge /C0068DESIGNED FOR DRIVING INDUCTIVE LOADS /C0068EXCELLENT DC PRECISION /C0068WIDE SYSTEM BANDWIDTH /C0068HIGH-RESOLUTION, LOW-TEMPERATURE DRIFT /C0068BUILT-IN DEGAUSS SYSTEM /C0068EXTENSIVE FAULT DETECTION /C0068EXTERNAL HIGH-POWER DRIVER OPTION

APPLICATIONS

/C0068GENERATOR/ALTERNATOR MONITORING AND CONTROL /C0068FREQUENCY AND VOLTAGE INVERTERS /C0068MOTOR DRIVE CONTROLLERS /C0068SYSTEM POWER CONSUMPTION /C0068PHOTOVOLTAIC SYSTEMS

DESCRIPTION

The DRV401 is designed to control and process signals from specific magnetic current sensors made by Vacuumschmelze GmbH & Co. KG (VAC). A variety of current ranges and mechanical configurations are available. Combined with a VAC sensor, the DRV401 monitors both ac and dc currents to high accuracy. Provided functions include: probe excitation, signal conditioning of the probe signal, signal loop amplifier, an H-bridge driver for the compensation coil, and an analog signal output stage that provides an output voltage proportional to the primary current. It offers overload and fault detection, as well as transient noise suppression. The DRV401 can directly drive the compensation coil, or connect to external power drivers. Therefore, the DRV401 combines with sensors to measure small to very large currents. To maintain the highest accuracy, the DRV401 can demagnetize (degauss) the sensor at power-up and on demand. Integrator Filter Probe Interface H−Bridge Driver VOUT REF IN ICOMP2 R S ICOMP1 Compensation Patents Pending. Diff Amp Timing, Error Detection, and Power Control Degauss VREF VREF GND+5V IS2 IS1 DRV401 IP Compensation Winding Magnetic Core Primary Winding Field Probe PWM PWM DRV401 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 Sensor Signal Conditioning IC for Closed-Loop Magnetic Current Sensor www.ti.com Copyright  2006, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) Signal Input Terminals: ESD Rating: Human Body Model (HBM) (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2)Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must be current limited, except for the differential amplifier input pins. (3)These inputs are not internally protected against over voltage. The differential amplifier input pins must be limited to 5mA, max or ±10V, max. (4)Power-limited; observe maximum junction temperature. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING DRV401 QFN-20 (5mm x 5mm) RGW HAAQ DRV401 SO-20 DWP DRV401A (1)For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range: TJ = −40°C to +125°C. At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, and zero output current ICOMP , unless otherwise noted. DRV401 PARAMETER CONDITIONS MIN TYP MAX UNITS DIFFERENTIAL AMPLIFIER R L = 10kΩ to 2.5V, VREFIN = 2.5V OFFSET VOLTAGE Offset Voltage, RTO(1)(2) VOS Gain 4V/V ±0.01 ±0.1 mV Drift, RTO(2) dVOS /dT ±0.1 ±1(3) µV/°C vs Common-Mode, RTO CMRR −1V to +6V, VREF = 2.5V ±50 ±250 µV/V vs Power-Supply, RTO PSRR V REF not included ±4 ±50 µV/V SIGNAL INPUT Common-Mode Voltage Range −1 (VDD ) + 1 V SIGNAL OUTPUT Signal Over-Range Indication (OVER-RANGE), Delay(2) VIN = 1V Step, See Notes 2 and 3 2.5 to 3.5 µs Voltage Output Swing From Negative Rail(2), OVER-RANGE Trip Level I = +2.5mA, CMP Trip Level +48 +85 mV Voltage Output Swing From Positive Rail(2), OVER-RANGE Trip Level I = −2.5mA, CMP Trip Level VDD − 85 VDD − 48 mV Short-Circuit Current(2) ISC VOUT Connected To GND −18 mA VOUT Connected To VDD +20 mA Gain, VOUT /VIN_DIFF 4 V/V Gain Error ±0.02 ±0.3 % Gain Error Drift ±0.1 ppm/ °C Linearity Error R L = 1kΩ 10 ppm FREQUENCY RESPONSE Bandwidth(2) BW −3dB 2 MHz Slew Rate(2) SR CMVR = −1V to = +4V 6.5 V/µs Settling Time, Large-Signal(2) dV ± 2V to 1%, No External Filter 0.9 µs Settling Time(2) dV ± 0.4V to 0.01% 14 µs INPUT RESISTANCE Differential 16.5 20 23.5 kΩ Common-Mode 41 50 59 kΩ External Reference Input 41 50 59 kΩ NOISE Output Voltage Noise Density, f = 1kHz, RTO(2) en Compensation Loop Disabled 170 nV/√Hz COMPENSATION LOOP DC STABILITY Probe f = 250kHz, RLOAD = 20Ω Offset Error(4) Deviation from 50% PWM, Pin Gain = L 0.03 % Offset Error Drift(2) Deviation from 50% PWM, Pin Gain = L 7.5 ppm/ °C Gain, Pin Gain = L(2) |VICOMP1 | − |VICOMP2 | −200 25 200 ppm/V Power-Supply Rejection Ratio PSRR Probe Loop f = 250kHz 500 ppm/V FREQUENCY RESPONSE Open-Loop Gain, Two Modes, 7.8kHz Pin Gain H/L 24/32 dB PROBE COIL LOOP Input Voltage Clamp Range Field Probe Current < 50mA −0.7 to VDD + 0.7 V Internal Resistor, IS1 or IS2 to VDD1 (2) R HIGH 47 59 71 Ω Internal Resistor, IS1 or IS2 to GND1(2) R LOW 60 75 90 Ω Resistance Mismatch Between IS1 and IS2(2) ppm of RHIGH + RLOW 300 1500 ppm Total Input Resistance(3) 134 200 /C0087 Comparator Threshold Current(3) 22 28 34 mA Minimum Probe Loop Half-Cycle(2) 250 280 310 ns Probe Loop Minimum Frequency 250 kHz No Oscillation Detect (Error) Suppression 35 µs COMPENSATION COIL DRIVER, H-BRIDGE Peak Current(2) VICOMP1 − VICOMP2 = 4.0VPP 250 mA Voltage Swing 20Ω Load 4.2 VPP Output Common-Mode Voltage VDD2 /2 V Wire Break Detect, Threshold Current(5) ICOMP1 and ICOMP2 Railed 33 57 mA

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Boldface limits apply over the specified temperature range, TJ = −40°C to +125°C, with zero output current ICOMP . At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. DRV401 PARAMETER CONDITIONS MIN TYP MAX UNITS VOLTAGE REFERENCE Voltage(2) No Load 2.495 2.5 2.505 V Drift(2) No Load ±5 ±50 ppm/ °C PSRR (2) ±15 ±200 µV/V Load Regulation(2) Load to GND/VDD , dI = 0mA to 5mA 0.15 mV/mA Short-Circuit Current ISC REF OUT Connected to VDD +20 mA REF OUT Connected to GND −18 mA DEMAGNETIZATION Duration See Timing Diagram 106 130(3) ms DIGITAL I/O LOGIC INPUTS (DEMAG, GAIN, and CCdiag Pins) CMOS Type Levels Pull-Up High Current (CCdiag) 3.5 < VIN < VDD 160 µA Pull-Up Low Current (CCdiag) 0 < VIN < 1.5 5 µA Logic Input Leakage Current 0 < VIN < VDD 0.01 5 µA Logic Level, Input: L/H 2.1/2.8 V Hysteresis 0.7 V OUTPUTS (ERROR AND OVER-RANGE Pins) Logic Level, Output: L 4mA Sink 0.3 V Logic Level, Output: H No Internal Pull-Up OUTPUTS (PWM and PWM Pins) Push-Pull Type Logic Level L 4mA Sink 0.2 V Logic Level H 4mA Source (VDD ) − 0.4 V POWER SUPPLY Specified Voltage Range VDD 4.5 5 5.5 V Power-On Reset Threshold VRST 1.8 V Quiescent Current [I(VDD1 ) + I(VDD2 )] IQ ICOMP = 0mA, Sensor Not Connected 6.8 mA Brownout Voltage Level(2) 4 V Brownout Indication Delay 135 µs TEMPERATURE RANGE Specified Range TJ −40 +125 °C Operating Range TJ −50 +150 °C Package Thermal Resistance QFN Surface-Mount /C0113JA See Note 6 40 °C/W SO PowerPAD Surface-Mount /C0113JA See Note 6 27 °C/W (1)Parameter value referred to output (RTO). (2)See Typical Characteristic curves. (3)Total input resistance and comparator threshold current are inversely related. See Figure 2a. (4)For VAC sensors, 0.2% of PWM offset approximately corresponds to 10mA primary current offset per winding. (5)See Compensation Driver section in Applications Information. (6)See Applications Information section for information on power dissipation, layout considerations, and proper PCB soldering and heat-sinking technique.

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com PIN CONFIGURATIONS Top View RGW Top View DWP ERROR DEMAG GAIN REF OUT REF IN VDD1 OVER−RANGE CCdiag V DD2 ICOMP1 Exposed Thermal Pad on Underside, Connect to GND1 PWM PWM IS1 GND1 IS2 V OUT IAIN2 IAIN1 GND2 ICOMP2 QFN−20 (5mm x 5mm) PWM PWM ERROR DEMAG GAIN REF OUT REF IN VOUT IAIN2 IAIN1 IS1 GND1 IS2 V DD1 OVER−RANGE CCdiag V DD2 ICOMP1 ICOMP2 GND2 Wide−Body SO−20 Exposed Thermal Pad on Underside, Connect to GND1 PIN ASSIGNMENTS NAME NO. DESCRIPTION ERROR 1 Error flag: open-drain output, see the Error Conditions section. DEMAG 2 Control input, see the Demagnetization section. GAIN 3 Control input for open-loop gain: low = normal, high = −8dB. REF OUT 4 Output for internal 2.5V reference voltage. REF IN 5 Input for zero reference to differential amplifier. VOUT 6 Output for differential amplifier. IAIN2 7 Noninverting input of differential amplifier. IAIN1 8 Inverting input of differential amplifier. GND2 9 Ground connection. Connect to GND1. ICOMP2 10 Output 2 of compensation coil driver. ICOMP1 11 Output 1 of compensation coil driver. VDD2 12 Supply voltage. Connect to VDD1 . CCdiag 13 Control input for wire-break detection: high = enable. OVER−RANGE 14 Open-drain output for over-range indication: low = over-range. VDD1 15 Supply voltage. IS2 16 Probe connection 2. GND1 17 Ground connection. IS1 18 Probe connection 1. PWM 19 PWM output from probe circuit (inverted). PWM 20 PWM output from probe circuit. Exposed Thermal Pad — Connect to GND1.

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. 0.04 0.03 0.02 0.01 −0.01 −0.02 −0.03 −0.04 4.34.1 IPRIM (A) DRV401 AND SENSOR: OFFSET vs SUPPLY VOLTAGE VDD (V) M4645−X211M4645−X211 M4645−X080 100 0.1 0.1 VN (µV/√Hz) 1 10 100 1k 10k 100k DRV401 AND SENSOR: OUTPUT VOLTAGE NOISE DENSITY (Sensor M4645−X080, RSHUNT =1 0Ω,M o d e=L o w ) Frequency (Hz) 60Hz Line Frequency and Multiples (measured in a 60Hz environment) Divided Field Probe Frequency DRV401 AND SENSOR: ABSOLUTE ERROR (Soldered DWP−20 with 1 Square−Inch Copper Pad) (Measurements by Vacuumschmelza GmbH) 0.3 0.2 0.1 −0.1 −0.2 −0.3 300200100−300 −200 −100 Primary Current (A) Absolute Error (A) TC (RSHUNT )±25ppm//C0095C. T= −50/C0095C T=+ 2 5/C0095C T=+ 8 5/C0095C T=+ 1 2 5/C0095C 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 Normalized Gain 100 1k 10k 100k 1M GAIN FLATNESS vs FREQUENCY (Measurements by Vacuumschmelze GmbH) Frequency (Hz) DRV401 with M4645−X600 Sensor DRV401 with M4645−X211 Sensor DRV401 with M4645−X080 Sensor 20 60 1000 2V/div 2000A/div IPRIM 40 80 120 140 160 180 200 3A ICOMP OVERLOAD RECOVERY (Measurements by Vacuumschmelze GmbH) Time (µs) IPRIM Over−Range ERROR ERROR VOUT O ver−Range VOUT NOTE: IPRIM = 3000A corresponds to ICOMP =3 A . −50 −45 −40 −35 −30 −25 −20 −15 −10 Population DIFFERENTIAL AMPLIFIER: VOLTAGE OFFSET PRODUCTION DISTRIBUTION Voltage Offset (µV) RTO

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com TYPICAL CHARACTERISTICS (Continued) At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. −12 −16 −20 −25 25 75−50 Input VOS (µV) 0 50 100 125 150 DIFFERENTIAL AMPLIFIER: OFFSET VOLTAGE vs TEMPERATURE, RTO Te m pe r at u r e (/C0095C) Sample Average −10 −15 −20 Gain (dB) 100 1k 10k 100k 1M 10M DIFFERENTIAL AMPLIFIER: GAIN vs FREQUENCY Frequency (Hz) 120 100 10 100 1k 10k 100k 1M PSRR and CMRR (dB) Frequency (Hz) CMRR PSRR DIFFERENTIAL AMPLIFIER: PSRR AND CMRR vs FREQUENCY DIFFERENTIAL AMPLIFIER: OUTPUT VOLTAGE vs OUTPUT CURRENT 5.0 4.9 4.8 4.7 0.3 0.2 0.1 0123456789 1 0 Load Current (mA) Output Voltage (V) −40/C0095C +85/C0095C +125/C0095C −40/C0095C+25/C0095C +85/C0095C+125/C0095C +25/C0095C 1000 100 100 Noise Density (nV/√Hz) 1k 10k 100k 1M DIFFERENTIAL AMPLIFIER: OUTPUT NOISE DENSITY Frequency (Hz) Autozero Frequency = 69kHz Sensor Not Running en = 162nV/√Hz (average over 250Hz to 50kHz) −10 −15 −20 −25 −25−50 Short−Circuit Current (mA) 0 2 55 07 5 1 0 0 1 2 5 1 5 0 DIFFERENTIAL AMPLIFIER: SHORT−CIRCUIT CURRENT vs TEMPERATURE T emperature (/C0095C) VOUT S h o r t e dt o0 V VOUT S h o r t e dt o5 V

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com TYPICAL CHARACTERISTICS (Continued) At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 Voltage (V) 1µs/div DIFFERENTIAL AMPLIFIER: TA = −50/C0095C LARGE−SIGNAL STEP RESPONSE 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 Voltage (V) 1µs/div DIFFERENTIAL AMPLIFIER: TA =+ 2 5/C0095C LARGE−SIGNAL STEP RESPONSE 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 Voltage (V) 1µs/div DIFFERENTIAL AMPLIFIER: TA = +150/C0095C LARGE−SIGNAL STEP RESPONSE 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 −25−50 Over−Range Delay (µs) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: OVER−RANGE DELAY vs TEMPERATURE T emperature (/C0095C) At 5.0V VIN Step 0V to±1V Positive Over−Range Negative Over−Range 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 −25−50 Slew Rate (V/µs) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: POSITIVE SLEW RATE vs TEMPERATURE T emperature (/C0095C) At 5.0V −6.5 −6.6 −6.7 −6.8 −6.9 −7.0 −7.1 −7.2 −7.3 −7.4 −7.5 −25−50 Slew Rate (V/µs) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: NEGATIVE SLEW RATE vs TEMPERATURE T emperature (/C0095C) At 5.0V

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com TYPICAL CHARACTERISTICS (Continued) At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. 50.250 50.125 50.000 49.875 49.750 49.625 −25−50 R REF IN (kΩ ) 0 25 50 75 100 125 150 DIFFERENTIAL AMPLIFIER: REF IN RESISTANCE vs TEMPERATURE T emperature (/C0095C) 1k100 Gain VPWM AVERAGE /(VICOMP1 ,VICOMP2 )( d B ) 10k 100k COMPENSATION LOOP: SMALL−SIGNAL GAIN Frequency (Hz) P i nG a i n=L o w P i nG a i n=H i g h 2000 1500 1000 500 −500 −1000 −1500 −2000 −25−50 Duty Cycle Error (ppm) 0 25 50 75 100 125 150 COMPENSATION LOOP: DUTY CYCLE ERROR vs TEMPERATURE T emperature (/C0095C) At 400kHz, 5.0V At 250kHz, 5.0V −200 −180 −160 −140 −120 −100 −80 −60 −40 −20 100 120 140 160 180 200 Population COMPENSATION LOOP: DC GAIN: DUTY CYCLE ERROR CHANGE Gain (ppm/V) VICOMP1 − VICOMP2 =4 . 2 V ILOAD = 210mA Gain Pin Low ICOMP O U T P U TS W I N GT OR A I L vs OUTPUT CURRENT 5.00 4.75 4.50 4.25 4.00 1.00 0.75 0.50 0.25 0 50 100 150 200 250 300 Output Current (mA) Output Swing (V) −50/C0095C+25/C0095C+125/C0095C −50/C0095C+25/C0095C+125/C0095C 35.0 32.5 30.0 27.5 25.0 −25−50 Probe Comparator Threshold Current (mA) 0 25 50 75 100 125 150 PROBE COMPARATOR THRESHOLD CURRENT vs TEMPERATURE T emperature (/C0095C)

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com TYPICAL CHARACTERISTICS (Continued) At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. −25−50 Resistance (Ω) 0 25 50 75 100 125 150 PROBE DRIVER: INTERNAL RESISTOR vs TEMPERATURE T emperature (/C0095C) Driver L Driver H 0.10 0.08 0.06 0.04 0.02 −25−50 Output Impedance Mismatch (Ω) 0 25 50 75 100 125 150 OUTPUT IMPEDANCE MISMATCH OF IS1 AND IS2 vs TEMPERATURE T emperature (/C0095C) 2.5010 2.5008 2.5006 2.5004 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 −4−6 VREF (V) −2 0246 VOLTAGE REFERENCE vs LOAD CURRENT ILOAD (mA) 2.4950 2.4955 2.4960 2.4965 2.4970 2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 2.5025 2.5030 2.5035 2.5040 2.5045 2.5050 Population VOLTAGE REFERENCE PRODUCTION DISTRIBUTION VREF (V) 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 35.0 37.5 40.0 42.5 45.0 47.5 50.0 Population VOLTAGE REFERENCE DRIFT PRODUCTION DISTRIBUTION Voltage Reference Drift (ppm//C0095C) 2.525 2.520 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 2.475 −25−50 VREF (V) 0 2 55 07 5 1 0 0 1 2 5 1 5 0 VOLTAGE REFERENCE vs TEMPERATURE T emperature (/C0095C)

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com TYPICAL CHARACTERISTICS (Continued) At TA = +25°C and VDD1 = VDD2 = +5V with external 100kHz filter BW, unless otherwise noted. −200 −175 −150 −125 −100 −75 −50 −25 100 125 150 175 200 Population VOLTAGE REFERENCE POWER−SUPPL Y REJECTION PRODUCTION DISTRIBUTION PSR (µV/V) 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 Population OSCILLATOR PRODUCTION DISTRIBUTION Minimum Probe Loop Half− Cycle (ns) 310 305 300 295 290 285 280 275 270 265 260 255 250 −25−50 Minimum Probe Loop Half−Cycle (ns) 0 25 50 75 100 125 150 OSCILLATOR vs TEMPERATURE T emperature (/C0095C) 310 305 300 295 290 285 280 275 270 265 260 255 250 4.6 5.2 5.84.3 Minimum Probe Loop Half−Cycle (ns) 4.9 5.5 6.0 OSCILLATOR vs SUPPL Y VOLTAGE VDD (V) 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 −25−50 Brown−Out Voltage (V) 0 25 50 75 100 125 150 BROWN−OUT VOLTAGE vs TEMPERATURE T emperature (/C0095C)

provides low output impedance. shunt resistor that is connected to the compensation loop. compensation current sensor. Figure 1. Principle of Compensation Current Sensor with the DRV401

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com FUNCTIONAL DESCRIPTION The DRV401 operates from a single +5V supply. It is a complete sensor signal conditioning circuit that directly connects to the current sensor, providing all necessary functions for the sensor operation. The DRV401 provides magnetic field probe excitation, signal conditioning, and compensation coil driver amplification. In addition, it detects error conditions and handles overload situations. A precise differential amplifier allows translation of the compensation current into an output voltage using a small shunt resistor. A buffered voltage reference can be used for comparator, analog-to-digital converter (ADC), or bipolar zero reference voltages. Dynamic error correction ensures high dc precision over temperature and long-term accuracy. The DRV401 uses analog signal conditioning; the internal loop filter and integrator are switched capacitor-based circuits. Therefore, the DRV401 allows combination with high-precision sensors for exceptional accuracy and resolution. The typical characteristic curve, DRV401 and Sensor Linearity, shows an example of the linearity and temperature stability achieved by the device. A demagnetization cycle can be initiated on demand or on power-up. This cycle reduces offset and restores high performance after a strong overload condition. An internal clock and counter logic generate the degauss function. The same clock controls power-up, overload detection and recovery, error, and time-out conditions. The DRV401 is built on a highly reliable CMOS process. Unique protection cells at critical connections enable the design to handle inductive energy. MAGNETIC PROBE (SENSOR) INTERFACE The magnetic field probe consists of an inductor wound on a soft magnetic core. The probe is connected between pins IS1 and IS2 of the probe driver that applies approximately +5V (the supply voltage) through resistors across the probe coil (see Figure 2a). The probe core reaches saturation at a current of typically 28mA (see Figure 2a). The comparator is connected to V REF by approximately 0.5V. A current comparator detects the saturation and inverts the excitation voltage polarity, causing the probe circuit to oscillate in a frequency range of 250kHz to 550kHz. The oscillating frequency is a function of the magnetic properties of the probe core and its coil. The current rise rate is a function of the coil inductance: dI = L × V × dT. However, the inductance of the field probe is low while its core material is in saturation (the horizontal part of the hysteresis curve) and is high at the vertical part of the hysteresis curve. The resulting inductance and the series resistance determine the output voltage and current versus time performance characteristic. Without external magnetic influence, the duty cycle is exactly 50% because of the inherent symmetry of the magnetic hysteresis; the probe inductor is driven from −B saturation through the high inductance range to +B saturation and back again in a time-symmetric manner (see Figure 2b). If the core material is magnetized in one direction, a long and a short charge time result because the probe current through the inductors generates a field that either subtracts or adds to the flux in the probe core, either driving the probe core out of saturation or further into saturation (see Figure 2c). The current into the probe is limited by the voltage drops across the probe driver resistors. The DRV401 continuously monitors the logic magnetic flux polarity state. In the case of distortion noise and excessive overload that could fully saturate the probe, the overload control circuit recovers the probe loop. During an overload condition, the probe oscillation frequency increases to approximately 1.6MHz until limited by the internal timing control. In an overload condition, the compensation current (I COMP ) driver cannot deliver enough current into the sensor secondary winding, and the magnetic flux in the sensor main core becomes uncompensated.

a) Simplified probe interface circuit. The probe is connected between S1 and S2. symmetrical and the probe loop generates 50% duty cycle. H-axis and the probe loop generates a nonsymmetrical duty cycle. NOTE: MOS components function as switches only. Figure 2. Magnetic Probe, Hysteresis, and Duty Cycle

probe stays completely in one of the saturated regions. comes out of the saturated region). normal operations as well as overload conditions. protected against coupled energy from the magnetic core. guarded against interference; see Layout Considerations.

1. If the probe driver comparator (CMP) output stays low

the compensation current (ICOMP ) is set to zero.

1. If the probe driver period is less than 275ns on three

consecutive pulses, the ERROR flag asserts active. See the Error Conditions section for more details. Compensation Coil Driver section). VOUT . This test uses the M4645-X030 sensor, no bandwidth limitation, but a 20-sample average. Figure 3. Primary Current Step Response

coil at a rate set by the winding ratio. pins are fully railed (see the Typical Characteristics). R MAX equals the sum of the coil and the shunt resistance. wire break indication, CCdiag has to be asserted low. Figure 4. DRV401 with External Compensation Coil Driver and RSHUNT Connected to GND

required to return the pin high). The gain of 4V/V allows an input swing of ±0.6125V. Characteristics, Output Voltage vs Output Current. such as output shorts, low load or low supply conditions. improvement over a voltage level comparator. differential amplifier may not overload with this current. and tolerates sink and source currents of ±5mA. transient load regulation with 1nF direct load. connection that would add on to the reference voltage. handle the currents and the high bandwidth of this IC. Figure 6. Pulse Response Test Circuit and Scope Shot of Reference

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com DEMAGNETIZATION Iron cores are not immune to residual (remanence) magnetism. The residual remanence can produce a signal offset error, especially after strong current overload, which goes along with high magnetic field density. Therefore, the DRV401 includes a signal generator for a demagnetization cycle. The digital control pin, DEMAG, starts this cycle on demand after this pin is held high for at least 25.6µs. Shorter pulses are ignored. The cycle lasts for approximately 110ms. During this time, the Error flag is asserted low to indicate that the output is not valid. When DEMAG is high during power-on, a demagnetization cycle immediately initiates (12µs) after power-on (V DD > 4V). Holding DEMAG low avoids this cycle at power-up (see the Power-On and Brownout section). The probe circuit is in normal operation and oscillates during the demagnetization cycle. The outputs PWM and PWM are active accordingly. A demagnetization cycle can be aborted by pulling DEMAG low, filtered by 25µs to ignore glitches (see Figure 7). In a typical circuit, the DEMAG pin may be connected to the positive supply, which enables a degauss cycle every time the unit is powered on. The degauss cycle is based on an internal clock and counter logic. The maximum current is limited by the resistance of the connected coil in series with the shunt resistor. The DEMAG logic input requires a +5V CMOS-compatible signal. POWER-ON AND BROWNOUT Power-on is detected with the supply voltage going higher than 4V at VDD1 . When DEMAG is high, a degauss cycle is started (see Figure 7a). During this time the ERROR flag remains low, indicating the not ready condition. Maintaining DEMAG low prevents this cycle, and the DRV401 starts operation approximately 32µs after power-up. If no probe error conditions are detected within four full cycles (that is, the probe half-periods are shorter than 32µs and longer than 280ns), the compensation driver starts and the ERROR pin indicates the ready condition by going high, typically about 42µs after power-up. NOTE: an external pull-up resistor is required to pull the ERROR pin high. Both supply pins (V DD1 and VDD2 ) should not differ by more than 100mV for proper device operation. They are normally connected together or separately filtered (see Layout Considerations). The DRV401 tests for low supply voltage with a brown-out voltage level of +4V; proper power conditions must be supplied. Good power-supply and low ESR bypass capacitors are required to maintain the supply voltage during the large current pulses that the DRV401 can drive. A critical voltage level is derived from the proper operation of the probe driver. The probe interface relies on a peak current flowing through the probe to trip the comparator. The probe resistance plus the internal resistance of the driver (see Electrical Characteristics specification, Probe Coil Loop, Internal Resistor) sets the lower limit for the acceptable supply voltage. Voltage drops lasting less than 31µs are ignored. The probe error detection activates the ERROR pin as soon as proper oscillation fails for more than 32µs. A low supply voltage condition, or brown-out, is detected at +4V. Short and light voltage drops of less than 100µs are ignored, provided the probe circuit continues to operate. If the probe no longer operates, the ERROR pin goes active. Signal overload recovery is only provided if the probe loop was not discontinued. A supply drop lasting longer than 100µs generates power-on reset. A voltage dip down to +1.8V (for V DD1 ) also initiates a power-on reset.

starts the cycle after the 4V threshold is exceeded. The ERROR flag resets to H after the cycle is completed. c) Demagnetization cycle on command. Figure 7. Demagnetization and Power-On Timing

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com ERROR CONDITIONS In addition to the Over-Range flag that indicates signal clipping in the output amplifier (differential amplifier), a system error flag is provided. The ERROR flag indicates conditions when the output voltage does not represent the primary current. It is active during a demagnetization cycle, during a power-fail or brown-out. It also goes active with an open or short-circuit in the probe loop. As soon as the error condition is no longer present and the circuit has returned to normal operation, the flag resets. Both the ERROR and Over-Range flags are open-drain logic outputs. They can be connected together for a wired-OR and require an external pull-up resistor for proper operation. The following conditions result in ERROR flag activation (ERROR asserts low): 1. The probe comparator stays low for more than 32µs. This condition occurs either if the probe coil connection is open or if the supply voltage dips to the level where the required saturation current cannot be reached. During the 32µs timeout, the I COMP driver remains active but goes inactive thereafter. In case of recovery, ERROR is low and the I COMP driver remains in reset for another 3.3ms. 2. The probe driver pulse-width is less than 280ns for three consecutive periods. This condition indicates either a shorted field probe coil or a fully-saturated sensor at start-up. If this condition persists longer than 25µs and then recovers, the ERROR flag remains low and I COMP is in reset for another 3.3ms. If the condition lasts less than 25µs, the ERROR flag recovers immediately and the ICOMP driver is not interrupted. 3. During demagnetization, if the cycle is aborted early by pulling DEMAG low, the ERROR flag stays low for another 3.3ms (ICOMP is disabled during this time). 4. An open compensation coil is detected (longer than 100µs). Note: the probe driver, the PWM signal filter and the ICOMP driver continue to function in normal mode—only the ERROR flag is asserted in this case. This condition indicates that not enough current is flowing in the I COMP driver output; this condition might be the result of a high-resistance compensation coil or the connection of an external driver. Detection of this condition can be disabled by setting the CCdiag pin low. 5. At power-on after V DD1 crosses the +4V threshold, the ERROR flag is low for approximately 42µs. 6. A supply voltage low (brown-out) condition lasts longer than 100µs. Recovery is the same as power-up, either with or without a demag cycle. PROTECTION RECOMMENDATIONS The inputs IAIN1 and IAIN2 require external protection to limit the voltage swing beyond 10V of the supply voltage. The driver outputs I COMP1 and ICOMP2 can handle high current pulses protected by internal clamp circuits to the supply voltage. If repeated over-currents of large magnitudes are expected, connect external Schottky diodes to the supply rails. This external protection prevents current flowing into the die. The probe connections IS1 and IS2 are protected with diode clamps to the supply rails. In normal applications, no external protection is required. The maximum current must be limited to ±75mA. All other pins offer standard protection—see the Absolute Maximum Ratings table.

The circuit shown in Figure 8 offers an axample of a fully-connected current sensor system. Figure 8. Basic Connection Circuit

/C0068/C0082/C0086/C0052/C0048/C0049 SBVS070A − JUNE 2006 − REVISED OCTOBER 2006 www.ti.com The connection example in Figure 8 illustrates the few external components required for optimal performance. Each component is described in the following list: IP is the primary current to be measured; K 1 and K 2 connect to the compensation coil. S1 and S2 connect to the magnetic field probe. The dots indicate the winding direction on the sensor main core. R 1 and R 2 form the shunt resistor RSHUNT . This resistance is split into two to allow for adjustments to the required R SHUNT value. The accuracy and temperature stability of these resistors are part of the final system performance. R 3 and R 4, together with C 3 and C 4, form a network that reduces the remaining probe oscillator ripple in the output signal. The component values depend on the sensor type and are tailored for best results. This network is not required for normal operation. R 5 is the dummy shunt (RD ) resistor used to restore the symmetry of both differential amplifier inputs. R 5 = 4 × RSHUNT , but the accuracy is less important. R 6 and R 7 are pull-up resistors connected to the logic outputs. C 1 and C 2 are decoupling capacitors. Use low ESR-type capacitors connected close to the pins. Use low impedance printed circuit board (PCB) traces, either avoiding vias (plated-through holes) or using multiple vias. A combination of a large (> 1µF) and a small (< 4.7nF) capacitor are suggested. When selecting capacitors, make sure to consider the large pulse currents handled from the DRV401. D 1 and D 2 are protection diodes for the differential amplifier input. They are only needed if the voltage drop at RSHUNT exceeds 10V at the maximum possible peak current. LAYOUT CONSIDERATIONS The DRV401 operates with relatively large currents and fast current pulses, and offers wide-bandwidth performance. It is often exposed to large distortion energy from both the primary signal and the operating environment. Therefore, the wiring layout must provide shielding and low-impedance connections between critical points. Use low ESR capacitors for power-supply decoupling. Use a combination of a small capacitor and a large capacitor of 1µF or larger. Use low-impedance tracks to connect the capacitors to the pins. Both grounds should be connected to a local ground plane. Both supplies can be connected together; however, best results are achieved with separate decoupling (to the local GND plane) and ferrite beads in series with the main supply. The ferrite beads decouple the DRV401, reducing interaction with other circuits powered from the same supply voltage source. The reference output is referred to GND2. A low-impedance, star-type connection is required to avoid the driver current and the probe current modulating the voltage drop on the ground track. The connection wires of the difference amplifier to the shunt must be low resistance and of equal length. For best accuracy, avoid current in this connection. Consider using a Kelvin Contact-type connection. The required resistance value can be set using two resistors. Wires and PCB traces for S1 and S2 should be very close or twisted. I COMP1 and ICOMP2 should also be wired close together. T o avoid capacitive coupling, run a ground shield between the S1/S2 and ICOMP wire pair or keep them distant from each other. The compensation driver outputs (ICOMP ) are low frequency only; however, the primary signal (with high-frequency content present) is coupled into the compensation winding, the shunt, and the difference amplifier. Therefore, careful layout is recommended. The output of REF OUT and VOUT can drive some capacitive loads, but avoid large direct capacitive loads; these loads increase internal pulse currents. Given the wide bandwidth of the differential amplifier, isolate any large capacitive load with a small series resistor. A small capacitor in the pF range can improve the transient response on a high resistive load. The exposed thermal pad on the bottom of the package must be soldered to GND because it is internally connected to the substrate, which must be connected to the most negative potential. It is also necessary to solder the exposed pad to the PCB to provide structural integrity and long-term reliability.

providing a good thermal path away from the thermal pad. COMP1 and ICOMP2 are linear outputs. according to the current-conducting side of the output. FET. Permanent damage to the device can occur. available for download at www.ti.com. Table 1. /C0113JA/JP Estimations According To lfm = linear foot per minute. NOTE : All thermal models have an accuracy ≈ 20%. Figure 9. SO-20 Package Example of Thermally-Enhanced PowerPAD

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DRV401AIDWP ACTIVE SO Power PAD DWP 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIDWPG4 ACTIVE SO Power PAD DWP 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIDWPR ACTIVE SO Power PAD DWP 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIDWPRG4 ACTIVE SO Power PAD DWP 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIRGWR ACTIVE QFN RGW 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIRGWRG4 ACTIVE QFN RGW 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIRGWT ACTIVE QFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DRV401AIRGWTG4 ACTIVE QFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

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