DRV3211QPFPQ1

DRV3211-Q1 TI1 | Alldatasheet

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Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV3211-Q1 SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 DRV3211-Q13-PhaseBrushlessMotorDriver Not Recommended for New Designs

1 Features

1• 3-Phase Pre-drivers for N-channel MOS Field Effect Transistors (MOSFETs)

• Pulse Width Modulation (PWM) Frequency up to 20 kHz
• Fault Diagnostics
• Charge Pump
• Phase Comparators
• Phase Monitoring Sample and Hold Op-Amps
• Central Processing Unit (CPU) Reset Generator
• Serial Port I/F (SPI)
• Motor Current Sense
• 80-pin HTQFP
• 5-V Regulator

2 Applications

3 Description

The DRV3211-Q1 device is a field effect transistor (FET) pre-driver designed for 3-phase motor control and its application such as an oil pump or a water pump. It is equipped with three high-side pre-FET drivers and three low-side drivers which are controlled by an external microcontroller (MCU). The power for the high side is supplied by a charge pump and no bootstrap cap is needed. For commutation, this integrated circuit (IC) sends a conditional motor drive signal and output to the MCU. Diagnostics provide undervoltage, overvoltage, overcurrent, overtemperature and power bridge faults. The motor current can be measured using an integrated current sense amplifier and comparator in a battery common- mode range, which allows the motor current to be used in a high-side current sense application. Gain is attained by external resistors. If the MCU does not have enough bandwidth, the phase monitoring sample and hold amplifiers can hold phase information until the MCU is ready to process it. The pre-driver and other internal settings can be configured through the SPI interface. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV3211-Q1 HTQFP (80) 12.00 mm × 12.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.

Not Recommended for New Designs DRV3211-Q1 SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3211-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Table of Contents 8.1 Receiving Notification of Documentation Updates.. 31

9 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2012) to Revision A Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
• Changed Vchv1_12 to Vchv1_1, Vchv1_20 to Vchv1_2, Vchv2_12 to Vchv2_1, Vchv2_20 to Vchv2_2, Vchv3_12 to Vchv3_1, Vchv3_20 to
• Added 3 new parameters to VCC and VDD Electrical Characteristics table. Changed min, typ, and max values
• Removed RONH_H row, removed cross-references from RONH_HP and RONH_HN, added conditions to RONH_HP and
• Removed "side" from VOH_L and VOL_L description, changed high side and low side to pull up and pull down respectively for RONH_L and RONL_L. Changed values for RONL_L from 10 typ to 7 typ and from 20 max to 14 max in

Not Recommended for New Designs DRV3211-Q1 www.ti.com SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 Product Folder Links: DRV3211-Q1 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Revision History (continued)

Not Recommended for New Designs DRV3211-Q1 SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3211-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

NO. NAME TYPE 1 AOUT O –0.3–6 V Test mode output

2 PHTM I –1–40 V Phase comparator reference input

3 PH1M I –1–40 V Phase comparator input

4 PH2M I –1–40 V Phase comparator input

5 PH3M I –1–40 V Phase comparator input

6 PMV1 O –0.3–6 V Phase comparator output 7 PMV2 O –0.3–6 V Phase comparator output 8 PMV3 O –0.3–6 V Phase comparator output 9, 20, 42, 49, 50 GND I –0.3–0.3 V GND

10 PH1T I –2–40 V Phase amplifier input

11 PSC1 O –0.3–6 V Sample and hold filter output 12 AMPG I –0.3–0.3 V Quiet GND

13 PH2T I –2–40 V Phase amplifier input

14 PSC2 O –0.3–6 V Sample and hold filter output

15 PH3T I –2–40 V Phase amplifier input

16 PSC3 O –0.3–6 V Sample and hold filter output 17 PTV1 O –0.3–6 V Phase amplifier output 18 PTV2 O –0.3–6 V Phase amplifier output 19 PTV3 O –0.3–6 V Phase amplifier output 21 PSS1 I –0.3–6 V Sample and hold control signal input 22 PSS2 I –0.3–6 V Sample and hold control signal input

Not Recommended for New Designs DRV3211-Q1 www.ti.com SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 Product Folder Links: DRV3211-Q1 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Pin Functions (continued) PIN MAX RATING FUNCTION NO. NAME TYPE 23 PSS3 I –0.3–6 V Sample and hold control signal input 24 CS I –0.3–6 V SPI chip select 25 DOUT O –0.3–6 V SPI data output 26 SCK I –0.3–6 V SPI clock 27 VDD O –0.3–3.6 V Digital supply output 28 DIN I –0.3–6 V SPI data input 29 DGND I –0.3–0.3 V Digital GND 30 CTLEN I –0.3–6 V Pre-driver parallel enable input 31 CTLWL I –0.3–6 V Pre-driver parallel input 32 CTLWH I –0.3–6 V Pre-driver parallel input 33 CTLVL I –0.3–6 V Pre-driver parallel input 34 CTLVH I –0.3–6 V Pre-driver parallel input 35 CTLUL I –0.3–6 V Pre-driver parallel input 36 CTLUH I –0.3–6 V Pre-driver parallel input 37 RES O –0.3–6 V Reset output 38 PRN I –0.3–6 V Pulse input 39 WDEN I –0.3–6 V Reset generator enable input 40 FAULT O –0.3–6 V Diagnosis output 41 OVCR I –0.3–6 V Over current reset input 43-48, 58, 67 N/C — — Not connected 51 ADTH I –0.3–6 V Motor overcurrent threshold input 52 AMPG I –0.3–0.3 V Quiet GND 53 ALV O –0.3–6 V Motor current sense amp output 54 AREF O –0.3–40 V Motor current sense reference output 55 ALFB O –0.3–40 V Motor current sense amp feedback 56 ALM I –0.3–40 V Motor current sense amp negative input 57 ALP I –0.3–40 V Motor current sense amp positive input 59 VLVD I –0.3–6 V VCC undervoltage threshold input 60 VCCT I –0.3–6 V VCC supply input 61 VCCB O –0.3–40 V VCC regulator base drive for PNP external transistor 62 VCFB I –0.3–40 V VCC regulator current sense input 63 VBPD I –0.3–40 V VB input 64 UL O -0.3–20 V Pre-driver output 65 VL O -0.3–20 V Pre-driver output 66 WL O -0.3–20 V Pre-driver output 68 TEST1 I –0.3–6 V Test input 69 GFB I –0.3–0.3 V Power GND 70 TEST3 I -0.3–20 V Test input 71 TEST2 I –0.3–6 V Test input 72 UH O –0.3–40 V Pre-driver output 73 VH O –0.3–40 V Pre-driver output 74 WH O –0.3–40 V Pre-driver output 75 PDCPV O –0.3–40 V Charge pump output 76 CPDR4 O –0.3–40 V Charge pump output 77 CPDR3 O –0.3–40 V Charge pump output 78 CPDR2 O –0.3–40 V Charge pump output

Not Recommended for New Designs DRV3211-Q1 SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3211-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Pin Functions (continued) PIN MAX RATING FUNCTION NO. NAME TYPE 79 CPDR1 O –0.3–40 V Charge pump output 80 VBCP I –0.3–4 0V VB input

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA Operating temperature range -40 125 degree TJ Junction temperature -40 150 degree Ts Storage temperature –55 150 degree (1) ESD testing is performed according to the ACE-Q100 standard.

6.2 ESD Ratings

V(ESD) Electrostatic discharge(1) Human-body model (HBM) ±2000 V Charged-device model (CDM) ±500 (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.3 Thermal Information

THERMAL METRIC(1) DRV3211-Q1 UNITPFP (HTQFP)

80 PINS

θJA Junction-to-ambient thermal resistance 23.0 °C/W θJCtop Junction-to-case (top) thermal resistance 7.5 °C/W θJB Junction-to-board thermal resistance 7.6 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 7.4 °C/W θJCbot Junction-to-case (bottom) thermal resistance 0.3 °C/W

Not Recommended for New Designs DRV3211-Q1 www.ti.com SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 Product Folder Links: DRV3211-Q1 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated (1) Specified by design

6.4 Electrical Characteristics

VB = 12 V, TA = –40°C to 125°C (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WATCHDOG VSTN Function start VCC voltage RES Refer to Figure 1 – 0.8 1.3 V tON Power-on time RES 32 40 48 ms tOFF Clock off reset time RES 64 80 96 ms tRL Reset pulse low time RES 16 20 24 ms tRH Reset pulse high time RES 64 80 96 ms tRES Reset delay time RES 30 71.5 90 µs Pwth Pulse width PRN 200 – – ns SPI Fop Operating frequency Refer to Figure 2 DC – 4 MHz Tlead Enable lead time 100 – – ns Twait Wait time between two successive communications 5 – – µs Tlag Enable lag time 100 – – ns Tpw SCLK pulse width 100 – – ns Tsu Data setup time 80 – – ns Th Data hold time 80 – – ns Tdis Disable time – – 80 ns Tdel Data delay time (SCK to DOUT) CL = 50 pF, Refer to Figure 2 – – 80 ns CHARGE PUMP(1) Vchv1_0 Output voltage VB = 5.3 V, Iload = 0 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 7 VB + 8 VB + 9 V Vchv1_1 VB = 5.3 V, Iload = 5 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 6 VB + 7 VB + 8 V Vchv1_2 VB = 5.3 V, Iload = 8 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 5 VB + 6 VB + 7 V Vchv2_0 VB = 12 V, Iload = 0 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 13 VB + 14 VB + 15 V Vchv2_1 VB = 12 V, Iload = 11 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 13 VB + 14 VB + 15 V Vchv2_2 VB = 12 V, Iload = 18 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 12.5 VB + 13.5 VB + 15 V Vchv3_0 VB = 18 V, Iload = 0 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 13 VB + 14 VB + 15 V Vchv3_1 VB = 18 V, Iload = 13 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 13 VB + 14 VB + 15 V Vchv3_2 VB = 18 V, Iload = 22 mA, C1 = C2 = 47 nF, CCP = 2.2 µF VB + 13 VB + 14 VB + 15 V Vchvmax Maximum voltage 35 37.5 40 V VchvUV Undervoltage detection threshold VB + 4 VB + 4.5 VB + 5 V Tchv (1) Rise time VB = 5.3 V, C1 = C2 = 47 nF, CCP = 2.2 µF, VchvUV released 1 2 ms Ron On resistance S1~S4 8 Ω HIGH SIDE PRE-DRIVER VOH_H Output voltage high Isink = 10 mA, U(V/W)H – GFB Vchv – 2.7 Vchv – 1.35 V VOL_H Output voltage low Isource = 10 mA, U(V/W)H – GFB 60 120 mV RONH_HP ON resistance pull up (Pch) U(V/W)H = PDCPV - 1 V 135 270 Ω

Not Recommended for New Designs DRV3211-Q1 www.ti.com SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 Product Folder Links: DRV3211-Q1 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VB = 12 V, TA = –40°C to 125°C (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) Vgain is an SPI setting VGain Gain 10 30 Tset_TR1 Settling time (Rise) ALV ±1% VB = 5.3 ~ 18 V, Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF, R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ, Imotor = 0 → 30 A, (ALV : 1→1.9 V) – 1 2.5 µs Tset_TR2 Settling time (Rise) ALV ±1% VB = 5.3 ~ 18 V, Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF, R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ, Imotor = 0 → 100 A, (ALV : 1 → 4 V) – 1 2.5 µs Tset_TF1 Settling time (Fall) ALV ±1% VB = 5.3 ~ 18 V, Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF, R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ, Imotor = 30 → 0 A, (ALV : 1.9 → 1 V) – 1 2.5 µs Tset_TF2 Settling time (Fall) ALV ±1% VB = 5.3 ~ 18 V, Rshunt = 1 mΩ, C1 = 4.7 pF, CL = 100 pF, R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ, Imotor = 100 → 0 A, (ALV : 4 → 1 V) – 1 2.5 µs OVAD Overcurrent threshold 150-A detection, Rshunt = 1 mΩ, R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ, R3 = 8.2 kΩ, R4 = 10 kΩ –10% 150 10% A TDEL_OV AD(1) Propagation delay (Rise or fall) – – 1.5 µs PHASE AMPLIFIER Vofs_SH Output offset voltage, sample and hold mode VB = 5.3–18 V, Gain = 1 –50 – 50 mV Vofs_TH Output offset voltage, through mode VB = 5.3–18 V, Gain = 1 –50 – 50 mV Vin_cm Common mode input range VB = 5.3–18 V, Gain = 1–4 1.5 VB – 1.5 V Vout_max Maximum output voltage VB = 5.3–18 V, Gain = 1–4 4.5 – – V Vout_min Minimum output voltage VB = 5.3–18 V, Gain = 1–4 – – 0.5 V Vgain (4) Gain – Vout_SH0 Output voltage, sample and hold mode VB = 5.3–18 V, Gain = 1–4, PHxT = VB / 2 – 2.5 – V Vout_TH0 Output voltage, through mode VB = 5.3–18 V, Gain = 1–4 PHxT = VB / 2 – 2.5 – V Vout_SH1 Output voltage, sample and hold mode VB = 12 V, Gain = 1, PHxT = 1.5 V – 1.375 – V Vout_TH1 Output voltage, through mode VB = 12 V, Gain = 1, PHxT = 1.5 V – 1.375 – V Vout_SH2 Output voltage, sample and hold mode VB = 12 V, Gain = 1, PHxT = 10.5 V – 3.625 – V Vout_TH2 Output voltage, through mode VB = 12 V, Gain = 1, PHxT = 10.5 V – 3.625 – V

RES is HIGH after tON from of NMI-HIGH.

6.5 Supply Voltage and Current

Figure 1. Watchdog Timing Chart

Figure 8. Settling Time Timing Chart (Through Mode)

Not Recommended for New Designs DRV3211-Q1 www.ti.com SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 Product Folder Links: DRV3211-Q1 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Functional Block Diagram

7.2 Feature Description

7.2.1 Watchdog

can be disabled if WDEN is set high. Figure 9. Watchdog Block Diagram

7.2.2 Serial Port I/F

utilized according to the timing chart of Figure 10. Figure 10. Block Diagram of SPI

• CS – Chip Select – This input signal is utilized to select this IC by CPU. – This input signal is normally high and the communication is possible only when it is forced low. – When this input signal falls, the communication between this IC and the CPU starts. – Transmitted data is latched and the DOUT pin comes out of high impedance. – When this input signal rises, the communication stops. – The DOUT pin goes into high impedance. Then, the internal input register updates with the received bits (only if the clock pulse numbers are right and the key bit of the DIN signals is correct). – The next falling edge starts another communication. – There is a minimum waiting time between two communications (Twait). – The pin has an internal pullup.
• SCK – Synchronization Serial Clock – This input signal is utilized to synchronize the communication by CPU. – It is normally high and the correct clock pulse number is 16. – At each falling edge, the CPU writes a new bit on the DIN input and this IC writes a new bit on the DOUT pin. At each rising edge, this IC reads the new bit on the DIN pin and the CPU reads the new bit on the DOUT pin. – The maximum clock frequency is 4 MHz. – The pin has an internal pullup. space

• DIN – Serial Input Data – This input signal is used to receive 16-bit data. – The bits are received in order from the MSB (first) to the LSB (last). – The pin has an internal pullup.
• DOUT – Serial Output Data – This output signal is used to transmit 16-bit data. – It is a 3-state output and it is in high impedance mode when CS is high. – The serial data bits are transmitted in order from the MSB (first) to the LSB (last).

7.2.3 Charge Pump

has a voltage supervisor for over and undervoltage, and a selectable stop condition for pre-drivers. Figure 11. Charge Pump Block Diagram

7.2.4 Pre-Driver

Figure 12. Pre-Driver Block Diagram

Figure 13. Delay Time from Input to Output

7.2.5 Phase Comparator

side and low-side FETs. PHTM is the threshold level of comparators usable for sensorless communication. Figure 14 shows an example of the threshold level. There is no detection when CTLEN = Low. Figure 14. Phase Comparator Block Diagram

7.2.6 Motor Current Sense

output voltage up to VB at ALFB. The gain of the amplifier is adjustable by external resistors from x10 to x30. recommended application, zero-point adjustment is required as a large error offset in the initial condition. Figure 15. Motor Current Sense Block Diagram

7.2.7 Phase Amplifier (Sample and Hold Mode and Through Mode)

amplifier has x1–x4 gain control. Figure 16. Sample and Hold Mode Block Diagram Figure 17. Through Mode Block Diagram

Figure 18. Short Mode (Optional) Block Diagram

7.2.8 Regulators

regulator regulates VB down to 3.3-V with an internal FET and a controller. The regulators detect the overvoltage and undervoltage events of both supplies. Figure 19. VCC Block Diagram Figure 20. VDD Block Diagram

7.2.9 VB Monitor

The block monitors VB overvoltage. Figure 21. VB Monitor Block Diagram

7.2.10 Thermal Shutdown

Figure 22. Thermal Shutdown Block Diagram

7.2.11 Oscillator

synchronization and timing control. OSC2 is the secondary clock which is used to monitor the status of OSC1. Figure 23. Oscillator Block Diagram

7.2.12 I/O

Figure 24. Input Buffer 1 Block Diagram Figure 25. Output Buffer 1 Block Diagram Figure 26. Output Buffer 2 Block Diagram

Figure 27. Output Buffer 3 Block Diagram

7.2.13 Error Detection

Table 1. Error Detection CTLEN is internally pulled down. (2) The OVAD is not set, even if a motor overcurrent error is generated during OVCR = 0. (3) The OVAD is cleared if OVCR = 0 even when the motor overcurrent error is generated.

7.3 Device Functional Modes

Table 2. Motor Overcurrent Truth Table

7.4 Register Maps

Figure 28. SPI Bit Sequence Table 3. SPI Bit Map (DIN) In Table 3, the B15–B10 are the control bits, so the each command depends on them (listed below). SPI communication, overvoltage detection, and input diagnosis.

This command is to read the diagnosis of SPI communication. This command sets the SPI-NG (DOUT, B7) bit. Table 4. SPI Bit Map (DOUT) This flag is cleared after the register is read by the CPU. This flag is cleared after the register is read by the CPU.

Figure 29. DIAG_READ

7.4.1 Internal Diagnosis Register (Status Register and Shadow Register)

The diagnosis information is stored in the shadow register when the diagnosis happens. and both registers are output through the DOUT pin. In this case, a FAULT signal continues to be output until a new diagnosis is read by the CPU. they are read by the next DIAG_READ1 command.

Not Recommended for New Designs DRV3211-Q1 SLVSBS4A – DECEMBER 2012– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3211-Q1 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

8 Device and Documentation Support

8.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

8.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

8.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 27-Jun-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV3211QPFPQ1 NRND HTQFP PFP 80 96 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV3211 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 27-Jun-2016 Addendum-Page 2

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