DRV3203QPHPRQ1

DRV3203-Q1 TI1 | Alldatasheet

Document overview

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Technical content

4.7 pF 30 KÖ

30 KÖ 1 KÖ

1 KÖ 10 Ö 10 Ö 10 KÖ 30 KÖ

100 KÖ 10 KÖ

10 KÖ 10 KÖ 10 KÖ 10 KÖ

10 KÖ15 pF

100 KÖ 100 KÖ 100 nF 1µF 100 µF VB 1m Ö 100 KÖ 100 µF 100 nF VB 1 µF 100 nF VB 10 Ö 10 Ö 10 Ö 10 Ö 47 nF 0 Ö 100 nF 47 Ö 15 pF 2.2 µF PNP Tr 0.51 Ö 1 µF GND GND PGND GND GND PGND GND BLDC Motor PGNDGND GND PGND Controller DRV3203-Q1 1 µF Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV3203-Q1 SLVSC09B – MAY 2013– REVISED JULY 2016 DRV3203-Q1Three-PhaseBrushlessMotorDriver Not Recommended for New Designs

1 Features

1• 3-Phase Pre-Drivers for N-Channel MOS Field- Effect Transistors (MOSFETs)

• Pulse-Width Modulation (PWM) Frequency up to 20 kHz
• Fault Diagnostics
• Charge Pump
• Phase Comparators
• Microcontroller (MCU) Reset Generator
• Serial Port I/F (SPI)
• Motor-Current Sense
• 3.3-V Regulator
• Low-Current Sleep Mode
• Operation VB Range From 5.3 to 28.5 V
• AEC-Q100 Grade 1 -40°C to +125°C Ambient Operating Temperature
• 48-Pin PHP

2 Applications

• Oil Pump
• Fuel Pump
• Water Pump Typical Application Schematic

3 Description

The DRV3203-Q1 device is a field-effect transistor (FET) pre-driver designed for three-phase motor control for applications such as an oil pump or a water pump. The device has three high-side pre-FET drivers and three low-side drivers which are under the control of an external MCU. A charge pump supplies the power for the high side, and there is no requirement for a bootstrap capacitor. For commutation, this integrated circuit (IC) sends a conditional motor signal and output to the MCU. Diagnostics provide undervoltage, overvoltage, overcurrent, overtemperature and power-bridge faults. One can measure the motor current using an integrated current-sense amplifier and comparator in a battery common-mode range, which allows the use of the motor current in a high-side current-sense application. External resistors set the gain. One can configure the pre-drivers and other internal settings through the SPI. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV3203-Q1 HTQFP (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.

Not Recommended for New Designs DRV3203-Q1 SLVSC09B –MAY 2013– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3203-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Table of Contents 9.1 Receiving Notification of Documentation Updates.. 33

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2013) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Application and Implementation section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
• Changed symbol for the Data delay time, SCK to DOUT parameter in the SPI ELECTRICAL CHARACTERISTICS
• Changed the delay time, SCK to DOUT image reference from Figure 23 to Figure 2 in the SPI ELECTRICAL

13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 Not Recommended for New Designs DRV3203-Q1 www.ti.com SLVSC09B – MAY 2013– REVISED JULY 2016 Product Folder Links: DRV3203-Q1 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

(Top View) Pin Functions PIN MAXIMUM RATING FUNCTION NAME NO. TYPE ALFB 18 O –0.3 V to 40 V Motor current-sense amplifier feedback ALM 16 I –0.3 V to 40 V Motor current- sense amplifier negative input ALP 17 I –0.3 V to 40 V Motor current- sense amplifier positive input ALV 15 O –0.3 V to 6 V Motor current- sense amplifier output AREF 19 O –0.3 V to 40 V Reference output of motor current- sense amplifier CPDR1 47 O –0.3 V to 40 V Charge-pump output CPDR2 46 O –0.3 V to 40 V Charge- pump output CPDR3 45 O –0.3 V to 40 V Charge- pump output CPDR4 44 O –0.3 V to 40 V Charge- pump output CS 32 I –0.3 V to 3.6 V SPI chip select CTLUH 3 I –0.3 V to 3.6 V Pre-driver parallel input CTLUL 9 I –0.3 V to 3.6 V Pre-driver parallel input CTLVH 4 I –0.3 V to 3.6 V Pre-driver parallel input CTLVL 10 I –0.3 V to 3.6 V Pre-driver parallel input CTLWH 5 I –0.3 V to 3.6 V Pre-driver parallel input CTLWL 11 I –0.3 V to 3.6 V Pre-driver parallel input DIN 34 I –0.3 V to 3.6 V SPI data input DOUT 30 O –0.3 V to 3.6 V SPI data output

Not Recommended for New Designs DRV3203-Q1 SLVSC09B –MAY 2013– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3203-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Pin Functions (continued) PIN MAXIMUM RATING FUNCTION NAME NO. TYPE ENABLE 23 I –0.3 V to 40 V Enable input FAULT 36 O –0.3 V to 3.6 V Diagnosis output GND 29 I –0.3 V to 0.3 V GND NGND 48 I –0.3 V to 0.3 V Power GND PDCPV 43 O –0.3 V to 40 V Charge pump output PH1M 27 I –1 V to 40 V Phase comparator input PH2M 26 I –1 V to 40 V Phase comparator input PH3M 25 I –1 V to 40 V Phase comparator input PHTM 28 I –1 V to 40 V Phase comparator reference input PMV1 22 O –0.3 V to 3.6 V Phase comparator output PMV2 21 O –0.3 V to 3.6 V Phase comparator output PMV3 20 O –0.3 V to 3.6 V Phase comparator output PRN 35 I –0.3 V to 3.6 V Watchdog timer-pulse input RES 24 O –0.3 V to 3.6 V MCU reset output SCK 33 I –0.3 V to 3.6 V SPI clock TEST 2 I –0.3 V to 20 V TEST input UH 42 O –5 V to 40 V Pre-driver output UHS 41 O –5 V to 40 V Pre-driver reference UL 6 O –0.3 V to 20 V Pre-driver output VB 1 I –0.3 V to 40 V VB input VCC 12 I –0.3 V to 3.6 V VCC supply input VCCB 13 O –0.3 V to 40 V VCC regulator base driver of PNP external transistor VCFB 14 I –0.3 V to 40 V VCC regulator current-sense input VDD 31 O –0.3 V to 3.6 V VDD supply output VH 40 O –5 V to 40 V Pre-driver output VHS 39 O –5 V to 40 V Pre-driver reference VL 7 O –0.3 V to 20 V Pre-driver output WH 38 O –5 V to 40 V Pre-driver output WHS 37 O –5 V to 40 V Pre-driver reference WL 8 O –0.3 V to 20 V Pre-driver output

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT TA Operating temperature range –40 125 ºC TJ Junction temperature –40 150 ºC Tstg Storage temperature –55 175 ºC (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±500

6.3 Thermal Information

48 PINS

6.4 Electrical Characteristics

Figure 2. 0 - 100 ns

Not Recommended for New Designs DRV3203-Q1 SLVSC09B –MAY 2013– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3203-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vchv2_0 Output voltage, PDCPV VB = 12 V, Ioad = 0 mA, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω VB + 10 VB + 12 VB + 14 V Vchv2_1 Output voltage, PDCPV VB = 12 V, Ioad = 11 mA, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω VB + 9.5 VB + 11.5 VB + 13.5 V Vchv2_2 Output voltage, PDCPV VB = 12 V, Ioad = 18 mA, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω VB + 9 VB + 11 VB + 13 V Vchv3_0 Output voltage, PDCPV VB = 18 V, Ioad = 0 mA, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω VB + 10 VB + 12 VB + 14 V Vchv3_1 Output voltage, PDCPV VB = 18 V, Ioad = 13 mA, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω VB + 10 VB + 12 VB + 14 V Vchv3_2 Output voltage, PDCPV VB = 18 V, Ioad = 22 mA, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω VB + 10 VB + 12 VB + 14 V VchvOV Overvoltage detection threshold 35 37.5 40 V VchvUV Undervoltage detection threshold VB + 4 VB + 4.5 VB + 5 V tchv (1) Rise time VB = 5.3 V, C1 = C2 = 47 nF, CCP = 2.2 µF, R1 = R2 = 0 Ω, Vchv, UV released 1 2 ms Ron On-resistance, S1-S4 See Figure 10 8 Ω

Not Recommended for New Designs DRV3203-Q1 www.ti.com SLVSC09B – MAY 2013– REVISED JULY 2016 Product Folder Links: DRV3203-Q1 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HIGH-SIDE PRE-DRIVER VOH_H Output voltage, turnon side Isink = 10 mA, PDCPV - xH 1.35 2.7 V VOL_H Output voltage, turnoff side Isource = 10 mA, xH - xHS 25 50 mV RONH_HP On-resistance, turnon side (Pch) U(V/W)H = PDCPV -

1 V 135 270 Ω

RONH_HN On-resistance, turnon side (Nch) U(V/W)H = PDCPV -

2.5 V 4 8 Ω

RONL_H On-resistance turnoff side 2.5 5 Ω ton_h1(1) Turnon time CL = 12 nF, RL = 0 Ω from 20% to 80% 50 - 200 ns toff_h1(1) Turnoff time CL = 12 nF, RL = 0 Ω from 80% to 20% 50 - 200 ns th-ondly1 (1) Output delay time CL = 12 nF, RL = 0 Ω to 20%, no dead time - 200 - ns th-offdly1 (1) Output delay time CL = 12 nF, RL = 0 Ω to 80%, no dead time - 200 - ns VGS_hs Gate-source high -side voltage difference xH-xHS –0.3 18 V LOW-SIDE PRE-DRIVER VOH_L1 Output voltage, turnon side VB = 12 V, Isink = 10 mA, xL -NGND 10 12 14 V VOH_L2 Output voltage, turnon side VB = 5.3 V, Isink = 10 mA, xL - NGND 5.5 7.5 10 V VOL_L Output voltage, turnoff side Isource = 10 mA, xL - NGND - 25 50 mV RONH_L On-resistance, turnon side - 6 12 Ω RONL_L On-resistance, turnoff side 2.5 5 Ω ton_l (1) Turnon time CL = 18 nF, RL = 0 from 20% to 80% of 12 V, from 20% to 80% of 6 V (VB = 5.3 V) 50 - 200 ns t off_h (1) Turnoff time CL = 18 nF, RL = 0 from 80% to 20% of 12 V, from 80% to 20% of 6 V (VB = 5.3 V) 50 - 200 ns tl-ondly (1) Output delay time CL = 18 nF, RL = 0 to 20% of 12 V, to 20% of VOH = 6 V (VB = 5.3 V), no dead time - 200 - ns tl-offdly (1) Output delay time CL = 18 nF, RL = 0 to 80% of 12 V, to 80% of VOH = 6 V (VB = 5.3 V), no dead time - 200 - ns tdiff1(1) Differential time1 (Th-on) - (Tl-off), no dead time, See Figure 3 –200 0 200 ns

Not Recommended for New Designs DRV3203-Q1 SLVSC09B –MAY 2013– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3203-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tdiff2(1) Differential time2 (Tl-on) - (Tl-off), no dead time, See Figure 3 –200 0 200 ns tdead(1) Dead time OSC1 = 10 MHz SPI register PDCFG.DEADT 1.5 0.5 2.2 1.7 1.2 0.7 µs PHASE COMPARTOR VIOfs Input offset voltage –15 - 15 mV VIm1 Input voltage range, PHTM VB = 6 V – 28.5 V 1.3 - 4.5 V VIm2 Input voltage range, PHTM VB = 5.3 V 1.3 - 4.2 V VIp Input voltage range, PHxM –1 - VB V Vhys Threshold hysteresis voltage SPI register SPARE. SEL_COMP_HYS - 0 - mV 12.5 25 50 25 50 100 50 100 200 VOH Output high voltage Isink = 2.5 mA 0.9 × VCC - - V VOL Output low voltage Isource = 2.5 mA - - 0.1 × VCC V tres_tr (1) Response time, rising CL = 100 pF - 0.7 1.5 µs tres_tf (1) Response time, falling CL = 100 pF - 0.7 1.5 µs MOTOR CURRENT SENSE VOfs Input offset voltage –5 5 mV VO_0 Output voltage, ALV Imotor = 0 A, SPI register CSCFG. CSOFFSET 0.5 1.5 - V VLine Linearity, ALV Rshunt = 1 mΩ, R11 = R12 = 1 kΩ, R21 = R22 = 30 kΩ 29.4 30 30.6 mV/A VGain Gain 10 30 - V/V Tset_TR1(1) Settling time (rise), ALV ±1% Rshunt = 1 mΩ, VGain = 30, CL = 100 pF, Imotor = 0 A → 30 (ALV: 1 V → 1.9 V, AREF = 1 V) - 1 2.5 µs Tset_TR2(1) Settling time(rise), ALV ±1% Rshunt = 1 mΩ, VGain = 30, CL = 100 pF, Imotor = 0 A → 100 (ALV: 1 V → 4 V, AREF = 1 V) - 1 2.5 µs Tset_TF1(1) Settling time(fall), ALV ±1% Rshunt = 1 mΩ, VGain = 30, CL = 100 pF, Imotor = 30 A → 0, (ALV: 1.9 V → 1 V, AREF = 1 V) - 1 2.5 µs

Not Recommended for New Designs DRV3203-Q1 www.ti.com SLVSC09B – MAY 2013– REVISED JULY 2016 Product Folder Links: DRV3203-Q1 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated Electrical Characteristics (continued) VB = 12 V, TA = –40°C to +125℃ (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Tset_TF2(1) Settling time(fall), ALV ±1% Rshunt = 1 mΩ, VGain = 30, CL = 100 pF, Imotor = 100 A → 0, (ALV: 0.4 V → 1 V, AREF = 1 V) - 1 2.5 µs OVADth Overcurrent threshold Rshunt = 1 mΩ, VGain = 30, AREF = 1 V, ADTH = 2.5 V, SPI register FLTCFG. MTOCTH, OVADth = (2 × ADTH -- AREF) / (Rshunt × VGain) 89.1 99 108.9 A TDEL_OVAD(1) Propagation delay (rise or fall) - - 1.5 µs tfiltMTOC filtering time OSC1 = 9 MHz-11 MHz 0.8 1 1.2 µs VCC VCC1 Output Voltage 3.23 3.3 3.37 V IBVCC Base Current 2 mA hfePNP DC current gain of external PNP 100 - - VLRVCC Load regulation ILVCC = 5 mA to 200 mA -20 - 20 mV CVCC External Capacitance 22 100 µF RVCC ESR of external Capacitor 300 mΩ VCCUV Under voltage detection threshold SPI register FLTCFG. VCCUVTH 2.2 2.2 2.4 2.4 2.6 V VCCUVHYS Under voltage detection threshold hysteresis 50 100 200 mV VCCOV Overvoltage detection threshold 3.5 3.8 4.1 V VCCOC Current Limit Rsns = 0.51 Ω, 0.2 V ⋍ Rsns x VCCOC 300 400 550 mA Tvcc1(1) Rise Time VCC > VCCUV, CVCC = 22 µF 0.5 ms Tvcc2(1) Rise Time VCC > VCCUV, CVCC = 100 µF 1.5 ms VDD VDD Output Voltage 3 3.3 3.6 V CVDD Load Capacitance 1 µF VDDUV Under voltage detection threshold 2.1 2.3 2.5 V VDDOV Overvoltage detection threshold 4 4.3 4.6 V Tvdd(1) Rise Time VDD > VDDUV, CVDD = 1 µF 100 µs VB MONITOR VBOV VB overvoltage detection threshold level 26.5 27.5 28.5 V VBUV VB Undervoltage detection threshold level SPI register FLTCFG. VBUVTH 3.65 4.15 4.65 5.15 4.5 5.5 4.35 4.85 5.35 5.85 V THERMAL SHUT DOWN TSD(1) Thermal shut down threshold level 155 175 195 °C TSDhys(1) Thermal shut down hysteresis 5 10 15 °C

(1) Performance of supply voltage 5.3 to 18 V is according to the ACE-Q100 (Grade 1) standard.

6.5 Supply Voltage and Current

NOTE: VCC undervoltage condition sets RES = Low. Figure 1. Watchdog Timing Chart

47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 Charge Pump VB SCK CS DOUT GND PHTM VDD VCC PMV2 PMV3 PH1M NGND PDCPV CPRD1 CPRD2 CPRD3 CPRD4 UH VB Monitor Control Logic PH2M VB UL VL WL RES VCC PMV1 VB VM VMS AMP VB 3.3V Reg 3.3V Reg OVAD ALV AREF ALFB ALM ALP TEST (OPEN) TEST I/F AMP - +COMP ADTH ENABLE VCC UHS VH VHS WH WHS PDCPV PDCPV PDCPV FAULT PRN DIN PH3M WHS VHS UHS VCOM +-+-+- COMP COMPCOMP VCFB VCCB VCCB VCFB VCC CTLWL CTLVL CTLUL CTLWH CTLVH CTLUH NGND VCP12 VCP12 TSD SLEEP WDVCC VM VB UHS VHS WHS Battery M UH VH WH UL VL WL VMS Not Recommended for New Designs DRV3203-Q1 SLVSC09B –MAY 2013– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3203-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Functional Block Diagram

7.2 Feature Description

7.2.1 Watchdog

A watchdog monitors the PRN signal and VCC supply level and generates a reset to the MCU through the RES pin if the status of PRN is not normal or VCC is lower than the specified threshold level. Detection of a special pattern on the PRN input during power up can disable the watchdog.

Figure 8. Watchdog Block Diagram

7.2.2 Serial Port I/F

uses four signals according to the timing chart of Figure 2. Figure 9. Block Diagram of SPI

7.2.2.1 CS - Chip Select

between the two communications (twait). The pin has an internal pullup.

7.2.2.2 SCK - Synchronization Serial Clock

The MCU uses SCK to synchronize communication. SCK is normally low, and the valid clock-pulse number is 16. maximum clock frequency is 4 MHz. The pin has an internal pulldown.

7.2.2.3 DIN - Serial Input Data

7.2.2.4 DOUT - Serial Output Data

order of serial data-bit transmission is from the MSB (first) to the LSB (last).

7.2.3 Charge Pump

supports pre-driver slope and switching-frequency requirements. R1 and R2 reduce switching current if required. Figure 10. Charge-Pump Block Diagram

7.2.4 Pre-Driver

conditions (Fault Detection) and SPI set (Serial Port I/F). Figure 11. Pre-Driver Block Diagram

7.2.5 Phase Comparator

communication. Figure 12 shows an example of the threshold level. Figure 12. Phase Comparator Block Diagram

7.2.6 Motor-Current Sense

required as large error offset in initial condition. Figure 13. Motor Current-Sense Block Diagram

7.2.7 Regulators

controlled by the regulator block. This 3.3-V LDO is supplied to MCU and other components. PNP is protected against short to GND fault. Overvoltage and undervoltage events of both supplies are detected. The under voltage of the 3.3-V LDO with the external PNP is set by SPI. Figure 14. VCC Block Diagram (External Driver) Figure 15. VDD Block Diagram

7.2.8 VB Monitor

Figure 16. VB Monitor Block Diagram

7.2.9 Thermal Shutdown

Figure 17. Thermal Shutdown Block Diagram

7.2.10 Oscillator

synchronization and timing control. OSC2 is the secondary clock used to monitor the status of OSC1. Figure 18. Oscillator Block Diagram

7.2.11 I/O

• V5INT is the internal power supply.

Figure 19. Input Buffer1 Block Diagram Figure 20. Output Buffer1 Block Diagram

Figure 21. Output Buffer2 Block Diagram Figure 22. Output Buffer3 Block Diagram Table 1. Recommended Pin Termination (1) Pre-driver is disabled if the conditions occur and SDNEN register bits are 1. (2) FAULT pin is asserted to low if the conditions occur and FLTEN register bits are 1. (3) Pre-driver is disabled by VCC undervoltage and VDD undervoltage conditions regardless of SPI register setting.

7.2.12 Fault Detection

Table 2. Fault Detection

7.3 Register Maps

Table 3. SPI Serial Input Format Table 4. SPI Serial Output Data Format Frame fault : 0: No error exists in the previous SPI frame. : 1: Error exists in the previous SPI frame. Table 5. SPI Register Map

7.3.1 Register Descriptions

Access type: R = Read and W = Write. Reserved register: Read of reserved bits return 0 and write has no effect.

7.3.1.1 CFGUNLK (address 0x01): Configuration Unlock Register

• FLTCFG
• FLTEN0 and FLTEN1
• SDNEN0 and SDNEN1
• CSCFG

Not Recommended for New Designs DRV3203-Q1 SLVSC09B –MAY 2013– REVISED JULY 2016 www.ti.com Product Folder Links: DRV3203-Q1 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Bit Name Type Reset Description

• PDCFG
• WDCFG In lock mode, read returns the values, but writing the registers have no effect. Device enters unlock mode by writing 0x5, 0x8, 0x7 to CFGUNLK register in series. Device exits from unlock mode by writing 0x0.

7.3.1.2 FLTCFG (address 0x02): Fault Detection Configuration Register

Bit Name Type Reset Description

7 FLGLATCH_EN RW 0 Fault-flag (FLTFLG*) latch enable

0: Fault events do not latch fault-flag register bits. 1: Latching of fault-flag register bits by the fault events occurs. The flag bits remain asserted until cleared. 6:4 MTOCTH RW 000 Motor overcurrent detection threshold 000: 1.32 V 001: 1.65 V 010: 1.98 V 011: 2.31 V 100: 2.64 V Others: 1.32 V

3 RSVD R 0 Reserved

2 VCCUVTH RW 0 VCC undervoltage detection threshold

0: 2.3 V 1: 2.4 V 1:0 VBUVTH RW 00 VB undervoltage detection threshold 00: 4 V 01: 4.5 V 10: 5 V 11: 5.5 V

7.3.1.3 FLTEN0 (address 0x04): FAULT Pin Enable Register 0

Bit Name Type Reset Description 7 FE_MTOC RW 1 FAULT pin enable of FLTFLG0 register bits. 0: Assertion of the FAULT pin does not occur when the fault flag bit is 1 1: Assertion of the FAULT pin to low level occurs when the fault flag bit is 1. See Figure 23

6 FE_VCCOC RW 1

5 FE_VCCOV RW 1

4 FE_VDDOV RW 1

3 FE_CPOV RW 1

2 FE_CPUV RW 1

1 FE_VBOV RW 1

0 FE_VBUV RW 1

7.3.1.4 FLTEN1 (address 0x05): FAULT Pin Enable Register 1

Bit Name Type Reset Description 7:1 RSVD R 0000 000 Reserved

0 FE_TSD RW 1 FAULT pin enable of TSD flag bit

0: Assertion of the FAULT pin does not occur when the fault flag bit is 1 1: Assertion of the FAULT pin to low level occurs when the TSD flag bit is 1. See Figure 23

Figure 23. FAULT Pin Enable Logic

7.3.1.5 SDNEN0 (address 0x06): Pre-Driver Shutdown Enable Register 0

7 SE_MTOC RW 1 Pre-driver shutdown enable of FLTFLG0 register bits

0: Disabling of the pre-driver outputs does not occur when the fault flag bit is 1.

6 SE_VCCOC RW 1

5 SE_VCCOV RW 1

4 SE_VDDOV RW 1

3 SE_CPOV RW 1

2 SE_CPUV RW 1

1 SE_VBOV RW 1

0 SE_VBUV RW 1

7.3.1.6 SDNEN1 (address 0x07): Pre-Driver Shutdown Enable Register 1

0 SE_TSD RW 1 Pre-driver shutdown enable of TSD flag bits

0: Disabling of the pre-driver outputs does not occur when the TSD flag bit is 1.

(2) Assertion of the fault flags may occur during power up. Figure 24. Pre-Driver Shutdown Logic

7.3.1.7 FLTFLG0 (address 0x08): Fault Flag Register 0

6 VCCOC RW 0 VCCOC: VCC overcurrent

5 VCCOV RW 0 VCCOV: VCC overvoltage

4 VDDOV RW 0 VDDOV: VDD overvoltage

3 CPOV RW 0 CPOV: Charge-pump overvoltage

2 CPUV RW 0 CPUV: Charge-pump undervoltage

1 VBOV RW 0 VBOV: VB overvoltage

0 VBUV RW 0 VBUV: VB undervoltage

0: Read = No fault condition exists since last cleared. 1: Read = Fault condition exists.

(2) Assertion of the fault flags may occur during power up.

7.3.1.8 FLGFLT1 (address 0x09): Fault Flag Register 1

0: Read = No fault condition exists since last cleared. 1: Read = Fault condition exists. Figure 25. SPI Data-Out Timing Chart of Fault Flag Registers

(1) Assertion of FAULT occurs if FLTEN = 1. (2) Disabling of pre-driveroccurs if SDNEN = 1. Figure 26. FLGFLG and FLGLATCH_EN

7.3.1.9 CSCFG (address 0x0A): Current Sense Configuration Register

7.3.1.10 PDCFG (address 0x0B): Pre-Driver Configuration Register

The actual dead time has ±0.2-µs variation from the typical value.

7.3.1.11 DIAG (address 0x0C): Diagnosis Register

2 VCCUVRST R 0 nRES reset source information

1 WDTRST R 0 Bit 2 = VCCUVRST - VCC undervoltage

0 CMRST R 0 Bit 1 = WDTRST - watchdog timer

0: Read = Reset has not occurred.

Not Recommended for New Designs DRV3203-Q1 www.ti.com SLVSC09B – MAY 2013– REVISED JULY 2016 Product Folder Links: DRV3203-Q1 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated Bit Name Type Reset Description Write = No effect 1: Read = A corresponding reset source caused the last reset condition. Write = No effect Read access to this register clears the bits. (1) R: Read W: Write

7.3.1.12 SPARE (address 0x0D): Spare Register

Bit Name Type(1) Reset Description 7:2 SPARE RW 0000 Spare registers for future use. Read and write have no effect. 1:0 SEL_COMP_HYS RW 00 Select phase comparator hysteresis voltage. The following show the typical values. MM 00: 0 V MM 01: 25 mV MM 10: 50 mV MM 11: 100 mV

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Typical Application

Figure 27. Typical Application Schematic

Not Recommended for New Designs DRV3203-Q1 www.ti.com SLVSC09B – MAY 2013– REVISED JULY 2016 Product Folder Links: DRV3203-Q1 Submit Documentation FeedbackCopyright © 2013–2016, Texas Instruments Incorporated

9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

9.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

9.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

9.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 27-Jun-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV3203QPHPQ1 NRND HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV3203 DRV3203QPHPRQ1 NRND HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV3203 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 27-Jun-2016 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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