DRV2665RGPTG4.A

DRV2665 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 35

Technical content

DRV2665 Piezo Haptic Driver with Integrated Boost Converter and Digital Front End

1 Features

• Integrated Digital Front End – Up to 400-kHz I2C Bus Control – 100-Byte Internal FIFO Interface – Immersion TS5000-Compliant – Optional Analog Inputs
• High Voltage Piezo-Haptic Driver – Drives up to 100 nF at 200 VPP and 300 Hz – Drives up to 150 nF at 150 VPP and 300 Hz – Drives up to 330 nF at 100 VPP and 300 Hz – Drives up to 680 nF at 50 VPP and 300 Hz – Differential Output
• 105-V Integrated Boost Converter – Adjustable Boost Voltage – Adjustable Boost Current Limit – Integrated Power FET and Diode – No Transformer Required
• 2-ms Fast Start Up Time
• 3.3- to 5.5-V Wide Supply Voltage Range
• 1.8-V Compatible, VDD Tolerant Digital Pins

2 Applications

• Mobile Phones
• Tablets
• Portable Computers
• Keyboards and Mice
• Electronic Gaming
• Touch Enabled Devices

3 Description

The DRV2665 device is a piezo haptic driver with integrated 105-V boost switch, integrated power diode, integrated fully-differential amplifier, and integrated digital front end. This versatile device is capable of driving both high-voltage and low-voltage piezo haptic actuators. The input signal can be driven as haptic packets over the I 2C port or through the analog inputs. The digital interface of the DRV2665 device is available through an I 2C compatible bus. A digital interface relieves the costly processor burden of the PWM generation or additional analog channel requirements in the host system. Any writes to the internal first-in, first-out buffer (FIFO) will automatically wake up the device and begin playing the waveform after the 2 ms internal start-up procedure. When the data flow stops or the FIFO under-runs, the DRV2665 device will automatically enter a pop-less shutdown procedure. The boost voltage is set using two external resistors, and the boost current limit is programmable through the R EXT resistor. A typical start-up time of 2 ms makes the DRV2665 device an ideal piezo driver for fast haptic responses. Thermal overload protection prevents the device from being damaged when overdriven. Device Information(1) PART NUMBER PACKAGE BODY SIZE (MAX) DRV2665 QFN (20) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. VDD REG SDA SCL IN+ IN- PUMP GND SW BST PVDD FB OUT+ OUT- REXT RPURPU I2C Analog Input 3.3 V to 5.5 V Piezo Actuator C(VDD) Cbulk C(REG) C(BST) R(EXT)C(PUMP) Simplified Schematic DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2015) to Revision C (January 2023) Page Changes from Revision A (January 2014) to Revision B (September 2015) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Changes from Revision * (May 2012) to Revision A (January 2014) Page DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

5 Pin Configuration and Functions

Figure 5-1. RGP Package 20-Pin QFN With Exposed Thermal Pad Top View Table 5-1. Pin Functions PIN TYPE DESCRIPTION NAME NO.1 PUMP 1 P Internal charge pump voltage VDD 2 P 3- to 5.5-V supply input. A 1 µF-capacitor is required. FB 3 I Boost feedback GND 4, 5, 6 P Supply ground SW 7, 8 P Internal boost switch pin NC 9 — No connect BST 10, 11 P Boost output voltage. A 0.1-µF capacitor is required. PVDD 12 P High-voltage amplifier input voltage OUT+ 13 O Positive haptic driver differential output OUT- 14 O Negative haptic driver differential output REXT 15 I Sets boost current limit. Resistor to ground. IN- 16 I Negative analog input IN+ 17 I Positive analog input SCL 18 I I2C clock SDA 19 I/O I2C data REG 20 O 1.8-V regulator output. A 0.1-µF capacitor is required. 1. I = Input, O = Output, P = Power www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRV2665

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply Voltage, VDD –0.3 6 V Input voltage, VI SDA, SCL, IN+, IN–, FB –0.3 VDD + 0.3 V Boost voltage BST, SW, OUT+, OUT–, PVDD –0.3 120 V Operating free-air temperature, TA –40 70 °C Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 85 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 VCharged device model (CDM), per JEDEC specification JESD22- C101(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage 3.3 5.5 V VBST Boost voltage 15 105 V VIN Differential input voltage 1.8 V CL Load capacitance VBST = 105 V, Frequency = 500 Hz, VOUT = 200 VPP 50 nF VBST = 105 V, Frequency = 300 Hz, VOUT = 200 VPP 100 VBST = 80 V, Frequency = 300 Hz, VOUT = 150 VPP 150 VBST = 55 V, Frequency = 300 Hz, VOUT = 100 VPP 330 VBST = 30 V, Frequency = 300 Hz, VOUT = 50 VPP 680 VBST = 25 V, Frequency = 300 Hz, VOUT = 40 VPP 1000 VBST = 15 V, Frequency = 300 Hz, VOUT = 20 VPP 3000 REXT Current limit control resistor 6 35 kΩ L Inductance for boost converter 3.3 µH

6.4 Thermal Information

THERMAL METRIC(1) DRV2665 UNITRGP (QFN)

20 PINS

RθJA Junction-to-ambient thermal resistance 32.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 30.4 °C/W RθJB Junction-to-board thermal resistance 8.2 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 8.1 °C/W DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

THERMAL METRIC(1) DRV2665 UNITRGP (QFN) RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25 °C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VREG Voltage at the REG pin 1.6 1.75 1.9 V IIL Digital low-level input current SDA, SCL VDD = 3.6 V, VI = 0 V 1 µA IIH Digital high-level input current SDA, SCL VDD = 3.6 V, VI = VDD 1 uA VIL Digital low-level input voltage SDA, SCL VDD = 3.6 V 0.5 V VIH Digital high-level input voltage SDA, SCL VDD = 3.6 V 1.4 V VOL Digital low-level output voltage SDA 3-mA sink current 0.4 V ISD Shutdown current VDD = 3.6 V, STANDBY = 1 10 µA IQ Quiescent current Digital mode VDD = 3.6 V, STANDBY = 0 130 175 µA Analog mode VDD = 3.6 V, analog input mode, VBST = 105 V 24 mA VDD = 3.6 V, analog input mode, VBST = 80 V 13 VDD = 3.6 V, analog input mode, VBST = 50 V 9 VDD = 3.6 V, analog input mode, VBST = 30 V 5 RIN Input impedance IN+, IN–; All gains 100 kΩ VOUT(FS) Full-scale output voltage (digital mode) GAIN[1:0] = 00 49 50 51 VPP GAIN[1:0] = 01 98 100 102 GAIN[1:0] = 10 147 150 153 GAIN[1:0] = 01 196 200 204 VOUT(OS) Output offset All gains –0.25 0.25 V BW Amplifier bandwidth GAIN[1:0] = 00, VOUT = 50 VPP, no load 20 kHz GAIN[1:0] = 01, VOUT = 100 VPP, no load 10 GAIN[1:0] = 10, VOUT = 150 VPP, no load 7.5 GAIN[1:0] = 11, VOUT = 200 VPP, no load 5 www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV2665

TA = 25 °C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IBAT, AVG Average battery current during operation CL = 220 nF, f = 200 Hz, VBST = 30 V, GAIN[1:0] = 00, VOUT = 50 VPP mA CL = 680 nF, f = 150 Hz, VBST = 30 V, GAIN[1:0] = 00, VOUT = 50 VPP CL = 680 nF, f = 300 Hz, VBST = 30 V, GAIN[1:0] = 00, VOUT = 50 VPP 115 CL = 22 nF, f = 200 Hz, VBST = 80 V, GAIN[1:0] = 10, VOUT = 150 VPP CL = 47 nF, f = 150 Hz, VBST = 105 V, GAIN[1:0] = 11, VOUT = 200 VPP 210 CL = 47 nF, f = 300 Hz, VBST = 105 V, GAIN[1:0] = 11, VOUT = 200 VPP 400 THD+N Total harmonic distortion plus noise f = 300 Hz, VOUT = 200 VPP 1% fS Output sample rate Digital playback engine sample rate 7.8 8 8.05 kHz

6.6 Timing Requirements

TA = 25 °C, VDD = 3.6 V (unless otherwise noted). For timing diagrams, see Figure 6-1 and Figure 6-2. MIN NOM MAX UNIT ƒSCL Frequency at the SCL pin with no wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 µs tw(L) Pulse duration, SCL low 1.3 µs tsu(1) Setup time, SDA to SCL 100 ns th(1) Hold time, SCL to SDA 10 ns tBUF Bus free time between stop and start condition 1.3 µs tsu(2) Setup time, SCL to start condition 0.6 µs th(2) Hold time, start condition to SCL 0.6 µs tsu(3) Setup time, SCL to stop condition 0.6 µs

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Tstart Start-up time Time from I2C write until boost and amplifier are fully enabled 2 ms tw(H) tw(L) SCL SDA tsu(1) th(1) Figure 6-1. SCL and SDA Timing DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

t(BUF) SCL SDA Start Condition Stop Condition tsu(2) th(2) tsu(3) Figure 6-2. Timing for Start and Stop Conditions www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRV2665

6.8 Typical Characteristics

10V − Output Voltage − VOUTPP − AIDD − Supply Current 1 1002000100m200m300m400m500m600m3.6 V5.0 VVDD = VDD = f = 200 Hz PVDD = 105 V CLOAD = 47 nF Gain = 40 dB Figure 6-3. Supply Current vs Output Voltage VOUT − Output Voltage − V PP IDD − Supply Current − A 1 10 100 200 100m 200m 300m 400m 500m 600m Frequency = 150 Hz Frequency = 200 Hz Frequency = 300 Hz VDD = 3.6 V PVDD = 105 V CLOAD = 47 nF Gain = 40 dB Figure 6-4. Supply Current vs Output Voltage A − 10V − Output Voltage − VOUTPP IDD − Supply Current 1 1000100m200m300m400m500m600mVDD = 3.6 VVDD = 5.0 V f = 200 Hz PVDD = 55 V CLOAD = 330 nF Gain = 34 dB Figure 6-5. Supply Current vs Output Voltage VOUT − Output Voltage − V PP IDD − Supply Current − A 1 10 100 100m 200m 300m 400m 500m 600m Frequency = 150 Hz Frequency = 200 Hz Frequency = 300 Hz VDD = 3.6 V PVDD = 55 V CLOAD = 330 nF Gain = 34 dB Figure 6-6. Supply Current vs Output Voltage − A 10V − Output Voltage − VOUTPP IDD − Supply Current 10 50100m200m300m400m500m600mVDD = 3.6 V = 5.0 VVDD f = 200 Hz PVDD = 30 V CLOAD = 680 nF Gain = 28 dB Figure 6-7. Supply Current vs Output Voltage VOUT − Output Voltage − V PP IDD − Supply Current − A 1 10 50 100m 200m 300m 400m 500m 600m Frequency = 150 Hz Frequency = 200 Hz Frequency = 300 Hz VDD = 3.6 V PVDD = 30 V CLOAD = 680 nF Gain = 28 dB Figure 6-8. Supply Current vs Output Voltage DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

7 Detailed Description

7.1 Overview

The DRV2665 device is a piezo haptic driver with integrated boost switch, integrated power diode, integrated fully-differential amplifier, and integrated digital front end. This versatile device is capable of driving both high- voltage and low-voltage piezo haptic actuators. The input signal can be driven over the I 2C port or the analog inputs. The digital interface of the DRV2665 device is available through an I 2C compatible bus. A digital interface relieves the costly processor burden of PWM generation or additional analog channel requirements in the host system. Any writes to the internal FIFO automatically wakes up the device and begin playing the waveform after the 2 ms internal startup procedure. When the data flow stops or the FIFO under runs, the device automatically enters a pop-less shutdown procedure. The boost voltage is set using two external resistors, and the boost current limit is programmable through the REXT resistor. A typical start-up time of 2 ms makes the DRV2665 an ideal piezo driver for fast haptic responses. Thermal overload protection prevents the device from being damaged when overdriven.

7.2 Functional Block Diagram

OUT– GND REG SDA SCL FIFO OUT+ VDD Short Circuit Protection Thermal Protection Battery Monitor DAC Piezo Actuator Boost SW BST 3.3 V to 5.5 V SDA SCL IN+ IN- MUX PVDDFBREXT PUMP PUMP IN+ IN- C(PUMP)C(REG) C(VDD) C(IN) C(IN) C(PVDD) CBULK R(EXT) RPU RPU

7.3 Feature Description

7.3.1 Support for Haptic Piezo Actuators

The DRV2665 device supports haptic piezo actuators of up to 200 VPP.

7.3.2 Flexible Front End Interface

The DRV2665 device supports multiple approaches to launch and control haptic effects, that are detailed in Section 7.4. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

Figure 7-1. Front-End Interface

7.3.3 Ramp Down Behavior

If the user leaves the state of the DAC at any level other than mid-scale (0x00), the DAC automatically ramps down at a safe rate after the timeout period has expired. If the DRV2665 device is properly programmed, the ramp down sequence will never be used. This is a failsafe for any unavoidable interruptions to the playback process. Any writes to the FIFO during the ramp down period are discarded.

7.3.4 Low Latency Startup

The DRV2665 device features a fast startup time, that is essential for achieving low latency in haptic applications. When the STANDBY bit is transitioned from high to low, the device is ready for operation. The device logic automatically controls the internal boost converter and amplifier enable signals. The boost converter and amplifier are enabled only when needed and otherwise remain in a lower power idle state. When the device received a data byte through the FIFO interface, the boost converter and amplifier wake up and the internal logic sends the first sample through the internal DAC after the wake-up is completed. In the system application, the entire system latency must be kept to less than 30 ms total to be imperceptible to the end user. At a 2-ms wake-up time, the device is a small percentage of the total system latency. If the EN_OVERRIDE bit is set, the device immediately enters the startup procedure and the boost converter and amplifier remain enabled, bypassing the internal controls. Subsequent transactions occur immediately with no wake-up overhead, but the boost converter and amplifier draw a quiescent current until the EN_OVERRIDE bit is cleared by the user.

7.3.5 Low Power Standby Mode

The DRV2665 device has a low-power standby mode through the I 2C interface that puts the device in its lowest power state. This mode is entered when the standby bit (STANDBY) is set from low to high. When the STANDBY bit is set high, no other mode of operation is enabled. When the STANDBY bit transitions from high to low, the device is readied for operation and may receive data.

7.3.6 Device Reset

The DRV2665 device has software-based reset functionality. When the DEV_RST bit is set, the device immediately stops any transaction in process, resets all of its internal registers to the default values, and enters standby mode.

7.3.7 Amplifier Gain

The amplifier gain determines the gain from IN+/IN– to OUT+/OUT– when using the analog playback mode. For digital playback, the gain is optimized for achieving approximately 50 V PP, 100 V PP, 150 V PP, 200 V PP without clipping. Note that clipping of the amplifier occurs if the expected peak voltage is greater than the boost converter output voltage (VBST) The DRV2665 device gain is programmable according to Table 7-1. Table 7-1. Amplifier Gain Table GAIN[1] GAIN[0] FULL SCALE PEAK VOLTAGE (V) GAIN (dB) ANALOG MODE 0 0 25 28.8 0 1 50 34.8 www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRV2665

Table 7-1. Amplifier Gain Table (continued) GAIN[1] GAIN[0] FULL SCALE PEAK VOLTAGE (V) GAIN (dB) ANALOG MODE 1 0 75 38.4 1 1 100 40.7

7.3.8 Adjustable Boost Voltage

The output voltage of the integrated boost converter may be adjusted by a resistive feedback divider between the boost output voltage (VBST) and the feedback pin (FB). The boost voltage must be programmed to a value greater than the maximum peak signal voltage that the user expects to create with the device amplifier. Lower boost voltages achieve better system efficiency when lower amplitude signals are applied, thus the user must take care not to use a higher boost voltage than necessary. The maximum allowed boost voltage is 105 V.

7.3.9 Adjustable Current Limit

The current limit of the boost switch can be adjusted through a resistor to ground placed on the REXT pin . To avoid damage to both the inductor and the DRV2665 device, the programmed current limit must be less than the rated saturation limit of the inductor selected by the user. If the combination of the programmed limit and inductor saturation is not high enough, then the output current of the boost converter will not be high enough to regulate the boost output voltage under heavy load conditions. This then causes the boosted rail to sag, possibly causing distortion of the output waveform.

7.3.10 Internal Charge Pump

The DRV2665 device has an integrated charge pump to provide adequate gate drive for internal nodes. The output of this charge pump is placed on the PUMP pin. An X5R or X7R storage capacitor of 0.1 µF with a voltage rating of 10 V or greater must be placed at this pin.

7.3.11 Device Protection

7.3.11.1 Thermal Protection

The DRV2665 device contains an internal temperature sensor that shuts down both the boost converter and the high-voltage amplifier when the temperature threshold is exceeded. When the device temperature falls below the threshold, the device will restart operation automatically. Continuous operation of the device is not recommended. Most haptic use models only operate the device in short bursts. The thermal shutdown function protects the device from damage when overdriven, but usage models which drive the device into thermal shutdown must always be avoided.

7.3.11.2 Overcurrent Protection

If the load demands more current than what the DRV2665 device can supply, the device automatically clamps the output voltage to avoid damage.

7.3.11.3 Brownout Protection

The DRV2665 device has on-chip brownout protection. When activated, a reset signal is issued that returns the DRV2665 device to the initial default state. If the voltage regulator V REG goes below the brownout protection threshold (VBOT) the DRV2665 device automatically shuts down. When VREG returns to the typical output voltage (1.75 V), the DRV2665 device returns to the initial device state. The brownout protection threshold, V BOT, is typically at 0.84 V. There is one exception to this behavior. The brownout circuit is designed to tolerate fast brownout conditions as shown by Case 1 in Figure 7-2. If the V DD ramp-up rate is slower than 3.6 kV/s, then the device can fall into an unknown state. In such a situation, to return to the initial default state the device must be power-cycled with a VDD ramp-up rate that is faster than 3.6 kV/s. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

V(BOT) REG Time Case 1 Case 2 Return to default state Unknown state 0 V Return to default state Unknown state Case 3 Case 4 Slew rate < 3.6 kV/sSlew rate > 3.6 kV/s Slew rate < 3.6 kV/s Slew rate > 3.6 kV/s 1.75 V VDD Figure 7-2. Brownout Behavior

7.4 Device Functional Modes

7.4.1 FIFO Mode

The DRV2665 device includes a 100-byte FIFO for real-time haptic waveform playback. The FIFO mode accepts 8-bit digital haptic waveform data over an I2C compatible bus and writes it into an on-chip FIFO. The data is read out of the FIFO automatically at an 8-kHz sampling rate and fed into a digital-to-analog converter (DAC). The DAC then drives the high-voltage amplifier. This mode is utilized when the user writes directly to the I 2C FIFO entry address (0x0B). When the first data byte is written to the FIFO, the device goes through the proper start-up sequence and begins outputting the waveform automatically. An internal timing sequence waits approximately 2 ms before the first data is sent through the DAC and output by the device. It is important that the data values start and end at or near the mid-scale code (0x00) to avoid large steps at the beginning and end of the waveform. When the FIFO is empty, the device waits for the timeout period , and then enters into an idle state. Because the speed of the serial interface could be faster than the read-out rate of the FIFO, the device does not acknowledge, or NAK, if the FIFO is full during a FIFO write transaction. If at any time the FIFO becomes completely full, the FIFO_FULL bit is set. When in this condition, the FIFO cannot accept more data without overwriting previous data that has not yet been played. If this occurs, the user must wait until data has had a chance to empty from the FIFO before sending more data. The data must be re-sent starting at the byte that received a NAK. Any multi-byte I 2C write to the FIFO register is treated as a continuous write to the FIFO. Multi-byte writes are preferred for optimum performance. The FIFO interprets the incoming data as twos complement. This means the maximum full-scale code is 0x7F, the maximum negative voltage is 0x80, and the mid-scale is 0x00.

7.4.2 Analog Playback Mode

In analog playback mode the signal in the IN+/IN– inputs is amplified and played through the high-voltage amplifier. When the INPUT_MUX bit is set, the DRV2665 device switches the analog inputs (IN+/IN–) to the high-voltage amplifier. While in the analog mode, the gain is still register-selectable . Also, the high-voltage amplifier enable is controlled directly through the EN_OVERRIDE bit, so the EN_OVERRIDE bit must be set for the boost and amplifier to be active.

7.4.3 Low Voltage Operation Mode

The lowest gain setting is optimized for 50 V PP with a boost voltage of 30 V. Some applications may not need 50 VPP, so the user may elect to program the boost converter as low as 15 V to improve efficiency. When using boost voltages lower than 30 V, consider the following: First, to reduce boost ripple to an acceptable level, a 50-V rater, 0.22-µF boost capacitor is recommended. Second, the maximum code range of the digital interface is limited. For example, the user may elect to program the boost voltage to 25 V, and plan for a maximum drive signal of 40 V PP at the actuator. Any digital code given to the FIFO that is greater than 20 V P / 25 V P x 127 = ±102 may induce clipping, so the user must only send digital codes between –102 and 102. Use of codes outside this range, for this example, may clip or drive the actuator beyond its rating. www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRV2665

7.5 Programming

7.5.1 Programming the Boost Voltage

The boost output voltage is programmed through two external resistors as shown in Figure 7-3. The boost output voltage is given by Equation 1. FB V(BST) Figure 7-3. FB Network © ¹ (BST) (FB) RV = V R (1) where

• V(FB) = 1.32 V V(BST) must be programmed to a value of 5.0 V greater than the largest peak voltage expected in the system to allow adequate amplifier headroom. Because the programming range for the boost voltage extends to 105 V, the leakage current through the resistor divider can become significant. It is recommended that the sum of the resistances R 1 + R 2 be greater than 400 k Ω. When resistor values greater than 1 M Ω are used, PCB contamination may cause boost voltage inaccuracy. Exercise caution when soldering large resistances, and clean the area when finished for best results. Table 7-2 shows examples on how to configure the device for different output voltages. Table 7-2. Boost Voltage Table R1 R2 GAIN[1:0] V(BST) FULL SCALE PEAK VOLTAGE (V) 402 kΩ 18.2 kΩ 00 30 25 392 kΩ 9.76 kΩ 01 55 50 768 kΩ 13 kΩ 10 80 75 768 kΩ 9.76 kΩ 11 105 100

7.5.2 Programming the Boost Current Limit

The peak current drawn from the supply through the inductor is set solely by the R (EXT) resistor. This peak current limit is independent of the inductance value chosen, but the inductor must be capable of handling this programmed limit. The relationship of R(EXT) and ILIM is approximated by Equation 2. © ¹ REF (EXT) INT LIM VR = K R I (2) where

• K = 10500, , and
• VREF = 1.35 V
• RINT = 60 Ω
• ILIM is the desired peak current limit through the inductor. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

7.5.3 I2C Interface

7.5.3.1 General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 7-4 shows a typical sequence. The master device generates the 7-bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection. The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word transfers, the master generates a stop condition to release the bus. Figure 7-4 shows a generic data-transfer sequence. Use external pullup resistors for the SDA and SCL signals to set the logic-high level for the bus. Pullup resistors with values between 660 Ω and 4.7 k Ω are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2665 supply voltage, VDD. The DRV2665 device operates as an I 2C-slave with 1.8-V logic thresholds, but can operate up to the V DD voltage. Note The slave address for the DRV2665 device is 0x59 (7-bit), or 1011001 in binary, which is equivalent to 0xB2 (8-bit) for writing and 0xB3 (8-bit) for reading. 7-bit slave address A 8-bit register address (N) A 8-bit register data for address (N) A 8-bit register data for address (N) A StopStart R/W b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 Figure 7-4. Typical I2C Sequence

7.5.3.2 Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read-write operations for all registers. During multi-byte transactions, the register address provided serves as the starting address. Subsequent data transfers automatically increment the register address accessed until a stop condition is reached.

7.5.3.3 Single-Byte Write

As shown in Figure 7-5 , a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I 2C device address and the read-write bit. The read-write bit determines the direction of the data transfer. For a write-data transfer, the read-write bit must be set to 0. After receiving the correct I2C device address and the read-write bit, the DRV2665 device responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the DRV2665 internal-memory address that is accessed. www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV2665

After receiving the register byte, the device responds again with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer. Stop conditionStart condition I2C device address and R/W bit Subaddress Data byte Acknowledge Acknowledge Acknowledge A5A6 D6A4 D5A3 D4A2 D3ACK D2A0 D1D7 D0A1 ACKA4 A3 A2 A1 A0 W ACK A7 A6 A5 Figure 7-5. Single-Byte Write Transfer

7.5.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DRV2665 device. After receiving each data byte, the DRV2665 device responds with an acknowledge bit as shown in Figure 7-6. Stop conditionStart condition I2C device address and R/W bit Subaddress First data byte Acknowledge Acknowledge AcknowledgeAcknowledge Other data bytes Acknowledge Last data byte D0 ACK D7 D0 ACKD0 ACK D7D1ACK D7 D6A0A1ACK A7 A6WA0A1A0A1 Figure 7-6. Multiple-Byte Write Transfer

7.5.3.5 Single-Byte Read

Figure 7-7 shows that a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I 2C device address and the read-write bit. For the data-read transfer, both a write followed by a read actually occur. Initially, a write occurs to transfer the address byte of the internal memory address to be read. As a result, the read-write bit is set to 0. After receiving the DRV2665 address and the read-write bit, the DRV2665 device responds with an acknowledge bit. The master then sends the internal memory address byte, after which the device issues an acknowledge bit. The master device transmits another start condition followed by the DRV2665 address and the read-write bit again. This time, the read-write bit is set to 1, indicating a read transfer. Next, the DRV2665 device transmits the data byte from the memory address that is read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. See the note in the Section 7.5.3.1 section for the device address. A6 A5 A1 A0 W A7 A6 A1 A0 A6 A5 D0 Stop Condition Start Condition I2C device address and R/W bit Subaddress Acknowledge Acknowledge Acknowledge A0 R Acknowledge Data ByteRepeat start condition I2C device address and R/W bit ACK ACK ACK ACK Figure 7-7. Single-Byte Read Transfer DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

16 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

7.5.3.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the DRV2665 device to the master device as shown in Figure 7-8. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte. W Start condition I2C device address and R/W bit Subaddress Acknowledge Acknowledge Acknowledge R Acknowledge First data byteRepeat start condition I2C device address and R/W bit Stop condition AcknowledgeAcknowledge Other data byte Last data byte A6 A0 ACK A7 A6 A1 A0 ACK A6 A5 A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK Figure 7-8. Multiple-Byte Read Transfer www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRV2665

7.6 Register Map

Table 7-3. Register Map Overview REG NO. DEFAULT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0x00 0x02 Reserved FIFO_EMPTY FIFO_FULL 0x01 0x28 Reserved CHIPID[3:0] INPUT_MUX GAIN[1:0] 0x02 0x40 DEV_RST STANDBY Reserved TIMEOUT[1:0] EN_OVERRIDE Reserved 0x0B 0x00 FIFO[7:0] DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

18 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

7.6.1 Address: 0x00

Figure 7-9. 0x00 7 6 5 4 3 2 1 0 Reserved FIFO_EMPTY[0] FIFO_FULL[0] RO-1 RO-0 Table 7-4. Address: 0x00 BIT FIELD TYPE DEFAULT DESCRIPTION 7-2 Reserved 1 FIFO_EMPTY RO 1 Indicates that the internal 100-byte FIFO is empty. 0 FIFO is not empty. 1 FIFO is empty.

0 FIFO_FULL RO 0 Indicates that the internal100-byte FIFO is full and

cannot accept data until another byte has played through the internal DAC. 0 FIFO is not full. 1 FIFO is full.

7.6.2 Address: 0x01

Figure 7-10. 0x01 7 6 5 4 3 2 1 0 Reserved CHIPID[3:0] INPUT_MUX[0] GAIN[1:0] RO-0 RO-1 RO-0 RO-1 R/W-0 R/W-0 R/W-0 Table 7-5. Address: 0x01 BIT FIELD TYPE DEFAULT DESCRIPTION

7 Reserved

6-3 CHIPID[3:0] RO 5 Identifies the device.

0 DRV2660

7 DRV2667

2 INPUT_MUX R/W 0 Selects the source to be played.

0 Digital input source

1 Analog input source

1-0 GAIN[1:0] R/W 0 Selects the gain for the amplifier. 0 25 V (Digital) - 28.8 dB (Analog) 1 50 V (Digital) - 34.8 dB (Analog) 2 75 V (Digital) - 38.4 dB (Analog) 3 100 V (Digital) - 40.7 dB (Analog) www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DRV2665

7.6.3 Address: 0x02

Figure 7-11. 0x02 7 6 5 4 3 2 1 0 DEV_RST[0] STANDBY[0] Reserved TIMEOUT[1:0] EN_OVERRIDE[0] Reserved R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 Table 7-6. Address: 0x02 BIT FIELD TYPE DEFAULT DESCRIPTION

7 DEV_RST R/W 0 When asserted, the device will immediately stop

any transaction in process, reset all of its internal register to their default values, and enters standby mode.

0 Normal operation

1 Reset device

6 STANDBY R/W 1 Low-power standby

0 Device is active and

ready to receive a signal.

1 Device is in low power

standby mode. 5-4 Reserved 3-2 TIMEOUT[1:0] R/W 0 Time period when the FIFO runs empty and the device goes into idle mode, powering down the boost converter and amplifier. 0 5 ms 1 10 ms 2 15 ms 3 20 ms

1 EN_OVERRIDE R/W 0 Override bit for the boost converter and amplifier

enables. Boost converter and amplifier enables are controlled by device logic. Boost converter and amplifier are enabled indefinitely. 0--1 Reserved

7.6.4 Address: 0x0B

Figure 7-12. 0x0B 7 6 5 4 3 2 1 0 FIFO[7:0] R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-7. Address: 0x0B BIT FIELD TYPE DEFAULT DESCRIPTION 7-0 FIFO[7:0] R/W 0 Entry point for FIFO data. The user repeatedly writes this register with continuous haptic waveform data. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

20 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers must validate and test their design implementation to confirm system functionality.

8.1 Application Information

The typical application for a haptic driver is in a touch-enabled system that already has an application processor that makes the decision on when to execute haptic effects. The DRV2665 device is configured and can be used fully with I 2C communication to stream or launch haptic effects. Additionally, the system designer may decide to use the analog input to stream the desired haptic effects. VDD REG SDA SCL IN+ IN- PUMP GND SW BST PVDD FB OUT+ OUT- REXT RPURPU 3.3 V to 5.5 V Piezo Actuator C(VDD) Cbulk C(REG) C(BST) R(EXT)C(PUMP) C(IN) C(IN) Application Processor DAC SDA SCL Optional Figure 8-1. Typical Application Configuration Table 8-1. Recommended External Components COMPONENT DESCRIPTION SPECIFICATION TYPICAL VALUE C(VDD) Input capacitor Capacitance 1 µF C(REG) Regulator capacitor Capacitance 0.1 µF C(BST) Boost capacitor Capacitance 0.1 µF CBULK Bulk capacitor Capacitance 10 µF C(PUMP) Internal charge pump capacitor Capacitance 0.1 µF C(IN) AC coupling capacitor (optional) Capacitance 1 µF Boost feedback resistor (see Section 7.5.1) Resistance 768 kΩ Boost feedback resistor (see Section 7.5.1) Resistance 9.76 kΩ Current limit resistor (see Section 7.5.2) Resistance 13 kΩ www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DRV2665

Table 8-1. Recommended External Components (continued) COMPONENT DESCRIPTION SPECIFICATION TYPICAL VALUE R(PU) Pullup resistor Resistance 2.2 kΩ L1 Boost inductor Inductance 3.3 µH

8.2 Typical Application

A typical application of the DRV2665 device is in a system that has external buttons which fire different haptic effects when pressed. Figure 8-2 shows a typical schematic of such a system. The buttons can be physical buttons, capacitive-touch buttons, or GPIO signals coming from the touch-screen system. Effects in this type of system are programmable. MSP430G2553 P1.6/SCL P1.7/SDA SCL SDA REG OUT- VDD GND OUT+ Rpu 2.2 k Rpu 2.2 k C(REG) C(VDD) Li-Ion TPS73633 GND IN EN OUT NR/FB CLDO DVSSAVSS AVCC DVCC 1 uF 0.1 uF Creg P2.0 P2.1 Captouch Buttons SBWTDIO SBWTCK Programming RSBW 9.76 k 3.3 V 0.1 uF 1 uF Piezo Actuator SW 3.3 uH BST C(BST) 0.1 uF 768 k FB 9.76 k PUMPC(PUMP) 0.1 uF EXT R(EXT) 13 k CBULK Figure 8-2. Example Application Schematic

8.2.1 Design Requirements

For this design example, use the values listed in Table 8-2 as the input parameters. Table 8-2. Design Parameters DESIGN PARAMETER EXAMPLE VALUE Actuator type 120 VPP Input power source Li-ion / Li-polymer

8.2.2 Detailed Design Procedure

8.2.2.1 Inductor Selection

Inductor selection plays a critical role in the performance of the DRV2665 device. The range of recommended inductances is from 3.3 µF to 22 µF . In general, higher inductances within an inductor series of a given manufacturer have lower saturation current limits, and vice-versa. When a larger inductance is chosen, the device boost converter automatically runs at a lower switching frequency and incurs less switching losses; however, larger values of inductance may have higher equivalent series resistance (ESR), that increases the parasitic inductor losses. Because lower values of inductance generally have higher saturation currents, they are a better choice when attempting to maximize the output current of the boost converter. Ensure that the saturation current of the inductor selected is higher than the programmed current limit for the device. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

22 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

8.2.2.2 Piezo Actuator Selection

There are several key specifications to consider when choosing a piezo actuator for haptics, such as dimensions, blocking force, and displacement. However, the key electrical specifications from the driver perspective are voltage rating and capacitance. At the maximum frequency of 500 Hz, the device is optimized to drive up to 50 nF at 200 V PP, that is the highest voltage swing capability. It drives larger capacitances if the programmed boost voltage is lowered and/or the user limits the input frequency range to lower frequencies (e.g. 300 Hz).

8.2.2.3 Boost Capacitor Selection

The boost output voltage may be programmed as high as 105 V. A capacitor with a voltage rating of at least the boost output voltage must be selected. A 250-V rated 100-nF capacitor of the X5R or X7R type is recommended for the 105 V case because ceramic capacitors tend to come in ratings of 100 V or 250 V. The selected boost capacitor must have a minimum working capacitance of at least 50 nF. For boost voltages from 30 V to 80 V, a 100-V rated or 250-V rated, 100-nF capacitor is acceptable. For boost voltages less than 30 V, a 50-V, 0.22-µF capacitor is recommended.

8.2.2.4 Bulk Capacitor Selection

The use of a bulk capacitor placed next to the inductor is recommended due to the switch pin current requirements. A ceramic capacitors of the X5R or X7R type with capacitance of at least 1 µF is recommended.

8.2.3 Application Curves

t − Time − s Voltage − V 0 100m 200m 300m 400m 500m 600m 700m −100 −75 −50 −25 100 [OUT+] − [OUT−] Figure 8-3. Example Waveform – Pinball Effect t − Time − s Voltage − V 0 5m 10m 15m 20m 25m 30m 35m 40m −50 100 150 200 OUT+ OUT− VBST I2C (5V/div) Figure 8-4. Typical Waveform www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: DRV2665

8.3 Initialization Setup

The DRV2665 device features a simple initialization procedure:

8.3.1 Initialization Procedure

1. Apply power to the DRV2665 device. 2. Wait for 1 ms for the DRV2665 device to power-up before attempting an I2C write. 3. Exit low-power standby mode by clearing the STANDBY bit in register 0x02, bit 6. 4. Choose the interface mode as analog or digital in register 0x01, bit 2. 5. Select the gain setting for your application in register 0x01, bits [1:0]. 6. Choose the desired timeout period in register 0x02, bits[3:2]. 7. If using the digital interface mode, the device is now ready to receive data. If using the analog input mode, set the EN_OVERRIDE bit in register 0x02, bit 1 to enable the boost and high-voltage amplifier and begin sourcing the waveform to the analog input.

9 Power Supply Recommendations

The DRV2665 device is designed to operate from an input-voltage supply range between 3.3 V and 5.5 V. The decoupling capacitor for the power supply must be placed as close to the device pin as possible. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

24 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

10 Layout

10.1 Layout Guidelines

Use the following guidelines for the DRV2665 device layout:

• The decoupling capacitor for the power supply (VDD) must be placed close to the device pin.
• The filtering capacitor for the regulator (REG) must be placed close to the device pin.
• The boost inductor must be placed as close as possible to the SW pin.
• The bulk capacitor for the boost must be placed as close as possible to the inductor.
• The charge pump capacitor (PUMP) must be placed close to the device pin. Use of the thermal footprint outlined by this datasheet is recommended to achieve optimum device performance. See land pattern diagram for exact dimensions. The DRV2665 device power pad must be soldered directly to the thermal pad on the printed circuit board. The printed circuit board thermal pad must be connected to the ground net and thermal vias to any existing backside/internal copper ground planes. Connection to a ground plane on the top layer near the corners of the device is also recommended. Another key layout consideration is to keep the boost programming resistors (R1 and R2) as close as possible to the FB pin of the device. Care must be taken to avoid getting the FB trace near the SW trace.

10.2 Layout Example

C(BST) Top Layer (1) Bottom Layer (4) Via R(EXT) C(VDD) C(REG)C(PUMP) C(BULK) Figure 10-1. Layout Example with a 4-Layer Board www.ti.com DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DRV2665

11 Device and Documentation Support

11.1 Community Resources

11.2 Trademarks

All trademarks are the property of their respective owners.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DRV2665 SLOS740C – MAY 2012 – REVISED JANUARY 2023 www.ti.com

26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: DRV2665

www.ti.com 21-Jul-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV2665RGPR Active Production QFN (RGP) | 20 3000 | LARGE T&R Yes NIPDAU Level-4-260C-72 HR -40 to 70 2665 DRV2665RGPR.A Active Production QFN (RGP) | 20 3000 | LARGE T&R Yes NIPDAU Level-4-260C-72 HR -40 to 70 2665 DRV2665RGPR.B Active Production QFN (RGP) | 20 3000 | LARGE T&R - Call TI Call TI -40 to 70 DRV2665RGPT Active Production QFN (RGP) | 20 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR -40 to 70 2665 DRV2665RGPT.A Active Production QFN (RGP) | 20 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR -40 to 70 2665 DRV2665RGPT.B Active Production QFN (RGP) | 20 250 | SMALL T&R - Call TI Call TI -40 to 70 DRV2665RGPTG4 Active Production QFN (RGP) | 20 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR -40 to 70 2665 DRV2665RGPTG4.A Active Production QFN (RGP) | 20 250 | SMALL T&R Yes NIPDAU Level-4-260C-72 HR -40 to 70 2665 DRV2665RGPTG4.B Active Production QFN (RGP) | 20 250 | SMALL T&R - Call TI Call TI -40 to 70 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 21-Jul-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 22-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 22-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV2665RGPR QFN RGP 20 3000 346.0 346.0 33.0 DRV2665RGPT QFN RGP 20 250 210.0 185.0 35.0 DRV2665RGPTG4 QFN RGP 20 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGP 20 VERY THIN QUAD FLATPACK4 x 4, 0.5 mm pitch 4224735/A

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4219028/A 12/2018 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD RGP0020D A 0.08 C

0.1 C A B

0.05 C B SYMM PIN 1 INDEX AREA 4.1 3.9 4.1 3.9

1 MAX

0.05 0.00 2.8 2.6 16X 0.5 (0.2) TYP PIN 1 IDENTIFICATION (OPTIONAL) LEAD DETAIL "A" (0.1) TYP LEAD DETAIL "A" OPTION 20X 0.5 0.3 6 10 1620 20X 0.30 0.18 SYMM SEATING PLANE C

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4219028/A 12/2018 www.ti.com VQFN - 1 mm max heightRGP0020D PLASTIC QUAD FLATPACK- NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X ( 2.7) (2) (3.8) (2) (3.8) (1.1) (1.1) 20X (0.6) 20X (0.24) 16X (0.5) (R0.05) TYP (Ø0.2) VIA TYP SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

0.07 MAX

0.07 MIN

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4219028/A 12/2018 www.ti.com VQFN - 1 mm max heightRGP0020D PLASTIC QUAD FLATPACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 77% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM 4X ( 1.19) (2) (3.8) (2) (3.8) (0.695) (0.695) 20X (0.6) 20X (0.24) 16X (0.5) (R0.05) TYP 20 16 106 METAL TYP

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated