Driver IC

DRV2605L

Texas Instruments

DRV2605L 2 to 5.2 V Haptic Driver for LRA and ERM With Effect Library and Smart-Loop Architecture

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DRV2605L 2- to 5.2-V Haptic Driver for LRA and ERM with Effect Library and Smart-Loop Architecture datasheet (Rev. D)

Document overview

Manufacturer or author: Texas Instruments, Incorporated [SLOS854,D]
PDF pages: 76

Technical content

M LRA or ERM OUT ± OUT+ GND REG IN/TRIG SDA SCL EN VDD Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV2605L SLOS854D –MAY 2014–REVISED MARCH 2018 DRV2605L2-to5.2-VHapticDriverforLRAandERM withEffectLibraryandSmart-LoopArchitecture

1 Features

1• Flexible Haptic and Vibration Driver – LRA (Linear Resonance Actuator) – ERM (Eccentric Rotating Mass)

I2C-Controlled Digital Playback Engine – Waveform Sequencer and Trigger – Real-Time Playback Mode through I2C – I2C Dual-Mode Drive (Open and Closed Loop)
Smart-Loop Architecture (Patent Pending Control Algorithm) – Automatic Overdrive and Braking – Automatic Resonance Tracking and Reporting (LRA Only) – Automatic Actuator Diagnostic – Automatic Level Calibration – Wide Support for Actuator Models
Licensed Immersion TouchSense® 2200 Features: – Integrated Immersion Effect Library – Audio-to-Vibe
Drive Compensation Over Battery Discharge
Wide Voltage Operation (2 V to 5.2 V)
Efficient Differential Switching Output Drive
PWM Input with 0% to 100% Duty-Cycle Control Range
Hardware Trigger Input
Fast Startup Time
1.8-V Compatible, VDD-Tolerant Digital Interface

2 Applications

Mobile Phones and Tablets
Watches and Wearable Technology
Remote Controls, Mice, and Peripheral Devices
Touch-Enabled Devices
Industrial Human-Machine Interfaces
Electronic Point of Sale (ePOS)

3 Description

The DRV2605L device is a low-voltage haptic driver that includes a haptic-effect library and provides a closed-loop actuator-control system for high-quality tactile feedback for ERM and LRA. This schema helps improve actuator performance in terms of acceleration consistency, start time, and brake time and is accessible through a shared I2C compatible bus or PWM input signal. The DRV2605L device offers a licensed version of TouchSense 2200 software from Immersion which eliminates the requirement to design haptic waveforms because the software includes over 100 licensed effects (6 ERM libraries and 1 LRA library) and audio-to-vibe features. Additionally, the real-time playback mode allows the host processor to bypass the library playback engine and play waveforms directly from the host through I2C. The smart-loop architecture inside the DRV2605L device allows simple auto-resonant drive for the LRA as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. The smart-loop architecture creates a simplified input waveform interface as well as reliable motor control and consistent motor performance. The DRV2605L device also features automatic transition to an open-loop system in the event that an LRA actuator is not generating a valid back-EMF voltage. When the LRA generates a valid back-EMF voltage, the DRV2605L device automatically synchronizes with the LRA. The DRV2605L also allows for open-loop driving through the use of internally-generated PWM. Additionally, the audio-to-vibe mode automatically converts an audio input signal to meaningful tactile effects. For an important notice regarding Immersion software, see the Legal Notice section. Device Information(1) PART NUMBER PACKAGE BODY SIZE (MAX) DRV2605L DSBGA (9) 1.50 mm × 1.50 mm DRV2605L VSSOP (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic

12.3 Receiving Notification of Documentation Updates 64

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (September 2014) to Revision D Page

Changed the Handling Ratings table to ESD Ratings and moved the storage temperature to the Absolute Maximum
Changed AC couple capacitor recommendation from 0.1 µF to 1 µF to be consistent with Recommended External Changes from Revision B (June 2014) to Revision C Page Changes from Revision A (May 2014) to Revision B Page

www.ti.com SLOS854D –MAY 2014–REVISED MARCH 2018 Product Folder Links: DRV2605L Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated Changes from Original (May 2014) to Revision A Page

A B C Not to scale EN REG OUT+ IN/TRIG SDA GND SCL VDD OUT ± DRV2605L SLOS854D –MAY 2014–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV2605L Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated (1) I = input, O = output, I/O = input and output, P = power

5 Pin Configuration and Functions

9-Pin DSBGA With 0.5-mm Pitch (Top View) Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME A1 EN I Device enable A2 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor is required. A3 OUT+ O Positive haptic driver differential output B1 IN/TRIG I Multi-mode Input. I2C selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND B2 SDA I/O I2C data B3 GND P Supply ground C1 SCL I I2C clock C3 OUT– O Negative haptic-driver differential output C2 VDD P Supply input (2 to 5.2 V). A 1-µF capacitor is required.

2SCL 9 OUT ± 3SDA 8 GND 4IN/TRIG 7 OUT+ 5EN 6 VDD /NC Not to scale DRV2605L www.ti.com SLOS854D –MAY 2014–REVISED MARCH 2018 Product Folder Links: DRV2605L Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated (1) I = input, O = output, I/O = input and output, P = power 10-Pin VSSOP (Top View) Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 REG O The REG pin is the 1.8-V regulator output. A 1-µF capacitor required

2 SCL I I2C clock

3 SDA I/O I2C data

4 IN/TRIG I Multi-mode Input. I2C is selectable as PWM, analog, or trigger. If not used, this pin should be connected to GND

5 EN I Device enable

6 VDD/NC P Optional supply input. This pin should be tied to VDD or left floating.

7 OUT+ O Positive haptic driver differential output

8 GND P Supply ground

9 OUT– O Negative haptic driver differential output

10 VDD P Supply Input (2 V to 5.2 V). A 1-µF capacitor is required.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range, TA = 25°C (unless otherwise noted) MIN MAX UNIT Input voltage VDD –0.3 5.5 V EN –0.3 VDD + 0.3 V SDA –0.3 VDD + 0.3 V SCL –0.3 VDD + 0.3 V IN/TRIG –0.3 VDD + 0.3 V Operating free-air temperature, TA –40 85 °C Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance. (3) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±250 10-PIN VSSOP PACKAGE V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 OUT+, OUT– pins(3) ±500 VOther pins(1) ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±250 (1) Ensured by design. Not production tested.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD Supply voltage VDD 2 5.2 V ƒ(PWM) PWM input frequency(1) IN/TRIG Pin 10 250 kHz ZL Load impedance(1) VDD = 5.2 V 8 Ω VIL Digital low-level input voltage EN, IN/TRIG, SDA, SCL 0.5 V VIH Digital high-level input voltage EN, IN/TRIG, SDA, SCL 1.3 V VI(ANA) Input voltage (analog mode) IN/TRIG 0 1.8 V ƒ(LRA) LRA Frequency Range(1) 125 300 Hz (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) DRV2605L UNITYZF (DSBGA) (9-PINS) RθJA Junction-to-ambient thermal resistance 145.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W RθJB Junction-to-board thermal resistance 105 °C/W φJT Junction-to-top characterization parameter 5.1 °C/W φJB Junction-to-board characterization parameter 103.3 °C/W

6.5 Electrical Characteristics

TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(REG) Voltage at the REG pin 1.83 V IIL Digital low-level input current EN, IN/TRIG, SDA, SCL VDD = 5.2 V , VI = 0 V 1 µA IIH Digital high-level input current IN/TRIG, SDA, SCL VDD = 5.2 V, VI = VDD µA EN VDD = 5.2 V, VI = VDD 3.5 VOL Digital low-level output voltage SDAIOL= 4 mA 0.4 V R(EN-GND) Digital pull-down resistance EN VDD = 5.2 V , VI = VDD 2 MΩ I(SD) Shutdown current V(EN) = 0 V 4 7 µA II(standby) Standby current V(EN) = 1.8 V, STANDBY = 1 4.1 7 µA IQ Quiescent current V(EN) = 1.8 V, STANDBY = 0, no signal 0.5 0.65 mA ZI Input impedance IN/TRIG to V(CM_ANA) 100 kΩ V(CM_ANA) IN/TRIG common-mode voltage (AC-coupled) AC_COUPLE = 1 0.9 V ZO(SD) Output impedance in shutdown OUT+ to GND, OUT– to GND 15 kΩ ZL(th) Load impedance threshold for over-current detection OUT+ to GND, OUT– to GND 4 Ω I(BAT_AV) Average battery current during operation Duty cycle = 90%, LRA mode, no load 2.4 3.5 mA Duty cycle = 90%, ERM mode, no load 2.3 3.5

6.6 Timing Requirements

TA = 25°C, VDD = 3.6 V (unless otherwise noted) MIN NOM MAX UNIT ƒ(SCL) Frequency at the SCL pin with no wait states 400 kHz tw(H) Pulse duration, SCL high See Figure 1. 0.6 µs tw(L) Pulse duration, SCL low 1.3 µs tsu(1) Setup time, SDA to SCL 100 ns th(1) Hold time, SCL to SDA 10 ns t(BUF) Bus free time between stop and start condition See Figure 2. 1.3 µs tsu(2) Setup time, SCL to start condition 0.6 µs th(2) Hold time, start condition to SCL 0.6 µs tsu(3) Setup time, SCL to stop condition 0.6 µs

6.7 Switching Characteristics

TA = 25°C, VDD = 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t(start) Start-up time Time from the GO bit or external trigger command to output signal 0.7 ms Time from EN high to output signal (PWM/Analog Modes) 1.5 ƒO(PWM) PWM Output Frequency 19.5 20.5 21.5 kHz

6.8 Typical Characteristics

Figure 3. ERM Click with and Without Braking (ROM) Figure 4. LRA Click with Braking (ROM) Figure 5. ERM Click-Bounce (ROM) Figure 6. LRA Transition-Click (ROM) Figure 7. ERM Buzz (RTP) Figure 8. LRA Click With and Without Braking (PWM)

Figure 9. Startup Latency for ERM and LRA Figure 10. Supply Current vs Supply Voltage (Full Vibration)

7 Parameter Measurement Information

7.1 Test Setup for Graphs

approximately 1% loss in measured amplitude because of the voltage-divider effect with the filter. Figure 11. Test Setup

7.1.1 Default Test Conditions

VDD = 3.6 V, unless otherwise noted.
Real actuators (as opposed to modeled actuators) were used as loads for both ERM and LRA modes with exception of the Supply Voltage vs Supply Current (Full Vibration) waveform in Figure 10, which used passive RL (resistance in series with an inductance) loads for test repeatability. Real actuators vary widely in supply currents because of variation in back-EMF voltages. Because real actuators have back EMF, the real supply current is generally less than what is shown in the waveform because of the reduction in the apparent load impedance. Therefore, the curve shows the worst-case current.
All ERM library waveforms were taken with Library A in open-loop mode
All LRA library waveforms were taken with the LRA Library in closed-loop mode
All traces are 2 V/div except for the accelerometer traces
All accelerometer traces are 0.87 g/div except for the LRA Click with and without Braking (PWM) curve in Figure 8, which is 1.74 g/div.

M LRA or ERM OUT ± OUT+ GND REG IN/TRIG SDA SCL EN VDD DRV2605L www.ti.com SLOS854D –MAY 2014–REVISED MARCH 2018 Product Folder Links: DRV2605L Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The DRV2605L device is a low-voltage haptic driver that relies on the back-EMF produced by an actuator to provide a closed-loop system that offers extremely flexible control of LRA and ERM actuators over a shared I2C- compatible bus or PWM input signal. This schema helps improve actuator performance in terms of acceleration consistency, start time, and brake time. The improved smart-loop architecture inside the DRV2605L device provides effortless auto-resonant drive for LRA, as well as feedback-optimized ERM drive allowing for automatic overdrive and braking. These features create a simplified input waveform paradigm as well as reliable motor control and consistent motor performance. The DRV2605L device also features an automatic transition to open-loop operation in the event that an LRA actuator is not generating a valid back-EMF voltage and automatic synchronization with the LRA when the LRA is generating a valid back-EMF voltage. The DRV2605L device also allows for open-loop driving by using internally-generated PWM. Additionally, the audio-to-vibe mode automatically converts an audio input signal to meaningful haptic effects. The DRV2605L device offers a licensed version of TouchSense 2200 software from Immersion which eliminates the requirement to design haptic waveforms because the software includes over 100 licensed effects (6 ERM libraries and 1 LRA library) and audio-to-vibe features. The waveforms can be instantly played back through an I2C or can be triggered through a hardware trigger pin. Additionally, the real-time playback mode allows the host processor to bypass the library playback engine and play waveforms directly from the host through the I2C. The DRV2605L device features a trinary-modulated output stage that provides more efficiency than linear-based output drivers.

8.2 Functional Block Diagram

(LRA_OL) ± OL_LRA_PERIOD[6:0] × 98.49 × 10 1 0 (LRA_NO-BEMF) (DRIVE_TIME[4:0]) (ZC _DET _ TIME[ : ]) W ±W u DRV2605L SLOS854D –MAY 2014–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV2605L Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Support for ERM and LRA Actuators

The DRV2605L device supports both ERM and LRA actuators. The ERM_LRA bit in register 0x1A must be configured to select the type of actuator that the device uses.

8.3.2 Smart-Loop Architecture

The smart-loop architecture is an advanced closed-loop system that optimizes the performance of the actuator and allows for failure detection. The architecture consists of automatic resonance tracking and reporting (for an LRA), automatic level calibration, accelerated startup and braking, diagnostics routines, and other proprietary algorithms.

8.3.2.1 Auto-Resonance Engine for LRA

The DRV2605L auto-resonance engine tracks the resonant frequency of an LRA in real time, effectively locking onto the resonance frequency after half of a cycle. If the resonant frequency shifts in the middle of a waveform for any reason, the engine tracks the frequency from cycle to cycle. The auto-resonance engine accomplishes the tracking by constantly monitoring the back-EMF of the actuator. The auto-resonance engine is not affected by the auto calibration process, which is only used for level calibration. No calibration is required for the auto resonance engine. See the Auto-Resonance Engine Programming for the LRA section for auto-resonance engine programming information.

8.3.2.2 Real-Time Resonance-Frequency Reporting for LRA

The smart-loop architecture makes the resonant frequency of the LRA available through I2C (see the LRA Resonance Period (Address: 0x22) section). Because frequency reporting occurs in real time, the frequency must be polled while the DRV2605L device synchronizes with the LRA. The data should not be polled when the actuator is idle or braking.

8.3.2.3 Automatic Switch to Open-Loop for LRA

In the event that an LRA produces a non-valid back-EMF signal, the DRV2605L device automatically switches to open-loop operation and continues to deliver energy to the actuator in overdrive mode at a default and configurable frequency. Use Equation 1 to calculate the default frequency. If the LRA begins to produce a valid back-EMF signal, the auto-resonance engine automatically takes control and continues to track the resonant frequency in real time. When synchronized, the mode enjoys all of the benefits that the smart-loop architecture has to offer. (1) The DRV2605L device offers an automatic transition to open-loop mode without the re-synchronization option. The feature is enabled by setting the LRA_AUTO_OPEN_LOOP bit in register 0x1F. The transition to open-loop mode only occurs when the driver fails to synchronize with the LRA. The AUTO_OL_CNT[1:0] bit in register 0x1F can be adjusted to set the amount of non-synchronized cycles allowed before the transition to the open-loop mode. Use Equation 2 to calculate the open-loop frequency. The open-loop mode does not receive benefits from the smart-loop architecture, such as automatic overdrive and braking. (2)

8.3.2.4 Automatic Overdrive and Braking

A key feature of the DRV2605L is the smart-loop architecture which employs actuator feedback control for both ERMs and LRAs. The feedback control desensitizes the input waveform from the motor-response behavior by providing automatic overdrive and automatic braking.

Figure 12. Waveform Simplification With Smart Loop

8.3.2.4.1 Startup Boost

higher loop gain to transient response of the actuator. The STARTUP_BOOST bit enables the feature.

8.3.2.4.2 Brake Factor

8.3.2.4.3 Brake Stabilizer

BRAKE_STABILIZER bit enables the feature.

8.3.2.5 Automatic Level Calibration

The smart-loop architecture uses actuator feedback by monitoring the back-EMF behavior of the actuator. The level of back-EMF voltage can vary across actuator manufacturers because of the specific actuator construction. Auto calibration compensates for the variation and also performs scaling for the desired actuator according to the specified rated voltage and overdrive clamp-register settings. When auto calibration is performed, a 100% signal level at any of the DRV2605L input interfaces supplies the rated voltage to the actuator at steady-state. The feedback allows the output level to increase above the rated voltage level for automatic overdrive and braking, but without allowing the output level to exceed the programmable overdrive clamp voltage. In the event where the automatic level-calibration routine fails, the DIAG_RESULT bit in register 0x00 is asserted to flag the problem. Calibration failures are typically fixed by adjusting the registers associated with the automatic level-calibration routine or, for LRA actuators, the registers associated with the automatic-resonance detection engine. See the Device and Documentation Support section for automatic-level calibration programming.

8.3.2.5.1 Automatic Compensation for Resistive Losses

The DRV2605L device automatically compensates for resistive losses in the driver. During the automatic level- calibration routine, the impedance of the actuator is checked and the compensation factor is determined and stored in the A_CAL_COMP[7:0] bit.

8.3.2.5.2 Automatic Back-EMF Normalization

The DRV2605L device automatically compensates for differences in back-EMF magnitude between actuators. The compensation factor is determined during the automatic level-calibration routine and the factor is stored in the A_CAL_BEMF[7:0] bit.

8.3.2.5.3 Calibration Time Adjustment

The duration of the automatic level-calibration routine has an impact on accuracy. The impact is highly dependent on the start-time characteristic of the actuator. The auto-calibration routine expects the actuator to have reached a steady acceleration before the calibration factors are calculated. Because the start-time characteristic can be different for each actuator, the AUTO_CAL_TIME[1:0] bit can change the duration of the automatic level-calibration routine to optimize calibration performance.

8.3.2.5.4 Loop-Gain Control

The DRV2605L device allows the user to control how fast the driver attempts to match the back-EMF (and thus motor velocity) and the input signal level. Higher loop-gain (or faster settling) options result in less-stable operation than lower loop gain (or slower settling). The LOOP_GAIN[1:0] bit controls the loop gain.

8.3.2.5.5 Back-EMF Gain Control

The BEMF_GAIN[1:0] bit sets the analog gain for the back-EMF amplifier. The auto-calibration routine automatically populates the bit with the most appropriate value for the actuator. Modifying the SAMPLE_TIME[1:0] bit also adjusts the back-EMF gain. The higher the sample time, the higher the gain. By default, the back-EMF is sampled once during a period. In the event that a twice per-period sampling is desired, assert the LRA_DRIVE_MODE bit.

8.3.2.6 Actuator Diagnostics

The DRV2605L device is capable of determining whether the actuator is not present (open) or shorted. If a fault is detected during the diagnostic process, the DIAG_RESULT bit is asserted.

8.3.2.7 Automatic Re-Synchronization

For the LRA, the DRV2605L device features an automatic re-synchronization mode which automatically pushes the actuator in the correct direction when a waveform begins playing while the actuator is moving. If the actuator is at rest when the waveform begins, the DRV2605L device drives in the default direction.

8.3.3 Open-Loop Operation for LRA

includes an open-loop LRA drive mode that is available through the PWM input or through the digital interface. drive, the host should drive the PWM frequency at 128 times the desired operating frequency. benefits of the smart-loop architecture.

8.3.4 Open-Loop Operation for ERM

amplitude. For details see the Rated Voltage Programming section.

8.3.5 Flexible Front-End Interface

0x01 is used to select the interface mode.

8.3.5.1 PWM Interface

PWM input signal. Specifically, the driving frequency is the PWM frequency divided by 128.

8.3.5.2 Internal Memory Interface

the Library Selection (Address: 0x03) section). Figure 13. Library Selection

Table 1. ERM Library Table

8.3.5.2.1 Waveform Sequencer

whichever scenario is reached first. step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

8.3.5.2.2 Library Parameterization

customizing the entire library of waveforms for a specific actuator rise time and fall time. The time values are additive offsets and are 8-bit signed values. The default offset of the time values is 0. two operative points for the period (see Equation 3).

t(ofs) is the time offset (3) Changing the playback interval can also manipulate the waveforms stored in memory. Each waveform in memory has a granularity of 5 ms. If the user desires greater granularity, a 1-ms playback interval can be obtained by asserting the PLAYBACK_INTERVAL bit in register 0x1F.

8.3.5.3 Real-Time Playback (RTP) Interface

The real-time playback mode is a simple, single 8-bit register interface that holds an amplitude value. When real- time playback is enabled, the real-time playback register is sent directly to the playback engine. The amplitude value is played until the user sends the device to standby mode or removes the device from RTP mode. The RTP mode operates exactly like the PWM mode except that the user enters a register value over the I2C rather than a duty cycle through the input pin. Therefore, any API (application-programming interface) designed for use with a PWM generator in the host processor can write the data values over the I2C rather than writing the data values to the host timer. This ability frees a timer in the host while retaining compatibility with the original software. For the LRA, the DRV2605L device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP bit is set (in register 0x1D). If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the open-loop frequency set in the OL_LRA_PERIOD[6:0] bit in register 0x20.

8.3.5.4 Analog Input Interface

When the DRV2605L device is in analog-input interface mode, the device accepts an analog voltage at the IN/TRIG pin. The DRV2605L device drives the actuator continuously in analog-input interface mode until the user sets the device to standby mode or to enter another interface mode. The reference voltage in standby mode is is interpreted as a 50% input value and a reference voltage of 0 V is interpreted as a 0% input value. The input value in standby mode is analogous to the duty-cycle percentage in PWM mode. For the LRA, the DRV2605L automatically tracks the resonance frequency unless the LRA_OPEN_LOOP bit is set (in register 0x1D). If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the open-loop frequency set in OL_LRA_PERIOD[6:0] bit in register 0x20.

8.3.5.5 Audio-to-Vibe Interface

The DRV2605L device features an audio-to-vibe mode that converts an audio input signal into meaningful haptic effects using the Immersion audio-to-vibe technology. Audio-to-Vibe mode adds a vibratory bass extension to portable devices which allows users to feel the audio and visual content. Audio-to-Vibe mode is a key feature because it allows for existing applications to include haptic sensations without requiring additional software drivers. Additionally, event-driven audio effects generated within an operating system can be used to automatically provide a product with haptic sensations. See the Waveform Playback Using Audio-to-Vibe Mode section for details.

8.3.5.6 Input Trigger Option

The DRV2605L device includes continuous haptic modes (such as PWM and RTP mode) as well as triggered modes (such as the internal memory interface). The haptic effects in the continuous haptic modes begin as soon as the device enters the mode and stop when the device goes into standby mode or exits the continuous haptic mode. For the triggered mode, the DRV2605L device has a variety of trigger options that are explained in this section. In the continuous haptic modes, the IN/TRIG pin provides external trigger control of the GO bit, which allows GPIO control to fire ROM waveforms. The external trigger control can provide improved latencies in systems where a significant delay exists between the desired effect time and the time a GO command can be sent over the I2C interface. NOTE The triggered effect must already be selected to take advantage of the lower latency. This option works best for accelerating a pre-queued high-priority effect (such as a button press) or for the repeated firing of the same effect (such as scrolling).

8.3.5.6.1 I2C Trigger

Setting the GO bit (in register 0x0C) launches the waveform. The user can cancel the launching of the waveform by clearing the GO bit.

8.3.5.6.2 Edge Trigger

long the waveform is. The pulse width should be at least 1 µs to ensure detection. Figure 14. Edge Trigger Mode

8.3.5.6.3 Level Trigger

must hold the IN/TRIG high for the entire duration of the waveform to complete the effect. Figure 15. Level Trigger Mode

8.3.5.7 Noise Gate Control

than a particular threshold. The NG_THRESH[1:0] bit in register 0x1D controls the threshold.

8.3.6 Edge Rate Control

8.3.7 Constant Vibration Strength

The DRV2605L PWM input uses a digital level-shifter. Therefore, as long as the input voltage meets the VIH and VIL levels, the vibration strength remains the same even if the digital levels vary. The DRV2605L device also features power-supply feedback. If the supply voltage drifts over time (because of battery discharge, for example), the vibration strength remains the same as long as enough supply voltage is available to sustain the required output voltage.

8.3.8 Battery Voltage Reporting

During playback, the DRV2605L device provides real-time voltage measurement of the VDD pin. The VBAT[7:0] bit located in register 0x21 provides this information.

8.3.9 One-Time Programmable (OTP) Memory for Configuration

The DRV2605L device contains nonvolatile, on-chip, OTP memory for specific configuration parameters. When written, the DRV2605L device retains the device settings in registers 0x16 through 0x1A including after power cycling. This retention allows the user to account for small variations in actuator manufacturing from unit to unit as well as to shorten the device-initialization process for device-specific parameters such as actuator type, actuator-rated voltage, and other parameters. An additional benefit of OTP is that the DRV2605L memory can be customized at the device-test level without driving changes in the device software.

8.3.10 Low-Power Standby

Setting the device to standby reduces the idle power consumption without resetting the registers. In Low-Power Standby mode, the DRV2605L device features a fast turnon time when it is requested to play a waveform.

8.3.11 I2C Watchdog Timer

If an I2C stops unexpectedly, the possibility exists for the I2C protocol to remain in a hanged state. To allow for the recovery of the communication without having to power cycle the device, the DRV2605L device includes an automatic watchdog timer that resets the I2C protocol without user intervention after 4.33 ms. This behavior happens in all conditions except in standby mode. If the I2C stops unexpectedly during standby mode, the only way to recover communication is by power-cycling the device.

8.3.12 Device Protection

8.3.12.1 Thermal Protection

The DRV2605L device has thermal protection that causes the device to shut down if it becomes too hot. In the event where the thermal protection kicks in, the DRV2605L device asserts a flag (bit OVER_TEMP in register 0x00) to notify the host processor.

8.3.12.2 Overcurrent Protection of the Actuator

If the impedance at the output pin of the DRV2605L device is too low, the device latches the over-current flag (OC_DETECT bit in register 0x00) and shuts down. The device periodically monitors the status of the short and remains in this condition until the short is removed. When the short is removed, the DRV2605L device restarts in the default state.

8.3.12.3 Overcurrent Protection of the Regulator

The DRV2605L device has an internal regulator that powers a portion of the system. If a short occurs at the output of the REG pin, an internal overcurrent protection circuit is enabled and limits the current. During a REG short, the device is not functional. When the short is removed, the DRV2605L device automatically resets to default conditions.

8.3.12.4 Brownout Protection

(V(BOT)) is typically at 0.84 V. cycled with a VDD ramp-up rate that is faster than 3.6 kV/s. Figure 16. Brownout Behavior

8.4 Device Functional Modes

8.4.1 Power States

functions. Figure 17 shows the transition in to and out of each state. Figure 17. Power-State Transition Diagram

8.4.1.1 Operation With VDD < 2 V (Minimum VDD)

Operating the device with a VDD value below 2 V is not recommended. exposed to voltages above 5.5 V, the device can suffer permanent damage.

8.4.1.3 Operation With EN Control

powerup state, set the DEV_RESET bit in register 0x01.

8.4.1.4 Operation With STANDBY Control

effect. For example, if a waveform is played, it immediately stops when the STANDBY bit is asserted. Clear the STANDBY bit to exit the standby state (and go to the ready state).

8.4.1.5 Operation With DEV_RESET Control

automatically-clears after the reset operation is complete.

8.4.1.6 Operation in the Active State

same as the GO bit. Figure 19 shows a diagram of the GO-signal behavior. required to resume normal playback. Figure 18. Diagram of Active States

8.4.2 Changing Modes of Operation

The DRV2605L has multiple modes for playing waveforms, as well as a calibration mode and a diagnostic mode. Table 2 lists the available modes. Table 2. Mode Selection Table

Table 2. Mode Selection Table (continued)

8.4.3 Operation of the GO Bit

(registers 0x04 to 0x0B). However, The GO bit can also fire the calibration or diagnostics processes. when in external trigger mode. The GO bit in register 0x0C mirrors the state of the external trigger. way has no impact on the GO bit located in register 0x0C. Figure 19. GO-Signal Logic

8.4.4 Operation During Exceptional Conditions

conditions. This section also describes how the device goes into and out of these states.

8.4.4.1 Operation With No Actuator Attached

pins toggle at the specified open-loop frequency.

8.4.4.2 Operation With a Non-Moving Actuator Attached

output pins toggle at the specified open-loop frequency.

8.4.4.3 Operation With a Short at REG Pin

If the REG pin is shorted to GND, the device automatically shuts down and an overcurrent-protection circuit is enabled and clamps the maximum current supplied by the regulator. When the short is removed, the device starts in the default condition.

8.4.4.4 Operation With a Short at OUT+, OUT–, or Both

If any of the output pins (OUT+ or OUT–) is shorted to VDD, GND, or to each other while the device is playing a waveform, the OC_DETECT bit is asserted and remains asserted until the short is removed. A current-protection circuit automatically enables to shutdown the current through the short. If the driver is playing a waveform the DRV2605L device checks for shorts in the output through either a haptic- playback, auto-calibration, or diagnostics process. If the short occurs when the device is idle, the short is not detected until the device attempts to run a waveform.

± ± (LRA-OL_RMS) (LRA)9 î î 2'B&/$03> @î ±¦ îî (ERM-OL_AV)V = 21.59 × 10 OD_CLAMP[7:0] (LRA-CL_RMS) ± (SAMPLE_TIME) (LRA) 20.58 × 10 × RATED_VOLTAGE[7:0]V = î W î ¦ u (ERM-CL_AV)V = 21.18 × 10 RATED_VOLTAGE[7:0] DRV2605L SLOS854D –MAY 2014–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV2605L Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated

8.5 Programming

8.5.1 Auto-Resonance Engine Programming for the LRA

8.5.1.1 Drive-Time Programming

The resonance frequency of each LRA actuator varies based on many factors and is generally dominated by mechanical properties. The auto-resonance engine-tracking system is optimized by providing information about the resonance frequency of the actuator. The DRIVE_TIME[4:0] bit is used as an initial guess for the half-period of the LRA. The drive time is automatically and quickly adjusted for optimum drive. For example, if the LRA has a resonance frequency of 200 Hz, then the drive time should be set to 2.5 ms. For ERM actuators, the DRIVE_TIME[4:0] bit controls the rate for back-EMF sampling. Lower drive times imply higher back-EMF sampling frequencies which cause higher peak-to-average ratios in the output signal, and requires more supply headroom. Higher drive times imply lower back-EMF sampling frequencies which cause the feedback to react at a slower rate.

8.5.1.2 Current-Dissipation Time Programming

To sense the back-EMF of the actuator, the DRV2605L device goes into high impedance mode. However, before the device enters high impedance mode, the device must dissipate the current in the actuator. The DRV2605L device controls the time allocated for dissipation-current through the IDISS_TIME[3:0] bit.

8.5.1.3 Blanking Time Programming

After the current in the actuator dissipates, the DRV2605L device waits for a blanking time of the signal to settle before the back-EMF analog-to-digital (AD) conversion converts. The BLANKING_TIME[3:0] bit controls this time.

8.5.1.4 Zero-Crossing Detect-Time Programming

When the blanking time expires, the back-EMF AD monitors for zero crossings. The ZC_DET_TIME[1:0] bit controls the minimum time allowed for detecting zero crossings.

8.5.2 Automatic-Level Calibration Programming

8.5.2.1 Rated Voltage Programming

The rated voltage is the driving voltage that the driver will output during steady state. However, in closed-loop drive mode, temporarily having an output voltage that is higher than the rated voltage is possible. See the Overdrive Voltage-Clamp Programming section for details. The RATED_VOLTAGE[7:0] bit in register 0x16 sets the rated voltage for the closed-loop drive modes. For the ERM, Equation 4 calculates the average steady-state voltage when a full-scale input signal is provided. For the LRA, Equation 5 calculates the root-mean-square (RMS) voltage when driven to steady state with a full-scale input signal. (4) (5) In open-loop mode, the RATED_VOLTAGE[7:0] bit is ignored. Instead, the OD_CLAMP[7:0] bit (in register 0x17) is used to set the rated voltage for the open-loop drive modes. For the ERM, Equation 6 calculates the rated voltage with a full-scale input signal. For the LRA, Equation 7 calculates the RMS voltage with a full-scale input signal. (6) (7) The auto-calibration routine uses the RATED_VOLTAGE[7:0] and OD_CLAMP[7:0] bits as inputs and therefore these registers must be written before calibration is performed. Any modification of this register value should be followed by calibration to appropriately set A_CAL_BEMF[7:0].

(LRA_clamp)V = 21.22 × 10 × OD_CLAMP[7:0] ± ± (DRIVE_TIME) (ERM_ clamp) (DRIVE_TIME) (IDISS_TIME) (BLANKING_TIME) î î 2'B&/$03> @ î W ± î V = t t t DRV2605L www.ti.com SLOS854D –MAY 2014–REVISED MARCH 2018 Product Folder Links: DRV2605L Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated Programming (continued)

8.5.2.2 Overdrive Voltage-Clamp Programming

During closed-loop operation, the actuator feedback allows the output voltage go above the rated voltage during the automatic overdrive and automatic braking periods. The OD_CLAMP[7:0] bit (in Register 0x17) sets a clamp so that the automatic overdrive is bounded. The OD_CLAMP[7:0] bit also serves as the full-scale reference voltage for open-loop operation. The OD_CLAMP[7:0] bit always represents the maximum peak voltage that is allowed, regardless of the mode. NOTE If the supply voltage (VDD) is less than the overdrive clamp voltage, the output driver is unable to reach the clamp voltage value because the output voltage cannot exceed the supply voltage. If the rated voltage exceeds the overdrive clamp voltage, the overdrive clamp voltage has priority over the rated voltage. In ERM mode, use Equation 8 to calculate the allowed maximum voltage. In LRA mode, use Equation 9 to calculate the maximum peak voltage. (8) (9)

8.5.3 I2C Interface

8.5.3.1 General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. The bus transfers data serially, one bit at a time. The 8-bit address and data bytes are transferred with the most-significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on the SDA signal indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. Figure 20 shows a typical sequence. The master device generates the 7- bit slave address and the read-write (R/W) bit to start communication with a slave device. The master device then waits for an acknowledge condition. The slave device holds the SDA signal low during the acknowledge clock period to indicate acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals through a bidirectional bus using a wired-AND connection. The number of bytes that can be transmitted between start and stop conditions is not limited. When the last word transfers, the master generates a stop condition to release the bus. Figure 20 shows a generic data-transfer sequence. Use external pullup resistors for the SDA and SCL signals to set the logic-high level for the bus. Pullup resistors with values between 660 Ω and 4.7 kΩ are recommended. Do not allow the SDA and SCL voltages to exceed the DRV2605L supply voltage, VDD. NOTE The DRV2605L slave address is 0x5A (7-bit), or 1011010 in binary.

Figure 20. Typical I2C Sequence The DRV2605L device operates as an I2C-slave 1.8-V logic thresholds, but can operate up to the VDD voltage.

8.5.3.2 Single-Byte and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte R/W operations for all registers. taken place if a register is issued followed by data for that register as well as the remaining registers that follow. transmitted subsequently before a stop or start is transmitted determines how many registers are written.

8.5.3.3 Single-Byte Write

transmits a stop condition to complete the single-byte data-write transfer. Figure 21. Single-Byte Write Transfer

8.5.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write

byte, the DRV2605L device responds with an acknowledge bit. Figure 22. Multiple-Byte Write Transfer

8.5.3.5 Single-Byte Read

read. As a result, the read-write bit is set to 0. device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer. See the note in the General I2C Operation section. Figure 23. Single-Byte Read Transfer

8.5.3.6 Multiple-Byte Read

last data byte, the master device responds with an acknowledge bit after receiving each data byte. Figure 24. Multiple-Byte Read Transfer

8.5.4 Programming for Open-Loop Operation

the first step is to determine which actuator type is to use, either ERM or LRA.

8.5.4.1 Programming for ERM Open-Loop Operation

N_ERM_LRA bit to 0 (in register 0x1A), and the ERM_OPEN_LOOP bit to 1 in register 0x1D.

8.5.4.2 Programming for LRA Open-Loop Operation

open-loop frequency is given by the OL_LRA_PERIOD[6:0] bit in register 0x20.

8.5.5 Programming for Closed-Loop Operation

adjusts the level and, for the LRA, automatically adjusts the driving frequency.

8.5.6 Auto Calibration Procedure

The calibration engine requires a number of bits as inputs before the engine can be executed (see Figure 25). parameters than the ERM. The LRA parameters are ignored when the device is in ERM mode. Figure 25. Calibration-Engine Functional Diagram

www.ti.com SLOS854D –MAY 2014–REVISED MARCH 2018 Product Folder Links: DRV2605L Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated Programming (continued) The following instructions list the step-by-step register configuration for auto-calibration. For additional details see the Register Map section. 1. Apply the supply voltage to the DRV2605L device, and pull the EN pin high. The supply voltage should allow for adequate drive voltage of the selected actuator. 2. Write a value of 0x07 to register 0x01. This value moves the DRV2605L device out of STANDBY and places the MODE[2:0] bits in auto-calibration mode. 3. Populate the input parameters required by the auto-calibration engine: a. ERM_LRA — selection will depend on desired actuator. b. FB_BRAKE_FACTOR[2:0] — A value of 2 is valid for most actuators. c. LOOP_GAIN[1:0] — A value of 2 is valid for most actuators. d. RATED_VOLTAGE[7:0] — See the Rated Voltage Programming section for calculating the correct register value. e. OD_CLAMP[7:0] — See the Overdrive Voltage-Clamp Programming section for calculating the correct register value. f. AUTO_CAL_TIME[1:0] — A value of 3 is valid for most actuators. g. DRIVE_TIME[3:0] — See the Drive-Time Programming for calculating the correct register value. h. SAMPLE_TIME[1:0] — A value of 3 is valid for most actuators. i. BLANKING_TIME[3:0] — A value of 1 is valid for most actuators. j. IDISS_TIME[3:0] — A value of 1 is valid for most actuators. k. ZC_DET_TIME[1:0] — A value of 0 is valid for most actuators. 4. Set the GO bit (write 0x01 to register 0x0C) to start the auto-calibration process. When auto calibration is complete, the GO bit automatically clears. The auto-calibration results are written in the respective registers as shown in Figure 25. 5. Check the status of the DIAG_RESULT bit (in register 0x00) to ensure that the auto-calibration routine is complete without faults. 6. Evaluate system performance with the auto-calibrated settings. Note that the evaluation should occur during the final assembly of the device because the auto-calibration process can affect actuator performance and behavior. If any adjustment is required, the inputs can be modified and this sequence can be repeated. If the performance is satisfactory, the user can do any of the following: a. Repeat the calibration process upon subsequent power ups. b. Store the auto-calibration results in host processor memory and rewrite them to the DRV2605L device upon subsequent power ups. The device retains these settings when in STANDBY mode or when the EN pin is low. c. Program the results permanently in nonvolatile, on-chip OTP memory. Even when a device power cycle occurs, the device retains the auto-calibration settings. See the Programming On-Chip OTP Memory section for additional information.

8.5.7 Programming On-Chip OTP Memory

The OTP memory can only be written once. To permanently program the OTP memory in registers 0x16 through 0x1A, use the following steps: 1. Write registers 0x16 through 0x1A with the desired configuration and calibration values which provide satisfactory performance. 2. Ensure that the supply voltage (VDD) is between 4 V and 4.4 V. This voltage is required for the nonvolatile memory to program properly. 3. Set the OTP_PROGRAM bit by writing a value of 0x01 to register 0x1E. When the OTP memory is written which can only occur once in the device, the OTP_STATUS bit (in register 0x1E) only reads 1. 4. Reset the device by power cycling the device or setting the DEV_RESET bit in register 0x01, and then read registers 0x16 to 0x1A to ensure that the programmed values were retained.

OD_CLAMP[7:0] 0 V Open Loop ERM_OPEN_LOOP = 1 OR LRA_OPEN_LOOP = 1 PWM Input Interface 0% 50% 100% RTP (8-bit) DATA_FORMAT_RTP = 10x00 0x7F 0xFF 0x81 0x00 0x7F -OD_CLAMP[7:0] RTP (8-bit) DATA_FORMAT_RTP = 0 DRV2605L SLOS854D –MAY 2014–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV2605L Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Programming (continued)

8.5.8 Waveform Playback Programming

8.5.8.1 Data Formats for Waveform Playback

The DRV2605L smart-loop architecture has three modes of operation. Each of the modes can drive either ERM or LRA devices. 1. Open-loop mode 2. Closed-loop mode (unidirectional) 3. Closed-loop mode (bidirectional) Each mode has different advantages and disadvantages. The DRV2605L device brings new cutting-edge actuator control with closed-loop operation around the back-EMF for automatic overdrive and braking. However, some existing haptic implementations already include overdrive and braking that are embedded in the waveform data. Open-loop mode is used to preserve compatibility with such systems. The following sections show how the input data for each DRV2605L interface is translated to the output drive signal.

8.5.8.1.1 Open-Loop Mode

In open-loop mode, the reference level for full-scale drive is set by the OD_CLAMP[7:0] bit in Register 0x17. A mid-scale input value gives no drive signal, and a less-than mid-scale gives a negative drive value. For an ERM, a negative drive value results in counter-rotation, or braking. For an LRA, a negative drive value results in a 180- degree phase shift in commutation. The RTP mode has 8 bits of resolution over the I2C bus. The RTP data can either be in a signed (2s complement) or unsigned format as defined by the DATA_FORMAT_RTP bit. Figure 26.

RATED_VOLTAGE[7:0] ½ RATED_VOLTAGE[7:0] Full Braking PWM Input Interface 0% 50% 100% 0x00 Closed Loop, BIDIR_INPUT = 0 0x7F 0xFFRTP (8-bit) DATA_FORMAT_RTP = 1 DRV2605L www.ti.com SLOS854D –MAY 2014–REVISED MARCH 2018 Product Folder Links: DRV2605L Submit Documentation FeedbackCopyright © 2014–2018, Texas Instruments Incorporated Programming (continued)

8.5.8.1.2 Closed-Loop Mode, Unidirectional

In closed-loop unidirectional mode, the DRV2605L device provides automatic overdrive and braking for both ERM and LRA actuators. Closed-loop unidirectional mode is the easiest mode to use and understand. Closed- loop unidirectional mode uses the full 8-bit resolution of the driver. Closed-loop unidirectional mode offers the best performance; however, the data format is not physically compatible with the open-loop mode data that can be used in some existing systems The reference level for steady-state full-scale drive is set by the RATED_VOLTAGE[7:0] bit (when auto- calibration is performed). The output voltage can momentarily exceed the rated voltage for automatic overdrive and braking, but does not exceed the OD_CLAMP[7:0] voltage. Braking occurs automatically based on the input signal when the back-EMF feedback determines that braking is necessary. Because the system is unidirectional in closed-loop unidirectional mode, only unsigned data should be used. The RTP mode has 8 bits of resolution over the I2C bus. Setting the DATA_FORMAT_RTP bit to 0 (signed) is not recommended for closed-loop unidirectional mode. Figure 27. NOTE The TS2200 library data is stored in bidirectional format and cannot be used in unidirectional mode. For the RTP interface, set the DATA_FORMAT_RTP bit to 1 (unsigned).

RATED_VOLTAGE[7:0] ½ RATED_VOLTAGE[7:0] PWM Input Interface 0% 50% 100% 0x00 Closed Loop, BIDIR_INPUT = 1 0x7F 0xFF Full Braking 0x81 0x00 0x7F 0x3F 0xBF 75% RTP (8-bit) DATA_FORMAT_RTP = 1 RTP (8-bit) DATA_FORMAT_RTP = 0 DRV2605L SLOS854D –MAY 2014–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV2605L Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Programming (continued)

8.5.8.1.3 Closed-Loop Mode, Bidirectional

In closed-loop bidirectional mode, the DRV2605L device provides automatic overdrive and braking for both ERM and LRA devices. Closed-loop bidirectional mode preserves compatibility with data created in open-loop signaling by maintaining zero drive-strength at the mid-scale value. When input values less than the mid-scale value are given, the DRV2605L device interprets them as the same as the mid-scale with zero drive. The reference level for steady-state full-scale drive is set by the RATED_VOLTAGE[7:0] bit (when auto calibration is performed). The output voltage can momentarily exceed the rated voltage for automatic overdrive and braking, but does not exceed the OD_CLAMP[7:0] voltage. Braking occurs automatically based on the input signal when the back-EMF feedback determines that braking is necessary. Although the Closed-Loop mode preserves compatibility with existing device data formats, it provides closed loop benefits and is the default configuration at power up. The RTP mode has 8 bits of resolution over the I2C bus. The RTP data can either be in signed (2s complement) or unsigned format as defined by the DATA_FORMAT_RTP bit. Figure 28. NOTE Closed-loop bidirectional mode is compatible with all DRV2605L interfaces except for TS2200 Library A (with fixed overdrive programming). Library A should only be used in open-loop mode. Libraries B through F (no overdrive) can take advantage of the automatic overdrive and braking of closed-loop bidirectional mode.

8.5.8.2 Waveform Setup and Playback

(register 0x0C), or by an external trigger.

8.5.8.2.1 Waveform Playback Using RTP Mode

8.5.8.2.2 Waveform Playback Using the Analog-Input Mode

to the selected mode of operation. See the Data Formats for Waveform Playback section for details.

8.5.8.2.3 Waveform Playback Using PWM Mode

8.5.8.2.4 Waveform Playback Using Audio-to-Vibe Mode

Figure 59. The full-scale range of the IN/TRIG pin in the audio-to-vibe mode is 1.8 VPP. A 1-µF capacitor is ATH_MAX_INPUT bit in register 0x13 can scale down the input range.

8.5.8.2.5 Waveform Sequencer

can be launched by using any of the trigger options (see the Waveform Triggers section for details). for that step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

Figure 29. Waveform Sequencer Programming

8.5.8.2.6 Waveform Triggers

set the MODE[2:0] bit to 2 and then follow the trigger instructions listed in the Level Trigger section.

8.6 Register Map

Table 3. Register Map Overview

8.6.1 Status (Address: 0x00)

Figure 30. Status Register Table 4. Status Register Field Descriptions 7-5 DEVICE_ID[2:0] RO 7 Device identifier. The DEVICE_ID bit indicates the part number to the user.

4 Reserved

3 DIAG_RESULT RO 0 This flag stores the result of the auto-calibration routine and the diagnostic

clears at the end of the routine.

2 Reserved

shuts down. This bit clears upon read. to restart until the impedance is above the threshold.

8.6.2 Mode (Address: 0x01)

Figure 31. Mode Register Table 5. Mode Register Field Descriptions clears after the reset operation is complete.

6 STANDBY R/W 1 Software standby mode

Waveforms are fired by setting the GO bit in register 0x0C. edge occurs before the GO bit has cleared. the GO bit is already in the appropriate state, no change occurs. AC_COUPLE and N_PWM_ANALOG bits should also be set. RTP_INPUT[7:0] bit in register 0x02. DIAG_RESULT bit in register 0x00. more information see the Auto Calibration Procedure section.

8.6.3 Real-Time Playback Input (Address: 0x02)

Figure 32. Real-Time Playback Input Register Table 6. Real-Time Playback Input Register Field Descriptions MODE[2:0] = 0, or alternatively by setting STANDBY = 1.

8.6.4 Library Selection (Address: 0x03)

Figure 33. Library Selection Register Table 7. Library Selection Register Field Descriptions if a transaction is taking place.

3 Reserved

ERM libraries see the Table 1 section.

8.6.5 Waveform Sequencer (Address: 0x04 to 0x0B)

Figure 34. Waveform Sequencer Register Table 8. Waveform Sequencer Register Field Descriptions

7 WAIT R/W 0 When this bit is set, the WAV_FRM_SEQ[6:0] bit is interpreted as a wait

delays between sequentially played waveforms. identifier for sequence playback. register address 0x04 when the user asserts the GO bit (register 0x0C). played (register addresses 0x04 through 0x0B), whichever comes first.

8.6.6 GO (Address: 0x0C)

Figure 35. GO Register Table 9. GO Register Field Descriptions be used to fire the auto-calibration process or the diagnostic process.

8.6.7 Overdrive Time Offset (Address: 0x0D)

Figure 36. Overdrive Time Offset Register Table 10. Overdrive Time Offset Register Field Descriptions the time offset can be positive or negative.

8.6.8 Sustain Time Offset, Positive (Address: 0x0E)

Figure 37. Sustain Time Offset, Positive Register Table 11. Sustain Time Offset, Positive Register Field Descriptions

8.6.9 Sustain Time Offset, Negative (Address: 0x0F)

Figure 38. Sustain Time Offset, Negative Register Table 12. Sustain Time Offset, Negative Register Field Descriptions

8.6.10 Brake Time Offset (Address: 0x10)

Figure 39. Brake Time Offset Register Table 13. Brake Time Offset Register Field Descriptions 7-0 BRT R/W 0 This bit adds a time offset to the braking portion of the library waveforms. allows the user to add or take away brake time from the library waveforms. 2s complement, therefore the time offset can be positive or negative.

8.6.11 Audio-to-Vibe Control (Address: 0x11)

Figure 40. Audio-to-Vibe Control Register Table 14. Audio-to-Vibe Control Register Field Descriptions

8.6.12 Audio-to-Vibe Minimum Input Level (Address: 0x12)

Figure 41. Audio-to-Vibe Minimum Input Level Register Table 15. Audio-to-Vibe Minimum Input Level Register Field Descriptions the audio-to-vibe engine. Levels below this are ignored.

8.6.13 Audio-to-Vibe Maximum Input Level (Address: 0x13)

Figure 42. Audio-to-Vibe Maximum Input Level Register Table 16. Audio-to-Vibe Maximum Input Level Register Field Descriptions

8.6.14 Audio-to-Vibe Minimum Output Drive (Address: 0x14)

Figure 43. Audio-to-Vibe Minimum Output Drive Register Table 17. Audio-to-Vibe Minimum Output Drive Register Field Descriptions

8.6.15 Audio-to-Vibe Maximum Output Drive (Address: 0x15)

Figure 44. Audio-to-Vibe Maximum Output Drive Register Table 18. Audio-to-Vibe Maximum Output Drive Register Field Descriptions

8.6.16 Rated Voltage (Address: 0x16)

Figure 45. Rated Voltage Register Table 19. Rated Voltage Register Field Descriptions

8.6.17 Overdrive Clamp Voltage (Address: 0x17)

Figure 46. Overdrive Clamp Voltage Register Table 20. Overdrive Clamp Voltage Register Field Descriptions

7 OD_CLAMP[7:0] R/W 0x8C During closed-loop operation the actuator feedback allows the output voltage

8.6.18 Auto-Calibration Compensation Result (Address: 0x18)

Figure 47. Auto-Calibration Compensation-Result Register Table 21. Auto-Calibration Compensation-Result Register Field Descriptions

8.6.19 Auto-Calibration Back-EMF Result (Address: 0x19)

Figure 48. Auto-Calibration Back-EMF Result Register Table 22. Auto-Calibration Back-EMF Result Register Field Descriptions the appropriate feedback gain for closed-loop operation.

8.6.20 Feedback Control (Address: 0x1A)

Figure 49. Feedback Control Register Table 23. Feedback Control Register Field Descriptions prior to running auto calibration. 6-4 FB_BRAKE_FACTOR[2:0] R/W 3 This bit selects the feedback gain ratio between braking gain and driving gain. actuators. This value should be set prior to running auto calibration. populates the BEMF_GAIN bit with the most appropriate value for the actuator.

8.6.21 Control1 (Address: 0x1B)

Figure 50. Control1 Register Table 24. Control1 Register Field Descriptions

7 STARTUP_BOOST R/W 1 This bit applies higher loop gain during overdrive to enhance actuator transient

6 Reserved

should not be asserted for PWM mode or external trigger mode. headroom. Higher drive times cause the feedback to react at a slower rate.

8.6.22 Control2 (Address: 0x1C)

Figure 51. Control2 Register Table 25. Control2 Register Field Descriptions 7 BIDIR_INPUT R/W 1 The BIDIR_INPUT bit selects how the engine interprets data. applied when the input signal is less than 50%.

6 BRAKE_STABILIZER R/W 1 When this bit is set, loop gain is reduced when braking is almost complete to

Table 25. Control2 Register Field Descriptions (continued) represents different values.

8.6.23 Control3 (Address: 0x1D)

Figure 52. Control3 Register Table 26. Control3 Register Field Descriptions 7-6 NG_THRESH[1:0] R/W 2 This bit is the noise-gate threshold for PWM and analog inputs. usually desired for because of automatic overdrive and braking properties. operation, therefore open-loop operation can be required for compatibility.

3 DATA_FORMAT_RTP R/W 0 This bit selects the input data interpretation for RTP (Real-Time Playback)

Therefore the PWM input frequency must be equal to 128 times the

resonant frequency of the LRA.

8.6.24 Control4 (Address: 0x1E)

Figure 53. Control4 Register Table 27. Control4 Register Field Descriptions

2 OTP_STATUS R 0 OTP Memory status

1 Reserved

0 OTP_PROGRAM R/W 0 This bit launches the programming process for one-time programmable (OTP)

nonvolatile memory. This process can only be executed one time per device. See the Programming On-Chip OTP Memory section for details.

8.6.25 Control5 (Address: 0x1F)

Figure 54. Control5 Register Table 28. Control5 Register Field Descriptions

5 LRA_AUTO_OPEN_LOOP R/W 0 This bit selects the automatic transition to open-loop drive when a back-EMF

signal is not detected (LRA only). 4 PLAYBACK_INTERVAL R/W 0 This bit selects the memory playback interval. BLANKING_TIME[3:0] bit in the Control2 (Address: 0x1C) section for details. Control2 (Address: 0x1C) section for details. Advanced use only.

8.6.26 LRA Open Loop Period (Address: 0x20)

Figure 55. LRA Open Loop Period Register Table 29. LRA Open Loop Period Register Field Descriptions

8.6.27 V(BAT) Voltage Monitor (Address: 0x21)

Figure 56. V(BAT) Voltage-Monitor Register

Table 30. V(BAT) Voltage-Monitor Register Field Descriptions device must be actively sending a waveform to take a reading.

8.6.28 LRA Resonance Period (Address: 0x22)

Figure 57. LRA Resonance-Period Register Table 31. LRA Resonance-Period Register Field Descriptions be actively sending a waveform to take a reading.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

which makes the decision on when to execute haptic effects. designer should not use the internal regulator (REG) to power any external load. Figure 58. I2C Control with Optional PWM Input or External Trigger Figure 59. I2C Control With Audio-to-Vibe Input and Optional AC Coupling Table 32. Recommended External Components

9.2 Typical Application

buttons, capacitive-touch buttons, or GPIO signals coming from the touch-screen system. Effects in this type of system are programmable. Figure 60. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the values listed in Table 33 as the input parameters. Table 33. Design Parameters

9.2.2 Detailed Design Procedure

9.2.2.1 Actuator Selection

basics of ERM and LRA actuators.

9.2.2.1.1 Eccentric Rotating-Mass Motors (ERM)

undesirable in haptic feedback systems.

Figure 61. Motor Spin Direction in ERM Motors overdrive voltage and duration.

9.2.2.1.2 Linear Resonance Actuators (LRA)

tracking auto-resonant algorithm critical when driving LRA to achieve consistent, optimized performance. Figure 62. Typical LRA Response

9.2.2.2 Capacitor Selection

X7R type near the VDD supply pin for proper operation of the output driver and the digital portion of the device. Place a 1-µF X5R or X7R-type capacitor from the REG pin to ground.

9.2.2.3 Interface Selection

available for backward compatibility. If audio-to-vibe is desired, then use C(IN) as shown in Figure 59.

9.2.2.4 Power Supply Selection

enough to support the desired vibration strength with the selected actuator is an important design consideration. particularly true if two AA batteries in series are being used to power the system.

9.2.3 Application Curves

Figure 63. ERM Click with and without Braking Figure 64. LRA Click With and Without Braking

9.3 Initialization Setup

9.3.1 Initialization Procedure

After powerup, wait at least 250 µs before the DRV2605L device accepts I2C commands. 2. Assert the EN pin (logic high). The EN pin can be asserted any time during or after the 250-µs wait period. 3. Write the MODE register (address 0x01) to value 0x00 to remove the device from standby mode. 4. If the nonvolatile auto-calibration memory has been programmed as described in the Auto Calibration Procedure section, skip Step 5 and proceed to Step 6. 5. Perform the steps as described in the Auto Calibration Procedure section. Alternatively, rewrite the results from a previous calibration. 6. If using the embedded ROM library, write the library selection register (address 0x03) to select a library. 7. The default setup is closed-loop bidirectional mode. To use other modes and features, write Control1 (0x1B), Control2 (0x1C), and Control3 (0x1D) as required. Open-loop operation is recommended for ERM mode when using the ROM libraries. 8. Put the device in standby mode or deassert the EN pin, whichever is the most convenient. Both settings are low-power modes. The user can select the desired MODE (address 0x01) at the same time the STANDBY bit is set.

9.3.2 Typical Usage Examples

9.3.2.1 Play a Waveform or Waveform Sequence from the ROM Waveform Memory

Initialize the device as listed in the Initialization Procedure section. 2. Assert the EN pin (active high) if it was previously deasserted. 3. If register 0x01 already holds the desired value and the STANDBY bit is low, the user can skip this step. Select the desired MODE[2:0] value of 0 (internal trigger), 1 (external edge trigger), or 2 (external level trigger) in the MODE register (address 0x01). If the STANDBY bit was previously asserted, this bit should be deasserted (logic low) at this time. 4. Select the waveform index to be played and write it to address 0x04. Alternatively, a sequence of waveform indices can be written to register 0x04 through 0x0B. See the Waveform Sequencer section for details. 5. If using the internal trigger mode, set the GO bit (in register 0x0C) to fire the effect or sequence of effects. If using an external trigger mode, send an appropriate trigger pulse to the IN/TRIG pin. See the Waveform Triggers section for details. 6. If desired, the user can repeat Step 5 to fire the effect or sequence again. 7. Put the device in low-power mode by deasserting the EN pin or setting the STANDBY bit.

9.3.2.2 Play a Real-Time Playback (RTP) Waveform

Initialize the device as shown in the Initialization Procedure section. 2. Assert the EN pin (active high) if it was previously deasserted. 3. Set the MODE[2:0] value to 5 (RTP Mode) at address 0x01. If the STANDBY bit was previously asserted, this bit should be deasserted (logic low) at this time. If register 0x01 already holds the desired value and the STANDBY bit is low, the user can skip this step. 4. Write the desired drive amplitude to the real-time playback input register (address 0x02). 5. When the desired sequence of drive amplitudes is complete, put the device in low-power mode by deasserting the EN pin or setting the STANDBY bit.

9.3.2.3 Play a PWM or Analog Input Waveform

Initialize the device as shown in the Initialization Procedure section. 2. Assert the EN pin (active high) if it was previously deasserted. 3. If register 0x01 already holds the desired value and the STANDBY bit is low, the user can skip this step. Set the MODE value to 3 (PWM/Analog Mode) at address 0x01. If the STANDBY bit was previously asserted, this bit should be deasserted (logic low) at this time. 4. Select the input mode (PWM or analog) in the Control3 register (address 0x1D). If this mode was selected during the initialization procedure, the user can skip this step. 5. Send the desired PWM or analog input waveform sequence from the external source. See the Data Formats for Waveform Playback section for drive amplitude scaling. 6. When the desired drive sequence is complete, put the device in low-power mode by deasserting the EN pin or setting the STANDBY bit.

10 Power Supply Recommendations

The DRV2605L device is designed to operate from an input-voltage supply range between 2 V to 5.2 V. The decoupling capacitor for the power supply should be placed closed to the device pin.

11 Layout

11.1 Layout Guidelines

The decoupling capacitor for the power supply (VDD) should be placed closed to the device pin.
The filtering capacitor for the regulator (REG) should be placed close to the device REG pin.
When creating the pad size for the WCSP pins, TI recommends that the PCB layout use nonsolder mask- defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area and the opening size is defined by the copper pad width. Figure 65 shows and Table 34 lists appropriate diameters for a wafer-chip scale package (WCSP) layout.

Figure 65. Land Pattern Dimensions Table 34. Land Pattern Dimensions

Circuit traces from NSMD defined PWB lands should be 75-µm to 100-µm wide in the exposed area inside

the solder mask opening. Wider trace widths reduce device stand-off and impact reliability.

The recommended solder paste is Type 3 or Type 4.
The best reliability results are achieved when the PWB laminate glass transition temperature is above the

operating the range of the intended application.

For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5 µm to avoid a reduction

in thermal fatigue performance.

Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
The best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of

chemically-etched stencils results in inferior solder paste volume control.

Trace routing away from the WCSP device should be balanced in X and Y directions to avoid unintentional

component movement because of solder-wetting forces.

11.1.1 Trace Width

around the device to provide even solder reflow on each of the pins.

11.2 Layout Example

Figure 66. DRV2605L Layout Example DSBGA Figure 67. DRV2605L Layout Example VSSOP

12 Device and Documentation Support

12.1 Device Support

12.1.1 Legal Notice

In order to assist purchasers and users of TI’s DRV2605L product, TI has paid a royalty on your behalf to Immersion Corporation to secure your rights to use certain Immersion Corporation software embedded (or designed specifically to be embedded) in TI’s DRV2605L product solely as incorporated in TI’s DRV2605L product, subject to the terms, conditions and restrictions of TI’s license with Immersion Corporation. Subject to the terms, conditions and restrictions of TI’s license with Immersion Corporation, you shall not (1) use or distribute any Immersion Corporation software incorporated in TI’s DRV2605L product except as incorporated in TI’s DRV2605L product in accordance with TI’s applicable published specifications and data sheets for the DRV2605L product, (2) modify any Immersion software, (3) change or delete any Immersion proprietary notices, (4) reverse engineer or disassemble any Immersion software or otherwise attempt to discover the internal workings or design of any Immersion software, or (5) distribute Immersion software as a stand-alone basis.

12.1.2 Waveform Library Effects List

NO. WAVEFORM NAME EFFECT ID NO> WAVEFORM NAME EFFECT ID NO. WAVEFORM NAME 1 Strong Click - 100% 42 Long Double Sharp Click Medium 2 – 80% 83 Transition Ramp Up Long Smooth 2 – 0 to 100% 2 Strong Click - 60% 43 Long Double Sharp Click Medium 3 – 60% 84 Transition Ramp Up Medium Smooth 1 – 0 to 100% 3 Strong Click - 30% 44 Long Double Sharp Tick 1 – 100% 85 Transition Ramp Up Medium Smooth 2 – 0 to 100%

4 Sharp Click - 100% 45 Long Double Sharp Tick 2 – 80% 86 Transition Ramp Up Short Smooth 1 – 0 to 100%

5 Sharp Click - 60% 46 Long Double Sharp Tick 3 – 60% 87 Transition Ramp Up Short Smooth 2 – 0 to 100%

6 Sharp Click - 30% 47 Buzz 1 – 100% 88 Transition Ramp Up Long Sharp 1 – 0 to 100%

7 Soft Bump - 100% 48 Buzz 2 – 80% 89 Transition Ramp Up Long Sharp 2 – 0 to 100%

8 Soft Bump - 60% 49 Buzz 3 – 60% 90 Transition Ramp Up Medium Sharp 1 – 0 to 100%

9 Soft Bump - 30% 50 Buzz 4 – 40% 91 Transition Ramp Up Medium Sharp 2 – 0 to 100%

10 Double Click - 100% 51 Buzz 5 – 20% 92 Transition Ramp Up Short Sharp 1 – 0 to 100%

11 Double Click - 60% 52 Pulsing Strong 1 – 100% 93 Transition Ramp Up Short Sharp 2 – 0 to 100%

12 Triple Click - 100% 53 Pulsing Strong 2 – 60% 94 Transition Ramp Down Long Smooth 1 – 50 to 0%

13 Soft Fuzz - 60% 54 Pulsing Medium 1 – 100% 95 Transition Ramp Down Long Smooth 2 – 50 to 0%

14 Strong Buzz - 100% 55 Pulsing Medium 2 – 60% 96 Transition Ramp Down Medium Smooth 1 – 50 to

15 750 ms Alert 100% 56 Pulsing Sharp 1 – 100% 97 Transition Ramp Down Medium Smooth 2 – 50 to 16 1000 ms Alert 100% 57 Pulsing Sharp 2 – 60% 98 Transition Ramp Down Short Smooth 1 – 50 to 0%

17 Strong Click 1 - 100% 58 Transition Click 1 – 100% 99 Transition Ramp Down Short Smooth 2 – 50 to 0%

18 Strong Click 2 - 80% 59 Transition Click 2 – 80% 100 Transition Ramp Down Long Sharp 1 – 50 to 0%

19 Strong Click 3 - 60% 60 Transition Click 3 – 60% 101 Transition Ramp Down Long Sharp 2 – 50 to 0%

20 Strong Click 4 - 30% 61 Transition Click 4 – 40% 102 Transition Ramp Down Medium Sharp 1 – 50 to 0%

21 Medium Click 1 - 100% 62 Transition Click 5 – 20% 103 Transition Ramp Down Medium Sharp 2 – 50 to 0%

22 Medium Click 2 - 80% 63 Transition Click 6 – 10% 104 Transition Ramp Down Short Sharp 1 – 50 to 0%

23 Medium Click 3 - 60% 64 Transition Hum 1 – 100% 105 Transition Ramp Down Short Sharp 2 – 50 to 0%

24 Sharp Tick 1 - 100% 65 Transition Hum 2 – 80% 106 Transition Ramp Up Long Smooth 1 – 0 to 50%

25 Sharp Tick 2 - 80% 66 Transition Hum 3 – 60% 107 Transition Ramp Up Long Smooth 2 – 0 to 50%

26 Sharp Tick 3 – 60% 67 Transition Hum 4 – 40% 108 Transition Ramp Up Medium Smooth 1 – 0 to 50%

27 Short Double Click Strong 1 – 100% 68 Transition Hum 5 – 20% 109 Transition Ramp Up Medium Smooth 2 – 0 to 50% 28 Short Double Click Strong 2 – 80% 69 Transition Hum 6 – 10% 110 Transition Ramp Up Short Smooth 1 – 0 to 50%

29 Short Double Click Strong 3 – 60% 70 Transition Ramp Down Long Smooth 1 –

100 to 0% 111 Transition Ramp Up Short Smooth 2 – 0 to 50%

30 Short Double Click Strong 4 – 30% 71 Transition Ramp Down Long Smooth 2 –

100 to 0% 112 Transition Ramp Up Long Sharp 1 – 0 to 50%

31 Short Double Click Medium 1 – 100% 72 Transition Ramp Down Medium Smooth 1 –

100 to 0% 113 Transition Ramp Up Long Sharp 2 – 0 to 50%

32 Short Double Click Medium 2 – 80% 73 Transition Ramp Down Medium Smooth 2 –

100 to 0% 114 Transition Ramp Up Medium Sharp 1 – 0 to 50%

33 Short Double Click Medium 3 – 60% 74 Transition Ramp Down Short Smooth 1 –

100 to 0% 115 Transition Ramp Up Medium Sharp 2 – 0 to 50%

SLOS854D –MAY 2014–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV2605L Submit Documentation Feedback Copyright © 2014–2018, Texas Instruments Incorporated Device Support (continued) EFFECT ID NO. WAVEFORM NAME EFFECT ID NO> WAVEFORM NAME EFFECT ID NO. WAVEFORM NAME

34 Short Double Sharp Tick 1 – 100% 75 Transition Ramp Down Short Smooth 2 –

100 to 0% 116 Transition Ramp Up Short Sharp 1 – 0 to 50%

35 Short Double Sharp Tick 2 – 80% 76 Transition Ramp Down Long Sharp 1 – 100

to 0% 117 Transition Ramp Up Short Sharp 2 – 0 to 50%

36 Short Double Sharp Tick 3 – 60% 77 Transition Ramp Down Long Sharp 2 – 100

to 0% 118 Long buzz for programmatic stopping – 100%

37 Long Double Sharp Click Strong 1 –

100% 78 Transition Ramp Down Medium Sharp 1 – 100 to 0% 119 Smooth Hum 1 (No kick or brake pulse) – 50%

38 Long Double Sharp Click Strong 2 –

80% 79 Transition Ramp Down Medium Sharp 2 – 100 to 0% 120 Smooth Hum 2 (No kick or brake pulse) – 40%

39 Long Double Sharp Click Strong 3 –

60% 80 Transition Ramp Down Short Sharp 1 – 100 to 0% 121 Smooth Hum 3 (No kick or brake pulse) – 30%

40 Long Double Sharp Click Strong 4 –

30% 81 Transition Ramp Down Short Sharp 2 – 100 to 0% 122 Smooth Hum 4 (No kick or brake pulse) – 20%

41 Long Double Sharp Click Medium 1 –

100% 82 Transition Ramp Up Long Smooth 1 – 0 to 100% 123 Smooth Hum 5 (No kick or brake pulse) – 10%

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

Haptic Energy Consumption, SLOA194
Haptic Implementation Considerations for Mobile and Wearable Devices, SLOA207
LRA Actuators: How to Move Them?, SLOA209

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.4 Community Resource

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. TouchSense is a registered trademark of Immersion Corporation. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV2605LDGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAUAG | SN Level-2-260C-1 YEAR -40 to 85 05L DRV2605LDGSR.A Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 85 05L DRV2605LDGST Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAUAG | SN Level-2-260C-1 YEAR -40 to 85 05L DRV2605LDGST.A Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 85 05L DRV2605LYZFR Active Production DSBGA (YZF) | 9 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 2605L DRV2605LYZFR.A Active Production DSBGA (YZF) | 9 3000 | LARGE T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 2605L DRV2605LYZFT Active Production DSBGA (YZF) | 9 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 2605L DRV2605LYZFT.A Active Production DSBGA (YZF) | 9 250 | SMALL T&R Yes SNAGCU Level-1-260C-UNLIM -40 to 85 2605L (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 10-Nov-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DRV2605L :

Automotive : DRV2605L-Q1 NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV2605LDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 DRV2605LDGST VSSOP DGS 10 250 366.0 364.0 50.0 DRV2605LYZFR DSBGA YZF 9 3000 182.0 182.0 20.0 DRV2605LYZFT DSBGA YZF 9 250 182.0 182.0 20.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA.

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4)

0.05 MAX

0.05 MIN

10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com PACKAGE OUTLINE C0.625 MAX 0.35 0.15 TYP

1 TYP

0.5 TYP

9X 0.35 0.25 B E A D 4219558/A 10/2018 DSBGA - 0.625 mm max heightYZF0009 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A 1 2 3

0.015 C A B

B C SCALE 8.000 D: Max = E: Max = 1.47 mm, Min = 1.47 mm, Min = 1.41 mm 1.41 mm

www.ti.com EXAMPLE BOARD LAYOUT 0.05 MIN0.05 MAX 9X ( 0.245) (0.5) TYP (0.5) TYP ( 0.245) SOLDER MASK OPENING ( 0.245) METAL 4219558/A 10/2018 DSBGA - 0.625 mm max heightYZF0009 DIE SIZE BALL GRID ARRAY NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). SOLDER MASK DETAILS NOT TO SCALE SYMM SYMM C 1 2 3 A B LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 40X NON-SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL SOLDER MASK OPENING SOLDER MASK DEFINED METAL UNDER SOLDER MASK EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP 4219558/A 10/2018 DSBGA - 0.625 mm max heightYZF0009 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM 1 2 3 C A B SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 40X METAL TYP

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2025, Texas Instruments Incorporated Last updated 10/2025

Selected Specification

Texas Instruments DRV2605L overview.

Summary

DRV2605L 2 to 5.2 V Haptic Driver for LRA and ERM With Effect Library and Smart-Loop Architecture

Description

DRV2605L 2 to 5.2 V Haptic Driver for LRA and ERM With Effect Library and Smart-Loop Architecture

Source title DRV2605L Datasheet(PDF) - Texas Instruments

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