DRV110APWR

DRV110 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 30

Technical content

Copyright © 2018, Texas Instruments Incorporated D1 LS Product Folder Order Now T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV110 SLVSBA8G –MARCH 2012–REVISED MARCH 2018 DRV110120-and230-VAC,6-to48-VDCCurrentControllerfor Solenoids,Relays,andValves

1 Features

1• Internal Zener Diode on Supply Pin for High- Voltage Operation – 120- and 230-V AC Supply Through Rectifier and RS Resistor – 24-V, 48-V, and Higher DC Supply Through RS Resistor

• Drives an External MOSFET With PWM to Control Solenoid Current – External Sense Resistor for Regulating Solenoid Current
• Fast Ramp-Up of Solenoid Current to Ensure Activation
• Solenoid Current is Reduced in Hold Mode for Lower Power and Thermal Dissipation
• Ramp Peak Current, Keep Time at Peak Current, Hold Current, and PWM Clock Frequency Can Be Set Externally. They Can Also Be Operated at Nominal Values Without External Components.
• Protection – Thermal Shutdown – Undervoltage Lockout (UVLO)
• Optional STATUS Output
• Operating Temperature Range: –40ºC to +125ºC
• 8-Pin and 14-Pin TSSOP Package Options

2 Applications

• Electromechanical Drivers: Solenoids, Valves, Relays, Contactors, Switchgear, Pneumatics
• White Goods, Solar, Transportation, Smart Grid, Power Distribution

3 Description

The DRV110 device is a PWM current controller for solenoids. The device is designed to regulate the current with a well-controlled waveform to reduce power dissipation. The solenoid current is ramped up fast to ensure opening of the valve or relay. After initial ramping, the solenoid current is kept at a peak value to ensure correct operation, after which the current is reduced to a lower hold level to avoid thermal problems and reduce power dissipation. The peak current duration is set with an external capacitor. The peak and hold levels of the current ramp, as well as the PWM frequency, can independently be set with external resistors. External setting resistors can also be omitted if the default values for the corresponding parameters are suitable for the application. The DRV110 device has an internal Zener diode that limits the supply at VIN to VZENER for applications that require a higher supply voltage. Using the internal Zener, the DRV110 can be powered from 120-V and 230-V AC supplies through a rectifier and current- limiting resistor. High DC voltages such as 48-V can also be accommodated this way. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV110 TSSOP (14) 5.00 mm × 4.40 mm TSSOP (8) 3.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DRV110 Supplied by Power Line Voltage

SLVSBA8G –MARCH 2012–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV110 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation Updates 19

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2017) to Revision G Page

• Deleted virtual from the operating junction temperature and changed its maximum value from 125°C to 150°C in the
• Added the temperature range for the parameters in the Recommended Operating Conditions table, add the VS
• Changed the RPEAK value for IPEAK = 450 mA from 50 kΩ to 55 kΩ in the Configuring Peak and Hold Currents section.... 10
• Changed the Configuring Peak and Hold Currents section and PEAK and HOLD Mode VREF Settings image (which
• Changed the Voltage Supply and Integrated Zener Diode section. Added the VZENER Value table and changed the Changes from Revision E (November 2016) to Revision F Page

www.ti.com SLVSBA8G –MARCH 2012–REVISED MARCH 2018 Product Folder Links: DRV110 Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated Changes from Revision D (June 2016) to Revision E Page Changes from Revision C (April 2016) to Revision D Page Changes from Revision B (July 2015) to Revision C Page

• Changed one test condition (ROSC = 50 kΩ to 160 kΩ) and the maximum value for the Externally set PWM clock Changes from Revision A (January 2013) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

SLVSBA8G –MARCH 2012–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV110 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

(1) In the 8-pin package, the HOLD pin is not bonded out. For this package, the HOLD mode is configured to default (internal) settings. Pin Functions PIN I/O DESCRIPTION NAME NO.

8 PINS 14 PINS

GND 5 8 — Ground HOLD — 4 I Hold current set(1) KEEP 1 2 I Keep time set NC — 1 — No connect NC — 6 — No connect NC — 10 — No connect NC — 14 — No connect OSC 3 5 I PWM frequency set OUT 7 11 O Solenoid switch gate drive PEAK 2 3 I Peak current set SENSE 6 9 I Solenoid current sense STATUS — 12 O Open drain status indicator VIN 4 7 I 6-V to 15-V supply

www.ti.com SLVSBA8G –MARCH 2012–REVISED MARCH 2018 Product Folder Links: DRV110 Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratings

See (1) and (2) MIN MAX UNIT VIN Input voltage –0.3 20 V Voltage on EN, STATUS, PEAK, HOLD, OSC, SENSE, KEEP –0.3 7 V Voltage on OUT –0.3 20 V TJ Operating junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22- C101(2) ±500 (1) The device regulates the supply with an internal Zener diode. The device sinks up to 3 mA with the added supply current. See Equation 5 to find appropriate value for the RS resistor. (2) The maximum input voltage of the device depends on the clamping voltage of the internal Zener diode, which changes over temperature. A current-limiting resistor is required to limit current to the Zener diode if the input voltage (VIN) is greater than VZENER. For more information on resistor sizing see the Detailed Description section and Application and Implementation section. (3) For VS voltages less than VZENER, VIN = VS. For VS voltages greater than VZENER, VIN = VZENER. (4) 4.7-µF input capacitor and full wave rectified 230-Vrms AC supply results in approximately 500-mV supply ripple.

6.3 Recommended Operating Conditions

–40°C ≤ TA ≤ 125°C (unless otherwise noted) MIN NOM MAX UNIT IQ Supply current (the device sinks additional current when VIN > VZENER (1)) 1 1.5 3 mA VIN Voltage at the VIN pin(2)(3) (see Detailed Description) 6 V VS Voltage directly from the supply before clamped by the Zener diode 6 330 V CIN Input capacitor between VIN and GND(4) 1 4.7 µF TA Operating ambient temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) DRV110 UNITPW (TSSOP) RθJA Junction-to-ambient thermal resistance 183.8 122.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 69.2 51.2 °C/W RθJB Junction-to-board thermal resistance 112.6 64.3 °C/W ψJT Junction-to-top characterization parameter 10.4 6.5 °C/W ψJB Junction-to-board characterization parameter 110.9 63.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

SLVSBA8G –MARCH 2012–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV110 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated

6.5 Electrical Characteristics

VIN = 14 V, –40°C ≤ TA ≤ 125°C, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY IQ Standby current EN = 0, VIN = 14 V, bypass deactivated 200 250 µA Quiescent current EN = 1, VIN = 14 V, bypass deactivated 360 570 Internally regulated supply EN = 0, IVIN = 2 mA, bypass activated 10.5 15 19 V EN = 1, IVIN = 2 mA, bypass activated 14.5 15 15.5 GATE DRIVER VDRV Gate drive voltage Supply voltage in regulation VIN V IDRV_SINK Gate drive sink current VOUT = 15 V; VIN = 15 V 8 15 mA IDRV_SOURCE Gate drive source current VOUT = GND; VIN = 15 V –15 –10 mA fPWM PWM clock frequency OSC = GND 15 20 27 kHz DMAX Maximum PWM duty cycle 100% DMIN Minimum PWM duty cycle 7.5% tD Start-up delay Delay between EN going high until gate driver starts switching, fPWM = 20 kHz 50 µs CURRENT CONTROLLER, INTERNAL SETTINGS IPEAK Peak current RSENSE = 1 Ω, PEAK = GND 270 300 330 mA IHOLD Hold current RSENSE = 1 Ω, HOLD = GND 40 50 65 mA CURRENT CONTROLLER, EXTERNAL SETTINGS tKEEP Externally set keep time at peak current CKEEP = 1 µF 100 ms VPEAK Voltage of internal reference to which the SENSE pin voltage is compared to for IPEAK RPEAK = 50 kΩ 900 mV RPEAK = 200 kΩ 300 VHOLD Voltage of internal reference to which the SENSE pin voltage is compared for IHOLD RHOLD = 50 kΩ 150 mV RHOLD = 200 kΩ 50 fPWM Externally set PWM clock frequency ROSC = 160 kΩ 25 kHz ROSC = 200 kΩ 20 LOGIC INPUT LEVELS (EN) VIL Input low level 1.3 V VIH Input high level 1.65 V REN Input pullup resistance 350 500 kΩ Input pulldown resistance 250 kΩ LOGIC OUTPUT LEVELS (STATUS) VOL Output low level Pulldown activated, ISTATUS = 2 mA 0.3 V IIL Output leakage current Pulldown deactivated, V(STATUS) = 5 V 2 µA UNDERVOLTAGE LOCKOUT VUVLO Undervoltage lockout threshold 4.6 V THERMAL SHUTDOWN TTSU Junction temperature start-up threshold 140 °C TTSD Junction temperature shutdown threshold 160 °C

6.6 Typical Characteristics

Figure 1. Solenoid Current, EN, and PWM vs Time

HOLD (1) GND SENSE OUT STATUS (1) R OSC R S VS C KEEP R PEAK R HOLD (1) R SENSE VS LS D1 1 k 250 k 500 k LDO UVLO Thermal Shutdown OSC PWM Control SW REF 1 µA 100 mV MUX VIN Copyright © 2017, Texas Instruments Incorporated DRV110 SLVSBA8G –MARCH 2012–REVISED MARCH 2018 www.ti.com Product Folder Links: DRV110 Submit Documentation Feedback Copyright © 2012–2018, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The DRV110 device provides a PWM current controller for use with solenoids. The device provides a quick ramp to a high peak current value in order to ensure opening of the valve or relay. The current is held for a programmable time and then lowered to the hold current value to maintain the open state of the valve or relay while reducing the total current consumption. Peak current duration, peak current amount, hold current amount (in the 14-pin package), and PWM frequency can all be controlled by external components or used at default levels by omitting these components (except peak current duration). Enable and disable of the switch is controlled by the EN pin. The EN pin contains an internal resistor network to set the pin to logic HIGH when the EN pin is floating. This feature can be used for situations where a control signal is not required and the solenoid is only energized when a supply voltage is present. Such applications could be valves or contactors. The DRV110 also features a wide VIN range with an internal bypass regulator to maintain VIN at an acceptable level. Finally, the 14-pin package features an open-drain pull-down path on the STATUS pin which is enabled as long as undervoltage lockout or thermal shutdown has not triggered.

7.2 Functional Block Diagram

(1) Available only in the 14-pin package.

7.3 Feature Description

before reducing it to IHOLD. The solenoid current is regulated at the hold value as long as the EN pin is kept high. to GND, DRV110 allows the solenoid current to decay to zero. Figure 2. Typical Current Waveform Through the Solenoid

7.3.1 Keep Time

from the external capacitor size can be calculated with Equation 1.

7.3.2 PWM Current Control

determined by the minimum PWM signal duty cycle, DMIN. the PWM frequency and duty cycle appear uneven for some solenoids (see Figure 3).

reference voltage (VREF) each clock cycle. The voltage at the output node (VOUT) becomes low when VSENSE ≥ VREF. Figure 3. DRV110 Current Control with Varying OUT Duty Cycle

7.3.3 Configuring Peak and Hold Currents

value of 300 mA for IPEAK and 50 mA for IHOLD. slipping from the maximum current setting to the default setting. but the current levels are 1/6 of the IPEAK levels for the same resistor setting. HOLD. Use Equation 2 and Equation 3 to calculate the values for IPEAK and IHOLD respectively.

Figure 4. IPEAK and IHOLD settings for RSENSE = 1 Ω

7.3.4 Configuring the PWM Frequency

Figure 5. Default frequency is used when OSC is connected to GND directly. Use Equation 4 to calculate the PWM frequency as a function of the external fixed adjustment resistor value (greater than 160 kΩ). Figure 5. PWM Clock Frequency Setting

7.3.5 Voltage Supply and Integrated Zener Diode

directly from an external voltage source. Supply voltages of at least 6 V are supported.

VIN current within the recommended operating conditions.

• IGate,AVE is the current flowing to the external switch. For a MOSFET, IGate,AVE is equal to the external FET gate charge multiplied by fPWM. (5) (6) Ideally, the DRV110 device clamps the input voltage to 15 V. For configurations that do not use the EN pin (force the pin high or leave it floating), the DRV110 device clamps at 15 V (VZENER = 15 V) across the temperature range of the device. If the EN pin is set to 0, then refer to the values in Table 1 to find the VZENER used when calculating the value of RS, based on the temperature range of the application. Because the VZENER changes when the EN state changes, select a value for RS that meets the current requirements at both VZENER voltages.

Table 1. VZENER Value blocks have triggered or if the EN pin is low.

7.4 Device Functional Modes

7.4.1 Normal Mode

OFF state In the OFF state, the EN pin is low and the PWM output is off. reached. During this state, the PWM operates to reach the IPEAK current set by the RPEAK resistor. IHOLD level. This continues until the EN pin is set low again and the PWM turns off.

7.4.2 Shutdown

provides an explanation of this operation. Table 2. Shutdown Operation

0 X X Hi-Z LOW

1 X 1 Hi-Z LOW

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

peak current, hold current, sense, and keep time will be derived for a sample application.

8.2 Typical Application

Figure 6. DRV110 Powered by a Rectified AC Power Source

16 V to 48 V

Figure 7. DRV110 Powered by a DC Power Source Greater than 15 V

8.2.1 Design Requirements

can be varied in order to tune the circuit to the chosen solenoid or relay.

8.2.2 Detailed Design Procedure

8.2.2.1 Current Limiting Resistor Selection

is greater than 15 V across all temperature.

Table 3. Recommended Resistor Values

24 V 9 kΩ

48 V 33 kΩ

110 V to 120 V 100 kΩ

220 V to 240 V 200 kΩ

10 V 510 Ω

11 V 510 Ω

12 V 1 kΩ

13 V 2 kΩ

14 V 3 kΩ

24 V 13 kΩ

48 V 36 kΩ

8.2.2.2 Passive Component Selection

package), CKEEP, and RSENSE can be determined. Table 4 lists the example values and results from calculation. Table 4. Example Application Values When RSENSE = 1 Ω using a 0-Ω resistor for prototyping in case changes to this value are desired. the filter capacitor is 100 pF. than 30 mV for reliable operation. Table 4 and the supply voltage. The current recirculation diode should be a fast recovery diode.

8.2.3 Application Curve

Figure 8. ISOLENOID, EN, and VIN vs Time

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

10.2 Layout Example

Figure 9. Layout Schematic

www.ti.com SLVSBA8G –MARCH 2012–REVISED MARCH 2018 Product Folder Links: DRV110 Submit Documentation FeedbackCopyright © 2012–2018, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Current Controlled Driver for 24-V DC Solenoid With Plunger Fault Detection reference design
• Texas Instruments, Current Controlled Driver for 230V AC Solenoids Reference Design
• Texas Instruments, DRV110 and DRV120 Evaluation Modules (EVM) user's guide

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 17-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV110APWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 110A DRV110APWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 110A DRV110APWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 110A DRV110APWRG4.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 110A DRV110PWR Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 110 DRV110PWR.B Active Production TSSOP (PW) | 8 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 110 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 17-Jun-2025 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV110APWR TSSOP PW 14 2000 353.0 353.0 32.0 DRV110APWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 DRV110PWR TSSOP PW 8 2000 353.0 353.0 32.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

www.ti.com PACKAGE OUTLINE C TYP6.6 6.2 6X 0.65 8X 0.30 0.19 1.95 0.15 0.05 (0.15) TYP 0 - 8 0.25 GAGE PLANE 0.75 0.50 A NOTE 3 3.1 2.9 B NOTE 4 4.5 4.3 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. 1 8 0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT (5.8) 8X (1.5) 8X (0.45) 6X (0.65) (R ) TYP 0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 4 5 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.8) 6X (0.65) 8X (0.45) 8X (1.5) (R ) TYP0.05 4221848/A 02/2015 TSSOP - 1.2 mm max heightPW0008A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 4 5 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated