DRV1101 TI | Alldatasheet
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HIGH POWER DIFFERENTIAL LINE DRIVER International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
DESCRIPTION
The DRV1101 is fixed gain differential line driver designed for very low distortion operation when driv- ing DSL line transformers. It is designed for use as the upstream line driver for ADSL G.Lite, and as both upstream and downstream line drivers in CAP sys- tems. Operating on a single 5V supply, the DRV1101 can supply up to 230mA peak output current. The output voltage can swing up to 9.5Vp-p on a single 5V supply. In ADSL G.Lite applications, DRV1101 can supply up to 10dBm average line power with a crest factor of 5.3 for a peak line power delivered of approximately 25dBm. It is packaged in a 8-lead SOIC.
FEATURES
l HIGH OUTPUT CURRENT: 230mA l SINGLE SUPPLY OPERATION: 5V l 10MHz BANDWIDTH: 6Vp-p into 15Ω l VERY LOW THD AT HIGH POWER: –81dBc at 6Vp-p, 100kHz, 100Ω l FIXED DIFFERENTIAL GAIN: 3V/V
APPLICATIONS
l DSL TWISTED PAIR LINE DRIVER l COMMUNICATIONS LINE DRIVER l TWISTED-PAIR CABLE DRIVER © 1998 Burr-Brown Corporation PDS-1462A Printed in U.S.A. July, 1998 DRV1101 In+ In– Out+ +5V G = 3V/V DRV1101 Patent Pending GND Out– 4Ω Protection 1:3.3 Transformer 100Ω SBWS009
PARAMETER CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE –3dB Bandwidth R L = 15Ω , VO = 1Vp-p 24 MHz R L = 100Ω , VO = 1Vp-p 42 MHz R L = 15Ω , VO = 6Vp-p 17 MHz R L = 100Ω , VO = 6Vp-p 23 MHz Slew Rate R L = 100Ω , VO = 6Vp-p 100 V/ µs Step Response Delay(2) VO = 1Vp-p 25 ns Settling Time to 1%, Step Input V O = 1Vp-p, RL = 100Ω 0.12 µs Settling Time to 1%, Step Input V O = 6Vp-p, RL = 100Ω 0.13 µs Settling Time to 0.1%, Step Input V O = 1Vp-p, RL = 100Ω 0.30 µs Settling Time to 0.1%, Step Input V O = 6Vp-p, RL = 100Ω 0.32 µs THD, Total Harmonic Distortion f = 10kHz R L = 100Ω , VO = 6Vp-p –88 dB f = 10kHz R L = 15Ω , VO = 6Vp-p –85 dB f = 100kHz R L = 100Ω , VO = 6Vp-p –83 dB f = 100kHz R L = 15Ω , VO = 6Vp-p –66 –71 dB Input Voltage Noise f = 100kHz 30 nV/ √Hz Input Current Noise f = 100kHz 0.5 fA/ √Hz INPUT Differential Input Resistance 109 Ω Differential Input Capacitance 1p F Common-Mode Input Resistance 109 Ω Common-Mode Input Capacitance 6p F Input Offset Voltage 3m V Input Bias Current 1n A Common-Mode Rejection Ratio Input Referred 46 dB Power Supply Rejection Ratio Input Referred 55 76 dB Input Common-Mode Voltage Range OUTPUT Differential Output Offset, RTO ±10 ±30 mV Differential Output Offset Drift, RTO –40 °C to +85°C3 0 µV/°C Differential Output Resistance 0.16 Ω Peak Current (Continuous) R L = 15Ω 200 230 mA Differential Output Voltage Swing(5) R L = 1kΩ 9.8 Vp-p R L = 100Ω 8.5 9.7 Vp-p R L = 15Ω 7.0 Vp-p Gain Fixed Gain, Differential 3.1 V/V Gain Error ±0.25 dB POWER SUPPLY Operating Voltage Range 4.5 5.0 5.5 V Quiescent Current V DD = 5.0V 25 38 mA TEMPERATURE RANGE –40 +85 °C Thermal Resistance, θJA 8-Pin SOIC 125 °C/W NOTES: (1) Measurement Bandwidth = 500kHz. (2) Time from 50% point of input step to 50% point of output step. (3) For step input. (4) Output common-mode voltage follows input common-mode voltage; therefore, if input VCM = VDD /2, then output VCM = VDD /2. (5) THD = 1%. SPECIFICATIONS Typical at 25°C, VCM = VDD /2, VDD = +5.0V, unless otherwise specified. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
±10mA, Continuous ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDERING INFORMATION PACKAGE DRAWING PRODUCT PACKAGE NUMBER (1) DRV1101U SO-8 Surface Mount 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. In+ 2 8In– Out+ +5V GND Out– GND In+ In– GND Out– VDD (+5V) VDD (+5V) Out+
FIGURE 5. AC-Coupled Differential Input Interface.FIGURE 4. Junction Temperature Rise From Ambient for junction for loads of 15Ω and 100Ω . determine four performance requirements.
- They bias the inputs at the supply midpoint.
- They provide a DC bias current path for the input of the DRV1101.
- They set the AC input impedance of the circuit to approxi- mately 1MΩ .
- They set the low cutoff frequency along with C B . The bias resistors maybe set to a lower level if a lower input impedance is desired. R L1M Ω C B C B 1M Ω 100kΩ 100kΩ 0.01µF 0 0.5 1 1.5 INTERNAL TEMPERATURE RISE OF DRV1101 Temperature Rise Load Voltage (rms) 2 2.5 3 3.5 R L = 15Ω Limit at 85°C Ambient R L = 100Ω
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DRV1101U Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR - DRV 1101U DRV1101U.B Active Production SOIC (D) | 8 75 | TUBE Yes NIPDAU Level-2-260C-1 YEAR See DRV1101U DRV 1101U (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DRV1101U D SOIC 8 75 506.6 8 3940 4.32 DRV1101U.B D SOIC 8 75 506.6 8 3940 4.32 Pack Materials-Page 1
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