DRV104

DRV104 BURR-BROWN | Alldatasheet

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SBVS036A – SEPTEMBER 2003 – REVISED NOVEMBER 2003 www.ti.com

DESCRIPTION

The DRV104 is a DMOS, high-side power switch employing a pulse-width modulated (PWM) output. Its rugged design is optimized for driving electromechanical devices such as valves, solenoids, relays, actuators, and positioners. It is also ideal for driving thermal devices such as heaters, coolers, and lamps. PWM operation conserves power and reduces heat rise, resulting in higher reliability. In addition, adjustable PWM allows fine control of the power delivered to the load. Time from dc-to-PWM output and oscillator frequency are externally adjustable. Separate supply pins for the circuit and driver transistor allow the output to operate on a different supply than the rest of the circuit. The DRV104 can be set to provide a strong initial solenoid closure, automatically switching to a soft hold mode for power savings. The duty cycle can be controlled by a resistor, analog voltage, or a digital-to-analog (D/A) converter for versatility. The Status OK Flag pin indicates when thermal shutdown or over-current occurs. The DRV104 is specified for –40°C to +85°C at its case. The exposed lead frame must be soldered to the circuit board.

FEATURES

G HIGH OUTPUT DRIVE: 1.2A G WIDE SUPPLY RANGE: +8V to +32V G COMPLETE FUNCTION: PWM Output Adjustable Internal Oscillator: 500Hz to 100kHz Digitally Controlled Input Adjustable Delay and Duty Cycle Over-Current Indicator Flag G FULLY PROTECTED: Thermal Shutdown with Indicator Flag Internal Current Limit G PACKAGE: HTSSOP-14 Surface-Mount PowerPAD™ PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003, Texas Instruments Incorporated 1.2A PWM High-Side Driver for Solenoids, Coils, Valves, Heaters, and Lamps Delay Adj Input On Off Thermal Shutdown Over/Under Current Status OK Flag +VS Coil OUT2 BOOT OscillatorVREF PWM Osc Freq Adj Duty Cycle Adj GND Delay DRV104 OUT1 +V PS 1 +V PS 2

APPLICATIONS

G ELECTROMECHANICAL DRIVERS: Solenoids, Valves, Positioners, Actuators, Relays, Power Contactor Coils, Heaters, and Lamps G FLUID AND GAS FLOW SYSTEMS G FACTORY AUTOMATION G PART HANDLERS AND SORTERS G PHOTOGRAPHIC PROCESSING G ENVIRONMENTAL MONITORING AND HVAC G THERMOELECTRIC COOLERS G MOTOR SPEED CONTROLS G SOLENOID PROTECTORS G MEDICAL ANALYZERS ®DRV104 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

SBVS036Awww.ti.com NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may de- grade device reliability. (2) See the Bypass section for discussion about operating near the maximum supply. (3) Higher voltage may be applied if current is limited to 2mA. (4) Status OK flag will internally current limit at about 10mA. ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR (1) RANGE MARKING NUMBER MEDIA, QUANTITY DRV104 PowerPAD HTSSOP-14 PWP –40°C to +85°C DRV104 DRV104PWP Rails, 90 " """ " DRV104PWPR Tape and Reel, 2000 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PACKAGE/ORDERING INFORMATION LOGIC BLOCK DIAGRAM Delay Adj Input On Off Thermal Shutdown Over Current Status OK Flag +VS Coil OUT2 C BOOT Oscillator1.25V VREF PWM Osc Freq Adj Duty Cycle Adj GND Delay DRV104 OUT1 +VPS 1 +VPS 2 C D R PWM DMOS DMOS 2.75 • IREF R FREQ IREF 13 10 11 513 SYNC 12 Master 4

SBVS036A www.ti.com

ELECTRICAL CHARACTERISTICS

At TC = +25°C, VS = VPS = +24V, Load = 100Ω , 4.99kΩ Status OK flag pull-up to +5V, Boot capacitor = 470pF, Delay Adj Capacitor (CD ) = 100pF to GND, Osc Freq Adj Resistor = 191kΩ to GND, Duty Cycle Adj Resistor = 147kΩ to GND, and Master and SYNC open, unless otherwise noted. DRV104 PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT Output Saturation Voltage, Source I O = 1A +0.45 +0.65 V Current Limit(1)(7) 1.2 2.0 2.6 A Leakage Current DMOS Output Off, V PS = VS = 32V 1 10 µA DELAY TO PWM (3) DC to PWM Mode Delay Equation(4) Delay to PWM ≈ CD • 106(CD in F • 1.24) s Delay Time C D = 0.1µF 60 80 100 ms Minimum Delay Time(5) C D = 0 18 µs DUTY CYCLE ADJUST Duty Cycle Range 10 to 90 % Duty Cycle Accuracy 50% Duty Cycle, 25kHz ±2 ±5% vs Supply Voltage 50% Duty Cycle, V S = VPS = 8V to 32V ±2% Nonlinearity(6) 10% to 90% Duty Cycle 1 % FSR DYNAMIC RESPONSE Output Voltage Rise Time V O = 10% to 90% of VPS 12 µs Output Voltage Fall Time V O = 90% to 10% of VPS 0.2 2 µs SYNC Output Rise Time V SYNC = 10% to 90% 0.5 2 µs SYNC Output Fall Time V SYNC = 10% to 90% 0.5 2 µs Oscillator Frequency Range External Adjust 0.5 to 100 kHz Oscillator Frequency Accuracy R FREQ = 191kΩ 20 25 30 kHz STATUS OK FLAG Normal Operation 20k Ω Pull-Up to +5V +4.5 +5 V Fault(7) 4.99kΩ Pull-Up to +5V +0.45 +0.6 V Over-Current Flag: Set— Delay 5 µs INPUT (2) VINPUT Low 0 +1.2 V VINPUT High +2.2 +5.5 V IINPUT Low (output disabled) V INPUT = 0V 0.01 1 µA IINPUT High (output enabled) V INPUT = +4.5V 0.01 1 µA Propagation Delay On to Off and Off to On, INPUT to OUT 2.2 µs (master mode) On to Off and Off to On, INPUT to SYNC 0.4 µs MASTER INPUT VMSTR Low 0 +1.2 V VMSTR High +2.2 +5.5 V IMSTR Low (slave mode) V INPUT = 0V 15 25 µA IMSTR High (master mode) V INPUT = +4.5V 15 25 µA SYNC INPUT VSYNC Low 0 +1.2 V VSYNC High +2.2 +5.5 V IMSTR Low (OUT disabled in slave mode) V INPUT = 0V 0.01 1 µA IMSTR High (OUT disabled in slave mode) V INPUT = +4.5V 0.01 1 µA Propagation Delay On to Off and Off to On, SYNC to OUT (slave) 2.2 µs SYNC OUTPUT (9) VOL Sync I SYNC = 100µA (sinking) 0.1 0.3 V VOH Sync I SYNC = 100µA (sourcing) +4.0 +4.2 V THERMAL SHUTDOWN Junction Temperature Shutdown +160 °C Reset from Shutdown +140 °C POWER SUPPLY Specified Operating Voltage +24 V Operating Voltage Range +8 +32 V Quiescent Current (VS)I O = 0 0.6 1 mA TEMPERATURE RANGE Specified Range –40 +85 °C Operating Range –55 +125 °C Storage Range –65 +150 °C Thermal Resistance, θJA(8) HTSSOP-14 with PowerPAD 37.5 °C/W NOTES: (1) Output current resets to zero when current limit is reached. (2) Logic high enables output (normal operation). (3) Constant dc output to PWM (Pulse- Width Modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin low corresponds to an infinite (continuous) delay. (5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 1 to percent of duty cycle at pins 6 and 7. (7) Flag indicates fault from over- master mode. Power output follows SYNC input in slave mode.

SBVS036Awww.ti.com PIN NAME DESCRIPTION 1 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x IREF ) current source from VS. The voltage at this node linearly sets the duty cycle. The duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, the output duty cycle is is in slave mode. 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 3µs by tying the pin to 5V. This pin connects internally to a 15µA current source from VS and to a 2.6V threshold comparator. When the pin voltage is below 2.6V, the output device is 100% On. The PWM oscillator is not synchronized to the Input (pin 1), so the duration of the first pulse may be any portion of the programmed duty cycle. No connection is required when the device is in slave mode. 3 Oscillator PWM frequency is adjustable. A resistor to ground sets the current IREF and the internal PWM oscillator frequency. A range of 500Hz Frequency Adjust to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors higher than 10MΩ will be required. The pin then becomes a very high-impedance node and is, therefore, sensitive to noise pickup and PCB leakage currents. Resistor connection to this pin in slave mode sets the frequency at which current limit reset occurs. 4 Master With no connection, this pin is driven to 5V by an internal 15µA current source. In this mode the device is the master and the SYNC pin becomes a 0V to 4.2V output, which is High when the power device is on. When the Master/Input is 0V, the SYNC pin is an input. In slave mode, the output follows the SYNC pin; the output is High when SYNC is High. 5 BOOT The bootstrap capacitor between this pin and the output, supplies the charge to provide the VGS necessary to turn on the power device. CBOOT should be larger than 100pF. Use of a smaller CBOOT may slow the output rise time, device is specified and tested with 470pF. 6, 7 OUT1, OUT2 The output is the source of a power DMOS transistor with its drain connected to VPS . Its low on-resistance (0.45Ω typ) assures low power dissipation in the DRV104. Gate drive to the power device is controlled to provide a slew-rate limited rise-and-fall time. This reduces the radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off cycle. The external diode should be selected for low forward voltage and low storage time. The internal diode should not be used as a flyback diode. If devices are connected in parallel, the outputs must be connected through individual diodes. Devices are current-limit protected for shorts to ground, but not to supply. 8, 9 V PS 1, VPS 2 These are the load power-supply pins to the drain of the power device. The load supply voltage may exceed the voltage at pin 10 by 5V, but must not exceed 37V. 10 +V S This is the power-supply connection for all but the drain of the power device. The operating range is 8V to 32V. 11 GND This pin must be connected to the system ground for the DRV104 to function. It does not carry the load current when the power DMOS device is switched on. 12 SYNC The SYNC pin is a 0V to 4.2V copy of the output when the Master/Slave pin is High. As an output, it can supply 100µA with 1kΩ output resistance. At 2mA, it current limits to either 4.2V or 0V. When the Master pin is Low, it is an input and the threshold is 2V. SYNC output follows power output in master mode, and is not affected by thermal or current-limit shutdown. Power output follows SYNC input in slave mode. 13 Status OK Flag Normally High (active Low), a Flag Low signals either an over-temperature or over-current fault. A thermal fault (thermal shutdown) occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull- up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA, typical. 14 Input The input is compatible with standard TTL levels. The device becomes enabled when the input voltage is driven above the typical switching threshold, 1.8V; below this level, the device is disabled. Input current is typically 1µA when driven High and 1µA when driven Low. The input should not be directly connected to the power supply (VS) or damage will occur. PIN DESCRIPTIONS PIN CONFIGURATION Top View HTSSOP Duty Cycle Adj Delay Adj Osc Freq Adj Master Boot OUT1 OUT2 Input Status OK Flag SYNC GND S VPS 1 VPS 2 DRV104 PowerPAD Duty Cycle Adj Delay Adj Osc Freq Adj GND Input Status OK Flag S OUT DRV103 PowerPAD DRV103 for Reference Top View SO

SBVS036A www.ti.com TYPICAL CHARACTERISTICS At TC = +25°C and VS = +24V, unless otherwise noted. VOUT AND ISOLENOID WAVEFORMS WITH SOLENOID LOAD ISOLENOID (A) Time (ms) 1000 Input VOUT PWM Mode pull-in ON drop-out +VS VOUT AND IOUT WAVEFORMS WITH RESISTIVE LOAD IOUT (A) Time (ms) 1000 +VS +VS R L PWM Mode IAVG ON CURRENT LIMIT SHUTDOWN WAVEFORMS VIN (V)VOUT (V) Time (µs) 1000 VIN VOUT Status OK Flag Off Off On OK OK OK OK OK OK OK 0.70 0.65 0.60 0.55 0.50 0.45 0.40 –10–60 Current (mA) 40 90 140 QUIESCENT CURRENT vs TEMPERATURE Temperature (°C) 12V32V 24V –10–60 Delay (ms) 40 90 140 DELAY TO PWM vs TEMPERATURE Temperature (°C) 24V 12V, 8V 32V C D = 0.1µF 2.5 2.3 2.1 1.9 1.7 1.5 1.3 –10–60 Current Limit (A) 40 90 140 CURRENT LIMIT SHUTDOWN vs TEMPERATURE Temperature (°C)

SBVS036Awww.ti.com TYPICAL CHARACTERISTICS (Cont.) At TC = +25°C and VS = +24V, unless otherwise noted. –60 Minimum Delay (µs) 40 140 MINIMUM DELAY vs JUNCTION TEMPERATURE Temperature (°C) 32V 24V 12V 8V C D = 0pF 26.0 25.5 25.0 24.5 24.0 –10–60 Frequency (kHz) 40 90 140 OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE Temperature (°C) 24V12V 12V32V R FREQ = 191kΩ –60 Duty Cycle (%) 140 DUTY CYCLE vs JUNCTION TEMPERATURE Temperature (°C) 12V 24V 32V R PWM = 147kΩ 0.8 0.6 0.4 0.2 –10–60 VSAT at 1 Amp (V) 40 90 140 VSAT vs JUNCTION TEMPERATURE Temperature (°C) 1.250 1.249 1.248 1.247 1.246 1.245 1.244 –10–60 VREF (V) 40 90 140 VREF vs TEMPERATURE Temperature (°C) 8V 12V 24V 32V 250 200 150 100 Input Current (µA) INPUT CURRENT vs INPUT VOLTAGE Input Voltage (V)

SBVS036Awww.ti.com At very high oscillator frequencies, the energy in the DRV104’s linear rise and fall times can become significant and cause an increase in P THERMAL PROTECTION Power dissipated in the DRV104 causes its internal junction temperature to rise. The DRV104 has an on-chip thermal shutdown circuitry that protects the IC from damage. The thermal protection circuitry disables the output when the junction temperature reaches approximately +160°C, allow- ing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again en- abled. Depending on load and signal conditions, the thermal protection circuit may cycle on and off. This limits the dissi- pation of the driver but may have an undesirable effect on the load. Any tendency to activate the thermal protection circuit indi- cates excessive power dissipation or an inadequate heat sink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate the margin of safety in a complete design (including heat-sink), increase the ambient temperature until the thermal protection is trig- gered. Use worst-case load and signal conditions. For good reliability, thermal protection should trigger more than 35°C above the maximum expected ambient condition of your application. This produces a junction temperature of 125°C at the maximum expected ambient condition. The internal protection circuitry of the DRV104 is designed to protect against overload conditions. It is not intended to replace proper heat sinking. Continuously running the DRV104 into thermal shutdown will degrade device reliability. HEAT SINKING Most applications do not require a heat-sink to assure that the maximum operating junction temperature (125°C) is not exceeded. However, junction temperature should be kept as low as possible for increased reliability. Junction temperature can be determined according to the following equations: T J = TA + PD θJA (3) θJA = θJC + θCH + θHA (4) where: T J = Junction Temperature (°C) TA = Ambient Temperature (°C) PD = Power Dissipated (W) θJC = Junction-to-Case Thermal Resistance (°C/W) θCH = Case-to-Heat Sink Thermal Resistance (°C/W) θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W) θJA = Junction-to-Air Thermal Resistance (°C/W) Using a heat sink significantly increases the maximum allow- able power dissipation at a given ambient temperature. The answer to the question of selecting a heat-sink lies in determining the power dissipated by the DRV104. For DC output into a purely resistive load, power dissipation is simply the load current times the voltage developed across the conducting output transistor times the duty cycle. Other loads are not as simple. (For further information on calculating power dissipation, refer to Application Bulletin SBFA002, available at www.ti.com.) Once power dissipation for an application is known, the proper heat-sink can be selected. Heat-Sink Selection Example A PowerPAD HTSSOP-14 package dissipates 2W. The maxi- mum expected ambient temperature is 35°C. Find the proper heat-sink to keep the junction temperature below 125°C. Combining Equations 1 and 2 gives: T J = TA + PD (θJC + θCH + θHA ) (5) TJ, TA, and PD are given. θJC is provided in the specification table: 2.07°C/W. θCH depends on heat sink size, area, and material used. Semiconductor package type and mounting can also affect θCH . A typical θCH for a soldered-in-place PowerPAD HTSSOP-14 package is 2°C/W. Now, solving for θHA : θθ θ θ θ HA JA D JC CH HA HA TT P CC W CW CW CW =+ ( ) = °° °+ °( ) – – – – ./ / 125 35 2 20 7 2 40 9 (6) To maintain junction temperature below 125°C, the heat-sink selected must have a θHA less than 40.9°C/W. In other words, the heat-sink temperature rise above ambient tem- perature must be less than 81.8°C (40.9°C/W • 2W). Another variable to consider is natural convection versus forced convection air flow. Forced-air cooling by a small fan can lower θCA (θCH + θHA ) dramatically. As mentioned above, once a heat-sink has been selected, the complete design should be tested under worst-case load and signal conditions to ensure proper thermal protection. RFI/EMI Any switching system can generate noise and interference by radiation or conduction. The DRV104 is designed with controlled slew rate current switching to reduce these effects. By slowing the rise time of the output to 1µs, much lower switching noise is generated. Radiation from the DRV104-to-load wiring (the antenna ef- fect) can be minimized by using twisted pair cable or by shielding. Good PCB ground planes are recommended for low noise and good heat dissipation. Refer to the Bypassing section for notes on placement of the flyback diode.

SBVS036A www.ti.com BYPASSING A 1µF ceramic bypass capacitor is adequate for uniform duty cycle control when switching loads of less than 0.5A. Larger bypass capacitors are required when switching high-current loads. A 10µF ceramic capacitor is recommended for heavy- duty (1.2A) applications. It may also be desirable to run the DRV104 and load driver on separate power supplies at high- load currents. Bypassing is especially critical near the abso- lute maximum supply voltage of 32V. In the event of a current overload, the DRV104 current limit responds in microsec- onds, dropping the load current to zero. With inadequate bypassing, energy stored in the supply line inductance can lift the supply sufficiently to exceed voltage breakdown with catastrophic results. Place the flyback diode at the DRV104 end when driving long (inductive) cables to a remotely located load. This minimizes RFI/EMI and helps protect the output DMOS transistor from breakdown caused by dI/dt transients. Fast rectifier diodes such as epitaxial silicon or Schottky types are recommended for use as flyback diodes. APPLICATIONS CIRCUITS SINGLE AND MULTICHANNEL The DRV104 can be used in a variety of ways with resistive and inductive loads. As a single-channel driver, it can be placed on one PC board or inside a solenoid, relay, actuator, valve, motor, heater, thermoelectric cooler, or lamp housing. In high-density systems, multichannel power drivers may be packed close together on a PC board. For these switching applications, it is important to provide power supply bypass- ing as close to the driver IC as possible to avoid cross- coupling of spikes from one circuit to another. Also, in some applications, it may be necessary to keep beat frequencies (sum and difference between DRV oscillators or between DRV oscillators and system clock frequencies) from interfer- ing with low-level analog circuits that are located relatively near to the power drivers. Paralleling device outputs is not recommended as unequal load sharing and device damage will result. BEAT FREQUENCIES IN NON-SYNCHRONIZED MULTICHANNEL SYSTEMS In many multichannel systems, beat frequencies are of no consequence where each DRV uses its own internal oscilla- tor. Beat frequencies can be intentionally set up to be outside the measurement base-band to avoid interference in sensitive analog circuits located nearby. For example, with two DRV104s, a beat frequency of 22.5kHz can be established by setting one internal oscillator to a center of 62.5kHz and the other to 40kHz. Considering the specification of ±20% frequency accuracy, the beat could range from 2kHz (48kHz and 50kHz) to 43kHz (75kHz and 32kHz). By limiting the analog measurement bandwidth to 100Hz, for example, interference can be avoided. BEAT FREQUENCY ELIMINATION — OPTIONAL SYNCHRONIZATION The benefit of synchronization in multichannel systems is that measurement interference can be avoided in low-level analog circuits, particularly when physically close to the DRVs. Specifically, synchronization will accomplish the fol- lowing: 1. Eliminate beat frequencies between DRVs or DRVs and the system clock. 2. Predict quiet or non-switching times. Synchronization of DRV104s is possible by using one oscil- lator frequency for all DRVs. See Figure 15 for an example of one DRV internal oscillator as the master and the others as slaves. Also, one external clock can be used as the master and all the others as slaves. PEAK SUPPLY CURRENT ELIMINATION — OPTIONAL SWITCHING SKEW In many systems, particularly where only a few channels are used or low magnitude load currents are present, it is unnecessary to skew the switching times. In some multichannel systems, where just PWM is used, without initial dc time delay, simultaneous switching of edges can cause large peak currents to be drawn from the main power supply. This is similar to that which occurs when multiple switching power supplies draw current from one power source. Peak currents can be reduced by synchronizing oscillators and skewing switching edges. Synchronization has the added benefit of eliminating beat frequencies, as discussed above. Skewing can be accomplished by using a polyphase clock approach, which intentionally delays the time that each DRV switches on PWM edges. The DRV104 is useful for a variety of relay driver applications (see Figures 16 and 17), as well as valve drivers (see Figures 18 and 19).

FIGURE 15. Multichannel DRV104s, Synchronized with One as the Master and the Others as Slaves.

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