DRV102

DRV102 TI | Alldatasheet

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Technical content

FEATURES

G HIGH OUTPUT DRIVE: 2.7A G WIDE SUPPLY RANGE: +8V to +60V G COMPLETE FUNCTION PWM Output Internal 24kHz Oscillator Digital Control Input Adjustable Delay and Duty Cycle Over/Under Current Indicator G FULLY PROTECTED Thermal Shutdown with Indicator Internal Current Limit G POWER PACKAGES: 7-Lead TO-220 and 7-Lead Surface-Mount DDPAK

APPLICATIONS

G ELECTROMECHANICAL DRIVER: Solenoids Positioners Actuators High Power Relays/Contactors Valves Clutches/Brakes G SOLENOID OVERHEAT PROTECTORS G FLUID AND GAS FLOW CONTROLLERS G PART HANDLERS G ELECTRICAL HEATERS/COOLERS G MOTOR SPEED CONTROLLERS G INDUSTRIAL CONTROL G FACTORY AUTOMATION G MEDICAL ANALYSIS G PHOTOGRAPHIC PROCESSING

DESCRIPTION

The DRV102 is a high-side power switch employing a pulse-width modulated (PWM) output. Its rugged design is optimized for driving electromechanical devices such as valves, solenoids, relays, actuators, and positioners. The DRV102 is also ideal for driving thermal devices such as heaters and lamps. PWM operation conserves power and reduces heat rise in the device, resulting in higher reliability. In addition, adjustable PWM allows fine control of the power delivered to the load. Time from dc output to PWM output is externally adjustable. DRV102 DRV102 Delay Adjust Input (TTL-Compatible)On Off Thermal Shutdown Over/Under Current Flag Duty Cycle Adjust Load DRV102 24kHz Oscillator PWM 5 (+8V to +60V) (Gnd electrically connected to tab) Out Gnd (1) 4 VS Delay The DRV102 can be set to provide a strong initial closure, automatically switching to a “soft” hold mode for power savings. Duty cycle can be controlled by a resistor, analog voltage, or digital-to-analog converter for versatility. A flag output indicates thermal shutdown and over/under current limit. A wide supply range allows use with a variety of actuators. The DRV102 is available in 7-lead staggered TO-220 pack- age and a 7-lead surface-mount DDPAK plastic power package. It operates from –55°C to +125°C. SBVS009A – JANUARY 1998 – REVISED OCTOBER 2003 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998-2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

SBVS009Awww.ti.com SPECIFICATIONS At TC = +25°C, VS = +24V, load = series diode MUR415 and 100Ω , and 4.99kΩ Flag pull-up to +5V, unless otherwise noted. DRV102T, F PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT Output Saturation Voltage, Source I O = 1A +1.7 +2.2 V Current Limit 2 2.7 3.4 A Under-Scale Current 16 mA Leakage Current Output Transistor Off, V S = +60V, VO = 0V ±0.01 ±2m A DIGITAL CONTROL INPUT (1) VCTR Low (output disabled) 0 +1.2 V VCTR High (output enabled) +2.2 V S V ICTR Low (output disabled) V CTR = 0V –80 (2) µA ICTR High (output enabled) V CTR = +5V 20 (2) µA Propagation Delay: On-to-Off 0.9 µs Off-to-On 1.8 µs DELAY TO PWM (3) dc to PWM Mode Delay Equation(4) Delay to PWM ≈ CD • 106 (CD in F) s Delay Time C D = 0.1µF 80 97 110 ms Minimum Delay Time(5) C D = 0 15 µs DUTY CYCLE ADJUST Duty Cycle Range 10 to 90 % Duty Cycle Accuracy 49% Duty Cycle, R PWM = 25.5kΩ± 1 ±7% vs Supply Voltage 49% Duty Cycle, V S = 8V to 60V ±1 ±5% Nonlinearity(6) 20% to 80% Duty Cycle ±2 % FSR DYNAMIC RESPONSE Output Voltage Rise Time V O = 10% to 90% of VS 0.25 2.5 µs Output Voltage Fall Time V O = 90% to 10% of VS 0.25 2.5 µs Oscillator Frequency 19 24 29 kHz FLAG Normal Operation 20k Ω Pull-Up to +5V, IO < 1.5A +4 +4.9 V Fault(7) Sinking 1mA +0.2 +0.4 V Sink Current V FLAG = 0.4V 2 mA Under-Current Flag: Set 5.2 µs Reset 11 µs Over-Current Flag: Set 5.2 µs Reset 11.5 µs THERMAL SHUTDOWN Junction Temperature Shutdown +165 °C Reset from Shutdown +150 °C POWER SUPPLY Specified Operating Voltage +24 V Operating Voltage Range +8 +60 V Quiescent Current I O = 0 6.5 9 mA TEMPERATURE RANGE Specified Range –55 +125 °C Storage Range –55 +125 °C Thermal Resistance, θJC 7-Lead DDPAK, 7-Lead TO-220 3 °C/W Thermal Resistance, θJA 7-Lead DDPAK, 7-Lead TO-220 No Heat Sink 65 °C/W NOTES: (1) Logic high enables output (normal operation). (2) Negative conventional current flows out of the terminals. (3) Constant dc output to PWM (pulse-width modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust pin low corresponds to an infinite (continuous) delay. (5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature, over-current, or under-current conditions.

SBVS009A www.ti.com CONNECTION DIAGRAMS NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may de- grade device reliability. (2) Vapor-phase or IR reflow techniques are recom- mended for soldering the DRV102F surface-mount package. Wave soldering is not recommended due to excessive thermal shock and “shadowing” of nearby devices. ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7-Lead Stagger-Formed TO-220 NOTE: Tabs are electrically connected to ground (pin 4). 1234 5 6 7 7-Lead DDPAK Surface-Mount PWM PWM Gnd Out VS Delay In 1234 5 6 Flag Gnd Out VS Delay In Flag PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.

SBVS009Awww.ti.com PIN # NAME DESCRIPTION Pin 1 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises to 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be driven to the power supply (VS) without damage. Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator. When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1), so the first pulse may be extended by any portion of the programmed duty cycle. Pin 3 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source (PWM) from V S. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or output of a D/A converter. The active voltage range is from 0.55V to 3.7V to facilitate the use of single-supply control electronics. At 0.56V (or R PWM = 4.4kΩ ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM frequency is a constant 24kHz. Pin 4 Ground This pin is electrically connected to the package tab. It must be connected to system ground for the DRV102 to function. It carries the 6.5mA quiescent current. Pin 5 V S This is the power supply pin. Operating range is +8V to +60V. Pin 6 Out The output is the emitter of a power npn with the collector connected to V S. Low power dissipation in the DRV102 is obtained by low saturation voltage and fast switching transitions. Rise time is less than 250ns, fall time depends on load impedance. A flyback diode is (D 1) needed with inductive loads to conduct the load current during the off cycle. The external diode should be selected for low forward voltage. The internal clamp diode provides protection but should not be used to conduct load currents. An additional diode (D 2), located in series with Out pin, is required for inductive loads. Pin 7 Flag Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under- current flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermal shutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its output requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED. PIN DESCRIPTIONS LOGIC BLOCK DIAGRAM C D R PWM Input On Off Over/Under Current DRV102 Flag Thermal Shutdown PWM (2) Delay Load NOTES: (1) Schottky Power Rectifier for low power dissipation. (2) Schottky or appropriately rated silicon diode. (+8V to +60V) Gnd 4 Out D 2 D 1 (1) VS

SBVS009A www.ti.com TYPICAL PERFORMANCE CURVES At TC = +25°C and VS = +24V, unless otherwise noted. OUTPUT SATURATION VOLTAGE vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Saturation Voltage (V) 2.25 1.75 1.5 1.25 0.75 IO = 2A IO = 1.5A IO = 1A IO = 0.1A QUIESCENT CURRENT vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Quiescent Current (mA) 7.5 6.5 5.5 VS = +60V VS = +8V VS = +24V DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE VPWM (V) Duty Cycle (%) Duty Cycle Error (%) Duty Cycle Error IO = 0.1A IO = 1A IO = 0.1A to 1A DUTY CYCLE vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Duty Cycle (%) VS = +8V R PWM = 25.5kΩ VS = +24V VS = +60V CURRENT LIMIT vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Current Limit (mA) 3.25 2.75 2.5 2.25 VS = +60V, Load = 5Ω VS = +24V, Load = 5Ω VS = +8V, Load = 1Ω UNDER-SCALE CURRENT vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Under-Scale Current (mA) VS = +8V to +60V

SBVS009Awww.ti.com TYPICAL PERFORMANCE CURVES (CONT) At TC = +25°C and VS = +24V, unless otherwise noted. V OUT FLAG OPERATION OVER-CURRENT LIMIT (VS = +60V, CD = 220pF, RPWM = 25.5kΩ , Load = 350mH || 47Ω ) FLAG OPERATION UNDER-CURRENT (VS = +60V, CD = 120pF, RPWM = 25.5kΩ , No Load) 0.5A V OUT DC TO PWM MODE DRIVING INDUCTIVE LOAD (VS = +60V, CD = 120pF, RPWM = 30.1kΩ , Load = 350mH) TYPICAL SOLENOID CURRENT WAVEFORM (VS = +60V, CD = 0.1µF, RPWM = 30.1kΩ , Load = 350mH) 50µs/div Inductive load ramp current 50µs/div 60V 40V 20V ISUPPLY PWM ModeConstant Output Flag only on during constant output or “ON ” portion of PWM mode 60V 40V 20V V IN V FLAG 50µs/div 25ms/div PWM Mode 60V 40V 20V V FLAG Onset of current limit where VOUT begins to drop Flag only set during constant output mode or “ON ” portion of PWM mode Solenoid Closure Solenoid Motion Period V IN Solenoid Current 0.5A 10µs/div CURRENT LIMIT REPSONSE (Load = 1Ω , 2kΩ pull-up to +5V on Flag pin) OSCILLATOR FREQUENCY vs TEMPERATURE –75 –55 –35 –15 5 25 45 65 85 105 125 Temperature (°C) Oscillator Frequency (kHz) 24.2 24.0 23.8 23.6 23.4 VS = +8V VS = +60V V FLAG 2.5V IOUT

SBVS009A www.ti.com TYPICAL PERFORMANCE CURVES (CONT) At TC = +25°C and VS = +24V, unless otherwise noted. OUTPUT LEAKAGE CURRENT vs TEMPERATURE –75 –55 –35 –15 5 25 45 65 85 105 125 Temperature (°C) Leakage Current (µA) –200 –175 –150 –125 –100 –75 Output Transistor Off VO = 0V VS = +60V VS = +8V VS = +24V NOMINAL DELAY TIME TO PWM vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Delay (ms) 103 101 C D = 0.1µFVS = +8V VS = +24V VS = +60V CURRENT LIMIT PRODUCTION DISTRIBUTION Percent of Units (%) Current Limit (A) Typical distribution of packaged units. DRV102F and DRV102T included. DELAY TIME TO PWM PRODUCTION DISTRIBUTION Percent of Units (%) Delay Time to PWM (ms) Typical distribution of packaged units. DRV102F and DRV102T included. C D = 0.1µF 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 DUTY CYCLE ACCURACY PRODUCTION DISTRIBUTION Percent of Units (%) Duty Cycle Accuracy (%) Typical distribution of packaged units. DRV102F and DRV102T included. Nominal Duty Cycle = 49% R PWM = 25.5kΩ

connected to the power supply pin. The Input (pin 1) is compatible with standard TTL levels. DRV102 output off. Input current is typically 80µA. FIGURE 1. Basic Circuit Connections and Timing Diagram. Ground (pin 4) is electrically connected to the package tab. 1 in Figure 1a) across the output is required. Flag and ground for noisy applications.

• • • Initial dc Output (set by value of CD ) PWM Mode (resistor or voltage controlled) NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle. Flyback diode shown near DRV102. For some applications with remotely located load, it may be desirable to place the diode near the solenoid— see “Flyback Diode” text. Motorola MSRS1100T3 (1A, 100V) or MBRS360T3 (3A, 60V). 0.1µF (+8V to +60V)

SBVS009Awww.ti.com The difficulty in selecting the heat sink required lies in determining the power dissipated by the DRV102. For dc output into a purely resistive load, power dissipation is simply the load current times the voltage developed across the conducting output transistor times the duty cycle. Other loads are not as simple. Once power dissipation for an application is known, the proper heat sink can be selected. Heat Sink Selection Example A TO-220 package’s maximum dissipation is 2 Watts. The maximum expected ambient temperature is 80°C. Find the proper heat sink to keep the junction temperature below 125°C. Combining Equations 1 and 2 gives: T J = TA + PD (θJC + θCH + θHA )( 3 ) TJ, TA , and PD are given. θJC is provided in the Specifica- tions table, 3°C/W. θCH can be obtained from the heat sink manufacturer. Its value depends on heat sink size, area, and material used. Semiconductor package type, mounting screw torque, insulating material used (if any), and thermal joint compound used (if any) also affect θCH . A typical θCH for a TO-220 mounted package is 1°C/W. Now we can solve for θHA : (4) To maintain junction temperature below 125°C, the heat sink selected must have a θHA less than 18.5°C/W. In other words, the heat sink temperature rise above ambient must be less than 37°C (18.5°C/W • 2W). For example, at 2 Watts Thermalloy model number 6030B has a heat sink temperature rise of about 33°C above ambient, which is below the 37°C required in this example. Figure 13 shows power dissipation versus ambient temperature for a TO-220 package with a 6030B heat sink. Another variable to consider is natural convection versus forced convection air flow. Forced-air cooling by a small fan can lower θCA (θCH + θHA ) dramatically. Heat sink manufac- turers provide thermal data for both of these cases. For additional information on determining heat sink require- ments, consult Application Bulletin AB-038. As mentioned earlier, once a heat sink has been selected, the complete design should be tested under worst-case load and signal conditions to ensure proper thermal protection. θθ θ θ HA JA D JC CH HA TT P=+ () = °° °+ °() =° – –

125 C – 80 C

2W – 3 C/W 1 C/W 18.5 C/W

FIGURE 14. Fluid Flow Control System. FIGURE 15. Instrument Light Dimmer Circuit. FIGURE 16. 4-20mA Input to PWM Output. loads to conduct load current during the off cycle.

34 G n d

a resistor, analog voltage, or D/A converter.

FIGURE 17. Improved Switching Time When Driving Multiple Loads.

FIGURE 18. (a) Constant Temperature Controller. (b) Improved Accuracy Constant Temperature Controller. to the mechanical mounting requirements.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DRV102F OBSOLETE DDPAK KTW 7 TBD Call TI Call TI DRV102F/500 ACTIVE DDPAK KTW 7 500 TBD CU SNPB Level-3-220C-168 HR DRV102FKTWT ACTIVE DDPAK KTW 7 50 TBD CU SNPB Level-3-220C-168 HR DRV102T ACTIVE TO-220 KV 7 49 TBD CU SNPB Level-NA-NA-NA (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2005 Addendum-Page 1

MPSF015 – AUGUST 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.010 (0,25) A M 4201284/A 08/01 0.385 (9,78) 0.410 (10,41) M MB C –A– 0.006 –B– 0.170 (4,32) 0.183 (4,65) 0.000 (0,00) 0.012 (0,305) 0.104 (2,64) 0.096 (2,44) 0.034 (0,86) 0.022 (0,57) 0.050 (1,27) 0.055 (1,40) 0.045 (1,14) 0.014 (0,36) 0.026 (0,66) 0.330 (8,38) 0.370 (9,40) 0.297 (7,54) 0.303 (7,70) 0.0585 (1,485) 0.0625 (1,587) 0.595 (15,11) 0.605 (15,37) 0.019 (0,48) 0.017 (0,43) 0°~3° 0.179 (4,55) 0.187 (4,75) 0.056 (1,42) 0.064 (1,63) 0.296 (7,52) 0.304 (7,72) 0.300 (7,62) 0.252 (6,40) F C C H H H C A NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead width and height dimensions apply to the plated lead. D. Leads are not allowed above the Datum B. E. Stand–off height is measured from lead tip with reference to Datum B. F. Lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum dimension by more than 0.003”. G. Cross–hatch indicates exposed metal surface. H. Falls within JEDEC MO–169 with the exception of the dimensions indicated.

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