DRV101T

DRV101_15 TI1 | Alldatasheet

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www.ti.com DRV101 PWM SOLENOID/VALVE DRIVER DRV101 DRV101

FEATURES

G HIGH OUTPUT DRIVE: 2.3A G WIDE SUPPLY RANGE: +9V to +60V G COMPLETE FUNCTION PWM Output Internal 24kHz Oscillator Digital Control Input Adjustable Delay and Duty Cycle Over/Under Current Indicator G FULLY PROTECTED Thermal Shutdown with Indicator Internal Current Limit G PACKAGES: 7-Lead TO-220 and 7-Lead Surface-Mount DDPAK

APPLICATIONS

G ELECTROMECHANICAL DRIVERS: Solenoids Positioners Actuators High Power Relays/Contactors Valves Clutch/Brake G FLUID AND GAS FLOW SYSTEMS G INDUSTRIAL CONTROL G FACTORY AUTOMATION G PART HANDLERS G PHOTOGRAPHIC PROCESSING G ELECTRICAL HEATERS G MOTOR SPEED CONTROL G SOLENOID/COIL PROTECTORS G MEDICAL ANALYZERS

DESCRIPTION

The DRV101 is a low-side power switch employing a pulse-width modulated (PWM) output. Its rugged design is optimized for driving electromechanical devices such as valves, solenoids, relays, actuators, and positioners. The DRV101 is also ideal for driving thermal devices such as heaters and lamps. PWM operation conserves power and reduces heat rise, resulting in higher reliability. In addition, adjustable PWM allows fine control of the power delivered to the load. Time from dc output to PWM output is externally adjustable. The DRV101 can be set to provide a strong initial closure, automatically switching to a soft hold mode for power savings. Duty cycle can be controlled by a resistor, analog voltage, or digital-to-analog converter for versatility. A flag output indicates thermal shutdown and over/under current limit. A wide supply range allows use with a variety of actuators. The DRV101 is available in a 7-lead staggered TO-220 package and a 7-lead surface-mount DDPAK plastic power package. It is specified over the extended industrial temperature range of –40°C to +85°C. Delay Adjust Input (TTL-Compatible)On Off Thermal Shutdown Over/Under Current Flag Load Duty Cycle Adjust VS (+9V to +60V) 24kHz Oscillator PWM Gnd Out (electrically connected to tab) Delay SBVS008B – JANUARY 1998 – REVISED MAY 2009 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998-2009, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. www.ti.com

SBVS008Bwww.ti.com SPECIFICATIONS At TC = +25°C, VS = +24V, Load = 100Ω || 1000pF, and 4.99kΩ Flag pullup to +5V, unless otherwise noted. DRV101T, F PARAMETER COMMENTS MIN TYP MAX UNITS OUTPUT Output Saturation Voltage, Sink I O = 1A +0.8 +1 V Current Limit 1.9 2.3 3 A Under-Scale Current(1) 23 mA Leakage Current Output Transistor Off, V S = VO = +60V ±0.01 ±1m A DIGITAL CONTROL INPUT (2) VCTR Low (output disabled) 0 +1.2 V VCTR High (output enabled) +2.2 +5.5 V ICTR Low (output disabled) V CTR = 0V –80 µA ICTR High (output enabled) V CTR = +5V 20 µA Propagation Delay On-to-Off and Off-to-On 2 µs DELAY TO PWM (3) dc to PWM Mode Delay Equation(4) Delay to PWM ≈ CD • 106 (CD in F) s Delay Time C D = 0.1µF 80 95 110 ms Minimum Delay Time(5) C D = 0 15 µs DUTY CYCLE ADJUST Duty Cycle Range 10 to 90 % Duty Cycle Accuracy 50% Duty Cycle, R PWM = 28.7kΩ± 2 ±5% vs Supply Voltage 50% Duty Cycle, V S = VO = +9V to +60V ±1 ±5% Nonlinearity(6) 10% to 80% Duty Cycle 2 % FSR DYNAMIC RESPONSE Output Voltage Rise Time V O = 10% to 90% of VS 1 2.5 µs Output Voltage Fall Time V O = 90% to 10% of VS 0.1 2.5 µs Oscillator Frequency 19 24 29 kHz FLAG Normal Operation 20k Ω Pull-Up to +5V, IO < 1.5A +4 +4.9 V Fault(7) Sinking 1mA +0.2 +0.8 V Sink Current V FLAG = 0.4V 2 mA Under-Current Flag: Set 4 µs Reset 2 µs Over-Current Flag: Set 2 µs Reset 2 µs THERMAL SHUTDOWN Junction Temperature Shutdown +165 °C Reset from Shutdown +150 °C POWER SUPPLY Specified Operating Voltage +24 V Operating Voltage Range +9 +60 V Quiescent Current I O = 0 3.5 5 mA TEMPERATURE RANGE Specified Range –40 +85 °C Operating Range –55 +125 °C Storage Range –65 +150 °C Thermal Resistance, θJC 7-Lead DDPAK, 7-Lead TO-220 3 °C/W Thermal Resistance, θJA 7-Lead DDPAK, 7-Lead TO-220 No Heat Sink 65 °C/W NOTES:(1) Under-scale current for TC < 100°C — see Under-Scale Current vs Temperature typical performance curve. (2) Logic High enables output (normal operation). (3) Constant dc output to PWM (pulse-width modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin low corresponds to an infinite (continuous) delay. (5) Connecting the Delay Adjust pin to +5V reduces delay time to 3µs. (6) VIN at pin 3 to percent of duty cycle at pin 6. (7) A fault results from over-temperature, over-current, or under-current conditions.

SBVS008B www.ti.com CONNECTION DIAGRAMS NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may de- grade device reliability. (2) Vapor-phase or IR reflow techniques are recom- mended for soldering the DRV101F surface-mount package. Wave soldering is not recommended due to excessive thermal shock and “shadowing” of nearby devices. ABSOLUTE MAXIMUM RATINGS (1) ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7-Lead Stagger-Formed TO-220 NOTE: Tabs are electrically connected to ground (pin 4). 1234 5 6 7 7-Lead DDPAK Surface-Mount PWM PWM Gnd Out VS Delay In 1234 5 6 Flag Gnd Out VS Delay In Flag PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.

SBVS008Bwww.ti.com PIN # NAME DESCRIPTION Pin 1 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises to 3.4V. Input current is 20µA when driven high and 80µA with the input low. The input may be momentarily driven to the power supply (VS) without damage. Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in a delay of approximately 15µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 3µs by tying the pin to 5V. This pin connects internally to a 3µA current source from VS and to a 3V threshold comparator. When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1), so the first pulse may be extended by any portion of the programmed duty cycle. Pin 3 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a 19kΩ resistor to ground. It is driven by a 200µA current source (PWM) from V S. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage, or output of a D/A converter. The active voltage range is from 0.75V to 3.7V to facilitate the use of single-supply control electronics. At 0.75V (or R PWM = 3.5kΩ ), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM frequency is a constant 24kHz. Pin 4 Ground This pin is electrically connected to the package tab. It must be connected to system ground for the DRV101 to function. It carries the 3.5mA quiescent current plus the load current when the device is on. Pin 5 V S This is the power supply pin. Operating range is +9V to +60V. Pin 6 Out The output is the collector of a power npn with the emitter connected to ground. Low power dissipation in the DRV101 is attained by the low saturation voltage and the fast switching transitions. Fall time is less than 75ns, rise time depends on load impedance. Base drive to the power device is limited with light loads to control turn-off delay. The response of this circuit causes the brief dip in saturation voltage after turn on. A flyback diode is needed with inductive loads to conduct the load current during the off cycle. The external diode should be selected for low forward voltage. The internal clamp diode provides protection but shouuld not be used to conduct load currents greater than 0.5A. Pin 7 Flag Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under- current flags are true only when the output is on (constant dc output or the “on” portion of PWM mode). A thermal fault (thermal shutdown) occurs when the die surface reaches approximately 165°C and latches until the die cools to 150°C. Its output requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED. PIN DESCRIPTIONS LOGIC BLOCK DIAGRAM C D R PWM Input On Off Over/Under Current Flag Load VS (+9V to +60V) Thermal Shutdown PWM Gnd Out Delay Schottky Power Rectifier

SBVS008B www.ti.com DUTY CYCLE vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Duty Cycle (%) 100 R PWM = 6.04kΩ R PWM = 30.1kΩ R PWM = 100kΩ R PWM = 301kΩ R PWM = 750kΩ TYPICAL PERFORMANCE CURVES At TC = +25°C and VS = +24V, unless otherwise noted. CURRENT LIMIT vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Current Limit (mA) 2.6 2.4 2.2 2.0 1.8 1.6 VS = +9V to +60V QUIESCENT CURRENT vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Quiescent Current (mA) 3.9 3.7 3.5 3.3 3.1 VS = +60V VS = +9V VS = +24V UNDER-SCALE CURRENT vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Under-Scale Current (mA) VS = +9V Lines represent maximum current before under-current Flag occurs. Under-current Flag may not occur for case temperature above 100°C. VS = +60V VS = +24V DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE VPWM (V) Duty Cycle (%) Duty Cycle Error (%) Duty Cycle Load = 1A Error OUTPUT SATURATION VOLTAGE vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Saturation Voltage (V) 2.5 2.0 1.5 1.0 0.5 IO = 2A IO = 1A IO = 1.5A IO = 0.5A IO = 0.1A Effect of Current-Limit

SBVS008Bwww.ti.com TYPICAL PERFORMANCE CURVES (CONT) At TC = +25°C and VS = +24V, unless otherwise noted. V OUT FLAG OPERATION OVER-CURRENT LIMIT (VS = +60V, CD = 110pF, RPWM = 750kΩ ) FLAG OPERATION UNDER-CURRENT (VS = +24V, CD = 110pF, RPWM = 6.04kΩ ) No Load V OUT DUTY CYCLE UNDERSHOOT Load = 1A DC TO PWM MODE DRIVING INDUCTIVE LOAD (VS = +60V, CD = 110pF, RPWM = 301kΩ ) 30V 20V 10V 30V 20V 10V V OUT TYPICAL SOLENOID CURRENT WAVEFORM (VS = +24V) 50µs/div Inductive load ramp current See Duty Cycle Undershoot curve for detail 25µs/div 60V 40V 20V IGND 1µs/div PWM ModeConstant Output Flag only on during constant output or “ON ” portion of PWM mode V IN V FLAG 50µs/div 0.5A 25ms/div PWM Mode OSCILLATOR FREQUENCY vs TEMPERATURE –75 –55 –35 –15 5 25 45 65 85 105 125 Temperature (°C) Oscillator Frequency (kHz) 24.2 24.0 23.8 23.6 23.4 VS = +9V VS = +60V 60V 40V 20V V FLAG Onset of current limit Flag only set during constant output mode or “ON ” portion of PWM mode Clean Layout Non-optimized Layout V OUT Solenoid Closure Solenoid Motion Period

SBVS008B www.ti.com TYPICAL PERFORMANCE CURVES (CONT) At TC = +25°C and VS = +24V, unless otherwise noted. MINIMUM DELAY TO PWM vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Delay (µs) VS = +24V No connection to Delay Adjust pin (CD = 0) VS = +60V VS = +9V NOMINAL DELAY TIME TO PWM vs TEMPERATURE –75 –50 –25 0 25 50 75 100 125 Temperature (°C) Delay (ms) 104 102 100 VS = +9V VS = +60V VS = +24VVS = +24V C D = 0.1µF

shown in the Typical Performance Curves. pull-in current requirement than hold requirement. ate capacitor values or pin connection. TABLE I. Delay Adjust Pin Connections. accurate means of controlling power delivered to the load. resistor, analog voltage, or the output of a D/A converter. Reduced duty cycle results in reduced power dissipation. connected between the Duty Cycle Adjust pin and ground. Increased resistor values correspond to decreased duty cycles. Table II provides resistor values for typical duty cycles. PWM is included in Figure 3. FIGURE 3. R PWM vs Duty Cycle.FIGURE 2. Simplified Circuit Model of the Delay Adjust Pin. current source and a 3V comparator as shown in Figure 2. is 100% on (dc output mode). TABLE II. Duty Cycle Adjust. TA = +25°C, VS = +24V.

FIGURE 16. Temperature Controller. to the mechanical mounting requirements.

FIGURE 24. Isolated High-Side Driver.

SBVS008Bwww.ti.com

Revision History

DATE REVISION PAGE SECTION DESCRIPTION 1 Front Page Updated front page appearance. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 5/09 B

www.ti.com 10-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DRV101F OBSOLETE DDPAK/ TO-263 KTW 7 TBD Call TI Call TI DRV101F/500 ACTIVE DDPAK/ TO-263 KTW 7 500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR DRV101F DRV101FKTWT ACTIVE DDPAK/ TO-263 KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR DRV101F DRV101FKTWTG3 ACTIVE DDPAK/ TO-263 KTW 7 50 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR DRV101F DRV101T ACTIVE TO-220 KVT 7 50 Green (RoHS & no Sb/Br) CU SN N / A for Pkg Type DRV101T DRV101TG3 ACTIVE TO-220 KVT 7 50 Green (RoHS & no Sb/Br) CU SN N / A for Pkg Type DRV101T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

www.ti.com 10-Apr-2013 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DRV101F/500 DDPAK/ TO-263 DRV101FKTWT DDPAK/ TO-263 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV101F/500 DDPAK/TO-263 KTW 7 500 346.0 346.0 41.0 DRV101FKTWT DDPAK/TO-263 KTW 7 50 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2015 Pack Materials-Page 2

MPSF015 – AUGUST 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT 0.010 (0,25) A M 4201284/A 08/01 0.385 (9,78) 0.410 (10,41) M MB C –A– 0.006 –B– 0.170 (4,32) 0.183 (4,65) 0.000 (0,00) 0.012 (0,305) 0.104 (2,64) 0.096 (2,44) 0.034 (0,86) 0.022 (0,57) 0.050 (1,27) 0.055 (1,40) 0.045 (1,14) 0.014 (0,36) 0.026 (0,66) 0.330 (8,38) 0.370 (9,40) 0.297 (7,54) 0.303 (7,70) 0.0585 (1,485) 0.0625 (1,587) 0.595 (15,11) 0.605 (15,37) 0.019 (0,48) 0.017 (0,43) 0°~3° 0.179 (4,55) 0.187 (4,75) 0.056 (1,42) 0.064 (1,63) 0.296 (7,52) 0.304 (7,72) 0.300 (7,62) 0.252 (6,40) F C C H H H C A NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead width and height dimensions apply to the plated lead. D. Leads are not allowed above the Datum B. E. Stand–off height is measured from lead tip with reference to Datum B. F. Lead width dimension does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum dimension by more than 0.003”. G. Cross–hatch indicates exposed metal surface. H. Falls within JEDEC MO–169 with the exception of the dimensions indicated.

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