DRF1300 MICROSEMI | Alldatasheet

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Technical content

500V, 30A, 30MHz The DRF1300 is a push-pull hybrid containing two high power gate drivers and two power MOSFETs. It was designed to provide the sys- tem designer increased fl exibility, higher performance, and lowered cost over a non-integrated solution. This low parasitic approach, coupled with the Schmitt trigger input, Kelvin signal ground, Anti-Ring function Invert and Non-invert select pin provide improved stability and control in Kilowatt to Multi-Kilowatt, High Frequency ISM applications. TYPICAL APPLICATIONS

  • Class C, D and E RF Generators
  • Switch Mode Power Amplifi ers
  • HV Pulse Generators
  • Ultrasound Transducer Drivers
  • Acoustic Optical Modulators

FEATURES

  • Switching Frequency: DC TO 30MHz
  • Inverting Non-Inverting Select
  • Low Pulse Width Distortion
  • Single Power Supply (Per Section)
  • 1V CMOS Schmitt Trigger Input 1V Hysteresis
  • Switching Speed 3-4ns
  • B Vds = 500V
  • I ds = 30A max. Per-section
  • R ds(on) ≤ .24 Ohm
  • P D = 550W Per-section
  • RoHS Compliant MOSFET Push-Pull Hybrid Microsemi Website - http://www.microsemi.com 050-4971 Rev D 4-2009 Symbol Parameter Ratings Unit VDD Supply Voltage 18 VIN, FN Input Single Voltages -.7 to +5.5 IO PK Output Current Peak 8A TJMAX Operating Temperature 175 °C Driver Absolute Maximum Ratings Driver Specifi cations Symbol Parameter Min Typ Max Unit VDD Supply Voltage 81 5 VIN Input Voltage 3 5 IN(R) Input Voltage Rising Edge 3 ns IN(F) Input Voltage Falling Edge 3 IDDQ Quiescent Current 2m A IO Output Current 8A Coss Output Capacitance 2500 pF Ciss Input Capacitance 3 RIN Input Parallel Resistance 1M Ω VT(ON) Input, Low to High Out 0.8 1.1 V VT(OFF) Input, High to Low Out 1.9 2.2 TDLY Time Delay (throughput) 38 ns tr Rise Time 5 ns tf Fall Time 5 D S IN DRIVER 30A MOSFETS D S IN

DRF1300MOSFET Specifi cations (Per-Section) Symbol Parameter Min Typ Max Unit BVDSS Drain Source Voltage 500 V ID Continuous Drain Current THS = 25°C 30 A RDS(on) Drain-Source On State Resistance 0.24 Ω Dynamic Characteristics (Per-Section) Section A and B Output Switching Performance Symbol Characteristic Min Typ Max Typ TON Leading Edge 10% to 90% 2 3 4 ns TOFF Trailing Edge 10% to 90% 45 TBD 49 TDLY(ON) Total Throughput Delay Time, ON 45 TBD 47 TDLY(OFF) Total Throughput Delay Time, OFF 49 50 51 ∆TDLY(ON) Delta TON Delay between Section A and B -0.5 0 1.5 ∆TDLY(OFF) Delta TOFF Delay between Section A and B 0 0.6 1.3 Symbol Parameter Min Typ Max Unit C ISS Input Capacitance 1800 pFCoss Output Capacitance 335 Crss Reverse Transfer Capacitance 75 Thermal Characteristics (Total Package) Symbol Parameter Ratings Unit RθJC Junction to Case Thermal Resistance .06 °C/W RθJHS Junction to Heat Sink Thermal Resistance .134 TJSTG Storage Junction Temperature -55 to 150 °C PD Maximum Power Dissipation @ TSINK = 25°C 1.1 KW PDC Total Power Dissipation @ TC = 25°C 2.5 Microsemi reserves the right to change, without notice, the specifi cations and information contained herein. 050-4971 Rev D 4-2009 Figure 1, DRF1300 Circuit Diagram The DRF1300 is confi gured as a Push Pull Hybrid incorporating two independent channels confi gured with a common source each consisting of a driver, a high voltage MOSFET and by-pass capacitors. The function of the by-pass capacitors C1 and C2 is to reduce the internal parasitic loop inductance. This coupled with the tight geometry of the hybrid allows optimal gate drive to the MOSFET. This low parasitic approach coupled with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the Anti-Ring function; provide improved stability and control in Kilowatt to Multi- Kilowatt high frequency applications. The IN pin should be referenced to the Kelvin Ground (SG) and is applied to a Schmitt Trigger. The SG pin is a Kelvin return for the IN pin only. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifi cally for ring abatement. To further increase the utility of the device the driver die and the MOSFET die are adjacent die selected. This provides a very close match in the turn on and propagation delays.

None of the inputs to U1 or U2 of the DRF1300 are isolated for direct connection to a ground referenced power supply or control circuitry. Isolation appropriate to the application is the responsibility of the end user. It is imperative that high output currents be restricted to the Source (14, 16, 18) and Drain (15, 17) pins by design. See DRF100 for more information on Driver IC used in the device. The Function (FN, pin 3 or pin 9) is the invert or non-invert select Pin, it is Internally held high. Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. us and Foreign patents pending. All Rights Reserved. DRF1300 050-4971 Rev D 4-2009 The test circuit illustrated in Figure 2 was used to evaluate the DRF1300 (available as an evaluation board DRF13XX/EVALSW.) The input control signal is applied via IN and SG pins using RG188. This provides excellent noise immunity and control of the signal ground currents. The +VDD inputs (pins 2, 6, 8 and 12) should be heavily by-passed by 1uF capacitors as close to the pins as possible. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. A 50 Ohm (RL) load is used to evaluate the output performance. Figure 2, DRF1300 Test Circuit Truth Table * Referenced to SG FN (pin 3) IN (pin 4) MOSFET HIGH HIGH ON HIGH LOW OFF LOW HIGH OFF LOW LOW ON Truth Table * Referenced to SG FN (pin 9) IN (pin 10) MOSFET HIGH HIGH ON HIGH LOW OFF LOW HIGH OFF LOW LOW ON

Figure 4, DRF1300 Mechanical Outline All dimensions are ± .005 DRF1300 050-4971 Rev D 4-2009 Pin Assignments Pin 1 Ground Pin 2 U1 +Vdd Pin 3 U1 FN Pin 4 U1 IN Pin 5 U1 SG Pin 6 U1 +Vdd Pin 7 Ground Pin 8 U2 +Vdd Pin 9 U2 FN Pin 10 U2 IN Pin 11 U2 SG Pin 12 U2 +Vdd Pin 13 Ground Pin 14 Source Pin 15 U2 Drain Pin 16 Source Pin 17 U1 Drain Pin 18 Source R0.150

4 PLCS

Ø0.125 0.750 0.250 0.250 2.000 0.125 0.125 0.300 0.040 1.000 0.300 .005" TYP. HALF HARD COPPER GOLD PLATED 0.263 GAPS - 0.080" , 2 PLCS GAPS - 0.090" , 2 PLCS MEDIUM LEADS - 0.175", 3 PLCS LARGE LEADS - 0.300", 2 PLCS LARGE LEADS - 0.135", 3 PLCS MEDIUM LEADS - 0.090", 4 PLCS 0.268 SMALL LEADS - 0.050", 6 PLCS GAPS - .0400", 4 PLCS GAPS - .0300", 8 PLCS 1 2 3 4 5 6 7 8 9 10 11 12 13 18 17 16 15 14 DRF1300