DRF1200 MICROSEMI | Alldatasheet

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Technical content

1000V, 13A, 30MHz The DRF1200 hybrid includes a high power gate driver and the power MOSFET. The driver output can be confi gured as Inverting and Non- Inverting. It was designed to provide the system designer increased fl exibility and lowered cost over a non-integrated solution. TYPICAL APPLICATIONS

  • Class C, D and E RF Generators
  • Switch Mode Power Amplifi ers
  • Pulse Generators
  • Ultrasound Transducer Drivers
  • Acoustic Optical Modulators

FEATURES

  • Switching Frequency: DC TO 30MHz
  • Low Pulse Width Distortion
  • Single Power Supply
  • 1V CMOS Schmitt Trigger Input 1V Hysteresis
  • Inverting Non-Inverting Select
  • RoHS Compliant
  • Switching Speed 3-4ns
  • B Vds = 1Kv
  • Ids = 13A Max
  • Rds(on) ≤ 0.90 Ohm
  • PD = 624W Symbol Parameter Min Typ Max Unit VDD Supply Voltage 15 VIN, FN Input Single Voltages -.7 to +5.5 IO PK Output Current Peak 8A TJMAX Operating Temperature 175 °C MOSFET Driver Hybrid Driver Absolute Maximum Ratings Driver Specifi cations Symbol Parameter Min Typ Max Unit VDD Supply Voltage 10 15 VIN Input Voltage 3 5.5 IN(R) Input Voltage Rising Edge 3 ns IN(F) Input Voltage Falling Edge 3 IDDQ Quiescent Current 2m A IO Output Current 8A Ciss Input Capacitance 3 RIN Input Parallel Resistance 1M Ω VTH(on) Input, Voltage Threshold Low (See truth table) 0.8 1.1 V VTH(off) Input, Voltage Threshold High (See truth table) 1.9 2.2 TDLY Time Delay (throughput) 38 ns tr Rise Time 7.5 ns tf Fall Time 7.5 Microsemi Website - http://www.microsemi.com 050-4913 Rev F 12-2009 D S IN DRIVER 13A MOSFET

Symbol Parameter Min Typ Max Unit BVDSS Drain Source Voltage 1000 V ID Continuous Drain Current THS = 25°C 13 A RDS(on) Drain-Source On State Resistance 0.90 Ω Tjmax Operating Temperature 175 °C MOSFET Dynamic Characteristics Symbol Parameter Min Typ Max Unit Ciss Input Capacitance 2000 pFCoss Output Capacitance 165 Crss Reverse Transfer Capacitance 75 MOSFET Thermal Characteristics Symbol Parameter Min Typ Max Unit RθJC Thermal Resistance Junction to Case 0.095 °C/W RθJHS Thermal Resistance Junction to Heat Sink 0.25 TJSTG Storage Temperature -55 to 150 °C PDHS Maximum Power Dissipation @ TSINK = 25°C 600 W PDC Total Power Dissipation @ TC = 25°C 1580 Microsemi reserves the right to change, without notice, the specifi cations and information contained herein. 050-4913 Rev F 12-2009 Figure 1, DRF1200 Simplifi ed Circuit Diagram The Simplifi ed DRF1200 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitor (C1), the contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows optimal gate drive to the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the Anti- Ring Function, provide improved stability and control in Kilowatt to Multi-Kilowatt, high Frequency applications. Both the FN and IN pins are referenced to the Kelvin ground (SG.) The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifi cally for the ring abatement. The power drivers provide high current to the gate of the MOSFETS. Symbol Parameter Min Typ Max Unit Cout Output Capacitance 2500 pF Rout Output Resistance .8 Ω Lout Output Inductance 3 nH FMAX Operating Frequency CL = 3000nF + 50Ω 30 MHz FMAX Operating Frequency RL = 50Ω 50 Driver Output Characteristics Symbol Parameter Min Typ Max Unit RθJC Thermal Resistance Junction to Case 1.5 °C/W RθJHS Thermal Resistance Junction to Heat Sink 2.5 TJSTG Storage Temperature -55 to 150 °C PDJHS Maximum Power Dissipation @ TSINK = 25°C 60 W PDJC Total Power Dissipation @ TC = 25°C 100 Driver Thermal Characteristics

The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high. DRF1200 050-4913 Rev F 12-2009 The Test Circuit illustrated above was used to evaluate the DRF1200 (available as an evaluation Board DRF12XX / EVALSW.) The input con- trol signal is applied to the DRF1200 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal ground currents. The +V DD inputs (2,6) are by-passed (C1, C2, C4-C9), this is in addition to the internal by-passing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. RL set for IDM at VDS max this load is used to evaluate the output performance of the DRF1201. Figure 2, DRF1200 Test Circuit Truth Table *Referenced to SG FN (pin 3)* IN (pin 4)* MOSFET HIGH HIGH ON HIGH LOW OFF LOW HIGH OFF LOW LOW ON Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743, 7,352,045 5,283,201 5,801,417 5,648,283 7,196,634 6,664,594 7,157,886 6,939,743 7,342,262 and foreign patents. US and Foreign patents pending. All Rights Reserved.

Figure 3, DRF1200 Mechanical Outline All dimensions are ± .005 DRF1200 050-4913 Rev F 12-2009 Pin Assignments Pin 1 Ground Pin 2 +Vdd Pin 3 FN Pin 4 IN Pin 5 SG Pin 6 +Vdd Pin 7 Ground Pin 8 Source Pin 9 Drain Pin 10 Source