DRF100 MICROSEMI | Alldatasheet

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Technical content

15V, 8A, 30MHz The DRF100 is a High-Speed Power MOSFET driver with a unique anti-ring function. It is intended to drive the gate of a power MOSFET with ≥3nF gate capacitance to 15V at frequencies up to 30MHz. It can produce output currents ≥8A RMS, while dissipating 60W. The Driver output can be configured as Inverting or Non-Inverting. TYPICAL APPLICATIONS

  • MOSFET Drivers
  • Switch Mode Power Amplifi ers
  • Digital Output Amplifi ers
  • Pulse Generators
  • Laser Diode Drivers
  • Ultrasound Transducer Drivers
  • Acoustic Optical Modulators

FEATURES

  • Switching Frequency: DC TO 30MHz
  • Low Pulse Width Distortion
  • Single Power Supply
  • 1V CMOS Schmitt Trigger Input 1V Hysteresis
  • Inverting Non-Inverting Select
  • RoHS Compliant
  • Output Capable of ≥ 8A RMS
  • Power Dissipation Capability 60W Symbol Parameter Ratings Unit VDD Supply Voltage 18 VIN, FN Input Single Voltages -.7 to +5.5 IO PK Output Current Peak 8A TJMAX Operating Temperature 175 °C MOSFET Driver Hybrid Driver Absolute Maximum Ratings Driver Specifi cations Symbol Parameter Min Typ Max Unit VDD Supply Voltage 81 5 1 8 VIN Input Voltage 3 5.5 IN(R) Input Voltage Rising Edge 3 ns IN(F) Input Voltage Falling Edge 3 IDDQ Quiescent Current 2m A IO Output Current 8A Coss Output Capacitance 2500 pF Ciss Input Capacitance 3 RIN Input Parallel Resistance 1m Ω VT(ON) Input, Low to High Out 2.0 2.8 V VT(OFF) Input, High to Low Out 1.0 1.4 TDLY Time Delay (throughput) 25 38 ns tr Rise Time 1.5 2.5 3.0 nstf Fall Time 1.5 2.5 3.0 TD Prop. Delay 35 Microsemi Website - http://www.microsemi.com 050-4912 Rev D 4-2009 DRF100

DRF100Output Characteristics Symbol Parameter Min Typ Max Unit Cout Output Capacitance 2500 pF Rout Output Resistance 1 Ω Lout Output Inductance 2 3 4 nH FMAX Operating Frequency CL=3000nF + 50Ω 30 MHz FMAX Operating Frequency RL=50Ω 50 Dynamic Characteristics Symbol Parameter Min Typ Max Unit Ciss Input Capacitance 2000 pFCoss Output Capacitance 165 Crss Reverse Transfer Capacitance 75 Thermal Characteristics Symbol Parameter Ratings Unit RθJC Thermal Resistance Junction to Case 1.44 °C/W RθJHS Thermal Resistance Junction to Heat Sink 2.53 TJSTG Storage Temperature -55 to 150 °C PD Maximum Power Dissipation @ TSINK = 25°C 60 W PDC Total Power Dissipation @ TC = 25°C 100 Microsemi reserves the right to change, without notice, the specifi cations and information contained herein. 050-4912 Rev D 4-2009 Figure 1, DRF100 Simplifi ed Circuit Diagram The Simplifi ed DRF100 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitor (C Internal), the contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This low parasitic approach, coupled with the Schmitt trig- ger input (pin 4), Kelvin signal ground (pin 5) and the Anti-Ring Function, provide improved stability and control. The IN pin (4) is applied to a Schmitt Trigger. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifi cally for ring abatement. The P channel and N channel power drivers provide the high current to the OUTPUT (pin 9.)

The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high, Normally Non-inverting. Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. US and Foreign patents pending. All Rights Reserved. DRF100 050-4912 Rev D 4-2009 The Test Circuit illustrated above was used to evaluate the DRF100 (available as an evaluation Board DRF100 / EVALSW.) The input control signal is applied to the DRF100 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal ground currents. The +V DD inputs (2,6) are by-passed (C1, C2, C4-C9), this is in addition to the internal by-passing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. Figure 2, DRF100 Test Circuit Truth Table *Referenced to SG FN (pin 3)* IN (pin 4)* Function OUTPUT HIGH HIGH Non-Invert HIGH HIGH LOW Non-Invert LOW LOW HIGH Inverting LOW LOW LOW Inverting HIGH

Figure 3, DRF100 Mechanical Outline All dimensions are ± .005 DRF100 050-4912 Rev D 4-2009 Pin Assignments Pin 1 Ground Pin 2 U1 +Vdd Pin 3 FN Pin 4 U1 IN Pin 5 U1 SG Pin 6 U1 +Vdd Pin 7 Ground Pin 8 Source Pin 9 Drain Pin 10 Source R0.150 4P L C S Ø0.125 4P L C S 0.320 0.250 0.250 1.500 0.300 0.040 0.570 0.300 0.275 LARGE LEADS - 0.200", 2 PLCS GAPS - 0.090" , 2 PLCS 0.125 0.125 MEDIUM LEADS - 0.065", 2 PLCS SMALL LEADS - 0.040", 3 PLCS GAPS - 0.050", 6 PLCS 1 23 45 6 7 10 9 8 .005" TYP. HALF HARD COPPER GOLD PLATED DRF 100