DRF100 ADPOW | Alldatasheet

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Technical content

Specifications TYPICAL APPLICATIONS

  • MOSFET Drivers
  • Switch Mode Power Amplifiers
  • Digital Output Amplifiers
  • Pulse Generators
  • Laser Diode Drivers
  • Ultrasound Transducer Drivers
  • Acoustic Optical Modulators

FEATURES

  • Switching Frequency: DC TO 30MHz
  • Switching Speeds 3-4ns 50Ω Load
  • Low Pulse Width Distortion
  • Single Power Supply
  • 3V CMOS Schmitt Trigger Input 1V Hysteresis
  • Output Capable of ≥ 8A RMS
  • Power Dissipation Capability >100W Unit V Unit °C/W W Unit V A V ns µA A pF V ns Ratings 5.5 Min Typ Max 0.71 175 >100 210 Min Typ Max 8 18 1.8 2.2 8 1.2 200 2500 0.8 1.0 1.9 2.2 Parameter Supply Voltage Input Single Voltage Characteristic Junction to Case Thermal Resistance Operating Junction Temperature Maximum Power Dissipation Total Power Dissipation @ TC = 25°C Parameter Supply Voltage Output Current Input Voltage Input Voltage Rising Edge Input Voltage Falling Edge Quiescent Current Max Output Current Output Capacitance Input Capacitance Input Low Input High Time Delay (throughput) Symbol VDD VIN Symbol RθJC TJ PD PDC Symbol VDD IOUT VIN VIN(R) VIN(F) IDDQ IO Coss Ciss VIL VIH VDLY VDD VDD DRF100 15V, 8A, 30MHz The DRF100 is a High-Speed Power MOSFET driver with a unique anti-ring function. It is intended to drive the gate of a power MOSFET ≥3nF, gate capacitance to an 18V maximum, at frequencies up to 30MHz. It can produce output currents ≥8A RMS, while dissipating 100W. 050-4912 Rev A 2-2006APT Website - http://www.advancedpower.com

A Simplified DRF100 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitors (C1- C8), their contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This, coupled with the tight geometry of the hybrid, allows optimum drive to the gate of the MOSFET. This low parasitic approach, coupled with the Schmitt trigger input, Kelvin signal ground (4,5) and the Anti-Ring Function, provide improved stability and control in Kilowatt to Multi-Kilowatt, High Frequency applications The IN pin (4) is applied to a Schmitt Trigger. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifically for ring abatement. The P channel and N channel power drivers provide the high current to the OUT pin (9). The FUNCTION, FN, pin (3) is used to disable the Anti-Ring function. It is recommended that the device be operated Driver Control Logic In (4) HIGHDriver Output (9) LOW In (4) LOWDriver Output (9) HIGH Figure 1, DRF100 Simplified Ciruit Diagram Driver Specifications TJ = 25°C unless otherwise specified Driver Output Characteristics TJ = 25°C unless otherwise specified Test curcuit show on page 3. All measurements were made with the Anti-Ring circuit activated unless noted. 1. Symmetry is the percent difference in high and low FWHM times with a 50% duty cycle square wave input. 2 R L = 50Ω, CL = 3000pF 3 10% - 90% See Test Circuit 4 50% - 50%, see Test Circuit 5 V DD = 18V, CL = 3000pF, F = 10MHz 6 Performance specified with this input. APT reserves the right to change, without notice, the specifications and information contained herein. Unit ns Unit pF Ω nH MHz Min Typical Max 3.1 7.5 2.8 7.5 33 38 1.2 RL CL Min Typ Max 2500 2 3 4 Test Conditions 15VDD 15VDD 15V 15VDD Parameter Rise Time 2,3 Fall Time 2,3 Prop. Delay 2,4 Symmetry 1 Parameter Output Capacitance 2,5 Output Resistance 2,5 Output Inductance 2,5 Operating Frequency Symbol tr tf TD Symbol Cout Rout Lout FMAX 050-4912 Rev A 2-2006 DRF100

The Test Circuit illustrated above was used to evaluate the DRF100 (available as an evaluation Board DRF-100EVAL). The input control signal is applied to the DRF100 via the IN(4) and SG(5) pins via RG188. This provides excellent noise immunity and control of the signal ground currents. The FN pin is off and unwanted signals can cause erratic behavior, Therefore FN pin is heavily by-passed on the Evaluation board, see FN (3) above. The +Vcc inputs (2,6) are heavily By-Passed (C1-C3, C5-C7), this is in addition to the internal bypassing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the load. Figure 2, Test Circuit 050-4912 Rev A 2-2006 DRF100

Figure 21, DRF100 Mechanical Outline 050-4912 Rev A 2-2006 DRF100

+VDD By-Pass LF +VDD By-Pass HF R2 50Ω Input Termination FN Input This Section Configured by User Figure 22, DRF100 Eval Board The DFR100 is a high power device and must have adequate cooling for full power operation Evaluation Boards are provided to facilitate the circuit design process by allowing the end user to quickly evaluate the performance of our components under a specific and single set of conditions. They are not intended to be used as a sub assembly in any final product(s). Care has been taken to insure that the Evaluation Boards are assembled to correctly represent the test circuit included in the component data sheet. There is no warranty of these Evaluation Boards beyond workmanship and materials. 050-4912 Rev A 2-2006 DRF100

4.936 5.25 3.196 1.425 .716 1.7 0.900 Advanced Power Technology DRF100 RE 12/06/05 revD 3.50 See DRF100 mechanical drawing for physical dimension details PCB material - .062 FR4 4 holes .150 dia. Figure 23, DRF100 Eval Board Mechanical 050-4912 Rev A 2-2006 DRF100