DRA829VMTGCALFRQ1

DRA829J_V05 TI | Alldatasheet

Document overview

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• PDF pages: 328

Technical content

1 Features

Processor cores:

• Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz – 1MB shared L2 cache per dual-core Arm® Cortex®-A72 cluster – 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core
• Six Arm® Cortex®-R5F MCUs at up to 1.0GHz – 16K I-Cache, 16K D-Cache, 64K L2 TCM – Two Arm® Cortex®-R5F MCUs in isolated MCU subsystem – Four Arm® Cortex®-R5F MCUs in general compute partition
• Deep-learning Matrix Multiply Accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
• C7x floating point, vector DSP, up to 1.0 GHz,

80 GFLOPS, 256 GOPS

• Two C66x floating point DSP, up to 1.35 GHz,

40 GFLOPS, 160 GOPS

• 3D GPU PowerVR® Rogue 8XE GE8430, up to

750 MHz, 96 GFLOPS, 6 Gpix/sec

Memory subsystem:

• Up to 8MB of on-chip L3 RAM with ECC and coherency – ECC error protection – Shared coherent cache – Supports internal DMA engine
• External Memory Interface (EMIF) module with ECC – Supports LPDDR4 memory types – Supports speeds up to 4266 MT/s – 32-bit data bus with inline ECC up to 14.9GB/s
• General-Purpose Memory Controller (GPMC)
• 512KB on-chip SRAM in MAIN domain, protected by ECC Display subsystem:
• One eDP/DP interface with Multi-Display Support (MST) – HDCP1.4/HDCP2.2 high-bandwidth digital content protection
• One DSI TX (up to 2.5K)
• Up to two DPI Video acceleration:
• Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
• Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
• Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode Functional Safety:
• Functional Safety-Compliant targeted (on select part numbers) – Developed for functional safety applications – Documentation available to aid ISO 26262/IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted – Systematic capability up to ASIL-D/SC-3 targeted – Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain – Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain – Safety-related certification
• ISO 26262 certification up to ASIL-D by TÜV SÜD planned
• IEC 61508 certification up to SIL-3 by TÜV SÜD planned
• AEC-Q100 qualified on part number variants ending in Q1
• Device security (on select part numbers):
• Secure boot with secure run-time support
• Customer programmable root key, up to RSA-4K or ECC-512
• Embedded hardware security module
• Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES High speed serial interfaces:
• Two CSI2.0 4L RX plus one CSI2.0 4L TX
• Integrated Ethernet switch supporting up to 8 external ports – All ports support 2.5Gb SGMII – All ports support 1Gb SGMII/RGMII – All ports support 100Mb RMII – Any two ports support QSGMII (using 4 internal ports per QSGMII)
• Up to four PCI-Express® (PCIe) Gen3 controllers – Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation – Up to two lanes per controller
• Two USB 3.0 dual-role device (DRD) subsystem – Two enhanced SuperSpeed Gen1 ports – Each port supports Type-C switching – Each port independently configurable as USB host, USB peripheral, or USB DRD Automotive interfaces:
• Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Audio interfaces:

• Twelve Multichannel Audio Serial Port (MCASP) modules Flash memory interfaces:
• Embedded MultiMediaCard interface ( eMMC™ 5.1)
• Universal Flash Storage (UFS 2.1) interface with two lanes
• Two Secure Digital® 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
• Two simultaneous flash interfaces configured as – One OSPI and one QSPI flash interfaces – or one HyperBus™ and one QSPI flash interface System-on-Chip (SoC) architecture:
• 16-nm FinFET technology
• 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing TPS6594-Q1 Companion Power Management ICs (PMIC):
• Functional Safety support up to ASIL-D
• Flexible mapping to support different use cases

2 Applications

• Automotive gateway
• Body control module
• Industrial transport
• Industrial robot
• High-end PLC

3 Description

DRA829 processors, based on the Arm ®v8 64-bit architecture, provide advanced system integration to enable lower system costs of automotive and industrial applications. The integrated diagnostics and functional safety features are targeted to ASIL-B/C or SIL-2 certification/requirements. The integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features a Gigabit Ethernet switch and a PCIe® hub which enables networking use cases that require heavy data bandwidth. Up to four Arm® Cortex®-R5F subsystems manage low level, timing critical processing tasks leaving the Arm® Cortex®-A72’s unencumbered for applications. A dual-core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor.

Package Information

PART NUMBER(1) PACKAGE PACKAGE SIZE(2) DRA829…ALF ALF (FCBGA, 827) 24.0mm × 24.0mm XJ721E…ALF ALF (FCBGA, 827) 24.0mm × 24.0mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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3.1 Functional Block Diagram

Figure 3-1 is functional block diagram for the device. Note To understand what device features are currently supported by TI Software Development Kits (SDKs), see the DRA829 and TDA4VM Software Build Sheet (PROCESSOR-SDK-J721E). C7x DSP w/ MMA Navigator Subsystem Memory Subsystem 8MB SRAM with ECC MSMC System Services Spinlock GP Timers Mailboxes Capture Subsystem CSI2 4L TX

2 CSI2 4L RX×

10 GP Timers×

2 WWDT×SA2UL

Control InterfacesMedia and Data Storage General Connectivity High-Speed Serial Interfaces eMMC Audio Peripherals

12 MCASP×

3 eQEP× 3 eCAP× 6 eHRPWM× 10/100/1000 Ethernet(A) DRA829

4 PCIe 2-Lane Ports×

(B)® intro_001 (with optional Lockstep)

2 Arm× ®

Cortex -R5F® 64K L2 RAM per Core Dual Arm® Cortex -A72®

4 Arm× ®

Cortex -R5F® GPMC EMIF 32 LPDDR4 w/ECC-bitELM 512KB SRAM Display Subsystem 4K Blend Scale Convert DSI DP/eDP(B) UDMA WWDT SMMU

1 MB SRAM

TIMER_MGR PVU INTR SecProxy MCRC INTA UDMA Proxy/RA Spinlock SMMUPAT Ethernet Subsystem (Supporting up to 4 external ports) Integrated Ethernet Switch (B) Security Accelerators AES SHA RNG DES PKA 3DES Video Acceleration (H.264 Encode and H.264/H.265 Decode) C66x DSP 3D GPU PowerVR Rogue 8XE GE8430

2 SD/SDIO×

3× I2C 7× I2C 8× GPIO 8 MCSPI×

3 MCSPI×

2 ADC×

1 UART0×

(A)

2 UART×

(A) (A)1 OSPI or×

1 HyperBus× (A)(C)

(A)(C)

1 QSPI×

2 I3C×

(A) I3C 2 USB 3.0 DRD× (B) Automotive Interfaces

2 CAN-FD×

(A)

14 CAN-FD×

(Up to 8-ports) QSGMII/SGMII/RGMII/RMII 1MB Shared L2 Cache with ECC (B) Debug

2 WKUP GPIO×

(A) (A) A. This interface is located on the MCU Island but is available for the full system to access. B. DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

C. Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus™ and OSPI1. Figure 3-1. Functional Block Diagram DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.7 VPP Specifications for One-Time Programmable

8.3 Peripheral- and Interface-Specific Design

11 Mechanical, Packaging, and Orderable

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4 Device Comparison

Table 4-1 shows the features of the SoC, highlighting the differences. Note To understand what device features are currently supported by TI Software Development Kits (SDKs), see the DRA829 and TDA4VM Software Build Sheet (PROCESSOR-SDK-J721E). Table 4-1. Device Comparison FEATURES(6) REFERENCE NAME DRA829JM DRA829VM

Features

PROCESSORS AND ACCELERATORS Speed Grades T T Arm Cortex-A72 Microprocessor Subsystem Arm A72 Dual Core Dual Core Arm Cortex-R5F Arm R5F Hexa Core Hexa Core Lockstep Optional (1) Optional (1) Device Management Security Controller DMSC Yes Yes C7x Floating Point, Vector DSP C7x DSP Yes No Deep Learning Accelerator MMA Yes No Two C66x Floating Point DSP C66x DSP Dual Core No Graphics Accelerator 3D GPU PowerVR Rogue 8XE GE8430 GPU Yes No Depth and Motion Processing Accelerators DMPAC No No Vision Processing Accelerators VPAC No No Security Accelerators SA Yes Yes Video Encoder / Decoder VENC/ VDEC Yes No SAFETY AND SECURITY Safety Targeted Safety Optional(1) Optional(1) Device Security Security Optional(2) Optional(2) AEC-Q100 Qualified Q1 Optional(3) Optional(3) PROGRAM AND DATA STORAGE On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM 512KB SRAM 512KB SRAM On-Chip Shared Memory (RAM) in MCU Domain MCU_MSRAM 1MB SRAM 1MB SRAM Multicore Shared Memory Controller MSMC 8MB (On-Chip SRAM with ECC) 8MB (On-Chip SRAM with ECC) LPDDR4 DDR Subsystem DDRSS Up to 8GB (32-bit data) with inline ECC Up to 8GB (32-bit data) with inline ECC SECDED 7-Bit 7-Bit General-Purpose Memory Controller GPMC Up to 1GB with ECC Up to 1GB with ECC PERIPHERALS Display Subsystem DSS Yes Yes Modular Controller Area Network Interface with Full CAN- FD Support MCAN 16 16 General-Purpose I/O GPIO Up to 226 Up to 226 Inter-Integrated Circuit Interface I2C 10 10 Improved Inter-Integrated Circuit Interface I3C 3 3 Analog-to-Digital Converter ADC 2 2 Capture Subsystem with Camera Serial Interface (CSI2) CSI2.0 4L RX 2 2 CSI2.0 4L TX 1 1 Multichannel Serial Peripheral Interface MCSPI 11 11 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 4-1. Device Comparison (continued) FEATURES(6) REFERENCE NAME DRA829JM DRA829VM Multichannel Audio Serial Port MCASP0 16 Serializers 16 Serializers MCASP1 12 Serializers 12 Serializers MCASP2 6 Serializers 6 Serializers MCASP3 4 Serializers 4 Serializers MCASP4 4 Serializers 4 Serializers MCASP5 4 Serializers 4 Serializers MCASP6 4 Serializers 4 Serializers MCASP7 4 Serializers 4 Serializers MCASP8 4 Serializers 4 Serializers MCASP9 4 Serializers 4 Serializers MCASP10 8 Serializers 8 Serializers MCASP11 8 Serializers 8 Serializers MultiMedia Card/ Secure Digital Interface MMCSD0 eMMC (8-bits) eMMC (8-bits) MMCSD1 SD/SDIO (4-bits) SD/SDIO (4-bits) MMCSD2 SD/SDIO (4-bits) SD/SDIO (4-bits) Universal Flash Storage UFS 2L Yes (2 Lanes) Yes (2 Lanes) Flash Subsystem (FSS) OSPI0 8-bits (5) 8-bits (5) OSPI1 (7) 4-bits 4-bits HyperBus Yes (5) Yes (5) 4x PCI Express Port with Integrated PHY PCIE0 Up to Two Lanes (4) Up to Two Lanes (4) PCIE1 Up to Two Lanes (4) Up to Two Lanes (4) PCIE2 Up to Two Lanes (4) Up to Two Lanes (4) PCIE3 Up to Two Lanes (4) Up to Two Lanes (4) 2x Programmable Real-Time Unit Subsystem and TSN Communication Subsystem (Ethernet Subsystem) PRU_ICSSG0 No No PRU_ICSSG1 No No Gigabit Ethernet Interface CPSW2G RMII or RGMII RMII or RGMII CPSW9G 8 × RMII 8 × RGMII 8 × SGMII(4) 8 × RMII 8 × RGMII 8 × SGMII(4) General-Purpose Timers TIMER 30 30 Enhanced High Resolution Pulse-Width Modulator Module eHRPWM 6 6 Enhanced Capture Module eCAP 3 3 Enhanced Quadrature Encoder Pulse Module eQEP 3 3 Universal Asynchronous Receiver and Transmitter UART 12 12 Universal Serial Bus (USB3.1) SuperSpeed Dual-Role- Device (DRD) Ports with SS PHY USB0 Yes(4) Yes(4) USB1 Yes(4) Yes(4) (1) Safety features including R5F Lockstep and SIL/ASIL ratings are only applicable to select part number variants as indicated by the Device Type (Y) identifier in the Table 9-1, Nomenclature Description table. (2) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as indicated by the Device Type (Y) identifier in the Table 9-1, Nomenclature Description table. (3) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Table 9-1, Nomenclature Description table. (4) DP, SGMII, USB3.0, and PCIE[3:0] share total of twelve SerDes lanes. (5) Two simultaneous flash interfaces configured as OSPI0 and OSPI1, or HyperBus and OSPI1. (6) Software should constrain the features used to match the intended production device. (7) OSPI1 module only pins out 4 pins and is referred to as QSPI in some contexts. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

4.1 Related Products

Companion Products for DRA829 Review products that are frequently purchased or used in conjunction with this product to complete your design. Software Development Kit for DRA8x & TDA4x Jacinto ™ Processors Processor SDK RTOS (PSDK RTOS) can be used together with Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX), to form a multi-processor software development platform for TDA4x and DRA8x SoCs within the TI’s Jacinto™ Processors platform. The SDK provides a comprehensive set of software tools and components to help users develop and deploy their applications on supported J7 SoCs. PSDK RTOS and either PSDK Linux or PSDK QNX can be used together to implement various use-cases in robotics, vision, factory and building automation, and automotive ADAS and gateway systems. DRA829 Evaluation Module The DRA829 evaluation module (EVM) platform is based on the Jacinto ™ DRA829J, V and is designed to speed up development efforts and reduce time to market for automotive gateway and vehicle compute systems. The integrated diagnostics and functional safety features are targeted to ASIL-D/SIL-3 certification/requirements. The integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features Gigabit Ethernet ports with integrated switch to meet networking use cases that require heavy data bandwidth and also includes PCIe hub functionality. CAN-FD and up to UART interfaces are available on the device. General purpose Arm ® Cortex®-R5F subsystems can handle low level, timing critical processing tasks and leave the Arm® Cortex®-A72’s unencumbered for advanced applications. This EVM kit features the main CPU board and an Ethernet expansion board option for additional gigabit Ethernet ports in order to jump start evaluation and development. Application Notes and White Paper Gateway & vehicle compute application processor. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5 Terminal Configuration and Functions

5.1 Pin Diagram

The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt is made to use "ball" only when referring to the physical package. Figure 5-1 shows the ball locations for the 827-ball flip chip ball grid array (FCBGA) package that are used in conjunction with Table 5-1 through Figure 5-1 to locate signal names and ball grid numbers. C E G J L N R U W AA AC D F H K M P T V Y AB AD A B AE AG AF AH AJ Figure 5-1. ALF FCBGA-N827 Pin Diagram (Bottom View) www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.2 Pin Attributes

MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT. Note Media Local Bus (MLB) is not available on this device. The following balls must be left unconnected if not used in GPIO mode: AE2, AD2, AD3, AC3, AC1, AD1. Note PRU_ICSSG0 and PRU_ICSSG1 are not available on this device. The prg* signals should not be used. Those pins can be used for other functions. Table 5-1. Pin Attributes BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE

4 TYPE 5

REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 U7 CAP_VDDS0 CAP_VDDS0 CAP K23 CAP_VDDS0_MCU CAP_VDDS0_MCU CAP AB21 CAP_VDDS1 CAP_VDDS1 CAP J18 CAP_VDDS1_MCU CAP_VDDS1_MCU CAP Y18 CAP_VDDS2 CAP_VDDS2 CAP J19 CAP_VDDS2_MCU CAP_VDDS2_MCU CAP W21 CAP_VDDS3 CAP_VDDS3 CAP AA22 CAP_VDDS4 CAP_VDDS4 CAP R22 CAP_VDDS5 CAP_VDDS5 CAP V22 CAP_VDDS6 CAP_VDDS6 CAP B20 CSI0_RXCLKN CSI0_RXCLKN I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY A21 CSI0_RXCLKP CSI0_RXCLKP I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY F16 csi0_rxrcalib CSI0_RXRCALIB A OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 F15 csi1_rxrcalib CSI1_RXRCALIB A OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY B17 CSI1_RXCLKN CSI1_RXCLKN I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY A18 CSI1_RXCLKP CSI1_RXCLKP I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY B19 CSI0_RXN0 CSI0_RXN0 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY D18 CSI0_RXN1 CSI0_RXN1 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY D17 CSI0_RXN2 CSI0_RXN2 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY E16 CSI0_RXN3 CSI0_RXN3 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY A20 CSI0_RXP0 CSI0_RXP0 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY C19 CSI0_RXP1 CSI0_RXP1 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY C18 CSI0_RXP2 CSI0_RXP2 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY E17 CSI0_RXP3 CSI0_RXP3 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY B16 CSI1_RXN0 CSI1_RXN0 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY D15 CSI1_RXN1 CSI1_RXN1 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 D14 CSI1_RXN2 CSI1_RXN2 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY E13 CSI1_RXN3 CSI1_RXN3 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY A17 CSI1_RXP0 CSI1_RXP0 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY C16 CSI1_RXP1 CSI1_RXP1 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY C15 CSI1_RXP2 CSI1_RXP2 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY E14 CSI1_RXP3 CSI1_RXP3 I OFF 1.8 V VDDA_0P8_CSI RX / VDDA_1P8_CSI RX D-PHY J1 ddr0_ckn DDR0_CKN IO OFF 1.1 V VDDS_DDR DDR0 H1 ddr0_ckp DDR0_CKP IO OFF 1.1 V VDDS_DDR DDR0 K6 ddr0_resetn DDR0_RESETn IO OFF 1.1 V VDDS_DDR DDR0 G4 ddr0_ca0 DDR0_CA0 IO OFF 1.1 V VDDS_DDR DDR0 H3 ddr0_ca1 DDR0_CA1 IO OFF 1.1 V VDDS_DDR DDR0 K5 ddr0_ca2 DDR0_CA2 IO OFF 1.1 V VDDS_DDR DDR0 J4 ddr0_ca3 DDR0_CA3 IO OFF 1.1 V VDDS_DDR DDR0 K2 ddr0_ca4 DDR0_CA4 IO OFF 1.1 V VDDS_DDR DDR0 H5 ddr0_ca5 DDR0_CA5 IO OFF 1.1 V VDDS_DDR DDR0 H2 ddr0_cal0 DDR0_CAL0 A OFF 1.1 V VDDS_DDR DDR0 G3 ddr0_cke0 DDR0_CKE0 IO OFF 1.1 V VDDS_DDR DDR0 J3 ddr0_cke1 DDR0_CKE1 IO OFF 1.1 V VDDS_DDR DDR0 J5 ddr0_csn0_0 DDR0_CSn0_0 IO OFF 1.1 V VDDS_DDR DDR0 K3 ddr0_csn0_1 DDR0_CSn0_1 IO OFF 1.1 V VDDS_DDR DDR0 G5 ddr0_csn1_0 DDR0_CSn1_0 IO OFF 1.1 V VDDS_DDR DDR0 J2 ddr0_csn1_1 DDR0_CSn1_1 IO OFF 1.1 V VDDS_DDR DDR0 A3 ddr0_dm0 DDR0_DM0 IO OFF 1.1 V VDDS_DDR DDR0 E4 ddr0_dm1 DDR0_DM1 IO OFF 1.1 V VDDS_DDR DDR0 N1 ddr0_dm2 DDR0_DM2 IO OFF 1.1 V VDDS_DDR DDR0 R5 ddr0_dm3 DDR0_DM3 IO OFF 1.1 V VDDS_DDR DDR0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 A5 ddr0_dq0 DDR0_DQ0 IO OFF 1.1 V VDDS_DDR DDR0 A6 ddr0_dq1 DDR0_DQ1 IO OFF 1.1 V VDDS_DDR DDR0 B5 ddr0_dq2 DDR0_DQ2 IO OFF 1.1 V VDDS_DDR DDR0 C2 ddr0_dq3 DDR0_DQ3 IO OFF 1.1 V VDDS_DDR DDR0 B4 ddr0_dq4 DDR0_DQ4 IO OFF 1.1 V VDDS_DDR DDR0 C3 ddr0_dq5 DDR0_DQ5 IO OFF 1.1 V VDDS_DDR DDR0 A2 ddr0_dq6 DDR0_DQ6 IO OFF 1.1 V VDDS_DDR DDR0 A4 ddr0_dq7 DDR0_DQ7 IO OFF 1.1 V VDDS_DDR DDR0 D1 ddr0_dq8 DDR0_DQ8 IO OFF 1.1 V VDDS_DDR DDR0 C4 ddr0_dq9 DDR0_DQ9 IO OFF 1.1 V VDDS_DDR DDR0 F1 ddr0_dq10 DDR0_DQ10 IO OFF 1.1 V VDDS_DDR DDR0 G2 ddr0_dq11 DDR0_DQ11 IO OFF 1.1 V VDDS_DDR DDR0 F2 ddr0_dq12 DDR0_DQ12 IO OFF 1.1 V VDDS_DDR DDR0 F3 ddr0_dq13 DDR0_DQ13 IO OFF 1.1 V VDDS_DDR DDR0 D3 ddr0_dq14 DDR0_DQ14 IO OFF 1.1 V VDDS_DDR DDR0 F5 ddr0_dq15 DDR0_DQ15 IO OFF 1.1 V VDDS_DDR DDR0 L5 ddr0_dq16 DDR0_DQ16 IO OFF 1.1 V VDDS_DDR DDR0 M5 ddr0_dq17 DDR0_DQ17 IO OFF 1.1 V VDDS_DDR DDR0 N5 ddr0_dq18 DDR0_DQ18 IO OFF 1.1 V VDDS_DDR DDR0 L4 ddr0_dq19 DDR0_DQ19 IO OFF 1.1 V VDDS_DDR DDR0 L2 ddr0_dq20 DDR0_DQ20 IO OFF 1.1 V VDDS_DDR DDR0 L1 ddr0_dq21 DDR0_DQ21 IO OFF 1.1 V VDDS_DDR DDR0 N2 ddr0_dq22 DDR0_DQ22 IO OFF 1.1 V VDDS_DDR DDR0 N4 ddr0_dq23 DDR0_DQ23 IO OFF 1.1 V VDDS_DDR DDR0 T3 ddr0_dq24 DDR0_DQ24 IO OFF 1.1 V VDDS_DDR DDR0 T2 ddr0_dq25 DDR0_DQ25 IO OFF 1.1 V VDDS_DDR DDR0 P2 ddr0_dq26 DDR0_DQ26 IO OFF 1.1 V VDDS_DDR DDR0 P3 ddr0_dq27 DDR0_DQ27 IO OFF 1.1 V VDDS_DDR DDR0 P5 ddr0_dq28 DDR0_DQ28 IO OFF 1.1 V VDDS_DDR DDR0 R4 ddr0_dq29 DDR0_DQ29 IO OFF 1.1 V VDDS_DDR DDR0 T4 ddr0_dq30 DDR0_DQ30 IO OFF 1.1 V VDDS_DDR DDR0 T5 ddr0_dq31 DDR0_DQ31 IO OFF 1.1 V VDDS_DDR DDR0 B1 ddr0_dqs0n DDR0_DQS0N IO OFF 1.1 V VDDS_DDR DDR0 B2 ddr0_dqs0p DDR0_DQS0P IO OFF 1.1 V VDDS_DDR DDR0 E2 ddr0_dqs1n DDR0_DQS1N IO OFF 1.1 V VDDS_DDR DDR0 E3 ddr0_dqs1p DDR0_DQS1P IO OFF 1.1 V VDDS_DDR DDR0 M2 ddr0_dqs2n DDR0_DQS2N IO OFF 1.1 V VDDS_DDR DDR0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 M3 ddr0_dqs2p DDR0_DQS2P IO OFF 1.1 V VDDS_DDR DDR0 R1 ddr0_dqs3n DDR0_DQS3N IO OFF 1.1 V VDDS_DDR DDR0 R2 ddr0_dqs3p DDR0_DQS3P IO OFF 1.1 V VDDS_DDR DDR0 P6 ddr_ret DDR_RET I OFF 1.1 V VDDS_DDR_BI AS DDR0 G6 dp0_auxn DP0_AUXN IO OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP AUX-PHY F7 dp0_auxp DP0_AUXP IO OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP AUX-PHY E10 DSI_TXCLKN DSI_TXCLKN O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXCLKN O E11 DSI_TXCLKP DSI_TXCLKP O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXCLKP O D11 DSI_TXN0 DSI_TXN0 IO OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXN0 O D12 DSI_TXN1 DSI_TXN1 O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXN1 O B13 DSI_TXN2 DSI_TXN2 O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXN2 O B14 DSI_TXN3 DSI_TXN3 O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXN3 O C12 DSI_TXP0 DSI_TXP0 IO OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXP0 O C13 DSI_TXP1 DSI_TXP1 O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXP1 O A14 DSI_TXP2 DSI_TXP2 O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXP2 O A15 DSI_TXP3 DSI_TXP3 O OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY CSI0_TXP3 O DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 F12 dsi_txrcalib DSI_TXRCALIB A OFF 1.8 V VDDA_0P8_DSI TX / VDDA_1P8_DSI TX D-PHY U2 ecap0_in_apwm_out ECAP0_IN_APWM_OUT 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 SYNC0_OUT 1 O CPTS0_RFT_CLK 2 I 0 SPI2_CS3 4 IO 1 I3C0_SDAPULLEN 5 O SPI7_CS0 6 IO 1 GPIO1_11 7 IO 0 C26 emu0 EMU0 0 IO PU 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 B29 emu1 EMU1 0 IO PU 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 AC18 extintn EXTINTn 0 I OFF 7 1.8 V/3.3 V VDDSHV2 Yes I2C OD FS 1 0/0 GPIO0_0 7 IO 0 U3 ext_refclk1 EXT_REFCLK1 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 SYNC1_OUT 1 O SPI7_CLK 6 IO 0 GPIO1_12 7 IO 0 AC5 i2c0_scl I2C0_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0 GPIO1_7 7 IO 0 AA5 i2c0_sda I2C0_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0 GPIO1_8 7 IO 0 Y6 i2c1_scl I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0 CPTS0_HW1TSPUSH 1 I 0 GPIO1_9 7 IO 0 AA6 i2c1_sda I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0 Yes I2C OD FS 1 1/0 CPTS0_HW2TSPUSH 1 I 0 GPIO1_10 7 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 W2 i3c0_scl I3C0_SCL 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 MMC2_SDCD 1 I 1 UART9_CTSn 2 I 1 MCAN2_RX 3 I 1 I2C6_SCL 4 IOD 1 DP0_HPD 5 I 0 PCIE0_CLKREQn 6 IO 0 GPIO1_5 7 IO 0 UART6_RXD 8 I 0 W1 i3c0_sda I3C0_SDA 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 MMC2_SDWP 1 I 1 UART9_RTSn 2 O MCAN2_TX 3 O I2C6_SDA 4 IOD 1 PCIE1_CLKREQn 6 IO 0 GPIO1_6 7 IO 0 UART6_TXD 8 O 0 W5 mcan0_rx MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 I2C2_SCL 4 IOD 1 GPIO1_1 7 IO 0 W6 mcan0_tx MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 I2C2_SDA 4 IOD 1 GPIO1_2 7 IO 0 W3 mcan1_rx MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 UART6_CTSn 1 I 1 UART9_RXD 2 I 1 USB0_DRVVBUS 3 O USB1_DRVVBUS 4 O GPIO1_3 7 IO 0 V4 mcan1_tx MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 UART6_RTSn 1 O UART9_TXD 2 O USB0_DRVVBUS 3 O USB1_DRVVBUS 4 O GPIO1_4 7 IO 0 K25 mcu_adc0_ain0 MCU_ADC0_AIN0 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_68 -1 I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 K26 mcu_adc0_ain1 MCU_ADC0_AIN1 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_69 -1 I K28 mcu_adc0_ain2 MCU_ADC0_AIN2 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_70 -1 I L28 mcu_adc0_ain3 MCU_ADC0_AIN3 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_71 -1 I K24 mcu_adc0_ain4 MCU_ADC0_AIN4 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_72 -1 I K27 mcu_adc0_ain5 MCU_ADC0_AIN5 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_73 -1 I K29 mcu_adc0_ain6 MCU_ADC0_AIN6 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_74 -1 I L29 mcu_adc0_ain7 MCU_ADC0_AIN7 0 A OFF 0 1.8 V VDDA_ADC0 ADC12B WKUP_GPIO0_75 -1 I N23 mcu_adc1_ain0 MCU_ADC1_AIN0 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_76 -1 I M25 mcu_adc1_ain1 MCU_ADC1_AIN1 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_77 -1 I L24 mcu_adc1_ain2 MCU_ADC1_AIN2 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_78 -1 I L26 mcu_adc1_ain3 MCU_ADC1_AIN3 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_79 -1 I N24 mcu_adc1_ain4 MCU_ADC1_AIN4 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_80 -1 I M24 mcu_adc1_ain5 MCU_ADC1_AIN5 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_81 -1 I L25 mcu_adc1_ain6 MCU_ADC1_AIN6 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_82 -1 I L27 mcu_adc1_ain7 MCU_ADC1_AIN7 0 A OFF 0 1.8 V VDDA_ADC1 ADC12B WKUP_GPIO0_83 -1 I J26 mcu_i2c0_scl MCU_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes I2C OD FS 1 1/0 WKUP_GPIO0_64 7 IO 0 H25 mcu_i2c0_sda MCU_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes I2C OD FS 1 1/0 WKUP_GPIO0_65 7 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 D26 mcu_i3c0_scl MCU_I3C0_SCL 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_UART0_CTSn 2 I 1 MCU_TIMER_IO8 4 IO 0 WKUP_GPIO0_60 7 IO 0 D25 mcu_i3c0_sda MCU_I3C0_SDA 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_UART0_RTSn 2 O MCU_TIMER_IO9 4 IO 0 WKUP_GPIO0_61 7 IO 0 C29 mcu_mcan0_rx MCU_MCAN0_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_59 7 IO 0 D29 mcu_mcan0_tx MCU_MCAN0_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_58 7 IO 0 F23 mcu_mdio0_mdc MCU_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_51 7 IO 0 E23 mcu_mdio0_mdio MCU_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_50 7 IO 0 E20 mcu_ospi0_clk MCU_OSPI0_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_CK 1 O WKUP_GPIO0_16 7 IO 0 D21 mcu_ospi0_dqs MCU_OSPI0_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_RWDS 1 IO 0 WKUP_GPIO0_18 7 IO 0 C21 mcu_ospi0_lbclko MCU_OSPI0_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 1/1 MCU_HYPERBUS0_CKn 1 O WKUP_GPIO0_17 7 IO 0 F22 mcu_ospi1_clk MCU_OSPI1_CLK 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_29 7 IO 0 B23 mcu_ospi1_dqs MCU_OSPI1_DQS 0 I OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_OSPI0_CSn3 1 O MCU_HYPERBUS0_INTn 2 I 1 MCU_OSPI0_ECC_FAIL 6 I 1 WKUP_GPIO0_31 7 IO 0 A23 mcu_ospi1_lbclko MCU_OSPI1_LBCLKO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 1/1 MCU_OSPI0_CSn2 1 O MCU_HYPERBUS0_RESETOn 2 I 1 MCU_OSPI0_RESET_OUT0 6 O WKUP_GPIO0_30 7 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 F19 mcu_ospi0_csn0 MCU_OSPI0_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_CSn0 1 O WKUP_GPIO0_27 7 IO 0 E19 mcu_ospi0_csn1 MCU_OSPI0_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_RESETn 1 O WKUP_GPIO0_28 7 IO 0 D20 mcu_ospi0_d0 MCU_OSPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ0 1 IO 0 WKUP_GPIO0_19 7 IO 0 G19 mcu_ospi0_d1 MCU_OSPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ1 1 IO 0 WKUP_GPIO0_20 7 IO 0 G20 mcu_ospi0_d2 MCU_OSPI0_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ2 1 IO 0 WKUP_GPIO0_21 7 IO 0 F20 mcu_ospi0_d3 MCU_OSPI0_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ3 1 IO 0 WKUP_GPIO0_22 7 IO 0 F21 mcu_ospi0_d4 MCU_OSPI0_D4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ4 1 IO 0 WKUP_GPIO0_23 7 IO 0 E21 mcu_ospi0_d5 MCU_OSPI0_D5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ5 1 IO 0 WKUP_GPIO0_24 7 IO 0 B22 mcu_ospi0_d6 MCU_OSPI0_D6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ6 1 IO 0 WKUP_GPIO0_25 7 IO 0 G21 mcu_ospi0_d7 MCU_OSPI0_D7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_HYPERBUS0_DQ7 1 IO 0 WKUP_GPIO0_26 7 IO 0 C22 mcu_ospi1_csn0 MCU_OSPI1_CSn0 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_36 7 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 E22 mcu_ospi1_csn1 MCU_OSPI1_CSn1 0 O OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0/1 MCU_HYPERBUS0_WPn 1 O MCU_TIMER_IO0 2 IO 0 MCU_HYPERBUS0_CSn1 3 O MCU_UART0_RTSn 4 O MCU_SPI0_CS2 5 IO 1 MCU_OSPI0_RESET_OUT1 6 O WKUP_GPIO0_37 7 IO 0 D22 mcu_ospi1_d0 MCU_OSPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 WKUP_GPIO0_32 7 IO 0 G22 mcu_ospi1_d1 MCU_OSPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_UART0_RXD 4 I 1 MCU_SPI1_CS1 5 IO 1 WKUP_GPIO0_33 7 IO 0 D23 mcu_ospi1_d2 MCU_OSPI1_D2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_UART0_TXD 4 O MCU_SPI1_CS2 5 IO 1 WKUP_GPIO0_34 7 IO 0 C23 mcu_ospi1_d3 MCU_OSPI1_D3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1_MC U Yes LVCMOS PU/PD 0 0/1 MCU_UART0_CTSn 4 I 1 MCU_SPI0_CS1 5 IO 1 WKUP_GPIO0_35 7 IO 0 H23 mcu_porz MCU_PORz I OFF 1.8 V VDDA_WKUP Yes FS Reset PU/PD B28 mcu_porz_out MCU_PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/0 C27 mcu_resetstatz MCU_RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/0 D28 mcu_resetz MCU_RESETz 0 I PU 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 C24 mcu_rgmii1_rxc MCU_RGMII1_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_REF_CLK 1 I 0 WKUP_GPIO0_45 7 IO 0 C25 mcu_rgmii1_rx_ctl MCU_RGMII1_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_RX_ER 1 I 0 WKUP_GPIO0_39 7 IO 0 B26 mcu_rgmii1_txc MCU_RGMII1_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_TX_EN 1 O WKUP_GPIO0_44 7 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 B27 mcu_rgmii1_tx_ctl MCU_RGMII1_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0/1 MCU_RMII1_CRS_DV 1 I 0 WKUP_GPIO0_38 7 IO 0 B24 mcu_rgmii1_rd0 MCU_RGMII1_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_RXD0 1 I 0 WKUP_GPIO0_49 7 IO 0 A24 mcu_rgmii1_rd1 MCU_RGMII1_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_RMII1_RXD1 1 I 0 WKUP_GPIO0_48 7 IO 0 D24 mcu_rgmii1_rd2 MCU_RGMII1_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_TIMER_IO5 1 IO 0 WKUP_GPIO0_47 7 IO 0 A25 mcu_rgmii1_rd3 MCU_RGMII1_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0 0/1 MCU_TIMER_IO4 1 IO 0 WKUP_GPIO0_46 7 IO 0 B25 mcu_rgmii1_td0 MCU_RGMII1_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0/1 MCU_RMII1_TXD0 1 O WKUP_GPIO0_43 7 IO 0 A26 mcu_rgmii1_td1 MCU_RGMII1_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0/1 MCU_RMII1_TXD1 1 O WKUP_GPIO0_42 7 IO 0 A27 mcu_rgmii1_td2 MCU_RGMII1_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0/1 MCU_TIMER_IO3 1 IO 0 MCU_ADC_EXT_TRIGGER1 3 I 0 WKUP_GPIO0_41 7 IO 0 A28 mcu_rgmii1_td3 MCU_RGMII1_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV2_MC U Yes LVCMOS PU/PD 0/1 MCU_TIMER_IO2 1 IO 0 MCU_ADC_EXT_TRIGGER0 3 I 0 WKUP_GPIO0_40 7 IO 0 D27 mcu_safety_errorn MCU_SAFETY_ERRORn 0 IO PD 0 1.8 V VDDA_WKUP Yes LVCMOS PU/PD 1/0 E27 mcu_spi0_clk MCU_SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 1/1 WKUP_GPIO0_52 7 IO 0 MCU_BOOTMODE00 Bootstrap I E25 mcu_spi0_cs0 MCU_SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_TIMER_IO1 4 IO 0 WKUP_GPIO0_55 7 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 E24 mcu_spi0_d0 MCU_SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 1/1 WKUP_GPIO0_53 7 IO 0 MCU_BOOTMODE01 Bootstrap I E28 mcu_spi0_d1 MCU_SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 1/1 MCU_TIMER_IO0 4 IO 0 WKUP_GPIO0_54 7 IO 0 MCU_BOOTMODE02 Bootstrap I V24 mdio0_mdc MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1 TRC_DATA23 5 O GPIO0_110 7 IO 0 GPMC0_WAIT2 8 I 0 V26 mdio0_mdio MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 TRC_DATA22 5 O GPIO0_109 7 IO 0 GPMC0_WAIT3 8 I 0 AE2 mlb0_mlbcn MLB0_MLBCN 0 I OFF 0 1.8 V VDDA_1P8_ML B MLB_LVDS GPIO1_35 7 IO 0 AD2 mlb0_mlbcp MLB0_MLBCP 0 I OFF 0 1.8 V VDDA_1P8_ML B MLB_LVDS GPIO1_34 7 IO 0 AD3 mlb0_mlbdn MLB0_MLBDN 0 IO OFF 0 1.8 V VDDA_1P8_ML B MLB_LVDS GPIO1_33 7 IO 0 AC3 mlb0_mlbdp MLB0_MLBDP 0 IO OFF 0 1.8 V VDDA_1P8_ML B MLB_LVDS GPIO1_32 7 IO 0 AC1 mlb0_mlbsn MLB0_MLBSN 0 IO OFF 0 1.8 V VDDA_1P8_ML B MLB_LVDS GPIO1_31 7 IO 0 AD1 mlb0_mlbsp MLB0_MLBSP 0 IO OFF 0 1.8 V VDDA_1P8_ML B MLB_LVDS GPIO1_30 7 IO 0 AE1 mmc0_calpad MMC0_CALPAD A OFF 1.8 V VDDS_MMC0 eMMCPHY PU/PD AF1 mmc0_clk MMC0_CLK O DRIVE 0 (OFF)

1.8 V VDDS_MMC0 eMMCPHY PU/PD

AE3 mmc0_cmd MMC0_CMD IO DRIVE 1 (OFF)

1.8 V VDDS_MMC0 eMMCPHY PU/PD 1

AE4 mmc0_ds MMC0_DS IO PD 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 P25 mmc1_clk MMC1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 0 0/1 UART8_RXD 1 I 1 I2C4_SCL 4 IOD 1 GPIO1_19 7 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 R29 mmc1_cmd MMC1_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1 UART8_TXD 1 O I2C4_SDA 4 IOD 1 GPIO1_20 7 IO 0 P23 mmc1_sdcd MMC1_SDCD 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 1 0/1 UART8_CTSn 1 I 1 UART0_DCDn 2 I 1 TIMER_IO2 3 IO 0 EQEP2_I 5 IO 0 PCIE2_CLKREQn 6 IO 0 GPIO1_21 7 IO 0 PRG0_IEP0_EDC_LATCH_IN1 8 I 0 R28 mmc1_sdwp MMC1_SDWP 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 1 0/1 UART8_RTSn 1 O UART0_DSRn 2 I 1 TIMER_IO3 3 IO 0 ECAP2_IN_APWM_OUT 4 IO 0 EQEP2_S 5 IO 0 PCIE3_CLKREQn 6 IO 0 GPIO1_22 7 IO 0 PRG0_IEP0_EDC_SYNC_OUT1 8 O 0 T26 mmc2_clk MMC2_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 0 0/1 USB0_DRVVBUS 1 O USB1_DRVVBUS 2 O TIMER_IO6 3 IO 0 I2C3_SCL 4 IOD 1 UART3_RXD 5 I 1 GPIO1_27 7 IO 0 T25 mmc2_cmd MMC2_CMD 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1 USB0_DRVVBUS 1 O USB1_DRVVBUS 2 O TIMER_IO7 3 IO 0 I2C3_SDA 4 IOD 1 UART3_TXD 5 O GPIO1_28 7 IO 0 AG2 mmc0_dat0 MMC0_DAT0 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 AH1 mmc0_dat1 MMC0_DAT1 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AG3 mmc0_dat2 MMC0_DAT2 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 AF4 mmc0_dat3 MMC0_DAT3 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 AE5 mmc0_dat4 MMC0_DAT4 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 AF3 mmc0_dat5 MMC0_DAT5 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 AG1 mmc0_dat6 MMC0_DAT6 IO PU 1.8 V VDDS_MMC0 eMMCPHY PU/PD 1 AF2 mmc0_dat7 MMC0_DAT7 IO PU 1.8 V VDDS_MMC0 eMMCPHY 1 R24 mmc1_dat0 MMC1_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1 UART7_RTSn 1 O ECAP1_IN_APWM_OUT 2 IO 0 TIMER_IO1 3 IO 0 UART4_TXD 5 O GPIO1_18 7 IO 0 P24 mmc1_dat1 MMC1_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1 UART7_CTSn 1 I 1 ECAP0_IN_APWM_OUT 2 IO 0 TIMER_IO0 3 IO 0 UART4_RXD 5 I 1 GPIO1_17 7 IO 0 R25 mmc1_dat2 MMC1_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1 UART7_TXD 1 O GPIO1_16 7 IO 0 R26 mmc1_dat3 MMC1_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD 1 0/1 UART7_RXD 1 I 1 GPIO1_15 7 IO 0 T24 mmc2_dat0 MMC2_DAT0 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1 UART9_RTSn 1 O UART0_RIn 2 I 1 TIMER_IO5 3 IO 0 UART6_TXD 4 O EQEP2_B 5 I 0 GPIO1_26 7 IO 0 PRG0_IEP1_EDC_SYNC_OUT1 8 O 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 T27 mmc2_dat1 MMC2_DAT1 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1 UART9_CTSn 1 I 1 UART0_DTRn 2 O TIMER_IO4 3 IO 0 UART6_RXD 4 I 1 EQEP2_A 5 I 0 GPIO1_25 7 IO 0 PRG0_IEP1_EDC_LATCH_IN1 8 I 0 T29 mmc2_dat2 MMC2_DAT2 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1 UART9_TXD 1 O CPTS0_HW2TSPUSH 2 I 0 I2C5_SDA 4 IOD 1 GPIO1_24 7 IO 0 T28 mmc2_dat3 MMC2_DAT3 0 IO OFF 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD 1 0/1 UART9_RXD 1 I 1 CPTS0_HW1TSPUSH 2 I 0 I2C5_SCL 4 IOD 1 GPIO1_23 7 IO 0 P29 osc1_xi OSC1_XI I OFF 1.8 V VDDS_OSC1 HFOSC P27 osc1_xo OSC1_XO O OFF 1.8 V VDDS_OSC1 HFOSC AE17 pcie_refclk0n PCIE_REFCLK0N IO OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AD16 pcie_refclk0p PCIE_REFCLK0P IO OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AE14 pcie_refclk1n PCIE_REFCLK1N IO OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AD15 pcie_refclk1p PCIE_REFCLK1P IO OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AE11 pcie_refclk2n PCIE_REFCLK2N IO OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AD12 pcie_refclk2p PCIE_REFCLK2P IO OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AE9 pcie_refclk3n PCIE_REFCLK3N IO OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY AD10 pcie_refclk3p PCIE_REFCLK3P IO OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY E26 pmic_power_en0 MCU_I3C0_SDAPULLEN 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/0 WKUP_GPIO0_66 7 IO 0 G23 pmic_power_en1 PMIC_POWER_EN1 0 O OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/0 MCU_I3C1_SDAPULLEN 5 O WKUP_GPIO0_67 7 IO 0 J24 porz PORz 0 I OFF 0 1.8 V VDDA_WKUP Yes FS Reset PU/PD U1 porz_out PORz_OUT 0 O OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0 AA27 prg0_mdio0_mdc PRG0_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0/1 I2C5_SDA 2 IOD 1 MCAN13_RX 6 I 1 GPIO0_84 7 IO 0 GPMC0_A0 8 OZ 0 DSS_FSYNC2 10 O MCASP2_ACLKR 12 IO MCASP2_AXR5 13 IO 0 Y26 prg0_mdio0_mdio PRG0_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 I2C5_SCL 2 IOD 1 MCAN13_TX 6 O GPIO0_83 7 IO 0 GPMC0_A27 8 OZ 0 DSS_FSYNC0 10 O MCASP2_AFSR 12 IO MCASP2_AXR4 13 IO 0 AF28 prg0_pru0_gpo0 PRG0_PRU0_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI0 1 I 0 PRG0_RGMII1_RD0 2 I 0 PRG0_PWM3_A0 3 IO 0 RGMII3_RD0 4 I 0 RMII3_RXD1 5 I 0 GPIO0_43 7 IO 0 MCASP0_AXR0 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AE28 prg0_pru0_gpo1 PRG0_PRU0_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI1 1 I 0 PRG0_RGMII1_RD1 2 I 0 PRG0_PWM3_B0 3 IO 1 RGMII3_RD1 4 I 0 RMII3_RXD0 5 I 0 GPIO0_44 7 IO 0 MCASP0_AXR1 12 IO AE27 prg0_pru0_gpo2 PRG0_PRU0_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI2 1 I 0 PRG0_RGMII1_RD2 2 I 0 PRG0_PWM2_A0 3 IO 0 RGMII3_RD2 4 I 0 RMII3_CRS_DV 5 I 0 GPIO0_45 7 IO 0 UART3_RXD 8 I 0 MCASP0_ACLKR 12 IO AD26 prg0_pru0_gpo3 PRG0_PRU0_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI3 1 I 0 PRG0_RGMII1_RD3 2 I 0 PRG0_PWM3_A2 3 IO 0 RGMII3_RD3 4 I 0 RMII3_RX_ER 5 I 0 GPIO0_46 7 IO 0 UART3_TXD 8 O 0 MCASP0_AFSR 12 IO AD25 prg0_pru0_gpo4 PRG0_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI4 1 I 0 PRG0_RGMII1_RX_CTL 2 I 0 PRG0_PWM2_B0 3 IO 1 RGMII3_RX_CTL 4 I 0 RMII3_TXD1 5 O GPIO0_47 7 IO 0 MCASP0_AXR2 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AC29 prg0_pru0_gpo5 PRG0_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1 PRG0_PRU0_GPI5 1 I 0 PRG0_PWM3_B2 3 IO 1 RMII3_TXD0 5 O GPIO0_48 7 IO 0 GPMC0_AD0 8 IO 0 MCASP0_AXR3 12 IO BOOTMODE2 Bootstrap I AE26 prg0_pru0_gpo6 PRG0_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI6 1 I 0 PRG0_RGMII1_RXC 2 I 0 PRG0_PWM3_A1 3 IO 0 RGMII3_RXC 4 I 0 RMII3_TX_EN 5 O GPIO0_49 7 IO 0 MCASP0_AXR4 12 IO AC28 prg0_pru0_gpo7 PRG0_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI7 1 I 0 PRG0_IEP0_EDC_LATCH_IN1 2 I 0 PRG0_PWM3_B1 3 IO 1 PRG0_ECAP0_SYNC_IN 4 I 0 MCAN9_TX 6 O GPIO0_50 7 IO 0 GPMC0_AD1 8 IO 0 MCASP0_AXR5 12 IO AC27 prg0_pru0_gpo8 PRG0_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI8 1 I 0 PRG0_PWM2_A1 3 IO 0 MCAN9_RX 6 I 1 GPIO0_51 7 IO 0 GPMC0_AD2 8 IO 0 MCASP0_AXR6 12 IO UART6_RXD 14 I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AB26 prg0_pru0_gpo9 PRG0_PRU0_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI9 1 I 0 PRG0_UART0_CTSn 2 I 1 PRG0_PWM3_TZ_IN 3 I 0 SPI3_CS1 4 IO 1 PRG0_IEP0_EDIO_DATA_IN_OUT28 5 IO 0 MCAN10_TX 6 O GPIO0_52 7 IO 0 GPMC0_AD3 8 IO 0 MCASP0_ACLKX 12 IO UART6_TXD 14 O AB25 prg0_pru0_gpo10 PRG0_PRU0_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI10 1 I 0 PRG0_UART0_RTSn 2 O PRG0_PWM2_B1 3 IO 1 SPI3_CS2 4 IO 1 PRG0_IEP0_EDIO_DATA_IN_OUT29 5 IO 0 MCAN10_RX 6 I 1 GPIO0_53 7 IO 0 GPMC0_AD4 8 IO 0 MCASP0_AFSX 12 IO AJ28 prg0_pru0_gpo11 PRG0_PRU0_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI11 1 I 0 PRG0_RGMII1_TD0 2 O PRG0_PWM3_TZ_OUT 3 O RGMII3_TD0 4 O GPIO0_54 7 IO 0 CLKOUT 9 OZ MCASP0_AXR7 12 IO AH27 prg0_pru0_gpo12 PRG0_PRU0_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI12 1 I 0 PRG0_RGMII1_TD1 2 O PRG0_PWM0_A0 3 IO 0 RGMII3_TD1 4 O GPIO0_55 7 IO 0 DSS_FSYNC0 10 O MCASP0_AXR8 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AH29 prg0_pru0_gpo13 PRG0_PRU0_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI13 1 I 0 PRG0_RGMII1_TD2 2 O PRG0_PWM0_B0 3 IO 1 RGMII3_TD2 4 O GPIO0_56 7 IO 0 DSS_FSYNC2 10 O MCASP0_AXR9 12 IO AG28 prg0_pru0_gpo14 PRG0_PRU0_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI14 1 I 0 PRG0_RGMII1_TD3 2 O PRG0_PWM0_A1 3 IO 0 RGMII3_TD3 4 O GPIO0_57 7 IO 0 UART4_RXD 8 I 0 MCASP0_AXR10 12 IO AG27 prg0_pru0_gpo15 PRG0_PRU0_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI15 1 I 0 PRG0_RGMII1_TX_CTL 2 O PRG0_PWM0_B1 3 IO 1 RGMII3_TX_CTL 4 O GPIO0_58 7 IO 0 UART4_TXD 8 O 0 DSS_FSYNC3 10 O MCASP0_AXR11 12 IO AH28 prg0_pru0_gpo16 PRG0_PRU0_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI16 1 I 0 PRG0_RGMII1_TXC 2 IO 0 PRG0_PWM0_A2 3 IO 0 RGMII3_TXC 4 O 0 GPIO0_59 7 IO 0 DSS_FSYNC1 10 O MCASP0_AXR12 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AB24 prg0_pru0_gpo17 PRG0_PRU0_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1 PRG0_PRU0_GPI17 1 I 0 PRG0_IEP0_EDC_SYNC_OUT1 2 O PRG0_PWM0_B2 3 IO 1 PRG0_ECAP0_SYNC_OUT 4 O GPIO0_60 7 IO 0 GPMC0_AD5 8 IO 0 OBSCLK1 9 O 0 MCASP0_AXR13 12 IO BOOTMODE7 Bootstrap I AB29 prg0_pru0_gpo18 PRG0_PRU0_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI18 1 I 0 PRG0_IEP0_EDC_LATCH_IN0 2 I 0 PRG0_PWM0_TZ_IN 3 I 0 PRG0_ECAP0_IN_APWM_OUT 4 IO 0 GPIO0_61 7 IO 0 GPMC0_AD6 8 IO 0 MCASP0_AXR14 12 IO AB28 prg0_pru0_gpo19 PRG0_PRU0_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU0_GPI19 1 I 0 PRG0_IEP0_EDC_SYNC_OUT0 2 O PRG0_PWM0_TZ_OUT 3 O GPIO0_62 7 IO 0 GPMC0_AD7 8 IO 0 MCASP0_AXR15 12 IO AE29 prg0_pru1_gpo0 PRG0_PRU1_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI0 1 I 0 PRG0_RGMII2_RD0 2 I 0 RGMII4_RD0 4 I 0 RMII4_RXD0 5 I 0 GPIO0_63 7 IO 0 UART4_CTSn 8 I 0 MCASP1_AXR0 12 IO UART5_RXD 14 I www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AD28 prg0_pru1_gpo1 PRG0_PRU1_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI1 1 I 0 PRG0_RGMII2_RD1 2 I 0 RGMII4_RD1 4 I 0 RMII4_RXD1 5 I 0 GPIO0_64 7 IO 0 UART4_RTSn 8 O 0 MCASP1_AXR1 12 IO UART5_TXD 14 O AD27 prg0_pru1_gpo2 PRG0_PRU1_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI2 1 I 0 PRG0_RGMII2_RD2 2 I 0 PRG0_PWM2_A2 3 IO 0 RGMII4_RD2 4 I 0 RMII4_CRS_DV 5 I 0 GPIO0_65 7 IO 0 GPMC0_A23 8 OZ 0 MCASP1_ACLKR 12 IO MCASP1_AXR10 13 IO 0 AC25 prg0_pru1_gpo3 PRG0_PRU1_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI3 1 I 0 PRG0_RGMII2_RD3 2 I 0 RGMII4_RD3 4 I 0 RMII4_RX_ER 5 I 0 GPIO0_66 7 IO 0 MCASP1_AFSR 12 IO MCASP1_AXR11 13 IO 0 AD29 prg0_pru1_gpo4 PRG0_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI4 1 I 0 PRG0_RGMII2_RX_CTL 2 I 0 PRG0_PWM2_B2 3 IO 1 RGMII4_RX_CTL 4 I 0 RMII4_TXD1 5 O GPIO0_67 7 IO 0 GPMC0_A24 8 OZ 0 MCASP1_AXR2 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AB27 prg0_pru1_gpo5 PRG0_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1 PRG0_PRU1_GPI5 1 I 0 GPIO0_68 7 IO 0 GPMC0_AD8 8 IO 0 MCASP1_ACLKX 12 IO BOOTMODE6 Bootstrap I AC26 prg0_pru1_gpo6 PRG0_PRU1_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI6 1 I 0 PRG0_RGMII2_RXC 2 I 0 RGMII4_RXC 4 I 0 RMII4_TXD0 5 O GPIO0_69 7 IO 0 GPMC0_A25 8 OZ 0 MCASP1_AXR3 12 IO AA24 prg0_pru1_gpo7 PRG0_PRU1_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI7 1 I 0 PRG0_IEP1_EDC_LATCH_IN1 2 I 0 SPI3_CS0 4 IO 1 MCAN11_TX 6 O GPIO0_70 7 IO 0 GPMC0_AD9 8 IO 0 MCASP1_AXR4 12 IO UART2_TXD 14 O AA28 prg0_pru1_gpo8 PRG0_PRU1_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI8 1 I 0 PRG0_PWM2_TZ_OUT 3 O MCAN11_RX 6 I 1 GPIO0_71 7 IO 0 GPMC0_AD10 8 IO 0 MCASP1_AFSX 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 Y24 prg0_pru1_gpo9 PRG0_PRU1_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI9 1 I 0 PRG0_UART0_RXD 2 I 1 SPI3_CS3 4 IO 1 PRG0_IEP0_EDIO_DATA_IN_OUT30 6 IO 0 GPIO0_72 7 IO 0 GPMC0_AD11 8 IO 0 DSS_FSYNC3 10 O MCASP1_AXR5 12 IO UART8_RXD 14 I AA25 prg0_pru1_gpo10 PRG0_PRU1_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI10 1 I 0 PRG0_UART0_TXD 2 O PRG0_PWM2_TZ_IN 3 I 0 PRG0_IEP0_EDIO_DATA_IN_OUT31 6 IO 0 GPIO0_73 7 IO 0 GPMC0_AD12 8 IO 0 CLKOUT 9 OZ 0 MCASP1_AXR6 12 IO UART8_TXD 14 O AG26 prg0_pru1_gpo11 PRG0_PRU1_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI11 1 I 0 PRG0_RGMII2_TD0 2 O RGMII4_TD0 4 O RMII4_TX_EN 5 O GPIO0_74 7 IO 0 GPMC0_A26 8 OZ 0 MCASP1_AXR7 12 IO AF27 prg0_pru1_gpo12 PRG0_PRU1_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI12 1 I 0 PRG0_RGMII2_TD1 2 O PRG0_PWM1_A0 3 IO 0 RGMII4_TD1 4 O GPIO0_75 7 IO 0 MCASP1_AXR8 12 IO UART8_CTSn 14 I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AF26 prg0_pru1_gpo13 PRG0_PRU1_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI13 1 I 0 PRG0_RGMII2_TD2 2 O PRG0_PWM1_B0 3 IO 1 RGMII4_TD2 4 O GPIO0_76 7 IO 0 MCASP1_AXR9 12 IO UART8_RTSn 14 O AE25 prg0_pru1_gpo14 PRG0_PRU1_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI14 1 I 0 PRG0_RGMII2_TD3 2 O PRG0_PWM1_A1 3 IO 0 RGMII4_TD3 4 O GPIO0_77 7 IO 0 MCASP2_AXR0 12 IO UART2_CTSn 14 I AF29 prg0_pru1_gpo15 PRG0_PRU1_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI15 1 I 0 PRG0_RGMII2_TX_CTL 2 O PRG0_PWM1_B1 3 IO 1 RGMII4_TX_CTL 4 O GPIO0_78 7 IO 0 MCASP2_AXR1 12 IO UART2_RTSn 14 O AG29 prg0_pru1_gpo16 PRG0_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI16 1 I 0 PRG0_RGMII2_TXC 2 IO 0 PRG0_PWM1_A2 3 IO 0 RGMII4_TXC 4 O 0 GPIO0_79 7 IO 0 MCASP2_AXR2 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 Y25 prg0_pru1_gpo17 PRG0_PRU1_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 1/1 PRG0_PRU1_GPI17 1 I 0 PRG0_IEP1_EDC_SYNC_OUT1 2 O PRG0_PWM1_B2 3 IO 1 SPI3_CLK 4 IO 0 GPIO0_80 7 IO 0 GPMC0_AD13 8 IO 0 MCASP2_AXR3 12 IO BOOTMODE3 Bootstrap I AA26 prg0_pru1_gpo18 PRG0_PRU1_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI18 1 I 0 PRG0_IEP1_EDC_LATCH_IN0 2 I 0 PRG0_PWM1_TZ_IN 3 I 0 SPI3_D0 4 IO 0 MCAN12_TX 6 O GPIO0_81 7 IO 0 GPMC0_AD14 8 IO 0 MCASP2_AFSX 12 IO UART2_RXD 14 I AA29 prg0_pru1_gpo19 PRG0_PRU1_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD 0 0/1 PRG0_PRU1_GPI19 1 I 0 PRG0_IEP1_EDC_SYNC_OUT0 2 O PRG0_PWM1_TZ_OUT 3 O SPI3_D1 4 IO 0 MCAN12_RX 6 I 1 GPIO0_82 7 IO 0 GPMC0_AD15 8 IO 0 MCASP2_ACLKX 12 IO AD18 prg1_mdio0_mdc PRG1_MDIO0_MDC 0 O OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0/1 SPI1_CS3 1 IO 1 I2C4_SDA 2 IOD 1 RMII_REF_CLK 5 I 0 GPIO0_42 7 IO 0 VPFE0_DATA12 11 I MCASP5_AXR3 12 IO 0 MCASP5_AFSR 13 IO 0 UART3_RTSn 14 O 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AD19 prg1_mdio0_mdio PRG1_MDIO0_MDIO 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 SPI1_CS2 1 IO 1 I2C4_SCL 2 IOD 1 GPIO0_41 7 IO 0 DSS_FSYNC1 10 O VPFE0_DATA11 11 I MCASP5_AXR2 12 IO 0 MCASP5_ACLKR 13 IO 0 UART3_CTSn 14 I 0 AC23 prg1_pru0_gpo0 PRG1_PRU0_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI0 1 I 0 PRG1_RGMII1_RD0 2 I 0 PRG1_PWM3_A0 3 IO 0 RGMII1_RD0 4 I 0 RMII1_RXD0 5 I 0 GPIO0_1 7 IO 0 GPMC0_BE1n 8 O 0 RGMII7_RD0 9 I MCASP6_ACLKX 12 IO UART0_RXD 14 I AG22 prg1_pru0_gpo1 PRG1_PRU0_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI1 1 I 0 PRG1_RGMII1_RD1 2 I 0 PRG1_PWM3_B0 3 IO 1 RGMII1_RD1 4 I 0 RMII1_RXD1 5 I 0 GPIO0_2 7 IO 0 GPMC0_WAIT0 8 I 0 RGMII7_RD1 9 I 0 MCASP6_AFSX 12 IO UART0_TXD 14 O www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AF22 prg1_pru0_gpo2 PRG1_PRU0_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI2 1 I 0 PRG1_RGMII1_RD2 2 I 0 PRG1_PWM2_A0 3 IO 0 RGMII1_RD2 4 I 0 RMII1_CRS_DV 5 I 0 GPIO0_3 7 IO 0 GPMC0_WAIT1 8 I 0 RGMII7_RD2 9 I 0 MCASP6_AXR0 12 IO UART1_RXD 14 I AJ23 prg1_pru0_gpo3 PRG1_PRU0_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI3 1 I 0 PRG1_RGMII1_RD3 2 I 0 PRG1_PWM3_A2 3 IO 0 RGMII1_RD3 4 I 0 RMII1_RX_ER 5 I 0 GPIO0_4 7 IO 0 GPMC0_DIR 8 O 0 RGMII7_RD3 9 I MCASP6_AXR1 12 IO UART1_TXD 14 O AH23 prg1_pru0_gpo4 PRG1_PRU0_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI4 1 I 0 PRG1_RGMII1_RX_CTL 2 I 0 PRG1_PWM2_B0 3 IO 1 RGMII1_RX_CTL 4 I 0 RMII1_TXD0 5 O GPIO0_5 7 IO 0 GPMC0_CSn2 8 O 0 RGMII7_RX_CTL 9 I MCASP6_AXR2 12 IO MCASP6_ACLKR 13 IO 0 UART2_RXD 14 I 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AD20 prg1_pru0_gpo5 PRG1_PRU0_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG1_PRU0_GPI5 1 I 0 PRG1_PWM3_B2 3 IO 1 RMII1_TX_EN 5 O GPIO0_6 7 IO 0 GPMC0_WEn 8 O 0 MCASP3_AXR0 12 IO BOOTMODE0 Bootstrap I AD22 prg1_pru0_gpo6 PRG1_PRU0_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI6 1 I 0 PRG1_RGMII1_RXC 2 I 0 PRG1_PWM3_A1 3 IO 0 RGMII1_RXC 4 I 0 RMII1_TXD1 5 O AUDIO_EXT_REFCLK0 6 IO 0 GPIO0_7 7 IO 0 GPMC0_CSn3 8 O 0 RGMII7_RXC 9 I MCASP6_AXR3 12 IO MCASP6_AFSR 13 IO 0 UART2_TXD 14 O 0 AE20 prg1_pru0_gpo7 PRG1_PRU0_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI7 1 I 0 PRG1_IEP0_EDC_LATCH_IN1 2 I 0 PRG1_PWM3_B1 3 IO 1 AUDIO_EXT_REFCLK1 5 IO 0 MCAN4_TX 6 O GPIO0_8 7 IO 0 MCASP3_AXR1 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AJ20 prg1_pru0_gpo8 PRG1_PRU0_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI8 1 I 0 PRG1_PWM2_A1 3 IO 0 RMII5_RXD0 5 I 0 MCAN4_RX 6 I 1 GPIO0_9 7 IO 0 GPMC0_OEn_REn 8 O 0 VOUT0_DATA22 10 O MCASP3_AXR2 12 IO AG20 prg1_pru0_gpo9 PRG1_PRU0_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI9 1 I 0 PRG1_UART0_CTSn 2 I 1 PRG1_PWM3_TZ_IN 3 I 0 SPI6_CS1 4 IO 1 RMII5_RXD1 5 I 0 GPIO0_10 7 IO 0 GPMC0_ADVn_ALE 8 O 0 PRG1_IEP0_EDIO_DATA_IN_OUT28 9 IO VOUT0_DATA23 10 O 0 MCASP3_ACLKX 12 IO AD21 prg1_pru0_gpo10 PRG1_PRU0_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI10 1 I 0 PRG1_UART0_RTSn 2 O PRG1_PWM2_B1 3 IO 1 SPI6_CS2 4 IO 1 RMII5_CRS_DV 5 I 0 GPIO0_11 7 IO 0 GPMC0_BE0n_CLE 8 O 0 PRG1_IEP0_EDIO_DATA_IN_OUT29 9 IO OBSCLK2 10 O 0 MCASP3_AFSX 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AF24 prg1_pru0_gpo11 PRG1_PRU0_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI11 1 I 0 PRG1_RGMII1_TD0 2 O PRG1_PWM3_TZ_OUT 3 O RGMII1_TD0 4 O MCAN4_TX 6 O GPIO0_12 7 IO 0 RGMII7_TD0 9 O VOUT0_DATA16 10 O VPFE0_DATA0 11 I MCASP7_ACLKX 12 IO 0 AJ24 prg1_pru0_gpo12 PRG1_PRU0_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI12 1 I 0 PRG1_RGMII1_TD1 2 O PRG1_PWM0_A0 3 IO 0 RGMII1_TD1 4 O MCAN4_RX 6 I 1 GPIO0_13 7 IO 0 RGMII7_TD1 9 O VOUT0_DATA17 10 O VPFE0_DATA1 11 I MCASP7_AFSX 12 IO 0 AG24 prg1_pru0_gpo13 PRG1_PRU0_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI13 1 I 0 PRG1_RGMII1_TD2 2 O PRG1_PWM0_B0 3 IO 1 RGMII1_TD2 4 O MCAN5_TX 6 O GPIO0_14 7 IO 0 RGMII7_TD2 9 O VOUT0_DATA18 10 O VPFE0_DATA2 11 I MCASP7_AXR0 12 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AD24 prg1_pru0_gpo14 PRG1_PRU0_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI14 1 I 0 PRG1_RGMII1_TD3 2 O PRG1_PWM0_A1 3 IO 0 RGMII1_TD3 4 O MCAN5_RX 6 I 1 GPIO0_15 7 IO 0 RGMII7_TD3 9 O VOUT0_DATA19 10 O VPFE0_DATA3 11 I MCASP7_AXR1 12 IO 0 AC24 prg1_pru0_gpo15 PRG1_PRU0_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI15 1 I 0 PRG1_RGMII1_TX_CTL 2 O PRG1_PWM0_B1 3 IO 1 RGMII1_TX_CTL 4 O MCAN6_TX 6 O GPIO0_16 7 IO 0 RGMII7_TX_CTL 9 O VOUT0_DATA20 10 O VPFE0_DATA4 11 I MCASP7_AXR2 12 IO 0 MCASP7_ACLKR 13 IO 0 AE24 prg1_pru0_gpo16 PRG1_PRU0_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI16 1 I 0 PRG1_RGMII1_TXC 2 IO 0 PRG1_PWM0_A2 3 IO 0 RGMII1_TXC 4 O 0 MCAN6_RX 6 I 1 GPIO0_17 7 IO 0 RGMII7_TXC 9 O VOUT0_DATA21 10 O 0 VPFE0_DATA5 11 I MCASP7_AXR3 12 IO 0 MCASP7_AFSR 13 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AJ21 prg1_pru0_gpo17 PRG1_PRU0_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI17 1 I 0 PRG1_IEP0_EDC_SYNC_OUT1 2 O PRG1_PWM0_B2 3 IO 1 RMII5_TXD1 5 O MCAN5_TX 6 O GPIO0_18 7 IO 0 VPFE0_DATA6 11 I MCASP3_AXR3 12 IO 0 AE21 prg1_pru0_gpo18 PRG1_PRU0_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI18 1 I 0 PRG1_IEP0_EDC_LATCH_IN0 2 I 0 PRG1_PWM0_TZ_IN 3 I 0 RMII5_RX_ER 5 I 0 MCAN5_RX 6 I 1 GPIO0_19 7 IO 0 VPFE0_DATA7 11 I MCASP4_ACLKX 12 IO 0 AH21 prg1_pru0_gpo19 PRG1_PRU0_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU0_GPI19 1 I 0 PRG1_IEP0_EDC_SYNC_OUT0 2 O PRG1_PWM0_TZ_OUT 3 O RMII5_TXD0 5 O MCAN6_TX 6 O GPIO0_20 7 IO 0 VOUT0_EXTPCLKIN 10 I VPFE0_PCLK 11 I 0 MCASP4_AFSX 12 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AE22 prg1_pru1_gpo0 PRG1_PRU1_GPO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI0 1 I 0 PRG1_RGMII2_RD0 2 I 0 RGMII2_RD0 4 I 0 RMII2_RXD0 5 I 0 GPIO0_21 7 IO 0 RGMII8_RD0 8 I 0 VOUT0_DATA0 10 O VPFE0_HD 11 I MCASP8_ACLKX 12 IO 0 AG23 prg1_pru1_gpo1 PRG1_PRU1_GPO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI1 1 I 0 PRG1_RGMII2_RD1 2 I 0 RGMII2_RD1 4 I 0 RMII2_RXD1 5 I 0 GPIO0_22 7 IO 0 RGMII8_RD1 8 I 0 VOUT0_DATA1 10 O VPFE0_FIELD 11 I MCASP8_AFSX 12 IO 0 AF23 prg1_pru1_gpo2 PRG1_PRU1_GPO2 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI2 1 I 0 PRG1_RGMII2_RD2 2 I 0 PRG1_PWM2_A2 3 IO 0 RGMII2_RD2 4 I 0 RMII2_CRS_DV 5 I 0 GPIO0_23 7 IO 0 RGMII8_RD2 8 I 0 VOUT0_DATA2 10 O VPFE0_VD 11 I MCASP8_AXR0 12 IO 0 MCASP3_ACLKR 13 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AD23 prg1_pru1_gpo3 PRG1_PRU1_GPO3 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI3 1 I 0 PRG1_RGMII2_RD3 2 I 0 RGMII2_RD3 4 I 0 RMII2_RX_ER 5 I 0 GPIO0_24 7 IO 0 RGMII8_RD3 8 I 0 EQEP1_A 9 I 0 VOUT0_DATA3 10 O 0 VPFE0_WEN 11 I MCASP8_AXR1 12 IO 0 MCASP3_AFSR 13 IO 0 TIMER_IO2 14 IO 0 AH24 prg1_pru1_gpo4 PRG1_PRU1_GPO4 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI4 1 I 0 PRG1_RGMII2_RX_CTL 2 I 0 PRG1_PWM2_B2 3 IO 1 RGMII2_RX_CTL 4 I 0 RMII2_TXD0 5 O GPIO0_25 7 IO 0 RGMII8_RX_CTL 8 I 0 EQEP1_B 9 I 0 VOUT0_DATA4 10 O 0 VPFE0_DATA13 11 I MCASP8_AXR2 12 IO 0 MCASP8_ACLKR 13 IO 0 TIMER_IO3 14 IO 0 AG21 prg1_pru1_gpo5 PRG1_PRU1_GPO5 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI5 1 I 0 RMII5_TX_EN 5 O MCAN6_RX 6 I 1 GPIO0_26 7 IO 0 GPMC0_WPn 8 O 0 EQEP1_S 9 IO VOUT0_DATA5 10 O 0 MCASP4_AXR0 12 IO TIMER_IO4 14 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AE23 prg1_pru1_gpo6 PRG1_PRU1_GPO6 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI6 1 I 0 PRG1_RGMII2_RXC 2 I 0 RGMII2_RXC 4 I 0 RMII2_TXD1 5 O GPIO0_27 7 IO 0 RGMII8_RXC 8 I 0 VOUT0_DATA6 10 O VPFE0_DATA14 11 I MCASP8_AXR3 12 IO 0 MCASP8_AFSR 13 IO 0 TIMER_IO5 14 IO 0 AC21 prg1_pru1_gpo7 PRG1_PRU1_GPO7 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI7 1 I 0 PRG1_IEP1_EDC_LATCH_IN1 2 I 0 SPI6_CS0 4 IO 1 RMII6_RX_ER 5 I 0 MCAN7_TX 6 O GPIO0_28 7 IO 0 VOUT0_DATA7 10 O VPFE0_DATA15 11 I MCASP4_AXR1 12 IO 0 UART3_TXD 14 O Y23 prg1_pru1_gpo8 PRG1_PRU1_GPO8 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI8 1 I 0 PRG1_PWM2_TZ_OUT 3 O RMII6_RXD0 5 I 0 MCAN7_RX 6 I 1 GPIO0_29 7 IO 0 GPMC0_CSn1 8 O 0 VOUT0_DATA8 10 O MCASP4_AXR2 12 IO UART3_RXD 14 I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AF21 prg1_pru1_gpo9 PRG1_PRU1_GPO9 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI9 1 I 0 PRG1_UART0_RXD 2 I 1 SPI6_CS3 4 IO 1 RMII6_RXD1 5 I 0 MCAN8_TX 6 O GPIO0_30 7 IO 0 GPMC0_CSn0 8 O 0 PRG1_IEP0_EDIO_DATA_IN_OUT30 9 IO VOUT0_DATA9 10 O 0 MCASP4_AXR3 12 IO AB23 prg1_pru1_gpo10 PRG1_PRU1_GPO10 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI10 1 I 0 PRG1_UART0_TXD 2 O PRG1_PWM2_TZ_IN 3 I 0 RMII6_CRS_DV 5 I 0 MCAN8_RX 6 I 1 GPIO0_31 7 IO 0 GPMC0_CLKOUT 8 O 0 PRG1_IEP0_EDIO_DATA_IN_OUT31 9 IO VOUT0_DATA10 10 O 0 GPMC0_FCLK_MUX 11 O MCASP5_ACLKX 12 IO AJ25 prg1_pru1_gpo11 PRG1_PRU1_GPO11 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI11 1 I 0 PRG1_RGMII2_TD0 2 O RGMII2_TD0 4 O RMII2_TX_EN 5 O GPIO0_32 7 IO 0 RGMII8_TD0 8 O 0 EQEP1_I 9 IO VOUT0_DATA11 10 O 0 MCASP9_ACLKX 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AH25 prg1_pru1_gpo12 PRG1_PRU1_GPO12 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI12 1 I 0 PRG1_RGMII2_TD1 2 O PRG1_PWM1_A0 3 IO 0 RGMII2_TD1 4 O MCAN7_TX 6 O GPIO0_33 7 IO 0 RGMII8_TD1 8 O 0 VOUT0_DATA12 10 O MCASP9_AFSX 12 IO AG25 prg1_pru1_gpo13 PRG1_PRU1_GPO13 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI13 1 I 0 PRG1_RGMII2_TD2 2 O PRG1_PWM1_B0 3 IO 1 RGMII2_TD2 4 O MCAN7_RX 6 I 1 GPIO0_34 7 IO 0 RGMII8_TD2 8 O 0 VOUT0_DATA13 10 O VPFE0_DATA8 11 I MCASP9_AXR0 12 IO 0 MCASP4_ACLKR 13 IO 0 AH26 prg1_pru1_gpo14 PRG1_PRU1_GPO14 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI14 1 I 0 PRG1_RGMII2_TD3 2 O PRG1_PWM1_A1 3 IO 0 RGMII2_TD3 4 O MCAN8_TX 6 O GPIO0_35 7 IO 0 RGMII8_TD3 8 O 0 VOUT0_DATA14 10 O MCASP9_AXR1 12 IO MCASP4_AFSR 13 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AJ27 prg1_pru1_gpo15 PRG1_PRU1_GPO15 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI15 1 I 0 PRG1_RGMII2_TX_CTL 2 O PRG1_PWM1_B1 3 IO 1 RGMII2_TX_CTL 4 O MCAN8_RX 6 I 1 GPIO0_36 7 IO 0 RGMII8_TX_CTL 8 O 0 VOUT0_DATA15 10 O VPFE0_DATA9 11 I MCASP9_AXR2 12 IO 0 MCASP9_ACLKR 13 IO 0 AJ26 prg1_pru1_gpo16 PRG1_PRU1_GPO16 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI16 1 I 0 PRG1_RGMII2_TXC 2 IO 0 PRG1_PWM1_A2 3 IO 0 RGMII2_TXC 4 O 0 GPIO0_37 7 IO 0 RGMII8_TXC 8 O 0 VOUT0_VP2_HSYNC 9 O 0 VOUT0_HSYNC 10 O MCASP9_AXR3 12 IO MCASP9_AFSR 13 IO 0 VOUT0_VP0_HSYNC 14 O 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AC22 prg1_pru1_gpo17 PRG1_PRU1_GPO17 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 1/1 PRG1_PRU1_GPI17 1 I 0 PRG1_IEP1_EDC_SYNC_OUT1 2 O PRG1_PWM1_B2 3 IO 1 SPI6_CLK 4 IO 0 RMII6_TX_EN 5 O PRG1_ECAP0_SYNC_OUT 6 O GPIO0_38 7 IO 0 VOUT0_VP2_DE 9 O VOUT0_DE 10 O VPFE0_DATA10 11 I MCASP5_AFSX 12 IO 0 VOUT0_VP0_DE 14 O BOOTMODE1 Bootstrap I AJ22 prg1_pru1_gpo18 PRG1_PRU1_GPO18 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI18 1 I 0 PRG1_IEP1_EDC_LATCH_IN0 2 I 0 PRG1_PWM1_TZ_IN 3 I 0 SPI6_D0 4 IO 0 RMII6_TXD0 5 O PRG1_ECAP0_SYNC_IN 6 I 0 GPIO0_39 7 IO 0 VOUT0_VP2_VSYNC 9 O VOUT0_VSYNC 10 O MCASP5_AXR0 12 IO VOUT0_VP0_VSYNC 14 O AH22 prg1_pru1_gpo19 PRG1_PRU1_GPO19 0 IO OFF 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD 0 0/1 PRG1_PRU1_GPI19 1 I 0 PRG1_IEP1_EDC_SYNC_OUT0 2 O PRG1_PWM1_TZ_OUT 3 O SPI6_D1 4 IO 0 RMII6_TXD1 5 O PRG1_ECAP0_IN_APWM_OUT 6 IO 0 GPIO0_40 7 IO 0 VOUT0_PCLK 10 O MCASP5_AXR1 12 IO T6 resetstatz RESETSTATz 0 O OFF 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 C28 RESET_REQZ RESET_REQz 0 I PU 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 U25 rgmii5_rxc RGMII5_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 I2C6_SDA 2 IOD 1 VOUT1_DATA7 4 O TRC_DATA5 5 O EHRPWM_TZn_IN1 6 I 0 GPIO0_92 7 IO 0 GPMC0_A8 8 OZ 0 MCASP10_AXR3 12 IO EHRPWM_SOCA 14 O U26 rgmii5_rx_ctl RGMII5_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 RMII7_RX_ER 1 I 0 I2C2_SDA 2 IOD 1 VOUT1_DATA1 4 O TRC_CTL 5 O EHRPWM0_SYNCO 6 O GPIO0_86 7 IO 0 GPMC0_A2 8 OZ 0 MCASP10_AFSX 12 IO U29 rgmii5_txc RGMII5_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 RMII7_TX_EN 1 O I2C6_SCL 2 IOD 1 VOUT1_DATA6 4 O TRC_DATA4 5 O EHRPWM1_B 6 IO 0 GPIO0_91 7 IO 0 GPMC0_A7 8 OZ 0 MCASP10_AXR2 12 IO U23 rgmii5_tx_ctl RGMII5_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1 RMII7_CRS_DV 1 I 0 I2C2_SCL 2 IOD 1 VOUT1_DATA0 4 O TRC_CLK 5 O EHRPWM0_SYNCI 6 I 0 GPIO0_85 7 IO 0 GPMC0_A1 8 OZ 0 MCASP10_ACLKX 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 W26 rgmii6_rxc RGMII6_RXC 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 AUDIO_EXT_REFCLK2 3 IO 0 VOUT1_DE 4 O TRC_DATA17 5 O EHRPWM4_B 6 IO 0 GPIO0_104 7 IO 0 GPMC0_A20 8 OZ 0 VOUT1_VP0_DE 9 O MCASP10_AXR7 12 IO V23 rgmii6_rx_ctl RGMII6_RX_CTL 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 RMII8_RX_ER 1 I 0 VOUT1_DATA13 4 O TRC_DATA11 5 O EHRPWM3_A 6 IO 0 GPIO0_98 7 IO 0 GPMC0_A14 8 OZ 0 MCASP10_AFSR 12 IO W29 rgmii6_txc RGMII6_TXC 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 RMII8_TX_EN 1 O SPI5_CLK 3 IO 0 VOUT1_PCLK 4 O TRC_DATA16 5 O EHRPWM4_A 6 IO 0 GPIO0_103 7 IO 0 GPMC0_A19 8 OZ 0 MCASP10_AXR6 12 IO Y28 rgmii6_tx_ctl RGMII6_TX_CTL 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1 RMII8_CRS_DV 1 I 0 VOUT1_DATA12 4 O TRC_DATA10 5 O GPIO0_97 7 IO 0 GPMC0_A13 8 OZ 0 MCASP10_ACLKR 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 T23 rgmii5_rd0 RGMII5_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 RMII7_RXD0 1 I 0 UART6_RTSn 3 O VOUT1_DATA11 4 O TRC_DATA9 5 O GPIO0_96 7 IO 0 GPMC0_A12 8 OZ 0 MCASP11_AXR3 12 IO R23 rgmii5_rd1 RGMII5_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 RMII7_RXD1 1 I 0 UART6_CTSn 3 I 1 VOUT1_DATA10 4 O TRC_DATA8 5 O EHRPWM_TZn_IN2 6 I 0 GPIO0_95 7 IO 0 GPMC0_A11 8 OZ 0 MCASP11_AXR2 12 IO EHRPWM_SOCB 14 O U24 rgmii5_rd2 RGMII5_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 UART3_RTSn 1 O UART6_TXD 3 O VOUT1_DATA9 4 O TRC_DATA7 5 O EHRPWM2_B 6 IO 0 GPIO0_94 7 IO 0 GPMC0_A10 8 OZ 0 MCASP11_AXR1 12 IO U27 rgmii5_rd3 RGMII5_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0 0/1 UART3_CTSn 1 I 1 UART6_RXD 3 I 1 VOUT1_DATA8 4 O TRC_DATA6 5 O EHRPWM2_A 6 IO 0 GPIO0_93 7 IO 0 GPMC0_A9 8 OZ 0 MCASP11_AXR0 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 U28 rgmii5_td0 RGMII5_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1 RMII7_TXD0 1 O I2C3_SDA 2 IOD 1 VOUT1_DATA5 4 O TRC_DATA3 5 O EHRPWM1_A 6 IO 0 GPIO0_90 7 IO 0 GPMC0_A6 8 OZ 0 MCASP11_AFSX 12 IO V27 rgmii5_td1 RGMII5_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1 RMII7_TXD1 1 O I2C3_SCL 2 IOD 1 VOUT1_DATA4 4 O TRC_DATA2 5 O EHRPWM0_B 6 IO 0 GPIO0_89 7 IO 0 GPMC0_A5 8 OZ 0 MCASP11_ACLKX 12 IO V29 rgmii5_td2 RGMII5_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1 UART3_TXD 1 O SYNC3_OUT 3 O VOUT1_DATA3 4 O TRC_DATA1 5 O EHRPWM0_A 6 IO 0 GPIO0_88 7 IO 0 GPMC0_A4 8 OZ 0 MCASP10_AXR1 12 IO V28 rgmii5_td3 RGMII5_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD 0/1 UART3_RXD 1 I 1 SYNC2_OUT 3 O VOUT1_DATA2 4 O TRC_DATA0 5 O EHRPWM_TZn_IN0 6 I 0 GPIO0_87 7 IO 0 GPMC0_A3 8 OZ 0 MCASP10_AXR0 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 W25 rgmii6_rd0 RGMII6_RD0 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 RMII8_RXD0 1 I 0 SPI5_CS1 3 IO 1 AUDIO_EXT_REFCLK3 4 IO 0 TRC_DATA21 5 O EHRPWM_TZn_IN5 6 I 0 GPIO0_108 7 IO 0 GPMC0_DIR 8 O 0 MCASP11_AXR7 12 IO W24 rgmii6_rd1 RGMII6_RD1 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 RMII8_RXD1 1 I 0 SPI5_D1 3 IO 0 VOUT1_EXTPCLKIN 4 I 0 TRC_DATA20 5 O EHRPWM5_B 6 IO 0 GPIO0_107 7 IO 0 GPMC0_BE1n 8 O 0 MCASP11_AXR6 12 IO Y27 rgmii6_rd2 RGMII6_RD2 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 UART4_RTSn 1 O UART5_TXD 3 O TRC_DATA19 5 O EHRPWM5_A 6 IO 0 GPIO0_106 7 IO 0 GPMC0_A22 8 OZ 0 MCASP11_AXR5 12 IO Y29 rgmii6_rd3 RGMII6_RD3 0 I OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0 0/1 UART4_CTSn 1 I 1 UART5_RXD 3 I 1 CLKOUT 4 OZ TRC_DATA18 5 O EHRPWM_TZn_IN4 6 I 0 GPIO0_105 7 IO 0 GPMC0_A21 8 OZ 0 MCASP11_AXR4 12 IO www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 W27 rgmii6_td0 RGMII6_TD0 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1 RMII8_TXD0 1 O SPI5_CS0 3 IO 1 VOUT1_HSYNC 4 O TRC_DATA15 5 O EHRPWM_TZn_IN3 6 I 0 GPIO0_102 7 IO 0 GPMC0_A18 8 OZ 0 VOUT1_VP0_HSYNC 9 O MCASP10_AXR5 12 IO V25 rgmii6_td1 RGMII6_TD1 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1 RMII8_TXD1 1 O SPI5_D0 3 IO 0 VOUT1_VSYNC 4 O TRC_DATA14 5 O EHRPWM3_SYNCO 6 O GPIO0_101 7 IO 0 GPMC0_A17 8 OZ 0 VOUT1_VP0_VSYNC 9 O MCASP10_AXR4 12 IO W28 rgmii6_td2 RGMII6_TD2 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1 UART4_TXD 1 O SPI5_CS2 3 IO 1 VOUT1_DATA15 4 O TRC_DATA13 5 O EHRPWM3_SYNCI 6 I 0 GPIO0_100 7 IO 0 GPMC0_A16 8 OZ 0 MCASP11_AFSR 12 IO DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 W23 rgmii6_td3 RGMII6_TD3 0 O OFF 7 1.8 V/3.3 V VDDSHV4 Yes LVCMOS PU/PD 0/1 UART4_RXD 1 I 1 SPI5_CS3 3 IO 1 VOUT1_DATA14 4 O TRC_DATA12 5 O EHRPWM3_B 6 IO 0 GPIO0_99 7 IO 0 GPMC0_A15 8 OZ 0 MCASP11_ACLKR 12 IO E7 SERDES4_REFCLK_N SERDES4_REFCLK_N IO OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY AE18 serdes0_rext SERDES0_REXT A OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AE13 serdes1_rext SERDES1_REXT A OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY AD13 serdes2_rext SERDES2_REXT A OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY F9 serdes4_rext SERDES4_REXT I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY E8 SERDES4_REFCLK_P SERDES4_REFCLK_P IO OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY AE8 serdes3_rext SERDES3_REXT A OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY AH19 SERDES0_RX0_N SERDES0_RX0_N I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII1_RXN0 I PCIE0_RXN0 I USB0_SSRX2N I AJ18 SERDES0_RX0_P SERDES0_RX0_P I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII1_RXP0 I PCIE0_RXP0 I USB0_SSRX2P I www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AH18 SERDES0_RX1_N SERDES0_RX1_N I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII2_RXN0 I PCIE0_RXN1 I USB0_SSRX1N I AJ17 SERDES0_RX1_P SERDES0_RX1_P I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII2_RXP0 I PCIE0_RXP1 I USB0_SSRX1P I AF19 SERDES0_TX0_N SERDES0_TX0_N O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII1_TXN0 O PCIE0_TXN0 O USB0_SSTX2N O AG18 SERDES0_TX0_P SERDES0_TX0_P O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII1_TXP0 O PCIE0_TXP0 O USB0_SSTX2P O AF18 SERDES0_TX1_N SERDES0_TX1_N O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII2_TXN0 O PCIE0_TXN1 O USB0_SSTX1N O AG17 SERDES0_TX1_P SERDES0_TX1_P O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII2_TXP0 O PCIE0_TXP1 O USB0_SSTX1P O AH15 SERDES1_RX0_N SERDES1_RX0_N I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII3_RXN0 I PCIE1_RXN0 I USB1_SSRX2N I PRG1_SGMII0_RXN0 I AJ14 SERDES1_RX0_P SERDES1_RX0_P I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII3_RXP0 I PCIE1_RXP0 I USB1_SSRX2P I PRG1_SGMII0_RXP0 I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AH16 SERDES1_RX1_N SERDES1_RX1_N I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII4_RXN0 I PCIE1_RXN1 I USB1_SSRX1N I PRG1_SGMII1_RXN0 I AJ15 SERDES1_RX1_P SERDES1_RX1_P I OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII4_RXP0 I PCIE1_RXP1 I USB1_SSRX1P I PRG1_SGMII1_RXP0 I AF15 SERDES1_TX0_N SERDES1_TX0_N O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII3_TXN0 O PCIE1_TXN0 O USB1_SSTX2N O PRG1_SGMII0_TXN0 O AG14 SERDES1_TX0_P SERDES1_TX0_P O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII3_TXP0 O PCIE1_TXP0 O USB1_SSTX2P O PRG1_SGMII0_TXP0 O AF16 SERDES1_TX1_N SERDES1_TX1_N O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII4_TXN0 O PCIE1_TXN1 O USB1_SSTX1N O PRG1_SGMII1_TXN0 O AG15 SERDES1_TX1_P SERDES1_TX1_P O OFF 0.8 V VDDA_0P8_SE RDES0_1 / VDD A_1P8_SERDE S0_1 2-L-PHY SGMII4_TXP0 O PCIE1_TXP1 O USB1_SSTX1P O PRG1_SGMII1_TXP0 O AH13 SERDES2_RX0_N SERDES2_RX0_N I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_RXN0 I USB1_SSRX2N I PRG1_SGMII0_RXN0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AJ12 SERDES2_RX0_P SERDES2_RX0_P I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_RXP0 I USB1_SSRX2P I PRG1_SGMII0_RXP0 AH12 SERDES2_RX1_N SERDES2_RX1_N I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_RXN1 I USB1_SSRX1N I PRG1_SGMII1_RXN0 AJ11 SERDES2_RX1_P SERDES2_RX1_P I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_RXP1 I USB1_SSRX1P I PRG1_SGMII1_RXP0 AF13 SERDES2_TX0_N SERDES2_TX0_N O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_TXN0 O USB1_SSTX2N O PRG1_SGMII0_TXN0 AG12 SERDES2_TX0_P SERDES2_TX0_P O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_TXP0 O USB1_SSTX2P O PRG1_SGMII0_TXP0 AF12 SERDES2_TX1_N SERDES2_TX1_N O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_TXN1 O USB1_SSTX1N O PRG1_SGMII1_TXN0 AG11 SERDES2_TX1_P SERDES2_TX1_P O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE2_TXP1 O USB1_SSTX1P O PRG1_SGMII1_TXP0 AH9 SERDES3_RX0_N SERDES3_RX0_N I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_RXN0 I USB0_SSRX2N I AJ8 SERDES3_RX0_P SERDES3_RX0_P I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_RXP0 I USB0_SSRX2P I AH10 SERDES3_RX1_N SERDES3_RX1_N I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_RXN1 I USB0_SSRX1N I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AJ9 SERDES3_RX1_P SERDES3_RX1_P I OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_RXP1 I USB0_SSRX1P I AF9 SERDES3_TX0_N SERDES3_TX0_N O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_TXN0 O USB0_SSTX2N O AG8 SERDES3_TX0_P SERDES3_TX0_P O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_TXP0 O USB0_SSTX2P O AF10 SERDES3_TX1_N SERDES3_TX1_N O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_TXN1 O USB0_SSTX1N O AG9 SERDES3_TX1_P SERDES3_TX1_P O OFF 0.8 V VDDA_0P8_SE RDES2_3 / VDD A_1P8_SERDE S2_3 2-L-PHY PCIE3_TXP1 O USB0_SSTX1P O D9 SERDES4_RX0_N SERDES4_RX0_N I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII5_RXN0 I C10 SERDES4_RX0_P SERDES4_RX0_P I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII5_RXP0 I D8 SERDES4_RX1_N SERDES4_RX1_N I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII6_RXN0 I C9 SERDES4_RX1_P SERDES4_RX1_P I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII6_RXP0 I D6 SERDES4_RX2_N SERDES4_RX2_N I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII7_RXN0 I C7 SERDES4_RX2_P SERDES4_RX2_P I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII7_RXP0 I D5 SERDES4_RX3_N SERDES4_RX3_N I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII8_RXN0 I C6 SERDES4_RX3_P SERDES4_RX3_P I OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY SGMII8_RXP0 I B11 SERDES4_TX0_N SERDES4_TX0_N O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX0_N O SGMII5_TXN0 O www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 A12 SERDES4_TX0_P SERDES4_TX0_P O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX0_P O SGMII5_TXP0 O B10 SERDES4_TX1_N SERDES4_TX1_N O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX1_N O SGMII6_TXN0 O A11 SERDES4_TX1_P SERDES4_TX1_P O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX1_P O SGMII6_TXP0 O B8 SERDES4_TX2_N SERDES4_TX2_N O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX2_N O SGMII7_TXN0 O A9 SERDES4_TX2_P SERDES4_TX2_P O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX2_P O SGMII7_TXP0 O B7 SERDES4_TX3_N SERDES4_TX3_N O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX3_N O SGMII8_TXN0 O A8 SERDES4_TX3_P SERDES4_TX3_P O OFF 0.8 V VDDA_0P8_DP VDDA_1P8_DP 4-L-PHY DP0_TX3_P O SGMII8_TXP0 O U4 soc_safety_errorn SOC_SAFETY_ERRORn 0 IO PD 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/0 AA1 spi0_clk SPI0_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 UART1_CTSn 1 I 1 I2C2_SCL 2 IOD 1 GPIO0_113 7 IO 0 Y1 spi1_clk SPI1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 UART5_CTSn 1 I 1 I2C4_SDA 2 IOD 1 UART2_RXD 3 I 1 GPIO0_118 7 IO 0 PRG0_IEP0_EDC_SYNC_OUT0 8 O 0 AA2 spi0_cs0 SPI0_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 UART0_RTSn 1 O GPIO0_111 7 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 Y4 spi0_cs1 SPI0_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 CPTS0_TS_COMP 1 O I2C3_SCL 2 IOD 1 DP0_HPD 5 I 0 PRG1_IEP0_EDIO_OUTVALID 6 O GPIO0_112 7 IO 0 AB5 spi0_d0 SPI0_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 UART1_RTSn 1 O I2C2_SDA 2 IOD 1 GPIO0_114 7 IO 0 AA3 spi0_d1 SPI0_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 I2C6_SCL 2 IOD 1 GPIO0_115 7 IO 0 Y3 spi1_cs0 SPI1_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 UART0_CTSn 1 I 1 UART5_RXD 3 I 1 PRG0_IEP0_EDIO_OUTVALID 6 O GPIO0_116 7 IO 0 PRG0_IEP0_EDC_LATCH_IN0 8 I 0 W4 spi1_cs1 SPI1_CS1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 CPTS0_TS_SYNC 1 O I2C3_SDA 2 IOD 1 UART5_TXD 3 O GPIO0_117 7 IO 0 Y5 spi1_d0 SPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 UART5_RTSn 1 O I2C4_SCL 2 IOD 1 UART2_TXD 3 O GPIO0_119 7 IO 0 PRG0_IEP1_EDC_LATCH_IN0 8 I 0 Y2 spi1_d1 SPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 0/1 I2C6_SDA 2 IOD 1 GPIO0_120 7 IO 0 PRG0_IEP1_EDC_SYNC_OUT0 8 O 0 E29 tck TCK 0 I PU 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 V1 tdi TDI 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1 V3 tdo TDO 0 OZ PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 V6 timer_io0 TIMER_IO0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 1/1 ECAP1_IN_APWM_OUT 1 IO 0 SYSCLKOUT0 2 O SPI7_D0 6 IO 0 GPIO1_13 7 IO 0 BOOTMODE4 Bootstrap I V5 timer_io1 TIMER_IO1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0 1/1 ECAP2_IN_APWM_OUT 1 IO 0 OBSCLK0 2 O SPI7_D1 6 IO 0 GPIO1_14 7 IO 0 BOOTMODE5 Bootstrap I V2 tms TMS 0 I PU 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1/1 F24 trstn TRSTn 0 I PD 0 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 AC2 uart0_ctsn UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 TIMER_IO6 1 IO 0 SPI0_CS2 2 IO 1 MCAN2_RX 3 I 1 SPI2_CS0 4 IO 1 EQEP0_A 5 I 0 GPIO0_123 7 IO 0 MLB0_MLBSIG 8 IO 0 AB1 uart0_rtsn UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 TIMER_IO7 1 IO 0 SPI0_CS3 2 IO 1 MCAN2_TX 3 O SPI2_CLK 4 IO 0 EQEP0_B 5 I 0 GPIO0_124 7 IO 0 AB2 uart0_rxd UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 SPI2_CS1 4 IO 1 GPIO0_121 7 IO 0 AB3 uart0_txd UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 SPI2_CS2 4 IO 1 SPI7_CS1 6 IO 1 GPIO0_122 7 IO 0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AC4 uart1_ctsn UART1_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 MCAN3_RX 1 I 1 SPI2_D0 4 IO 0 EQEP0_S 5 IO 0 GPIO0_127 7 IO 0 MLB0_MLBCLK 8 I 0 AD5 uart1_rtsn UART1_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 MCAN3_TX 1 O SPI2_D1 4 IO 0 EQEP0_I 5 IO 0 GPIO1_0 7 IO 0 MLB0_MLBDAT 8 IO 0 AA4 uart1_rxd UART1_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 1 0/1 SPI7_CS2 6 IO 1 GPIO0_125 7 IO 0 AB4 uart1_txd UART1_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 I3C0_SDAPULLEN 5 O SPI7_CS3 6 IO 1 GPIO0_126 7 IO 0 AE6 ufs0_ref_clk UFS0_REF_CLK O OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AD6 ufs0_rstn UFS0_RSTn O OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AH3 ufs0_rx_dn0 UFS0_RX_DN0 I OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AH4 ufs0_rx_dn1 UFS0_RX_DN1 I OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AJ2 ufs0_rx_dp0 UFS0_RX_DP0 I OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AJ3 ufs0_rx_dp1 UFS0_RX_DP1 I OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AG6 ufs0_tx_dn0 UFS0_TX_DN0 O OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AG5 ufs0_tx_dn1 UFS0_TX_DN1 O OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AF7 ufs0_tx_dp0 UFS0_TX_DP0 O OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AF6 ufs0_tx_dp1 UFS0_TX_DP1 O OFF 0.8 V VDDA_0P8_UF S / VDDA_1P8_UF S M-PHY AJ5 usb0_dm USB0_DM IO OFF 3.3 V VDDA_0P8_US B / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AH6 usb0_dp USB0_DP IO OFF 3.3 V VDDA_0P8_US B / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY U6 usb0_drvvbus USB0_DRVVBUS 0 O PD 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD 0/1 USB1_DRVVBUS 1 O GPIO1_29 7 IO 0 AC6 usb0_id USB0_ID A OFF 3.3 V VDDA_0P8_US B / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AB6 usb0_rcalib USB0_RCALIB IO OFF 3.3 V VDDA_0P8_US B / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AC7 usb0_vbus USB0_VBUS A OFF 3.3 V VDDA_0P8_US B / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 AH7 usb1_dm USB1_DM IO OFF 3.3 V VDDA_0P8_U SB / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AJ6 usb1_dp USB1_DP IO OFF 3.3 V VDDA_0P8_U SB / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AD7 usb1_id USB1_ID A OFF 3.3 V VDDA_0P8_U SB / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AD9 usb1_rcalib USB1_RCALIB IO OFF 3.3 V VDDA_0P8_U SB / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY AD8 usb1_vbus USB1_VBUS A OFF 3.3 V VDDA_0P8_U SB / VDDA_1P8_US B / VDDA_3P3_US B USB2PHY L14, V13, V16, W19 VDDAR_CORE VDDAR_CORE PWR L11, W12 VDDAR_CPU VDDAR_CPU PWR K19, T19 vddar_mcu vddar_mcu PWR H17 VDDA_0P8_CSIRX VDDA_0P8_CSIRX PWR G12, J12 VDDA_0P8_DP VDDA_0P8_DP PWR G14, H13 VDDA_0P8_DP_C VDDA_0P8_DP_C PWR H15 VDDA_0P8_DSITX VDDA_0P8_DSITX PWR J16 VDDA_0P8_DSITX_C VDDA_0P8_DSITX_C PWR AB9 VDDA_0P8_UFS VDDA_0P8_UFS PWR AA10 VDDA_0P8_USB VDDA_0P8_USB PWR AA15, Y14, Y16 VDDA_0P8_SERDES0_1 VDDA_0P8_SERDES0_1 PWR AA12, Y11, Y13 VDDA_0P8_SERDES2_3 VDDA_0P8_SERDES2_3 PWR AB14, AB15 VDDA_0P8_SERDES_C0_1 VDDA_0P8_SERDES_C0_1 PWR AB12, AB13 VDDA_0P8_SERDES_C2_3 VDDA_0P8_SERDES_C2_3 PWR G16 VDDA_1P8_CSIRX VDDA_1P8_CSIRX PWR www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 H11 VDDA_1P8_DP VDDA_1P8_DP PWR J14 VDDA_1P8_DSITX VDDA_1P8_DSITX PWR AC8 VDDA_1P8_UFS VDDA_1P8_UFS PWR AC9 vdda_1p8_usb vdda_1p8_usb PWR AC14, AC15 VDDA_1P8_SERDES0_1 VDDA_1P8_SERDES0_1 PWR AC11, AC12 VDDA_1P8_SERDES2_3 VDDA_1P8_SERDES2_3 PWR AB10 vdda_3p3_usb vdda_3p3_usb PWR N22 VDDA_ADC0 VDDA_ADC0 PWR M23 VDDA_ADC1 VDDA_ADC1 PWR N9 VDDA_0P8_PLL_DDR VDDA_0P8_PLL_DDR PWR G18 VDDA_MCU_PLLGRP0 VDDA_MCU_PLLGRP0 PWR P21 VDDA_MCU_TEMP VDDA_MCU_TEMP PWR W7 VDDA_1P8_MLB VDDA_1P8_MLB PWR Y20 VDDA_PLLGRP0 VDDA_PLLGRP0 PWR W17 VDDA_PLLGRP1 VDDA_PLLGRP1 PWR M17 VDDA_PLLGRP2 VDDA_PLLGRP2 PWR L12 VDDA_PLLGRP3 VDDA_PLLGRP3 PWR R11 VDDA_PLLGRP4 VDDA_PLLGRP4 PWR P9 VDDA_PLLGRP5 VDDA_PLLGRP5 PWR W18 VDDA_PLLGRP6 VDDA_PLLGRP6 PWR W8 VDDA_0P8_PLL_MLB VDDA_0P8_PLL_MLB PWR P22 vdda_por_wkup vdda_por_wkup PWR W15 VDDA_TEMP0_1 VDDA_TEMP0_1 PWR H9 VDDA_TEMP2_3 VDDA_TEMP2_3 PWR M26 VMON_ER_VSYS VMON_ER_VSYS A V19 VMON_IR_VEXT VMON_IR_VEXT A H22 VDDA_WKUP VDDA_WKUP PWR U8, V7 VDDSHV0 VDDSHV0 PWR L22, M22 VDDSHV0_MCU VDDSHV0_MCU PWR AA19, AA20, AC19, AC20 VDDSHV1 VDDSHV1 PWR H19, H21, J20 VDDSHV1_MCU VDDSHV1_MCU PWR AA17, AB16, AB18, AC17 VDDSHV2 VDDSHV2 PWR J22, K21 VDDSHV2_MCU VDDSHV2_MCU PWR V21, W22 VDDSHV3 VDDSHV3 PWR AA21, Y22 VDDSHV4 VDDSHV4 PWR T20, T22 VDDSHV5 VDDSHV5 PWR DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 U20, U22 VDDSHV6 VDDSHV6 PWR A1, G8, J8, K7, L8, M7, N8, P7, R8, T1 vdds_ddr vdds_ddr PWR H7, J6, R6, T7 vdds_ddr_bias vdds_ddr_bias PWR M9 VDDS_DDR_C VDDS_DDR_C PWR AA8, AB7, Y7 vdds_mmc0 vdds_mmc0 PWR R21 VDDS_OSC1 VDDS_OSC1 PWR J10, K11, K13, K15, K17, K9, L10, L16, L18, M15, N14, N16, N18, P13, P15, P17, R14, R16, R18, R20, T15, T17, T9, U14, U16, U18, V15, V17, V20, W14 VDD_CORE VDD_CORE PWR N10, P11, R10, R12, U10, V11, V9, W10 VDD_CPU VDD_CPU PWR Y9 VDDA_0P8_DLL_MMC0 VDDA_0P8_DLL_MMC0 PWR L20, M19, M21, N20, P19 vdd_mcu vdd_mcu PWR AB11 vpp_core vpp_core PWR F17 VPP_MCU VPP_MCU PWR AA13, AC10, AC13, AD11, AD14, AD17, AE10, AE12, AE15, AE16, AE19, AE7, AF20, AF25, AF5, AG4, AG7, AH2, AH20, AH5, AJ4, AJ7, B3, B6, C1, C5, D2, D4, E1, E5, F4, G1, G7, H4, H6, K1, K4, L3, M1, M28, M4, M6, N27, N29, N3, P1, P28, P4, R3, U5 vss vss GND www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 A10, A13, A16, A19, A22, A7, AA11, AA14, AA16, AA18, AA7, AA9, AB17, AB19, AB20, AB22, AB8, AC16, AF11, AF14, AF17, AF8, AG10, AG13, AG16, AG19, AH11, AH14, AH17, AH8, AJ10, AJ13, AJ16, AJ19, B12, B15, B18, B21, B9, C11, C14, C17, C20, C8, D10, D13, D16, D19, D7, E12, E15, E9, F14, F8, G11, G13, G15, G17, H10, H12, H14, H16, H18, H20, H8, J11, J13, J15, J17, J21, J23, J7, J9, K10, K12, K14, K16, K18, K20, K22, K8, L13, L15, L17, L19, L21, L23, L7, L9, M10, M14, M16, M18, M20, M8, N15, N17, N19, N21, N7, P10, P12, P14, P16, P18, P20, P8, R13, R15, R17, R19, R7, R9, T10, T14, T16, T18, T21, T8, U15, U17, U19, U21, U9, V10, V12, V14, V18, V8, W11, W13, W16, W20, W9, Y10, Y12, Y15, Y17, Y19, Y21, Y8 VSS VSS GND DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 F26 wkup_gpio0_0 MCU_SPI1_CLK 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 1/1 MCU_SPI1_CLK 1 IO 0 WKUP_GPIO0_0 7 IO 0 MCU_BOOTMODE03 Bootstrap I F25 wkup_gpio0_1 MCU_SPI1_D0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 1/1 MCU_SPI1_D0 1 IO 0 WKUP_GPIO0_1 7 IO 0 MCU_BOOTMODE04 Bootstrap I F28 wkup_gpio0_2 MCU_SPI1_D1 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 1/1 MCU_SPI1_D1 1 IO 0 WKUP_GPIO0_2 7 IO 0 MCU_BOOTMODE05 Bootstrap I F27 wkup_gpio0_3 MCU_SPI1_CS0 0 IO OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_SPI1_CS0 1 IO 1 WKUP_GPIO0_3 7 IO 0 G25 wkup_gpio0_4 MCU_MCAN1_TX 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/1 MCU_MCAN1_TX 1 O MCU_SPI0_CS3 2 IO 1 MCU_ADC_EXT_TRIGGER0 3 I pad WKUP_GPIO0_4 7 IO 0 G24 wkup_gpio0_5 MCU_MCAN1_RX 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_MCAN1_RX 1 I 1 MCU_SPI1_CS3 2 IO 1 MCU_ADC_EXT_TRIGGER1 3 I pad WKUP_GPIO0_5 7 IO 0 F29 wkup_gpio0_6 WKUP_UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 WKUP_UART0_CTSn 1 I 1 MCU_CPTS0_HW1TSPUSH 2 I 0 MCU_I2C1_SCL 3 IOD 1 WKUP_GPIO0_6 7 IO 0 G28 wkup_gpio0_7 WKUP_UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/1 WKUP_UART0_RTSn 1 O MCU_CPTS0_HW2TSPUSH 2 I 0 MCU_I2C1_SDA 3 IOD 1 WKUP_GPIO0_7 7 IO 0 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 G27 wkup_gpio0_8 MCU_I2C1_SCL 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_I2C1_SCL 1 IOD 1 MCU_CPTS0_TS_SYNC 2 O MCU_I3C1_SCL 3 IO 1 MCU_TIMER_IO6 4 IO 0 WKUP_GPIO0_8 7 IO 0 G26 wkup_gpio0_9 MCU_I2C1_SDA 0 IOD OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 MCU_I2C1_SDA 1 IOD 1 MCU_CPTS0_TS_COMP 2 O MCU_I3C1_SDA 3 IO 1 MCU_TIMER_IO7 4 IO 0 WKUP_GPIO0_9 7 IO 0 H26 wkup_gpio0_10 MCU_EXT_REFCLK0 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0 0/1 MCU_EXT_REFCLK0 1 I 0 MCU_UART0_TXD 2 O MCU_ADC_EXT_TRIGGER0 3 I 0 MCU_CPTS0_RFT_CLK 4 I 0 MCU_SYSCLKOUT0 5 O WKUP_GPIO0_10 7 IO 0 H27 wkup_gpio0_11 MCU_OBSCLK0 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/1 MCU_OBSCLK0 1 O MCU_UART0_RXD 2 I 1 MCU_ADC_EXT_TRIGGER1 3 I 0 MCU_TIMER_IO1 4 IO 0 MCU_I3C1_SDAPULLEN 5 O MCU_CLKOUT0 6 OZ WKUP_GPIO0_11 7 IO 0 G29 wkup_gpio0_12 MCU_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 MCU_SPI0_CS1 1 O WKUP_GPIO0_12 7 IO 0 MCU_BOOTMODE08 Bootstrap I H28 wkup_gpio0_13 MCU_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 1/1 MCU_SPI1_CS1 1 O WKUP_GPIO0_13 7 IO 0 MCU_BOOTMODE09 Bootstrap I DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-1. Pin Attributes (continued) BALL NO. 1 BALL NAME 2 SIGNAL NAME 3 MUXMODE REL. MUXMODE I/O VOLTAGE VALUE 8 POWER 9 HYS 10 BUFFER TYPE 11 PULL UP/ DOWN TYPE 12 DSIS 13 RXACTIVE/ TXDISABL E 14 H29 wkup_gpio0_14 MCU_UART0_CTSn 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 1/1 MCU_SPI0_CS2 1 O WKUP_GPIO0_14 7 IO 0 MCU_BOOTMODE06 Bootstrap I J27 wkup_gpio0_15 MCU_UART0_RTSn 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1/1 MCU_SPI1_CS2 1 O WKUP_GPIO0_15 7 IO 0 MCU_BOOTMODE07 Bootstrap I J25 wkup_i2c0_scl WKUP_I2C0_SCL 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes I2C OD FS 1 1/0 WKUP_GPIO0_62 7 IO 0 H24 wkup_i2c0_sda WKUP_I2C0_SDA 0 IOD OFF 0 1.8 V/3.3 V VDDSHV0_MC U Yes I2C OD FS 1 1/0 WKUP_GPIO0_63 7 IO 0 N28 wkup_lfosc0_xi WKUP_LFOSC0_XI I OFF 1.8 V VDDA_WKUP LFOSC N26 wkup_lfosc0_xo WKUP_LFOSC0_XO O OFF 1.8 V VDDA_WKUP LFOSC M29 wkup_osc0_xi WKUP_OSC0_XI I OFF 1.8 V VDDA_WKUP HFOSC M27 wkup_osc0_xo WKUP_OSC0_XO O OFF 1.8 V VDDA_WKUP HFOSC J29 wkup_uart0_rxd WKUP_UART0_RXD 0 I OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 1 0/1 WKUP_GPIO0_56 7 IO 0 J28 wkup_uart0_txd WKUP_UART0_TXD 0 O OFF 7 1.8 V/3.3 V VDDSHV0_MC U Yes LVCMOS PU/PD 0/1 WKUP_GPIO0_57 7 IO 0 1. The MUXMODE field is not used to select the multiplexed signal function for this pin. For more information, see ADC Integration Details section in Device Configuration chapter of the device TRM. The following list describes the table column headers: 1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom. 2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0). 3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0). Note Table 5-1, Pin Attributes, does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 5.3, Signal Descriptions. 4. MUXMODE: Multiplexing mode number: a. MUXMODE 0 is the primary muxmode. The primary muxmode is not necessarily the default muxmode. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

The default muxmode is the mode at the release of the reset; also see the BALL RESET REL. MUXMODE column. b. MUXMODE 1 through 7 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used. c. MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. BOOTMODE pins are latched on the rising edge of PORz_OUT. d. An empty box means Not Applicable. 5. TYPE: Signal type and direction:

• I = Input
• O = Output
• IO = Input or Output
• IOD = Open drain terminal - Input or Output
• IOZ = Input, Output or Three-state terminal
• OZ = Output or Three-state terminal
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor. 6. BALL RESET STATE: The state of the terminal at power-on reset:
• DRIVE 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
• DRIVE 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
• OFF: High-impedance
• PD: High-impedance with an active pulldown resistor
• PU: High-impedance with an active pullup resistor
• An empty box means Not Applicable. 7. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal. An empty box means Not Applicable. 8. I/O VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply). An empty box means Not Applicable. 9. POWER: The voltage supply that powers the terminal IO buffers. An empty box means Not Applicable. 10. HYS: Indicates if the input buffer has hysteresis:
• Yes: With hysteresis
• No: Without hysteresis An empty box means No. For more information, see the hysteresis values in, Electrical Characteristics. 11. BUFFER TYPE: This column describes the associated output buffer type DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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An empty box means Not Applicable. For drive strength of the associated output buffer, refer to, Electrical Characteristics. 12. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.

• PU: Internal pullup
• PD: Internal pulldown
• PU/PD: Internal pullup and pulldown
• An empty box means No pull. 13. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin function is not selected by any of the PINCNTLx registers.
• 0: Logic 0 driven on the input signal port of the peripheral.
• 1: Logic 1 driven on the input signal port of the peripheral.
• An empty box means Not Applicable. 14. RXACTIVE / TXDISABLE: This column indicates the default value of the RXACTIVE / TXDISABLE bits in the PADCONFIG register.
• RXACTIVE: 0 = receiver disabled, 1 = receiver enabled.
• TXDISABLE: 0 = driver enabled, 1 = driver disabled.
• An empty box means Not Applicable. Note Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (HiZ mode is not an input signal). Note When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.3 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options. The following list describes the column headers: 1. SIGNAL NAME: The name of the signal passing through the pin. Note In Pin Attributes and Pin Multiplexing are not described the subsystem multiplexing signals. 2. DESCRIPTION: Description of the signal 3. PIN TYPE: Signal direction and type:

• I = Input
• O = Output
• IO = Input or Output
• IOD = Open drain terminal - Input or Output
• IOZ = Input, Output or Three-state terminal
• OZ = Output or Three-state terminal
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor 4. BALL: Associated balls bottom For more information on the I/O cell configurations, see Pad Configuration Registers section of Device Configuration chapter in the MAIN.

5.3.1 ADC

The ADC can be configured to be used as a GPI. For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.

5.3.1.1 MCU Domain

Table 5-2. ADC Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC_EXT_TRIGGER0 ADC Trigger Input I A28, G25, H26 MCU_ADC_EXT_TRIGGER1 ADC Trigger Input I A27, G24, H27 Table 5-3. ADC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC0_AIN0 ADC Analog Input 0 A K25 MCU_ADC0_AIN1 ADC Analog Input 1 A K26 MCU_ADC0_AIN2 ADC Analog Input 2 A K28 MCU_ADC0_AIN3 ADC Analog Input 3 A L28 MCU_ADC0_AIN4 ADC Analog Input 4 A K24 MCU_ADC0_AIN5 ADC Analog Input 5 A K27 MCU_ADC0_AIN6 ADC Analog Input 6 A K29 MCU_ADC0_AIN7 ADC Analog Input 7 A L29 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-4. ADC1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_ADC1_AIN0 ADC Analog Input 0 A N23 MCU_ADC1_AIN1 ADC Analog Input 1 A M25 MCU_ADC1_AIN2 ADC Analog Input 2 A L24 MCU_ADC1_AIN3 ADC Analog Input 3 A L26 MCU_ADC1_AIN4 ADC Analog Input 4 A N24 MCU_ADC1_AIN5 ADC Analog Input 5 A M24 MCU_ADC1_AIN6 ADC Analog Input 6 A L25 MCU_ADC1_AIN7 ADC Analog Input 7 A L27

5.3.2 DDRSS

5.3.2.1 MAIN Domain

Table 5-5. DDRSS Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DDR_RET External IO Retention Enable I P6 Table 5-6. DDRSS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DDR0_CKN DDRSS Differential Clock (negative) IO J1 DDR0_CKP DDRSS Differential Clock (positive) IO H1 DDR0_RESETn DDRSS Reset IO K6 DDR0_CA0 DDRSS Command Address IO G4 DDR0_CA1 DDRSS Command Address IO H3 DDR0_CA2 DDRSS Command Address IO K5 DDR0_CA3 DDRSS Command Address IO J4 DDR0_CA4 DDRSS Command Address IO K2 DDR0_CA5 DDRSS Command Address IO H5 DDR0_CAL0 (1) IO Pad Calibration Resistor A H2 DDR0_CKE0 DDRSS Clock Enable IO G3 DDR0_CKE1 DDRSS Clock Enable IO J3 DDR0_CSn0_0 DDRSS Chip Select IO J5 DDR0_CSn0_1 DDRSS Chip Select IO K3 DDR0_CSn1_0 DDRSS Chip Select IO G5 DDR0_CSn1_1 DDRSS Chip Select IO J2 DDR0_DM0 DDRSS Data Mask IO A3 DDR0_DM1 DDRSS Data Mask IO E4 DDR0_DM2 DDRSS Data Mask IO N1 DDR0_DM3 DDRSS Data Mask IO R5 DDR0_DQ0 DDRSS Data IO A5 DDR0_DQ1 DDRSS Data IO A6 DDR0_DQ2 DDRSS Data IO B5 DDR0_DQ3 DDRSS Data IO C2 DDR0_DQ4 DDRSS Data IO B4 DDR0_DQ5 DDRSS Data IO C3 DDR0_DQ6 DDRSS Data IO A2 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-6. DDRSS0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DDR0_DQ7 DDRSS Data IO A4 DDR0_DQ8 DDRSS Data IO D1 DDR0_DQ9 DDRSS Data IO C4 DDR0_DQ10 DDRSS Data IO F1 DDR0_DQ11 DDRSS Data IO G2 DDR0_DQ12 DDRSS Data IO F2 DDR0_DQ13 DDRSS Data IO F3 DDR0_DQ14 DDRSS Data IO D3 DDR0_DQ15 DDRSS Data IO F5 DDR0_DQ16 DDRSS Data IO L5 DDR0_DQ17 DDRSS Data IO M5 DDR0_DQ18 DDRSS Data IO N5 DDR0_DQ19 DDRSS Data IO L4 DDR0_DQ20 DDRSS Data IO L2 DDR0_DQ21 DDRSS Data IO L1 DDR0_DQ22 DDRSS Data IO N2 DDR0_DQ23 DDRSS Data IO N4 DDR0_DQ24 DDRSS Data IO T3 DDR0_DQ25 DDRSS Data IO T2 DDR0_DQ26 DDRSS Data IO P2 DDR0_DQ27 DDRSS Data IO P3 DDR0_DQ28 DDRSS Data IO P5 DDR0_DQ29 DDRSS Data IO R4 DDR0_DQ30 DDRSS Data IO T4 DDR0_DQ31 DDRSS Data IO T5 DDR0_DQS0N DDRSS Complimentary Data Strobe IO B1 DDR0_DQS0P DDRSS Data Strobe IO B2 DDR0_DQS1N DDRSS Complimentary Data Strobe IO E2 DDR0_DQS1P DDRSS Data Strobe IO E3 DDR0_DQS2N DDRSS Complimentary Data Strobe IO M2 DDR0_DQS2P DDRSS Data Strobe IO M3 DDR0_DQS3N DDRSS Complimentary Data Strobe IO R1 DDR0_DQS3P DDRSS Data Strobe IO R2 (1) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.

5.3.3 GPIO

5.3.3.1 MAIN Domain

Table 5-7. GPIO0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_0 General Purpose Input/Output IO AC18 GPIO0_1 General Purpose Input/Output IO AC23 GPIO0_2 General Purpose Input/Output IO AG22 GPIO0_3 General Purpose Input/Output IO AF22 GPIO0_4 General Purpose Input/Output IO AJ23 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-7. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_5 General Purpose Input/Output IO AH23 GPIO0_6 General Purpose Input/Output IO AD20 GPIO0_7 General Purpose Input/Output IO AD22 GPIO0_8 General Purpose Input/Output IO AE20 GPIO0_9 General Purpose Input/Output IO AJ20 GPIO0_10 General Purpose Input/Output IO AG20 GPIO0_11 General Purpose Input/Output IO AD21 GPIO0_12 General Purpose Input/Output IO AF24 GPIO0_13 General Purpose Input/Output IO AJ24 GPIO0_14 General Purpose Input/Output IO AG24 GPIO0_15 General Purpose Input/Output IO AD24 GPIO0_16 General Purpose Input/Output IO AC24 GPIO0_17 General Purpose Input/Output IO AE24 GPIO0_18 General Purpose Input/Output IO AJ21 GPIO0_19 General Purpose Input/Output IO AE21 GPIO0_100 General Purpose Input/Output IO W28 GPIO0_101 General Purpose Input/Output IO V25 GPIO0_102 General Purpose Input/Output IO W27 GPIO0_103 General Purpose Input/Output IO W29 GPIO0_104 General Purpose Input/Output IO W26 GPIO0_105 General Purpose Input/Output IO Y29 GPIO0_106 General Purpose Input/Output IO Y27 GPIO0_107 General Purpose Input/Output IO W24 GPIO0_108 General Purpose Input/Output IO W25 GPIO0_109 General Purpose Input/Output IO V26 GPIO0_110 General Purpose Input/Output IO V24 GPIO0_111 General Purpose Input/Output IO AA2 GPIO0_112 General Purpose Input/Output IO Y4 GPIO0_113 General Purpose Input/Output IO AA1 GPIO0_114 General Purpose Input/Output IO AB5 GPIO0_115 General Purpose Input/Output IO AA3 GPIO0_116 General Purpose Input/Output IO Y3 GPIO0_117 General Purpose Input/Output IO W4 GPIO0_118 General Purpose Input/Output IO Y1 GPIO0_119 General Purpose Input/Output IO Y5 GPIO0_120 General Purpose Input/Output IO Y2 GPIO0_121 General Purpose Input/Output IO AB2 GPIO0_122 General Purpose Input/Output IO AB3 GPIO0_123 General Purpose Input/Output IO AC2 GPIO0_124 General Purpose Input/Output IO AB1 GPIO0_125 General Purpose Input/Output IO AA4 GPIO0_126 General Purpose Input/Output IO AB4 GPIO0_127 General Purpose Input/Output IO AC4 GPIO0_20 General Purpose Input/Output IO AH21 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-7. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_21 General Purpose Input/Output IO AE22 GPIO0_22 General Purpose Input/Output IO AG23 GPIO0_23 General Purpose Input/Output IO AF23 GPIO0_24 General Purpose Input/Output IO AD23 GPIO0_25 General Purpose Input/Output IO AH24 GPIO0_26 General Purpose Input/Output IO AG21 GPIO0_27 General Purpose Input/Output IO AE23 GPIO0_28 General Purpose Input/Output IO AC21 GPIO0_29 General Purpose Input/Output IO Y23 GPIO0_30 General Purpose Input/Output IO AF21 GPIO0_31 General Purpose Input/Output IO AB23 GPIO0_32 General Purpose Input/Output IO AJ25 GPIO0_33 General Purpose Input/Output IO AH25 GPIO0_34 General Purpose Input/Output IO AG25 GPIO0_35 General Purpose Input/Output IO AH26 GPIO0_36 General Purpose Input/Output IO AJ27 GPIO0_37 General Purpose Input/Output IO AJ26 GPIO0_38 General Purpose Input/Output IO AC22 GPIO0_39 General Purpose Input/Output IO AJ22 GPIO0_40 General Purpose Input/Output IO AH22 GPIO0_41 General Purpose Input/Output IO AD19 GPIO0_42 General Purpose Input/Output IO AD18 GPIO0_43 General Purpose Input/Output IO AF28 GPIO0_44 General Purpose Input/Output IO AE28 GPIO0_45 General Purpose Input/Output IO AE27 GPIO0_46 General Purpose Input/Output IO AD26 GPIO0_47 General Purpose Input/Output IO AD25 GPIO0_48 General Purpose Input/Output IO AC29 GPIO0_49 General Purpose Input/Output IO AE26 GPIO0_50 General Purpose Input/Output IO AC28 GPIO0_51 General Purpose Input/Output IO AC27 GPIO0_52 General Purpose Input/Output IO AB26 GPIO0_53 General Purpose Input/Output IO AB25 GPIO0_54 General Purpose Input/Output IO AJ28 GPIO0_55 General Purpose Input/Output IO AH27 GPIO0_56 General Purpose Input/Output IO AH29 GPIO0_57 General Purpose Input/Output IO AG28 GPIO0_58 General Purpose Input/Output IO AG27 GPIO0_59 General Purpose Input/Output IO AH28 GPIO0_60 General Purpose Input/Output IO AB24 GPIO0_61 General Purpose Input/Output IO AB29 GPIO0_62 General Purpose Input/Output IO AB28 GPIO0_63 General Purpose Input/Output IO AE29 GPIO0_64 General Purpose Input/Output IO AD28 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-7. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO0_65 General Purpose Input/Output IO AD27 GPIO0_66 General Purpose Input/Output IO AC25 GPIO0_67 General Purpose Input/Output IO AD29 GPIO0_68 General Purpose Input/Output IO AB27 GPIO0_69 General Purpose Input/Output IO AC26 GPIO0_70 General Purpose Input/Output IO AA24 GPIO0_71 General Purpose Input/Output IO AA28 GPIO0_72 General Purpose Input/Output IO Y24 GPIO0_73 General Purpose Input/Output IO AA25 GPIO0_74 General Purpose Input/Output IO AG26 GPIO0_75 General Purpose Input/Output IO AF27 GPIO0_76 General Purpose Input/Output IO AF26 GPIO0_77 General Purpose Input/Output IO AE25 GPIO0_78 General Purpose Input/Output IO AF29 GPIO0_79 General Purpose Input/Output IO AG29 GPIO0_80 General Purpose Input/Output IO Y25 GPIO0_81 General Purpose Input/Output IO AA26 GPIO0_82 General Purpose Input/Output IO AA29 GPIO0_83 General Purpose Input/Output IO Y26 GPIO0_84 General Purpose Input/Output IO AA27 GPIO0_85 General Purpose Input/Output IO U23 GPIO0_86 General Purpose Input/Output IO U26 GPIO0_87 General Purpose Input/Output IO V28 GPIO0_88 General Purpose Input/Output IO V29 GPIO0_89 General Purpose Input/Output IO V27 GPIO0_90 General Purpose Input/Output IO U28 GPIO0_91 General Purpose Input/Output IO U29 GPIO0_92 General Purpose Input/Output IO U25 GPIO0_93 General Purpose Input/Output IO U27 GPIO0_94 General Purpose Input/Output IO U24 GPIO0_95 General Purpose Input/Output IO R23 GPIO0_96 General Purpose Input/Output IO T23 GPIO0_97 General Purpose Input/Output IO Y28 GPIO0_98 General Purpose Input/Output IO V23 GPIO0_99 General Purpose Input/Output IO W23 Table 5-8. GPIO1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO1_0 General Purpose Input/Output IO AD5 GPIO1_1 General Purpose Input/Output IO W5 GPIO1_2 General Purpose Input/Output IO W6 GPIO1_3 General Purpose Input/Output IO W3 GPIO1_4 General Purpose Input/Output IO V4 GPIO1_5 General Purpose Input/Output IO W2 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-8. GPIO1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPIO1_6 General Purpose Input/Output IO W1 GPIO1_7 General Purpose Input/Output IO AC5 GPIO1_8 General Purpose Input/Output IO AA5 GPIO1_9 General Purpose Input/Output IO Y6 GPIO1_10 General Purpose Input/Output IO AA6 GPIO1_11 General Purpose Input/Output IO U2 GPIO1_12 General Purpose Input/Output IO U3 GPIO1_13 General Purpose Input/Output IO V6 GPIO1_14 General Purpose Input/Output IO V5 GPIO1_15 General Purpose Input/Output IO R26 GPIO1_16 General Purpose Input/Output IO R25 GPIO1_17 General Purpose Input/Output IO P24 GPIO1_18 General Purpose Input/Output IO R24 GPIO1_19 General Purpose Input/Output IO P25 GPIO1_20 General Purpose Input/Output IO R29 GPIO1_21 General Purpose Input/Output IO P23 GPIO1_22 General Purpose Input/Output IO R28 GPIO1_23 General Purpose Input/Output IO T28 GPIO1_24 General Purpose Input/Output IO T29 GPIO1_25 General Purpose Input/Output IO T27 GPIO1_26 General Purpose Input/Output IO T24 GPIO1_27 General Purpose Input/Output IO T26 GPIO1_28 General Purpose Input/Output IO T25 GPIO1_29 General Purpose Input/Output IO U6 GPIO1_30 General Purpose Input/Output IO AD1 GPIO1_31 General Purpose Input/Output IO AC1 GPIO1_32 General Purpose Input/Output IO AC3 GPIO1_33 General Purpose Input/Output IO AD3 GPIO1_34 General Purpose Input/Output IO AD2 GPIO1_35 General Purpose Input/Output IO AE2

5.3.3.2 WKUP Domain

Table 5-9. GPIO0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_GPIO0_0 General Purpose Input/Output IO F26 WKUP_GPIO0_1 General Purpose Input/Output IO F25 WKUP_GPIO0_2 General Purpose Input/Output IO F28 WKUP_GPIO0_3 General Purpose Input/Output IO F27 WKUP_GPIO0_4 General Purpose Input/Output IO G25 WKUP_GPIO0_5 General Purpose Input/Output IO G24 WKUP_GPIO0_6 General Purpose Input/Output IO F29 WKUP_GPIO0_7 General Purpose Input/Output IO G28 WKUP_GPIO0_8 General Purpose Input/Output IO G27 WKUP_GPIO0_9 General Purpose Input/Output IO G26 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-9. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_GPIO0_10 General Purpose Input/Output IO H26 WKUP_GPIO0_11 General Purpose Input/Output IO H27 WKUP_GPIO0_12 General Purpose Input/Output IO G29 WKUP_GPIO0_13 General Purpose Input/Output IO H28 WKUP_GPIO0_14 General Purpose Input/Output IO H29 WKUP_GPIO0_15 General Purpose Input/Output IO J27 WKUP_GPIO0_16 General Purpose Input/Output IO E20 WKUP_GPIO0_17 General Purpose Input/Output IO C21 WKUP_GPIO0_18 General Purpose Input/Output IO D21 WKUP_GPIO0_19 General Purpose Input/Output IO D20 WKUP_GPIO0_20 General Purpose Input/Output IO G19 WKUP_GPIO0_21 General Purpose Input/Output IO G20 WKUP_GPIO0_22 General Purpose Input/Output IO F20 WKUP_GPIO0_23 General Purpose Input/Output IO F21 WKUP_GPIO0_24 General Purpose Input/Output IO E21 WKUP_GPIO0_25 General Purpose Input/Output IO B22 WKUP_GPIO0_26 General Purpose Input/Output IO G21 WKUP_GPIO0_27 General Purpose Input/Output IO F19 WKUP_GPIO0_28 General Purpose Input/Output IO E19 WKUP_GPIO0_29 General Purpose Input/Output IO F22 WKUP_GPIO0_30 General Purpose Input/Output IO A23 WKUP_GPIO0_31 General Purpose Input/Output IO B23 WKUP_GPIO0_32 General Purpose Input/Output IO D22 WKUP_GPIO0_33 General Purpose Input/Output IO G22 WKUP_GPIO0_34 General Purpose Input/Output IO D23 WKUP_GPIO0_35 General Purpose Input/Output IO C23 WKUP_GPIO0_36 General Purpose Input/Output IO C22 WKUP_GPIO0_37 General Purpose Input/Output IO E22 WKUP_GPIO0_38 General Purpose Input/Output IO B27 WKUP_GPIO0_39 General Purpose Input/Output IO C25 WKUP_GPIO0_40 General Purpose Input/Output IO A28 WKUP_GPIO0_41 General Purpose Input/Output IO A27 WKUP_GPIO0_42 General Purpose Input/Output IO A26 WKUP_GPIO0_43 General Purpose Input/Output IO B25 WKUP_GPIO0_44 General Purpose Input/Output IO B26 WKUP_GPIO0_45 General Purpose Input/Output IO C24 WKUP_GPIO0_46 General Purpose Input/Output IO A25 WKUP_GPIO0_47 General Purpose Input/Output IO D24 WKUP_GPIO0_48 General Purpose Input/Output IO A24 WKUP_GPIO0_49 General Purpose Input/Output IO B24 WKUP_GPIO0_50 General Purpose Input/Output IO E23 WKUP_GPIO0_51 General Purpose Input/Output IO F23 WKUP_GPIO0_52 General Purpose Input/Output IO E27 WKUP_GPIO0_53 General Purpose Input/Output IO E24 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-9. GPIO0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_GPIO0_54 General Purpose Input/Output IO E28 WKUP_GPIO0_55 General Purpose Input/Output IO E25 WKUP_GPIO0_56 General Purpose Input/Output IO J29 WKUP_GPIO0_57 General Purpose Input/Output IO J28 WKUP_GPIO0_58 General Purpose Input/Output IO D29 WKUP_GPIO0_59 General Purpose Input/Output IO C29 WKUP_GPIO0_60 General Purpose Input/Output IO D26 WKUP_GPIO0_61 General Purpose Input/Output IO D25 WKUP_GPIO0_62 General Purpose Input/Output IO J25 WKUP_GPIO0_63 General Purpose Input/Output IO H24 WKUP_GPIO0_64 General Purpose Input/Output IO J26 WKUP_GPIO0_65 General Purpose Input/Output IO H25 WKUP_GPIO0_66 General Purpose Input/Output IO E26 WKUP_GPIO0_67 General Purpose Input/Output IO G23 WKUP_GPIO0_68 General Purpose Input I K25 WKUP_GPIO0_69 General Purpose Input I K26 WKUP_GPIO0_70 General Purpose Input I K28 WKUP_GPIO0_71 General Purpose Input I L28 WKUP_GPIO0_72 General Purpose Input I K24 WKUP_GPIO0_73 General Purpose Input I K27 WKUP_GPIO0_74 General Purpose Input I K29 WKUP_GPIO0_75 General Purpose Input I L29 WKUP_GPIO0_76 General Purpose Input I N23 WKUP_GPIO0_77 General Purpose Input I M25 WKUP_GPIO0_78 General Purpose Input I L24 WKUP_GPIO0_79 General Purpose Input I L26 WKUP_GPIO0_80 General Purpose Input I N24 WKUP_GPIO0_81 General Purpose Input I M24 WKUP_GPIO0_82 General Purpose Input I L25 WKUP_GPIO0_83 General Purpose Input I L27 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.4 I2C

5.3.4.1 MAIN Domain

Table 5-10. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C0_SCL I2C Clock IOD AC5 I2C0_SDA I2C Data IOD AA5 Table 5-11. I2C1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C1_SCL I2C Clock IOD Y6 I2C1_SDA I2C Data IOD AA6 Table 5-12. I2C2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C2_SCL I2C Clock IOD AA1, U23, W5 I2C2_SDA I2C Data IOD AB5, U26, W6 Table 5-13. I2C3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C3_SCL I2C Clock IOD T26, V27, Y4 I2C3_SDA I2C Data IOD T25, U28, W4 Table 5-14. I2C4 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C4_SCL I2C Clock IOD AD19, P25, Y5 I2C4_SDA I2C Data IOD AD18, R29, Y1 Table 5-15. I2C5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C5_SCL I2C Clock IOD T28, Y26 I2C5_SDA I2C Data IOD AA27, T29 Table 5-16. I2C6 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I2C6_SCL I2C Clock IOD AA3, U29, W2 I2C6_SDA I2C Data IOD U25, W1, Y2

5.3.4.2 MCU Domain

Table 5-17. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_I2C0_SCL I2C Clock IOD J26 MCU_I2C0_SDA I2C Data IOD H25 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-18. I2C1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_I2C1_SCL I2C Clock IOD F29, G27 MCU_I2C1_SDA I2C Data IOD G26, G28

5.3.4.3 WKUP Domain

Table 5-19. I2C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_I2C0_SCL I2C Clock IOD J25 WKUP_I2C0_SDA I2C Data IOD H24

5.3.5 I3C

5.3.5.1 MAIN Domain

Table 5-20. I3C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] I3C0_SCL I3C Clock IO W2 I3C0_SDA I3C Data IO W1 I3C0_SDAPULLEN MAIN domain I3C Data Pull Enable O AB4, U2

5.3.5.2 MCU Domain

Table 5-21. I3C0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_I3C0_SCL I3C Clock IO D26 MCU_I3C0_SDA I3C Data IO D25 MCU_I3C0_SDAPULLEN MCU domain I3C Data Pull Enable O E26 Table 5-22. I3C1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_I3C1_SCL I3C Clock IO G27 MCU_I3C1_SDA I3C Data IO G26 MCU_I3C1_SDAPULLEN MCU domain I3C Data Pull Enable O G23, H27 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.6 MCAN

5.3.6.1 MAIN Domain

Table 5-23. MCAN0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN0_RX MCAN Receive Data I W5 MCAN0_TX MCAN Transmit Data O W6 Table 5-24. MCAN1 Signal Descriptions SIGNAL NAME 1 DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN1_RX MCAN Receive Data I W3 MCAN1_TX MCAN Transmit Data O V4 Table 5-25. MCAN2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN2_RX MCAN Receive Data I AC2, W2 MCAN2_TX MCAN Transmit Data O AB1, W1 Table 5-26. MCAN3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN3_RX MCAN Receive Data I AC4 MCAN3_TX MCAN Transmit Data O AD5 Table 5-27. MCAN4 Signal Descriptions SIGNAL NAME 1 DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN4_RX MCAN Receive Data I AJ20, AJ24 MCAN4_TX MCAN Transmit Data O AE20, AF24 Table 5-28. MCAN5 Signal Descriptions SIGNAL NAME 1 DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN5_RX MCAN Receive Data I AD24, AE21 MCAN5_TX MCAN Transmit Data O AG24, AJ21 Table 5-29. MCAN6 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN6_RX MCAN Receive Data I AE24, AG21 MCAN6_TX MCAN Transmit Data O AC24, AH21 Table 5-30. MCAN7 Signal Descriptions SIGNAL NAME 1 DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN7_RX MCAN Receive Data I AG25, Y23 MCAN7_TX MCAN Transmit Data O AC21, AH25 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-31. MCAN8 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN8_RX MCAN Receive Data I AB23, AJ27 MCAN8_TX MCAN Transmit Data O AF21, AH26 Table 5-32. MCAN9 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN9_RX MCAN Receive Data I AC27 MCAN9_TX MCAN Transmit Data O AC28 Table 5-33. MCAN10 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN10_RX MCAN Receive Data I AB25 MCAN10_TX MCAN Transmit Data O AB26 Table 5-34. MCAN11 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN11_RX MCAN Receive Data I AA28 MCAN11_TX MCAN Transmit Data O AA24 Table 5-35. MCAN12 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN12_RX MCAN Receive Data I AA29 MCAN12_TX MCAN Transmit Data O AA26 Table 5-36. MCAN13 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCAN13_RX MCAN Receive Data I AA27 MCAN13_TX MCAN Transmit Data O Y26

5.3.6.2 MCU Domain

Table 5-37. MCAN0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_MCAN0_RX MCAN Receive Data I C29 MCU_MCAN0_TX MCAN Transmit Data O D29 Table 5-38. MCAN1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_MCAN1_RX MCAN Receive Data I G24 MCU_MCAN1_TX MCAN Transmit Data O G25 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.7 MCSPI

5.3.7.1 MAIN Domain

Table 5-39. MCSPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI0_CLK SPI Clock IO AA1 SPI0_CS0 SPI Chip Select 0 IO AA2 SPI0_CS1 SPI Chip Select 1 IO Y4 SPI0_CS2 SPI Chip Select 2 IO AC2 SPI0_CS3 SPI Chip Select 3 IO AB1 SPI0_D0 SPI Data 0 IO AB5 SPI0_D1 SPI Data 1 IO AA3 Table 5-40. MCSPI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI1_CLK SPI Clock IO Y1 SPI1_CS0 SPI Chip Select 0 IO Y3 SPI1_CS1 SPI Chip Select 1 IO W4 SPI1_CS2 SPI Chip Select 2 IO AD19 SPI1_CS3 SPI Chip Select 3 IO AD18 SPI1_D0 SPI Data 0 IO Y5 SPI1_D1 SPI Data 1 IO Y2 Table 5-41. MCSPI2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI2_CLK SPI Clock IO AB1 SPI2_CS0 SPI Chip Select 0 IO AC2 SPI2_CS1 SPI Chip Select 1 IO AB2 SPI2_CS2 SPI Chip Select 2 IO AB3 SPI2_CS3 SPI Chip Select 3 IO U2 SPI2_D0 SPI Data 0 IO AC4 SPI2_D1 SPI Data 1 IO AD5 Table 5-42. MCSPI3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI3_CLK SPI Clock IO Y25 SPI3_CS0 SPI Chip Select 0 IO AA24 SPI3_CS1 SPI Chip Select 1 IO AB26 SPI3_CS2 SPI Chip Select 2 IO AB25 SPI3_CS3 SPI Chip Select 3 IO Y24 SPI3_D0 SPI Data 0 IO AA26 SPI3_D1 SPI Data 1 IO AA29 Table 5-43. MCSPI5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI5_CLK SPI Clock IO W29 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-43. MCSPI5 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI5_CS0 SPI Chip Select 0 IO W27 SPI5_CS1 SPI Chip Select 1 IO W25 SPI5_CS2 SPI Chip Select 2 IO W28 SPI5_CS3 SPI Chip Select 3 IO W23 SPI5_D0 SPI Data 0 IO V25 SPI5_D1 SPI Data 1 IO W24 Table 5-44. MCSPI6 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI6_CLK SPI Clock IO AC22 SPI6_CS0 SPI Chip Select 0 IO AC21 SPI6_CS1 SPI Chip Select 1 IO AG20 SPI6_CS2 SPI Chip Select 2 IO AD21 SPI6_CS3 SPI Chip Select 3 IO AF21 SPI6_D0 SPI Data 0 IO AJ22 SPI6_D1 SPI Data 1 IO AH22 Table 5-45. MCSPI7 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] SPI7_CLK SPI Clock IO U3 SPI7_CS0 SPI Chip Select 0 IO U2 SPI7_CS1 SPI Chip Select 1 IO AB3 SPI7_CS2 SPI Chip Select 2 IO AA4 SPI7_CS3 SPI Chip Select 3 IO AB4 SPI7_D0 SPI Data 0 IO V6 SPI7_D1 SPI Data 1 IO V5

5.3.7.2 MCU Domain

Table 5-46. MCSPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI0_CLK SPI Clock IO E27 MCU_SPI0_CS0 SPI Chip Select 0 IO E25 MCU_SPI0_CS1 SPI Chip Select 1 IO C23, G29 MCU_SPI0_CS2 SPI Chip Select 2 O E22, H29 MCU_SPI0_CS3 SPI Chip Select 3 IO G25 MCU_SPI0_D0 SPI Data 0 IO E24 MCU_SPI0_D1 SPI Data 1 IO E28 Table 5-47. MCSPI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI1_CLK SPI Clock IO F26 MCU_SPI1_CS0 SPI Chip Select 0 IO F27 MCU_SPI1_CS1 SPI Chip Select 1 O G22, H28 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-47. MCSPI1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_SPI1_CS2 SPI Chip Select 2 O D23, J27 MCU_SPI1_CS3 SPI Chip Select 3 IO G24 MCU_SPI1_D0 SPI Data 0 IO F25 MCU_SPI1_D1 SPI Data 1 IO F28

5.3.8 UART

5.3.8.1 MAIN Domain

Table 5-48. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART0_CTSn UART Clear to Send (active low) I AC2, Y3 UART0_DCDn UART Data Carrier Detect (active low) I P23 UART0_DSRn UART Data Set Ready (active low) I R28 UART0_DTRn UART Data Terminal Ready (active low) O T27 UART0_RIn UART Ring Indicator I T24 UART0_RTSn UART Request to Send (active low) O AA2, AB1 UART0_RXD UART Receive Data I AB2, AC23 UART0_TXD UART Transmit Data O AB3, AG22 Table 5-49. UART1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART1_CTSn UART Clear to Send (active low) I AA1, AC4 UART1_RTSn UART Request to Send (active low) O AB5, AD5 UART1_RXD UART Receive Data I AA4, AF22 UART1_TXD UART Transmit Data O AB4, AJ23 Table 5-50. UART2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART2_CTSn UART Clear to Send (active low) I AE25 UART2_RTSn UART Request to Send (active low) O AF29 UART2_RXD UART Receive Data I AA26, AH23, Y1 UART2_TXD UART Transmit Data O AA24, AD22, Y5 Table 5-51. UART3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART3_CTSn UART Clear to Send (active low) I AD19, U27 UART3_RTSn UART Request to Send (active low) O AD18, U24 UART3_RXD UART Receive Data I AE27, T26, V28, Y23 UART3_TXD UART Transmit Data O AC21, AD26, T25, V29 Table 5-52. UART4 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART4_CTSn UART Clear to Send (active low) I AE29, Y29 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-52. UART4 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART4_RTSn UART Request to Send (active low) O AD28, Y27 UART4_RXD UART Receive Data I AG28, P24, W23 UART4_TXD UART Transmit Data O AG27, R24, W28 Table 5-53. UART5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART5_CTSn UART Clear to Send (active low) I Y1 UART5_RTSn UART Request to Send (active low) O Y5 UART5_RXD UART Receive Data I AE29, Y29, Y3 UART5_TXD UART Transmit Data O AD28, W4, Y27 Table 5-54. UART6 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART6_CTSn UART Clear to Send (active low) I R23, W3 UART6_RTSn UART Request to Send (active low) O T23, V4 UART6_RXD UART Receive Data I AC27, T27, U27, W2 UART6_TXD UART Transmit Data O AB26, T24, U24, W1 Table 5-55. UART7 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART7_CTSn UART Clear to Send (active low) I P24 UART7_RTSn UART Request to Send (active low) O R24 UART7_RXD UART Receive Data I R26 UART7_TXD UART Transmit Data O R25 Table 5-56. UART8 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART8_CTSn UART Clear to Send (active low) I AF27, P23 UART8_RTSn UART Request to Send (active low) O AF26, R28 UART8_RXD UART Receive Data I P25, Y24 UART8_TXD UART Transmit Data O AA25, R29 Table 5-57. UART9 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UART9_CTSn UART Clear to Send (active low) I T27, W2 UART9_RTSn UART Request to Send (active low) O T24, W1 UART9_RXD UART Receive Data I T28, W3 UART9_TXD UART Transmit Data O T29, V4

5.3.8.2 MCU Domain

Table 5-58. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_UART0_CTSn UART Clear to Send (active low) I C23, D26, H29 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-58. UART0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_UART0_RTSn UART Request to Send (active low) O D25, E22, J27 MCU_UART0_RXD UART Receive Data I G22, H27, H28 MCU_UART0_TXD UART Transmit Data O D23, G29, H26

5.3.8.3 WKUP Domain

Table 5-59. UART0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_UART0_CTSn UART Clear to Send (active low) I F29 WKUP_UART0_RTSn UART Request to Send (active low) O G28 WKUP_UART0_RXD UART Receive Data I J29 WKUP_UART0_TXD UART Transmit Data O J28

5.3.9 MDIO

5.3.9.1 MCU Domain

Table 5-60. MDIO0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_MDIO0_MDC MDIO Clock O F23 MCU_MDIO0_MDIO MDIO Data IO E23

5.3.10 CPSW2G

The subsystem (SS) applies to both CPSW2G and the CPTS. For more details about CPTS signal characteristics, see the Section 5.3.21, CPTS signal descriptions.

5.3.10.1 MCU Domain

Table 5-61. CPSW2G0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_RGMII1_RXC RGMII Receive Clock I C24 MCU_RGMII1_RX_CTL RGMII Receive Control I C25 MCU_RGMII1_TXC RGMII Transmit Clock O B26 MCU_RGMII1_TX_CTL RGMII Transmit Control O B27 MCU_RGMII1_RD0 RGMII Receive Data 0 I B24 MCU_RGMII1_RD1 RGMII Receive Data 1 I A24 MCU_RGMII1_RD2 RGMII Receive Data 2 I D24 MCU_RGMII1_RD3 RGMII Receive Data 3 I A25 MCU_RGMII1_TD0 RGMII Transmit Data 0 O B25 MCU_RGMII1_TD1 RGMII Transmit Data 1 O A26 MCU_RGMII1_TD2 RGMII Transmit Data 2 O A27 MCU_RGMII1_TD3 RGMII Transmit Data 3 O A28 MCU_RMII1_CRS_DV RMII Carrier Sense / Data Valid I B27 MCU_RMII1_REF_CLK RMII Reference Clock I C24 MCU_RMII1_RX_ER RMII Receive Data Error I C25 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-61. CPSW2G0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_RMII1_TX_EN RMII Transmit Enable O B26 MCU_RMII1_RXD0 RMII Receive Data 0 I B24 MCU_RMII1_RXD1 RMII Receive Data 1 I A24 MCU_RMII1_TXD0 RMII Transmit Data 0 O B25 MCU_RMII1_TXD1 RMII Transmit Data 1 O A26

5.3.11 CPSW9G

5.3.11.1 MAIN Domain

Table 5-62. CPSW9G0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CLKOUT RMII Clock Output (50 MHz). This pin is used for clock source to the external PHY and must be routed back to the RMII_REF_CLK pin for proper device operation. OZ AA25, AJ28, Y29 MDIO0_MDC MDIO Clock O V24 MDIO0_MDIO MDIO Data IO V26 RGMII1_RXC RGMII Receive Clock I AD22 RGMII1_RX_CTL RGMII Receive Control I AH23 RGMII1_TXC RGMII Transmit Clock O AE24 RGMII1_TX_CTL RGMII Transmit Control O AC24 RGMII2_RXC RGMII Receive Clock I AE23 RGMII2_RX_CTL RGMII Receive Control I AH24 RGMII2_TXC RGMII Transmit Clock O AJ26 RGMII2_TX_CTL RGMII Transmit Control O AJ27 RGMII3_RXC RGMII Receive Clock I AE26 RGMII3_RX_CTL RGMII Receive Control I AD25 RGMII3_TXC RGMII Transmit Clock O AH28 RGMII3_TX_CTL RGMII Transmit Control O AG27 RGMII4_RXC RGMII Receive Clock I AC26 RGMII4_RX_CTL RGMII Receive Control I AD29 RGMII4_TXC RGMII Transmit Clock O AG29 RGMII4_TX_CTL RGMII Transmit Control O AF29 RGMII5_RXC RGMII Receive Clock I U25 RGMII5_RX_CTL RGMII Receive Control I U26 RGMII5_TXC RGMII Transmit Clock O U29 RGMII5_TX_CTL RGMII Transmit Control O U23 RGMII6_RXC RGMII Receive Clock I W26 RGMII6_RX_CTL RGMII Receive Control I V23 RGMII6_TXC RGMII Transmit Clock O W29 RGMII6_TX_CTL RGMII Transmit Control O Y28 RGMII7_RXC RGMII Receive Clock I AD22 RGMII7_RX_CTL RGMII Receive Control I AH23 RGMII7_TXC RGMII Transmit Clock O AE24 RGMII7_TX_CTL RGMII Transmit Control O AC24 RGMII8_RXC RGMII Receive Clock I AE23 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-62. CPSW9G0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] RGMII8_RX_CTL RGMII Receive Control I AH24 RGMII8_TXC RGMII Transmit Clock O AJ26 RGMII8_TX_CTL RGMII Transmit Control O AJ27 RGMII1_RD0 RGMII Receive Data 0 I AC23 RGMII1_RD1 RGMII Receive Data 1 I AG22 RGMII1_RD2 RGMII Receive Data 2 I AF22 RGMII1_RD3 RGMII Receive Data 3 I AJ23 RGMII1_TD0 RGMII Transmit Data 0 O AF24 RGMII1_TD1 RGMII Transmit Data 1 O AJ24 RGMII1_TD2 RGMII Transmit Data 2 O AG24 RGMII1_TD3 RGMII Transmit Data 3 O AD24 RGMII2_RD0 RGMII Receive Data 0 I AE22 RGMII2_RD1 RGMII Receive Data 1 I AG23 RGMII2_RD2 RGMII Receive Data 2 I AF23 RGMII2_RD3 RGMII Receive Data 3 I AD23 RGMII2_TD0 RGMII Transmit Data 0 O AJ25 RGMII2_TD1 RGMII Transmit Data 1 O AH25 RGMII2_TD2 RGMII Transmit Data 2 O AG25 RGMII2_TD3 RGMII Transmit Data 3 O AH26 RGMII3_RD0 RGMII Receive Data 0 I AF28 RGMII3_RD1 RGMII Receive Data 1 I AE28 RGMII3_RD2 RGMII Receive Data 2 I AE27 RGMII3_RD3 RGMII Receive Data 3 I AD26 RGMII3_TD0 RGMII Transmit Data 0 O AJ28 RGMII3_TD1 RGMII Transmit Data 1 O AH27 RGMII3_TD2 RGMII Transmit Data 2 O AH29 RGMII3_TD3 RGMII Transmit Data 3 O AG28 RGMII4_RD0 RGMII Receive Data 0 I AE29 RGMII4_RD1 RGMII Receive Data 1 I AD28 RGMII4_RD2 RGMII Receive Data 2 I AD27 RGMII4_RD3 RGMII Receive Data 3 I AC25 RGMII4_TD0 RGMII Transmit Data 0 O AG26 RGMII4_TD1 RGMII Transmit Data 1 O AF27 RGMII4_TD2 RGMII Transmit Data 2 O AF26 RGMII4_TD3 RGMII Transmit Data 3 O AE25 RGMII5_RD0 RGMII Receive Data 0 I T23 RGMII5_RD1 RGMII Receive Data 1 I R23 RGMII5_RD2 RGMII Receive Data 2 I U24 RGMII5_RD3 RGMII Receive Data 3 I U27 RGMII5_TD0 RGMII Transmit Data 0 O U28 RGMII5_TD1 RGMII Transmit Data 1 O V27 RGMII5_TD2 RGMII Transmit Data 2 O V29 RGMII5_TD3 RGMII Transmit Data 3 O V28 RGMII6_RD0 RGMII Receive Data 0 I W25 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-62. CPSW9G0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] RGMII6_RD1 RGMII Receive Data 1 I W24 RGMII6_RD2 RGMII Receive Data 2 I Y27 RGMII6_RD3 RGMII Receive Data 3 I Y29 RGMII6_TD0 RGMII Transmit Data 0 O W27 RGMII6_TD1 RGMII Transmit Data 1 O V25 RGMII6_TD2 RGMII Transmit Data 2 O W28 RGMII6_TD3 RGMII Transmit Data 3 O W23 RGMII7_RD0 RGMII Receive Data 0 I AC23 RGMII7_RD1 RGMII Receive Data 1 I AG22 RGMII7_RD2 RGMII Receive Data 2 I AF22 RGMII7_RD3 RGMII Receive Data 3 I AJ23 RGMII7_TD0 RGMII Transmit Data 0 O AF24 RGMII7_TD1 RGMII Transmit Data 1 O AJ24 RGMII7_TD2 RGMII Transmit Data 2 O AG24 RGMII7_TD3 RGMII Transmit Data 3 O AD24 RGMII8_RD0 RGMII Receive Data 0 I AE22 RGMII8_RD1 RGMII Receive Data 1 I AG23 RGMII8_RD2 RGMII Receive Data 2 I AF23 RGMII8_RD3 RGMII Receive Data 3 I AD23 RGMII8_TD0 RGMII Transmit Data 0 O AJ25 RGMII8_TD1 RGMII Transmit Data 1 O AH25 RGMII8_TD2 RGMII Transmit Data 2 O AG25 RGMII8_TD3 RGMII Transmit Data 3 O AH26 RMII1_CRS_DV RMII Carrier Sense / Data Valid I AF22 RMII1_RX_ER RMII Receive Data Error I AJ23 RMII1_TX_EN RMII Transmit Enable O AD20 RMII2_CRS_DV RMII Carrier Sense / Data Valid I AF23 RMII2_RX_ER RMII Receive Data Error I AD23 RMII2_TX_EN RMII Transmit Enable O AJ25 RMII3_CRS_DV RMII Carrier Sense / Data Valid I AE27 RMII3_RX_ER RMII Receive Data Error I AD26 RMII3_TX_EN RMII Transmit Enable O AE26 RMII4_CRS_DV RMII Carrier Sense / Data Valid I AD27 RMII4_RX_ER RMII Receive Data Error I AC25 RMII4_TX_EN RMII Transmit Enable O AG26 RMII5_CRS_DV RMII Carrier Sense / Data Valid I AD21 RMII5_RX_ER RMII Receive Data Error I AE21 RMII5_TX_EN RMII Transmit Enable O AG21 RMII6_CRS_DV RMII Carrier Sense / Data Valid I AB23 RMII6_RX_ER RMII Receive Data Error I AC21 RMII6_TX_EN RMII Transmit Enable O AC22 RMII7_CRS_DV RMII Carrier Sense / Data Valid I U23 RMII7_RX_ER RMII Receive Data Error I U26 RMII7_TX_EN RMII Transmit Enable O U29 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-62. CPSW9G0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] RMII8_CRS_DV RMII Carrier Sense / Data Valid I Y28 RMII8_RX_ER RMII Receive Data Error I V23 RMII8_TX_EN RMII Transmit Enable O W29 RMII1_RXD0 RMII Receive Data 0 I AC23 RMII1_RXD1 RMII Receive Data 1 I AG22 RMII1_TXD0 RMII Transmit Data 0 O AH23 RMII1_TXD1 RMII Transmit Data 1 O AD22 RMII2_RXD0 RMII Receive Data 0 I AE22 RMII2_RXD1 RMII Receive Data 1 I AG23 RMII2_TXD0 RMII Transmit Data 0 O AH24 RMII2_TXD1 RMII Transmit Data 1 O AE23 RMII3_RXD0 RMII Receive Data 0 I AE28 RMII3_RXD1 RMII Receive Data 1 I AF28 RMII3_TXD0 RMII Transmit Data 0 O AC29 RMII3_TXD1 RMII Transmit Data 1 O AD25 RMII4_RXD0 RMII Receive Data 0 I AE29 RMII4_RXD1 RMII Receive Data 1 I AD28 RMII4_TXD0 RMII Transmit Data 0 O AC26 RMII4_TXD1 RMII Transmit Data 1 O AD29 RMII5_RXD0 RMII Receive Data 0 I AJ20 RMII5_RXD1 RMII Receive Data 1 I AG20 RMII5_TXD0 RMII Transmit Data 0 O AH21 RMII5_TXD1 RMII Transmit Data 1 O AJ21 RMII6_RXD0 RMII Receive Data 0 I Y23 RMII6_RXD1 RMII Receive Data 1 I AF21 RMII6_TXD0 RMII Transmit Data 0 O AJ22 RMII6_TXD1 RMII Transmit Data 1 O AH22 RMII7_RXD0 RMII Receive Data 0 I T23 RMII7_RXD1 RMII Receive Data 1 I R23 RMII7_TXD0 RMII Transmit Data 0 O U28 RMII7_TXD1 RMII Transmit Data 1 O V27 RMII8_RXD0 RMII Receive Data 0 I W25 RMII8_RXD1 RMII Receive Data 1 I W24 RMII8_TXD0 RMII Transmit Data 0 O W27 RMII8_TXD1 RMII Transmit Data 1 O V25 RMII_REF_CLK RMII Reference Clock I AD18 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.3.12 ECAP

5.3.12.1 MAIN Domain

Table 5-63. ECAP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] ECAP0_IN_APWM_OUT Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO P24, U2 Table 5-64. ECAP1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] ECAP1_IN_APWM_OUT Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO R24, V6 Table 5-65. ECAP2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] ECAP2_IN_APWM_OUT Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO R28, V5

5.3.13 EQEP

5.3.13.1 MAIN Domain

Table 5-66. EQEP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EQEP0_A EQEP Quadrature Input A I AC2 EQEP0_B EQEP Quadrature Input B I AB1 EQEP0_I EQEP Index IO AD5 EQEP0_S EQEP Strobe IO AC4 Table 5-67. EQEP1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EQEP1_A EQEP Quadrature Input A I AD23 EQEP1_B EQEP Quadrature Input B I AH24 EQEP1_I EQEP Index IO AJ25 EQEP1_S EQEP Strobe IO AG21 Table 5-68. EQEP2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EQEP2_A EQEP Quadrature Input A I T27 EQEP2_B EQEP Quadrature Input B I T24 EQEP2_I EQEP Index IO P23 EQEP2_S EQEP Strobe IO R28 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.14 EHRPWM

5.3.14.1 MAIN Domain

Table 5-69. EHRPWM Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM_SOCA EHRPWM Start of Conversion A O U25 EHRPWM_SOCB EHRPWM Start of Conversion B O R23 Table 5-70. EHRPWM0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM0_A EHRPWM Output A IO V29 EHRPWM0_B EHRPWM Output B IO V27 EHRPWM0_SYNCI Sync Input to EHRPWM module from an external pin I U23 EHRPWM0_SYNCO Sync Output to EHRPWM module to an external pin O U26 EHRPWM_TZn_IN0 EHRPWM Trip Zone Input 0 (active low) I V28 Table 5-71. EHRPWM1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM1_A EHRPWM Output A IO U28 EHRPWM1_B EHRPWM Output B IO U29 EHRPWM_TZn_IN1 EHRPWM Trip Zone Input 1 (active low) I U25 Table 5-72. EHRPWM2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM2_A EHRPWM Output A IO U27 EHRPWM2_B EHRPWM Output B IO U24 EHRPWM_TZn_IN2 EHRPWM Trip Zone Input 2 (active low) I R23 Table 5-73. EHRPWM3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM3_A EHRPWM Output A IO V23 EHRPWM3_B EHRPWM Output B IO W23 EHRPWM3_SYNCI Sync Input to EHRPWM module from an external pin I W28 EHRPWM3_SYNCO Sync Output to EHRPWM module to an external pin O V25 EHRPWM_TZn_IN3 EHRPWM Trip Zone Input 3 (active low) I W27 Table 5-74. EHRPWM4 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM4_A EHRPWM Output A IO W29 EHRPWM4_B EHRPWM Output B IO W26 EHRPWM_TZn_IN4 EHRPWM Trip Zone Input 4 (active low) I Y29 Table 5-75. EHRPWM5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM5_A EHRPWM Output A IO Y27 EHRPWM5_B EHRPWM Output B IO W24 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-75. EHRPWM5 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EHRPWM_TZn_IN5 EHRPWM Trip Zone Input 5 (active low) I W25

5.3.15 USB

5.3.15.1 MAIN Domain

USB3 functionality is available on the SERDES pins. For more information, refer to Section 5.3.16, SERDES. Table 5-76. USB0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] USB0_DM USB 2.0 Differential Data (negative) IO AJ5 USB0_DP USB 2.0 Differential Data (positive) IO AH6 USB0_DRVVBUS USB VBUS control output (active high) O T25, T26, U6, V4, W3 USB0_ID USB 2.0 Dual-Role Device Role Select A AC6 USB0_RCALIB (2) Pin to connect to calibration resistor A AB6 USB0_VBUS (1) USB Level-shifted VBUS Input A AC7 (1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.3.4, USB Design Guidelines. (2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused. Table 5-77. USB1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] USB1_DM USB 2.0 Differential Data (negative) IO AH7 USB1_DP USB 2.0 Differential Data (positive) IO AJ6 USB1_DRVVBUS USB VBUS control output (active high) O T25, T26, U6, V4, W3 USB1_ID USB 2.0 Dual-Role Device Role Select A AD7 USB1_RCALIB (2) Pin to connect to calibration resistor A AD9 USB1_VBUS (1) USB Level-shifted VBUS Input A AD8 (1) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.3.4, USB Design Guidelines. (2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.

5.3.16 SERDES

5.3.16.1 MAIN Domain

Table 5-78. SERDES0 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE0_CLKREQn PCIE Clock Request Signal IO W2 PCIE_REFCLK0N PCIE Reference Clock Input/Output (negative) IO AE17 PCIE_REFCLK0P PCIE Reference Clock Input/Output (positive) IO AD16 SERDES0_REXT (1) External Calibration Resistor A AE18 SERDES0_RX0_N SERDES Differential Receive Data (negative) I AH19 SERDES0_RX0_P SERDES Differential Receive Data (positive) I AJ18 SERDES0_RX1_N SERDES Differential Receive Data (negative) I AH18 SERDES0_RX1_P SERDES Differential Receive Data (positive) I AJ17 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-78. SERDES0 Signal Descriptions (continued) SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES0_TX0_N SERDES Differential Transmit Data (negative) O AF19 SERDES0_TX0_P SERDES Differential Transmit Data (positive) O AG18 SERDES0_TX1_N SERDES Differential Transmit Data (negative) O AF18 SERDES0_TX1_P SERDES Differential Transmit Data (positive) O AG17 (1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES0_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-79. SERDES1 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE1_CLKREQn PCIE Clock Request Signal IO W1 PCIE_REFCLK1N PCIE Reference Clock Input/Output (negative) IO AE14 PCIE_REFCLK1P PCIE Reference Clock Input/Output (positive) IO AD15 SERDES1_REXT (1) External Calibration Resistor A AE13 SERDES1_RX0_N SERDES Differential Receive Data (negative) I AH15 SERDES1_RX0_P SERDES Differential Receive Data (positive) I AJ14 SERDES1_RX1_N SERDES Differential Receive Data (negative) I AH16 SERDES1_RX1_P SERDES Differential Receive Data (positive) I AJ15 SERDES1_TX0_N SERDES Differential Transmit Data (negative) O AF15 SERDES1_TX0_P SERDES Differential Transmit Data (positive) O AG14 SERDES1_TX1_N SERDES Differential Transmit Data (negative) O AF16 SERDES1_TX1_P SERDES Differential Transmit Data (positive) O AG15 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES1_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-80. SERDES2 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE2_CLKREQn PCIE Clock Request Signal IO P23 PCIE_REFCLK2N PCIE Reference Clock Input/Output (negative) IO AE11 PCIE_REFCLK2P PCIE Reference Clock Input/Output (positive) IO AD12 SERDES2_REXT (1) External Calibration Resistor A AD13 SERDES2_RX0_N SERDES Differential Receive Data (negative) I AH13 SERDES2_RX0_P SERDES Differential Receive Data (positive) I AJ12 SERDES2_RX1_N SERDES Differential Receive Data (negative) I AH12 SERDES2_RX1_P SERDES Differential Receive Data (positive) I AJ11 SERDES2_TX0_N SERDES Differential Transmit Data (negative) O AF13 SERDES2_TX0_P SERDES Differential Transmit Data (positive) O AG12 SERDES2_TX1_N SERDES Differential Transmit Data (negative) O AF12 SERDES2_TX1_P SERDES Differential Transmit Data (positive) O AG11 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES2_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-81. SERDES3 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE3_CLKREQn PCIE Clock Request Signal IO R28 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-81. SERDES3 Signal Descriptions (continued) SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] PCIE_REFCLK3N PCIE Reference Clock Input/Output (negative) IO AE9 PCIE_REFCLK3P PCIE Reference Clock Input/Output (positive) IO AD10 SERDES3_REXT (1) External Calibration Resistor A AE8 SERDES3_RX0_N SERDES Differential Receive Data (negative) I AH9 SERDES3_RX0_P SERDES Differential Receive Data (positive) I AJ8 SERDES3_RX1_N SERDES Differential Receive Data (negative) I AH10 SERDES3_RX1_P SERDES Differential Receive Data (positive) I AJ9 SERDES3_TX0_N SERDES Differential Transmit Data (negative) O AF9 SERDES3_TX0_P SERDES Differential Transmit Data (positive) O AG8 SERDES3_TX1_N SERDES Differential Transmit Data (negative) O AF10 SERDES3_TX1_P SERDES Differential Transmit Data (positive) O AG9 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES3_LN[1:0]_CTRL LANE_FUNC_SEL. Table 5-82. SERDES4 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] SERDES4_REFCLK_N SERDES Reference Differential Clock (negative) IO E7 SERDES4_REFCLK_P SERDES Reference Differential Clock (positive) IO E8 SERDES4_REXT (1) External Calibration Resistor A F9 SERDES4_RX0_N SERDES Differential Receive Data (negative) I D9 SERDES4_RX0_P SERDES Differential Receive Data (positive) I C10 SERDES4_RX1_N SERDES Differential Receive Data (negative) I D8 SERDES4_RX1_P SERDES Differential Receive Data (positive) I C9 SERDES4_RX2_N SERDES Differential Receive Data (negative) I D6 SERDES4_RX2_P SERDES Differential Receive Data (positive) I C7 SERDES4_RX3_N SERDES Differential Receive Data (negative) I D5 SERDES4_RX3_P SERDES Differential Receive Data (positive) I C6 SERDES4_TX0_N SERDES Differential Transmit Data (negative) O B11 SERDES4_TX0_P SERDES Differential Transmit Data (positive) O A12 SERDES4_TX1_N SERDES Differential Transmit Data (negative) O B10 SERDES4_TX1_P SERDES Differential Transmit Data (positive) O A11 SERDES4_TX2_N SERDES Differential Transmit Data (negative) O B8 SERDES4_TX2_P SERDES Differential Transmit Data (positive) O A9 SERDES4_TX3_N SERDES Differential Transmit Data (negative) O B7 SERDES4_TX3_P SERDES Differential Transmit Data (positive) O A8 (1) The external 3.01 kΩ ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) The functionality of these pins is controlled by SERDES4_LN[4:0]_CTRL LANE_FUNC_SEL.

5.3.17 OSPI

5.3.17.1 MCU Domain

Table 5-83. OSPI0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_OSPI0_CLK OSPI Clock O E20 MCU_OSPI0_DQS OSPI Data Strobe (DQS) or Loopback Clock Input I D21 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-83. OSPI0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_OSPI0_ECC_FAIL (1) OSPI ECC Status I B23 MCU_OSPI0_LBCLKO OSPI Loopback Clock Output IO C21 MCU_OSPI0_CSn0 OSPI Chip Select 0 (active low) O F19 MCU_OSPI0_CSn1 OSPI Chip Select 1 (active low) O E19 MCU_OSPI0_CSn2 OSPI Chip Select 2 (active low) O A23 MCU_OSPI0_CSn3 OSPI Chip Select 3 (active low) O B23 MCU_OSPI0_D0 OSPI Data 0 IO D20 MCU_OSPI0_D1 OSPI Data 1 IO G19 MCU_OSPI0_D2 OSPI Data 2 IO G20 MCU_OSPI0_D3 OSPI Data 3 IO F20 MCU_OSPI0_D4 OSPI Data 4 IO F21 MCU_OSPI0_D5 OSPI Data 5 IO E21 MCU_OSPI0_D6 OSPI Data 6 IO B22 MCU_OSPI0_D7 OSPI Data 7 IO G21 MCU_OSPI0_RESET_OUT0 OSPI Reset O A23 MCU_OSPI0_RESET_OUT1 OSPI Reset O E22 (1) An external pull-up resistor to corresponting power supply is recommended on this signal. Table 5-84. OSPI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_OSPI1_CLK OSPI Clock O F22 MCU_OSPI1_DQS OSPI Data Strobe (DQS) or Loopback Clock Input I B23 MCU_OSPI1_LBCLKO OSPI Loopback Clock Output IO A23 MCU_OSPI1_CSn0 OSPI Chip Select 0 (active low) O C22 MCU_OSPI1_CSn1 OSPI Chip Select 1 (active low) O E22 MCU_OSPI1_D0 OSPI Data 0 IO D22 MCU_OSPI1_D1 OSPI Data 1 IO G22 MCU_OSPI1_D2 OSPI Data 2 IO D23 MCU_OSPI1_D3 OSPI Data 3 IO C23

5.3.18 Hyperbus

5.3.18.1 MCU Domain

Table 5-85. HYPERBUS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_HYPERBUS0_CK Hyperbus Differential Clock (positive) O E20 MCU_HYPERBUS0_CKn Hyperbus Differential Clock (negative) O C21 MCU_HYPERBUS0_INTn Hyperbus Interrupt (active low) I B23 MCU_HYPERBUS0_RESETn Hyperbus Reset (active low) Output O E19 MCU_HYPERBUS0_RESETOn Hyperbus Reset Status Indicator (active low) from Hyperbus Memory I A23 MCU_HYPERBUS0_RWDS Hyperbus Read-Write Data Strobe IO D21 MCU_HYPERBUS0_WPn Hyperbus Write Protect (not in use) O E22 MCU_HYPERBUS0_CSn0 Hyperbus Chip Select 0 O F19 MCU_HYPERBUS0_CSn1 Hyperbus Chip Select 1 O E22 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-85. HYPERBUS0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_HYPERBUS0_DQ0 Hyperbus Data 0 IO D20 MCU_HYPERBUS0_DQ1 Hyperbus Data 1 IO G19 MCU_HYPERBUS0_DQ2 Hyperbus Data 2 IO G20 MCU_HYPERBUS0_DQ3 Hyperbus Data 3 IO F20 MCU_HYPERBUS0_DQ4 Hyperbus Data 4 IO F21 MCU_HYPERBUS0_DQ5 Hyperbus Data 5 IO E21 MCU_HYPERBUS0_DQ6 Hyperbus Data 6 IO B22 MCU_HYPERBUS0_DQ7 Hyperbus Data 7 IO G21

5.3.19 GPMC

5.3.19.1 MAIN Domain

Table 5-86. GPMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_FCLK_MUX GPMC functional clock output selected through a mux logic O AB23 GPMC0_ADVn_ALE GPMC Address Valid (active low) or Address Latch Enable O AG20 GPMC0_CLKOUT GPMC clock generated for external synchronization O AB23 GPMC0_DIR GPMC Data Bus Signal Direction Control O AJ23, W25 GPMC0_OEn_REn GPMC Output Enable (active low) or Read Enable (active low) O AJ20 GPMC0_WEn GPMC Write Enable (active low) O AD20 GPMC0_WPn GPMC Flash Write Protect (active low) O AG21 GPMC0_A0 GPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memories OZ AA27 GPMC0_A1 GPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode OZ U23 GPMC0_A2 GPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode OZ U26 GPMC0_A3 GPMC address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed mode OZ V28 GPMC0_A4 GPMC address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed mode OZ V29 GPMC0_A5 GPMC address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed mode OZ V27 GPMC0_A6 GPMC address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed mode OZ U28 GPMC0_A7 GPMC address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed mode OZ U29 GPMC0_A8 GPMC address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed mode OZ U25 GPMC0_A9 GPMC address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed mode OZ U27 GPMC0_A10 GPMC address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed mode OZ U24 GPMC0_A11 GPMC address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ R23 GPMC0_A12 GPMC address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ T23 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-86. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_A13 GPMC address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ Y28 GPMC0_A14 GPMC address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ V23 GPMC0_A15 GPMC address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ W23 GPMC0_A16 GPMC address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ W28 GPMC0_A17 GPMC address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ V25 GPMC0_A18 GPMC address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ W27 GPMC0_A19 GPMC address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ W29 GPMC0_A20 GPMC address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ W26 GPMC0_A21 GPMC address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ Y29 GPMC0_A22 GPMC address 22 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ Y27 GPMC0_A23 GPMC address 23 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AD27 GPMC0_A24 GPMC address 24 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AD29 GPMC0_A25 GPMC address 25 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AC26 GPMC0_A26 GPMC address 26 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode OZ AG26 GPMC0_A27 GPMC address 27 in A/D non-multiplexed mode and Address 27 in A/D multiplexed mode OZ Y26 GPMC0_AD0 GPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed mode IO AC29 GPMC0_AD1 GPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed mode IO AC28 GPMC0_AD2 GPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed mode IO AC27 GPMC0_AD3 GPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed mode IO AB26 GPMC0_AD4 GPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed mode IO AB25 GPMC0_AD5 GPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed mode IO AB24 GPMC0_AD6 GPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed mode IO AB29 GPMC0_AD7 GPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed mode IO AB28 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 105 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-86. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_AD8 GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode IO AB27 GPMC0_AD9 GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode IO AA24 GPMC0_AD10 GPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed mode IO AA28 GPMC0_AD11 GPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed mode IO Y24 GPMC0_AD12 GPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed mode IO AA25 GPMC0_AD13 GPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed mode IO Y25 GPMC0_AD14 GPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed mode IO AA26 GPMC0_AD15 GPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed mode IO AA29 GPMC0_BE0n_CLE GPMC Lower-Byte Enable (active low) or Command Latch Enable O AD21 GPMC0_BE1n GPMC Upper-Byte Enable (active low) O AC23, W24 GPMC0_CSn0 GPMC Chip Select 0 (active low) O AF21 GPMC0_CSn1 GPMC Chip Select 1 (active low) O Y23 GPMC0_CSn2 GPMC Chip Select 2 (active low) O AH23 GPMC0_CSn3 GPMC Chip Select 3 (active low) O AD22 GPMC0_WAIT0 GPMC External Indication of Wait I AG22 GPMC0_WAIT1 GPMC External Indication of Wait I AF22 GPMC0_WAIT2 GPMC External Indication of Wait I V24 GPMC0_WAIT3 GPMC External Indication of Wait I V26

5.3.20 MMC

5.3.20.1 MAIN Domain

Table 5-87. MMC0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC0_CALPAD (1) MMC/SD/SDIO Calibration Resistor A AE1 MMC0_CLK MMC/SD/SDIO Clock O AF1 MMC0_CMD (2) MMC/SD/SDIO Command IO AE3 MMC0_DS MMC Data Strobe IO AE4 MMC0_DAT0 (2) MMC/SD/SDIO Data IO AG2 MMC0_DAT1 (2) MMC/SD/SDIO Data IO AH1 MMC0_DAT2 (2) MMC/SD/SDIO Data IO AG3 MMC0_DAT3 (2) MMC/SD/SDIO Data IO AF4 MMC0_DAT4 (2) MMC/SD/SDIO Data IO AE5 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-87. MMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC0_DAT5 (2) MMC/SD/SDIO Data IO AF3 MMC0_DAT6 (2) MMC/SD/SDIO Data IO AG1 MMC0_DAT7 (2) MMC/SD/SDIO Data IO AF2 (1) An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin. (2) An external pull-up of 10 kΩ ~ 50 kΩ ±1% resistor, as specified in the specification, must be connected to this ball to ensure proper operation. Table 5-88. MMC1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC1_CLK (1) MMC/SD/SDIO Clock IO P25 MMC1_CMD MMC/SD/SDIO Command IO R29 MMC1_SDCD(2) SD Card Detect I P23 MMC1_SDWP SD Write Protect I R28 MMC1_DAT0 MMC/SD/SDIO Data IO R24 MMC1_DAT1 MMC/SD/SDIO Data IO P24 MMC1_DAT2 MMC/SD/SDIO Data IO R25 MMC1_DAT3 MMC/SD/SDIO Data IO R26 (1) For MMC1_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG171 register should be set to 0x1 because of retiming purposes. (2) For ROM boot from MMC1 interface to work properly, the MMC1_SDCD pin should be pulled low externally with a resistor to indicate an SD Card/Memory device is present. Table 5-89. MMC2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MMC2_CLK (1) MMC/SD/SDIO Clock IO T26 MMC2_CMD MMC/SD/SDIO Command IO T25 MMC2_SDCD(2) SD Card Detect I W2 MMC2_SDWP SD Write Protect I W1 MMC2_DAT0 MMC/SD/SDIO Data IO T24 MMC2_DAT1 MMC/SD/SDIO Data IO T27 MMC2_DAT2 MMC/SD/SDIO Data IO T29 MMC2_DAT3 MMC/SD/SDIO Data IO T28 (1) For MMC2_CLK signal to work properly, the RXACTIVE bit of the CTRLMMR_PADCONFIG172 register should be set to 0x1 because of retiming purposes. (2) For MMC2 module to work properly, the MMC2_SDCD pin should be pulled low to indicate an SD Card/Memory device is present.

5.3.21 CPTS

Some CPTS signals are connected directly to CPTS modules within the device. Other CPTS signals are connected to the Time Sync Router and fanned out to peripherals linked to the router. Input signals are sent to the peripherals while output signals are sourced from the peripherals. For more information, see the Time Sync and Compare Events section in the Time Sync chapter in the device TRM. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 107 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.3.21.1 MCU Domain

Table 5-90. MCU_CPTS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_CPTS0_RFT_CLK CPTS Reference Clock I H26 MCU_CPTS0_TS_COMP Time Stamp Counter Compare from MCU_CPSW0_CPTS0 O G26 MCU_CPTS0_TS_SYNC Time Stamp Counter Bit from MCU_CPSW0_CPTS0 O G27 MCU_CPTS0_HW1TSPUSH Hardware Time Stamp Push 1 input to Time Sync Router and MCU_CPSW0_CPTS0 I F29 MCU_CPTS0_HW2TSPUSH Hardware Time Stamp Push 2 input to Time Sync Router and MCU_CPSW0_CPTS0 I G28

5.3.21.2 MAIN Domain

Table 5-91. CPTS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CPTS0_RFT_CLK CPTS Reference Clock I U2 CPTS0_TS_COMP Time Stamp Counter Compare from NAVSS0_CPTS0 O Y4 CPTS0_TS_SYNC Time Stamp Counter Bit from NAVSS0_CPTS0 O W4 CPTS0_HW1TSPUSH Hardware Time Stamp Push input to Time Sync Router I T28, Y6 CPTS0_HW2TSPUSH Hardware Time Stamp Push input to Time Sync Router I AA6, T29 SYNC0_OUT Time Stamp Generator Bit 0 from Time Sync Router O U2 SYNC1_OUT Time Stamp Generator Bit 1 from Time Sync Router O U3 SYNC2_OUT Time Stamp Generator Bit 2 from Time Sync Router O V28 SYNC3_OUT Time Stamp Generator Bit 3 from Time Sync Router O V29

5.3.22 UFS

5.3.22.1 MAIN Domain

Table 5-92. UFS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] UFS0_REF_CLK UFS Reference Clock O AE6 UFS0_RSTn UFS Reset Out O AD6 UFS0_RX_DN0 UFS Lane 0 Differential Receive Data (negative) I AH3 UFS0_RX_DP0 UFS Lane 0 Differential Receive Data (positive) I AJ2 UFS0_RX_DN1 UFS Lane 1 Differential Receive Data (negative) I AH4 UFS0_RX_DP1 UFS Lane 1 Differential Receive Data (positive) I AJ3 UFS0_TX_DN0 UFS Lane 0 Differential Transmit Data (negative) O AG6 UFS0_TX_DP0 UFS Lane 0 Differential Transmit Data (positive) O AF7 UFS0_TX_DN1 UFS Lane 1 Differential Transmit Data (negative) O AG5 UFS0_TX_DP1 UFS Lane 1 Differential Transmit Data (positive) O AF6 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.23 PRU_ICSSG [Currently Not Supported]

5.3.23.1 MAIN Domain

Table 5-93. PRU_ICSSG0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_ECAP0_IN_APWM_OUT PRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO AB29 PRG0_ECAP0_SYNC_IN PRU_ICSSG ECAP Sync Input I AC28 PRG0_ECAP0_SYNC_OUT PRU_ICSSG ECAP Sync Output O AB24 PRG0_IEP0_EDIO_OUTVALID PRU_ICSSG Industrial Ethernet Digital I/O Outvalid O Y3 PRG0_IEP0_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AB29, Y3 PRG0_IEP0_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AC28, P23 PRG0_IEP0_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AB28, Y1 PRG0_IEP0_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AB24, R28 PRG0_IEP0_EDIO_DATA_IN_OUT28 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AB26 PRG0_IEP0_EDIO_DATA_IN_OUT29 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AB25 PRG0_IEP0_EDIO_DATA_IN_OUT30 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO Y24 PRG0_IEP0_EDIO_DATA_IN_OUT31 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AA25 PRG0_IEP1_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AA26, Y5 PRG0_IEP1_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AA24, T27 PRG0_IEP1_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AA29, Y2 PRG0_IEP1_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O T24, Y25 PRG0_MDIO0_MDC PRU_ICSSG MDIO Clock O AA27 PRG0_MDIO0_MDIO PRU_ICSSG MDIO Data IO Y26 PRG0_PRU0_GPI0 PRU_ICSSG PRU Data Input I AF28 PRG0_PRU0_GPI1 PRU_ICSSG PRU Data Input I AE28 PRG0_PRU0_GPI2 PRU_ICSSG PRU Data Input I AE27 PRG0_PRU0_GPI3 PRU_ICSSG PRU Data Input I AD26 PRG0_PRU0_GPI4 PRU_ICSSG PRU Data Input I AD25 PRG0_PRU0_GPI5 PRU_ICSSG PRU Data Input I AC29 PRG0_PRU0_GPI6 PRU_ICSSG PRU Data Input I AE26 PRG0_PRU0_GPI7 PRU_ICSSG PRU Data Input I AC28 PRG0_PRU0_GPI8 PRU_ICSSG PRU Data Input I AC27 PRG0_PRU0_GPI9 PRU_ICSSG PRU Data Input I AB26 PRG0_PRU0_GPI10 PRU_ICSSG PRU Data Input I AB25 PRG0_PRU0_GPI11 PRU_ICSSG PRU Data Input I AJ28 PRG0_PRU0_GPI12 PRU_ICSSG PRU Data Input I AH27 PRG0_PRU0_GPI13 PRU_ICSSG PRU Data Input I AH29 PRG0_PRU0_GPI14 PRU_ICSSG PRU Data Input I AG28 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-93. PRU_ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_PRU0_GPI15 PRU_ICSSG PRU Data Input I AG27 PRG0_PRU0_GPI16 PRU_ICSSG PRU Data Input I AH28 PRG0_PRU0_GPI17 PRU_ICSSG PRU Data Input I AB24 PRG0_PRU0_GPI18 PRU_ICSSG PRU Data Input I AB29 PRG0_PRU0_GPI19 PRU_ICSSG PRU Data Input I AB28 PRG0_PRU0_GPO0 PRU_ICSSG PRU Data Output IO AF28 PRG0_PRU0_GPO1 PRU_ICSSG PRU Data Output IO AE28 PRG0_PRU0_GPO2 PRU_ICSSG PRU Data Output IO AE27 PRG0_PRU0_GPO3 PRU_ICSSG PRU Data Output IO AD26 PRG0_PRU0_GPO4 PRU_ICSSG PRU Data Output IO AD25 PRG0_PRU0_GPO5 PRU_ICSSG PRU Data Output IO AC29 PRG0_PRU0_GPO6 PRU_ICSSG PRU Data Output IO AE26 PRG0_PRU0_GPO7 PRU_ICSSG PRU Data Output IO AC28 PRG0_PRU0_GPO8 PRU_ICSSG PRU Data Output IO AC27 PRG0_PRU0_GPO9 PRU_ICSSG PRU Data Output IO AB26 PRG0_PRU0_GPO10 PRU_ICSSG PRU Data Output IO AB25 PRG0_PRU0_GPO11 PRU_ICSSG PRU Data Output IO AJ28 PRG0_PRU0_GPO12 PRU_ICSSG PRU Data Output IO AH27 PRG0_PRU0_GPO13 PRU_ICSSG PRU Data Output IO AH29 PRG0_PRU0_GPO14 PRU_ICSSG PRU Data Output IO AG28 PRG0_PRU0_GPO15 PRU_ICSSG PRU Data Output IO AG27 PRG0_PRU0_GPO16 PRU_ICSSG PRU Data Output IO AH28 PRG0_PRU0_GPO17 PRU_ICSSG PRU Data Output IO AB24 PRG0_PRU0_GPO18 PRU_ICSSG PRU Data Output IO AB29 PRG0_PRU0_GPO19 PRU_ICSSG PRU Data Output IO AB28 PRG0_PRU1_GPI0 PRU_ICSSG PRU Data Input I AE29 PRG0_PRU1_GPI1 PRU_ICSSG PRU Data Input I AD28 PRG0_PRU1_GPI2 PRU_ICSSG PRU Data Input I AD27 PRG0_PRU1_GPI3 PRU_ICSSG PRU Data Input I AC25 PRG0_PRU1_GPI4 PRU_ICSSG PRU Data Input I AD29 PRG0_PRU1_GPI5 PRU_ICSSG PRU Data Input I AB27 PRG0_PRU1_GPI6 PRU_ICSSG PRU Data Input I AC26 PRG0_PRU1_GPI7 PRU_ICSSG PRU Data Input I AA24 PRG0_PRU1_GPI8 PRU_ICSSG PRU Data Input I AA28 PRG0_PRU1_GPI9 PRU_ICSSG PRU Data Input I Y24 PRG0_PRU1_GPI10 PRU_ICSSG PRU Data Input I AA25 PRG0_PRU1_GPI11 PRU_ICSSG PRU Data Input I AG26 PRG0_PRU1_GPI12 PRU_ICSSG PRU Data Input I AF27 PRG0_PRU1_GPI13 PRU_ICSSG PRU Data Input I AF26 PRG0_PRU1_GPI14 PRU_ICSSG PRU Data Input I AE25 PRG0_PRU1_GPI15 PRU_ICSSG PRU Data Input I AF29 PRG0_PRU1_GPI16 PRU_ICSSG PRU Data Input I AG29 PRG0_PRU1_GPI17 PRU_ICSSG PRU Data Input I Y25 PRG0_PRU1_GPI18 PRU_ICSSG PRU Data Input I AA26 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-93. PRU_ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_PRU1_GPI19 PRU_ICSSG PRU Data Input I AA29 PRG0_PRU1_GPO0 PRU_ICSSG PRU Data Output IO AE29 PRG0_PRU1_GPO1 PRU_ICSSG PRU Data Output IO AD28 PRG0_PRU1_GPO2 PRU_ICSSG PRU Data Output IO AD27 PRG0_PRU1_GPO3 PRU_ICSSG PRU Data Output IO AC25 PRG0_PRU1_GPO4 PRU_ICSSG PRU Data Output IO AD29 PRG0_PRU1_GPO5 PRU_ICSSG PRU Data Output IO AB27 PRG0_PRU1_GPO6 PRU_ICSSG PRU Data Output IO AC26 PRG0_PRU1_GPO7 PRU_ICSSG PRU Data Output IO AA24 PRG0_PRU1_GPO8 PRU_ICSSG PRU Data Output IO AA28 PRG0_PRU1_GPO9 PRU_ICSSG PRU Data Output IO Y24 PRG0_PRU1_GPO10 PRU_ICSSG PRU Data Output IO AA25 PRG0_PRU1_GPO11 PRU_ICSSG PRU Data Output IO AG26 PRG0_PRU1_GPO12 PRU_ICSSG PRU Data Output IO AF27 PRG0_PRU1_GPO13 PRU_ICSSG PRU Data Output IO AF26 PRG0_PRU1_GPO14 PRU_ICSSG PRU Data Output IO AE25 PRG0_PRU1_GPO15 PRU_ICSSG PRU Data Output IO AF29 PRG0_PRU1_GPO16 PRU_ICSSG PRU Data Output IO AG29 PRG0_PRU1_GPO17 PRU_ICSSG PRU Data Output IO Y25 PRG0_PRU1_GPO18 PRU_ICSSG PRU Data Output IO AA26 PRG0_PRU1_GPO19 PRU_ICSSG PRU Data Output IO AA29 PRG0_PWM0_TZ_IN PRU_ICSSG PWM Trip Zone Input I AB29 PRG0_PWM0_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AB28 PRG0_PWM1_TZ_IN PRU_ICSSG PWM Trip Zone Input I AA26 PRG0_PWM1_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AA29 PRG0_PWM2_TZ_IN PRU_ICSSG PWM Trip Zone Input I AA25 PRG0_PWM2_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AA28 PRG0_PWM3_TZ_IN PRU_ICSSG PWM Trip Zone Input I AB26 PRG0_PWM3_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AJ28 PRG0_PWM0_A0 PRU_ICSSG PWM Output A IO AH27 PRG0_PWM0_A1 PRU_ICSSG PWM Output A IO AG28 PRG0_PWM0_A2 PRU_ICSSG PWM Output A IO AH28 PRG0_PWM0_B0 PRU_ICSSG PWM Output B IO AH29 PRG0_PWM0_B1 PRU_ICSSG PWM Output B IO AG27 PRG0_PWM0_B2 PRU_ICSSG PWM Output B IO AB24 PRG0_PWM1_A0 PRU_ICSSG PWM Output A IO AF27 PRG0_PWM1_A1 PRU_ICSSG PWM Output A IO AE25 PRG0_PWM1_A2 PRU_ICSSG PWM Output A IO AG29 PRG0_PWM1_B0 PRU_ICSSG PWM Output B IO AF26 PRG0_PWM1_B1 PRU_ICSSG PWM Output B IO AF29 PRG0_PWM1_B2 PRU_ICSSG PWM Output B IO Y25 PRG0_PWM2_A0 PRU_ICSSG PWM Output A IO AE27 PRG0_PWM2_A1 PRU_ICSSG PWM Output A IO AC27 PRG0_PWM2_A2 PRU_ICSSG PWM Output A IO AD27 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-93. PRU_ICSSG0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG0_PWM2_B0 PRU_ICSSG PWM Output B IO AD25 PRG0_PWM2_B1 PRU_ICSSG PWM Output B IO AB25 PRG0_PWM2_B2 PRU_ICSSG PWM Output B IO AD29 PRG0_PWM3_A0 PRU_ICSSG PWM Output A IO AF28 PRG0_PWM3_A1 PRU_ICSSG PWM Output A IO AE26 PRG0_PWM3_A2 PRU_ICSSG PWM Output A IO AD26 PRG0_PWM3_B0 PRU_ICSSG PWM Output B IO AE28 PRG0_PWM3_B1 PRU_ICSSG PWM Output B IO AC28 PRG0_PWM3_B2 PRU_ICSSG PWM Output B IO AC29 PRG0_RGMII1_RXC PRU_ICSSG RGMII Receive Clock I AE26 PRG0_RGMII1_RX_CTL PRU_ICSSG RGMII Receive Control I AD25 PRG0_RGMII1_TXC PRU_ICSSG RGMII Transmit Clock IO AH28 PRG0_RGMII1_TX_CTL PRU_ICSSG RGMII Transmit Control O AG27 PRG0_RGMII2_RXC PRU_ICSSG RGMII Receive Clock I AC26 PRG0_RGMII2_RX_CTL PRU_ICSSG RGMII Receive Control I AD29 PRG0_RGMII2_TXC PRU_ICSSG RGMII Transmit Clock IO AG29 PRG0_RGMII2_TX_CTL PRU_ICSSG RGMII Transmit Control O AF29 PRG0_RGMII1_RD0 PRU_ICSSG RGMII Receive Data I AF28 PRG0_RGMII1_RD1 PRU_ICSSG RGMII Receive Data I AE28 PRG0_RGMII1_RD2 PRU_ICSSG RGMII Receive Data I AE27 PRG0_RGMII1_RD3 PRU_ICSSG RGMII Receive Data I AD26 PRG0_RGMII1_TD0 PRU_ICSSG RGMII Transmit Data O AJ28 PRG0_RGMII1_TD1 PRU_ICSSG RGMII Transmit Data O AH27 PRG0_RGMII1_TD2 PRU_ICSSG RGMII Transmit Data O AH29 PRG0_RGMII1_TD3 PRU_ICSSG RGMII Transmit Data O AG28 PRG0_RGMII2_RD0 PRU_ICSSG RGMII Receive Data I AE29 PRG0_RGMII2_RD1 PRU_ICSSG RGMII Receive Data I AD28 PRG0_RGMII2_RD2 PRU_ICSSG RGMII Receive Data I AD27 PRG0_RGMII2_RD3 PRU_ICSSG RGMII Receive Data I AC25 PRG0_RGMII2_TD0 PRU_ICSSG RGMII Transmit Data O AG26 PRG0_RGMII2_TD1 PRU_ICSSG RGMII Transmit Data O AF27 PRG0_RGMII2_TD2 PRU_ICSSG RGMII Transmit Data O AF26 PRG0_RGMII2_TD3 PRU_ICSSG RGMII Transmit Data O AE25 PRG0_UART0_CTSn PRU_ICSSG UART Clear to Send (active low) I AB26 PRG0_UART0_RTSn PRU_ICSSG UART Request to Send (active low) O AB25 PRG0_UART0_RXD PRU_ICSSG UART Receive Data I Y24 PRG0_UART0_TXD PRU_ICSSG UART Transmit Data O AA25 Table 5-94. PRU_ICSSG1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_ECAP0_IN_APWM_OUT PRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput IO AH22 PRG1_ECAP0_SYNC_IN PRU_ICSSG ECAP Sync Input I AJ22 PRG1_ECAP0_SYNC_OUT PRU_ICSSG ECAP Sync Output O AC22 PRG1_IEP0_EDIO_OUTVALID PRU_ICSSG Industrial Ethernet Digital I/O Outvalid O Y4 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-94. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_IEP0_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AE21 PRG1_IEP0_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AE20 PRG1_IEP0_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AH21 PRG1_IEP0_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AJ21 PRG1_IEP0_EDIO_DATA_IN_OUT28 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AG20 PRG1_IEP0_EDIO_DATA_IN_OUT29 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AD21 PRG1_IEP0_EDIO_DATA_IN_OUT30 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AF21 PRG1_IEP0_EDIO_DATA_IN_OUT31 PRU_ICSSG Industrial Ethernet Digital I/O Data Input/ Output IO AB23 PRG1_IEP1_EDC_LATCH_IN0 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AJ22 PRG1_IEP1_EDC_LATCH_IN1 PRU_ICSSG Industrial Ethernet Distributed Clock Latch Input I AC21 PRG1_IEP1_EDC_SYNC_OUT0 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AH22 PRG1_IEP1_EDC_SYNC_OUT1 PRU_ICSSG Industrial Ethernet Distributed Clock Sync Output O AC22 PRG1_MDIO0_MDC PRU_ICSSG MDIO Clock O AD18 PRG1_MDIO0_MDIO PRU_ICSSG MDIO Data IO AD19 PRG1_PRU0_GPI0 PRU_ICSSG PRU Data Input I AC23 PRG1_PRU0_GPI1 PRU_ICSSG PRU Data Input I AG22 PRG1_PRU0_GPI2 PRU_ICSSG PRU Data Input I AF22 PRG1_PRU0_GPI3 PRU_ICSSG PRU Data Input I AJ23 PRG1_PRU0_GPI4 PRU_ICSSG PRU Data Input I AH23 PRG1_PRU0_GPI5 PRU_ICSSG PRU Data Input I AD20 PRG1_PRU0_GPI6 PRU_ICSSG PRU Data Input I AD22 PRG1_PRU0_GPI7 PRU_ICSSG PRU Data Input I AE20 PRG1_PRU0_GPI8 PRU_ICSSG PRU Data Input I AJ20 PRG1_PRU0_GPI9 PRU_ICSSG PRU Data Input I AG20 PRG1_PRU0_GPI10 PRU_ICSSG PRU Data Input I AD21 PRG1_PRU0_GPI11 PRU_ICSSG PRU Data Input I AF24 PRG1_PRU0_GPI12 PRU_ICSSG PRU Data Input I AJ24 PRG1_PRU0_GPI13 PRU_ICSSG PRU Data Input I AG24 PRG1_PRU0_GPI14 PRU_ICSSG PRU Data Input I AD24 PRG1_PRU0_GPI15 PRU_ICSSG PRU Data Input I AC24 PRG1_PRU0_GPI16 PRU_ICSSG PRU Data Input I AE24 PRG1_PRU0_GPI17 PRU_ICSSG PRU Data Input I AJ21 PRG1_PRU0_GPI18 PRU_ICSSG PRU Data Input I AE21 PRG1_PRU0_GPI19 PRU_ICSSG PRU Data Input I AH21 PRG1_PRU0_GPO0 PRU_ICSSG PRU Data Output IO AC23 PRG1_PRU0_GPO1 PRU_ICSSG PRU Data Output IO AG22 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-94. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_PRU0_GPO2 PRU_ICSSG PRU Data Output IO AF22 PRG1_PRU0_GPO3 PRU_ICSSG PRU Data Output IO AJ23 PRG1_PRU0_GPO4 PRU_ICSSG PRU Data Output IO AH23 PRG1_PRU0_GPO5 PRU_ICSSG PRU Data Output IO AD20 PRG1_PRU0_GPO6 PRU_ICSSG PRU Data Output IO AD22 PRG1_PRU0_GPO7 PRU_ICSSG PRU Data Output IO AE20 PRG1_PRU0_GPO8 PRU_ICSSG PRU Data Output IO AJ20 PRG1_PRU0_GPO9 PRU_ICSSG PRU Data Output IO AG20 PRG1_PRU0_GPO10 PRU_ICSSG PRU Data Output IO AD21 PRG1_PRU0_GPO11 PRU_ICSSG PRU Data Output IO AF24 PRG1_PRU0_GPO12 PRU_ICSSG PRU Data Output IO AJ24 PRG1_PRU0_GPO13 PRU_ICSSG PRU Data Output IO AG24 PRG1_PRU0_GPO14 PRU_ICSSG PRU Data Output IO AD24 PRG1_PRU0_GPO15 PRU_ICSSG PRU Data Output IO AC24 PRG1_PRU0_GPO16 PRU_ICSSG PRU Data Output IO AE24 PRG1_PRU0_GPO17 PRU_ICSSG PRU Data Output IO AJ21 PRG1_PRU0_GPO18 PRU_ICSSG PRU Data Output IO AE21 PRG1_PRU0_GPO19 PRU_ICSSG PRU Data Output IO AH21 PRG1_PRU1_GPI0 PRU_ICSSG PRU Data Input I AE22 PRG1_PRU1_GPI1 PRU_ICSSG PRU Data Input I AG23 PRG1_PRU1_GPI2 PRU_ICSSG PRU Data Input I AF23 PRG1_PRU1_GPI3 PRU_ICSSG PRU Data Input I AD23 PRG1_PRU1_GPI4 PRU_ICSSG PRU Data Input I AH24 PRG1_PRU1_GPI5 PRU_ICSSG PRU Data Input I AG21 PRG1_PRU1_GPI6 PRU_ICSSG PRU Data Input I AE23 PRG1_PRU1_GPI7 PRU_ICSSG PRU Data Input I AC21 PRG1_PRU1_GPI8 PRU_ICSSG PRU Data Input I Y23 PRG1_PRU1_GPI9 PRU_ICSSG PRU Data Input I AF21 PRG1_PRU1_GPI10 PRU_ICSSG PRU Data Input I AB23 PRG1_PRU1_GPI11 PRU_ICSSG PRU Data Input I AJ25 PRG1_PRU1_GPI12 PRU_ICSSG PRU Data Input I AH25 PRG1_PRU1_GPI13 PRU_ICSSG PRU Data Input I AG25 PRG1_PRU1_GPI14 PRU_ICSSG PRU Data Input I AH26 PRG1_PRU1_GPI15 PRU_ICSSG PRU Data Input I AJ27 PRG1_PRU1_GPI16 PRU_ICSSG PRU Data Input I AJ26 PRG1_PRU1_GPI17 PRU_ICSSG PRU Data Input I AC22 PRG1_PRU1_GPI18 PRU_ICSSG PRU Data Input I AJ22 PRG1_PRU1_GPI19 PRU_ICSSG PRU Data Input I AH22 PRG1_PRU1_GPO0 PRU_ICSSG PRU Data Output IO AE22 PRG1_PRU1_GPO1 PRU_ICSSG PRU Data Output IO AG23 PRG1_PRU1_GPO2 PRU_ICSSG PRU Data Output IO AF23 PRG1_PRU1_GPO3 PRU_ICSSG PRU Data Output IO AD23 PRG1_PRU1_GPO4 PRU_ICSSG PRU Data Output IO AH24 PRG1_PRU1_GPO5 PRU_ICSSG PRU Data Output IO AG21 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-94. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_PRU1_GPO6 PRU_ICSSG PRU Data Output IO AE23 PRG1_PRU1_GPO7 PRU_ICSSG PRU Data Output IO AC21 PRG1_PRU1_GPO8 PRU_ICSSG PRU Data Output IO Y23 PRG1_PRU1_GPO9 PRU_ICSSG PRU Data Output IO AF21 PRG1_PRU1_GPO10 PRU_ICSSG PRU Data Output IO AB23 PRG1_PRU1_GPO11 PRU_ICSSG PRU Data Output IO AJ25 PRG1_PRU1_GPO12 PRU_ICSSG PRU Data Output IO AH25 PRG1_PRU1_GPO13 PRU_ICSSG PRU Data Output IO AG25 PRG1_PRU1_GPO14 PRU_ICSSG PRU Data Output IO AH26 PRG1_PRU1_GPO15 PRU_ICSSG PRU Data Output IO AJ27 PRG1_PRU1_GPO16 PRU_ICSSG PRU Data Output IO AJ26 PRG1_PRU1_GPO17 PRU_ICSSG PRU Data Output IO AC22 PRG1_PRU1_GPO18 PRU_ICSSG PRU Data Output IO AJ22 PRG1_PRU1_GPO19 PRU_ICSSG PRU Data Output IO AH22 PRG1_PWM0_TZ_IN PRU_ICSSG PWM Trip Zone Input I AE21 PRG1_PWM0_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AH21 PRG1_PWM1_TZ_IN PRU_ICSSG PWM Trip Zone Input I AJ22 PRG1_PWM1_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AH22 PRG1_PWM2_TZ_IN PRU_ICSSG PWM Trip Zone Input I AB23 PRG1_PWM2_TZ_OUT PRU_ICSSG PWM Trip Zone Output O Y23 PRG1_PWM3_TZ_IN PRU_ICSSG PWM Trip Zone Input I AG20 PRG1_PWM3_TZ_OUT PRU_ICSSG PWM Trip Zone Output O AF24 PRG1_PWM0_A0 PRU_ICSSG PWM Output A IO AJ24 PRG1_PWM0_A1 PRU_ICSSG PWM Output A IO AD24 PRG1_PWM0_A2 PRU_ICSSG PWM Output A IO AE24 PRG1_PWM0_B0 PRU_ICSSG PWM Output B IO AG24 PRG1_PWM0_B1 PRU_ICSSG PWM Output B IO AC24 PRG1_PWM0_B2 PRU_ICSSG PWM Output B IO AJ21 PRG1_PWM1_A0 PRU_ICSSG PWM Output A IO AH25 PRG1_PWM1_A1 PRU_ICSSG PWM Output A IO AH26 PRG1_PWM1_A2 PRU_ICSSG PWM Output A IO AJ26 PRG1_PWM1_B0 PRU_ICSSG PWM Output B IO AG25 PRG1_PWM1_B1 PRU_ICSSG PWM Output B IO AJ27 PRG1_PWM1_B2 PRU_ICSSG PWM Output B IO AC22 PRG1_PWM2_A0 PRU_ICSSG PWM Output A IO AF22 PRG1_PWM2_A1 PRU_ICSSG PWM Output A IO AJ20 PRG1_PWM2_A2 PRU_ICSSG PWM Output A IO AF23 PRG1_PWM2_B0 PRU_ICSSG PWM Output B IO AH23 PRG1_PWM2_B1 PRU_ICSSG PWM Output B IO AD21 PRG1_PWM2_B2 PRU_ICSSG PWM Output B IO AH24 PRG1_PWM3_A0 PRU_ICSSG PWM Output A IO AC23 PRG1_PWM3_A1 PRU_ICSSG PWM Output A IO AD22 PRG1_PWM3_A2 PRU_ICSSG PWM Output A IO AJ23 PRG1_PWM3_B0 PRU_ICSSG PWM Output B IO AG22 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-94. PRU_ICSSG1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] PRG1_PWM3_B1 PRU_ICSSG PWM Output B IO AE20 PRG1_PWM3_B2 PRU_ICSSG PWM Output B IO AD20 PRG1_RGMII1_RXC PRU_ICSSG RGMII Receive Clock I AD22 PRG1_RGMII1_RX_CTL PRU_ICSSG RGMII Receive Control I AH23 PRG1_RGMII1_TXC PRU_ICSSG RGMII Transmit Clock IO AE24 PRG1_RGMII1_TX_CTL PRU_ICSSG RGMII Transmit Control O AC24 PRG1_RGMII2_RXC PRU_ICSSG RGMII Receive Clock I AE23 PRG1_RGMII2_RX_CTL PRU_ICSSG RGMII Receive Control I AH24 PRG1_RGMII2_TXC PRU_ICSSG RGMII Transmit Clock IO AJ26 PRG1_RGMII2_TX_CTL PRU_ICSSG RGMII Transmit Control O AJ27 PRG1_RGMII1_RD0 PRU_ICSSG RGMII Receive Data I AC23 PRG1_RGMII1_RD1 PRU_ICSSG RGMII Receive Data I AG22 PRG1_RGMII1_RD2 PRU_ICSSG RGMII Receive Data I AF22 PRG1_RGMII1_RD3 PRU_ICSSG RGMII Receive Data I AJ23 PRG1_RGMII1_TD0 PRU_ICSSG RGMII Transmit Data O AF24 PRG1_RGMII1_TD1 PRU_ICSSG RGMII Transmit Data O AJ24 PRG1_RGMII1_TD2 PRU_ICSSG RGMII Transmit Data O AG24 PRG1_RGMII1_TD3 PRU_ICSSG RGMII Transmit Data O AD24 PRG1_RGMII2_RD0 PRU_ICSSG RGMII Receive Data I AE22 PRG1_RGMII2_RD1 PRU_ICSSG RGMII Receive Data I AG23 PRG1_RGMII2_RD2 PRU_ICSSG RGMII Receive Data I AF23 PRG1_RGMII2_RD3 PRU_ICSSG RGMII Receive Data I AD23 PRG1_RGMII2_TD0 PRU_ICSSG RGMII Transmit Data O AJ25 PRG1_RGMII2_TD1 PRU_ICSSG RGMII Transmit Data O AH25 PRG1_RGMII2_TD2 PRU_ICSSG RGMII Transmit Data O AG25 PRG1_RGMII2_TD3 PRU_ICSSG RGMII Transmit Data O AH26 PRG1_UART0_CTSn PRU_ICSSG UART Clear to Send (active low) I AG20 PRG1_UART0_RTSn PRU_ICSSG UART Request to Send (active low) O AD21 PRG1_UART0_RXD PRU_ICSSG UART Receive Data I AF21 PRG1_UART0_TXD PRU_ICSSG UART Transmit Data O AB23

5.3.24 MCASP

5.3.24.1 MAIN Domain

Table 5-95. MCASP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP0_ACLKR MCASP Receive Bit Clock IO AE27 MCASP0_ACLKX MCASP Transmit Bit Clock IO AB26 MCASP0_AFSR MCASP Receive Frame Sync IO AD26 MCASP0_AFSX MCASP Transmit Frame Sync IO AB25 MCASP0_AXR0 MCASP Serial Data (Input/Output) IO AF28 MCASP0_AXR1 MCASP Serial Data (Input/Output) IO AE28 MCASP0_AXR2 MCASP Serial Data (Input/Output) IO AD25 MCASP0_AXR3 MCASP Serial Data (Input/Output) IO AC29 MCASP0_AXR4 MCASP Serial Data (Input/Output) IO AE26 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-95. MCASP0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP0_AXR5 MCASP Serial Data (Input/Output) IO AC28 MCASP0_AXR6 MCASP Serial Data (Input/Output) IO AC27 MCASP0_AXR7 MCASP Serial Data (Input/Output) IO AJ28 MCASP0_AXR8 MCASP Serial Data (Input/Output) IO AH27 MCASP0_AXR9 MCASP Serial Data (Input/Output) IO AH29 MCASP0_AXR10 MCASP Serial Data (Input/Output) IO AG28 MCASP0_AXR11 MCASP Serial Data (Input/Output) IO AG27 MCASP0_AXR12 MCASP Serial Data (Input/Output) IO AH28 MCASP0_AXR13 MCASP Serial Data (Input/Output) IO AB24 MCASP0_AXR14 MCASP Serial Data (Input/Output) IO AB29 MCASP0_AXR15 MCASP Serial Data (Input/Output) IO AB28 Table 5-96. MCASP1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP1_ACLKR MCASP Receive Bit Clock IO AD27 MCASP1_ACLKX MCASP Transmit Bit Clock IO AB27 MCASP1_AFSR MCASP Receive Frame Sync IO AC25 MCASP1_AFSX MCASP Transmit Frame Sync IO AA28 MCASP1_AXR0 MCASP Serial Data (Input/Output) IO AE29 MCASP1_AXR1 MCASP Serial Data (Input/Output) IO AD28 MCASP1_AXR2 MCASP Serial Data (Input/Output) IO AD29 MCASP1_AXR3 MCASP Serial Data (Input/Output) IO AC26 MCASP1_AXR4 MCASP Serial Data (Input/Output) IO AA24 MCASP1_AXR5 MCASP Serial Data (Input/Output) IO Y24 MCASP1_AXR6 MCASP Serial Data (Input/Output) IO AA25 MCASP1_AXR7 MCASP Serial Data (Input/Output) IO AG26 MCASP1_AXR8 MCASP Serial Data (Input/Output) IO AF27 MCASP1_AXR9 MCASP Serial Data (Input/Output) IO AF26 MCASP1_AXR10 MCASP Serial Data (Input/Output) IO AD27 MCASP1_AXR11 MCASP Serial Data (Input/Output) IO AC25 Table 5-97. MCASP2 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP2_ACLKR MCASP Receive Bit Clock IO AA27 MCASP2_ACLKX MCASP Transmit Bit Clock IO AA29 MCASP2_AFSR MCASP Receive Frame Sync IO Y26 MCASP2_AFSX MCASP Transmit Frame Sync IO AA26 MCASP2_AXR0 MCASP Serial Data (Input/Output) IO AE25 MCASP2_AXR1 MCASP Serial Data (Input/Output) IO AF29 MCASP2_AXR2 MCASP Serial Data (Input/Output) IO AG29 MCASP2_AXR3 MCASP Serial Data (Input/Output) IO Y25 MCASP2_AXR4 MCASP Serial Data (Input/Output) IO Y26 MCASP2_AXR5 MCASP Serial Data (Input/Output) IO AA27 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-98. MCASP3 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP3_ACLKR MCASP Receive Bit Clock IO AF23 MCASP3_ACLKX MCASP Transmit Bit Clock IO AG20 MCASP3_AFSR MCASP Receive Frame Sync IO AD23 MCASP3_AFSX MCASP Transmit Frame Sync IO AD21 MCASP3_AXR0 MCASP Serial Data (Input/Output) IO AD20 MCASP3_AXR1 MCASP Serial Data (Input/Output) IO AE20 MCASP3_AXR2 MCASP Serial Data (Input/Output) IO AJ20 MCASP3_AXR3 MCASP Serial Data (Input/Output) IO AJ21 Table 5-99. MCASP4 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP4_ACLKR MCASP Receive Bit Clock IO AG25 MCASP4_ACLKX MCASP Transmit Bit Clock IO AE21 MCASP4_AFSR MCASP Receive Frame Sync IO AH26 MCASP4_AFSX MCASP Transmit Frame Sync IO AH21 MCASP4_AXR0 MCASP Serial Data (Input/Output) IO AG21 MCASP4_AXR1 MCASP Serial Data (Input/Output) IO AC21 MCASP4_AXR2 MCASP Serial Data (Input/Output) IO Y23 MCASP4_AXR3 MCASP Serial Data (Input/Output) IO AF21 Table 5-100. MCASP5 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP5_ACLKR MCASP Receive Bit Clock IO AD19 MCASP5_ACLKX MCASP Transmit Bit Clock IO AB23 MCASP5_AFSR MCASP Receive Frame Sync IO AD18 MCASP5_AFSX MCASP Transmit Frame Sync IO AC22 MCASP5_AXR0 MCASP Serial Data (Input/Output) IO AJ22 MCASP5_AXR1 MCASP Serial Data (Input/Output) IO AH22 MCASP5_AXR2 MCASP Serial Data (Input/Output) IO AD19 MCASP5_AXR3 MCASP Serial Data (Input/Output) IO AD18 Table 5-101. MCASP6 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP6_ACLKR MCASP Receive Bit Clock IO AH23 MCASP6_ACLKX MCASP Transmit Bit Clock IO AC23 MCASP6_AFSR MCASP Receive Frame Sync IO AD22 MCASP6_AFSX MCASP Transmit Frame Sync IO AG22 MCASP6_AXR0 MCASP Serial Data (Input/Output) IO AF22 MCASP6_AXR1 MCASP Serial Data (Input/Output) IO AJ23 MCASP6_AXR2 MCASP Serial Data (Input/Output) IO AH23 MCASP6_AXR3 MCASP Serial Data (Input/Output) IO AD22 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-102. MCASP7 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP7_ACLKR MCASP Receive Bit Clock IO AC24 MCASP7_ACLKX MCASP Transmit Bit Clock IO AF24 MCASP7_AFSR MCASP Receive Frame Sync IO AE24 MCASP7_AFSX MCASP Transmit Frame Sync IO AJ24 MCASP7_AXR0 MCASP Serial Data (Input/Output) IO AG24 MCASP7_AXR1 MCASP Serial Data (Input/Output) IO AD24 MCASP7_AXR2 MCASP Serial Data (Input/Output) IO AC24 MCASP7_AXR3 MCASP Serial Data (Input/Output) IO AE24 Table 5-103. MCASP8 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP8_ACLKR MCASP Receive Bit Clock IO AH24 MCASP8_ACLKX MCASP Transmit Bit Clock IO AE22 MCASP8_AFSR MCASP Receive Frame Sync IO AE23 MCASP8_AFSX MCASP Transmit Frame Sync IO AG23 MCASP8_AXR0 MCASP Serial Data (Input/Output) IO AF23 MCASP8_AXR1 MCASP Serial Data (Input/Output) IO AD23 MCASP8_AXR2 MCASP Serial Data (Input/Output) IO AH24 MCASP8_AXR3 MCASP Serial Data (Input/Output) IO AE23 Table 5-104. MCASP9 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP9_ACLKR MCASP Receive Bit Clock IO AJ27 MCASP9_ACLKX MCASP Transmit Bit Clock IO AJ25 MCASP9_AFSR MCASP Receive Frame Sync IO AJ26 MCASP9_AFSX MCASP Transmit Frame Sync IO AH25 MCASP9_AXR0 MCASP Serial Data (Input/Output) IO AG25 MCASP9_AXR1 MCASP Serial Data (Input/Output) IO AH26 MCASP9_AXR2 MCASP Serial Data (Input/Output) IO AJ27 MCASP9_AXR3 MCASP Serial Data (Input/Output) IO AJ26 Table 5-105. MCASP10 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP10_ACLKR MCASP Receive Bit Clock IO Y28 MCASP10_ACLKX MCASP Transmit Bit Clock IO U23 MCASP10_AFSR MCASP Receive Frame Sync IO V23 MCASP10_AFSX MCASP Transmit Frame Sync IO U26 MCASP10_AXR0 MCASP Serial Data (Input/Output) IO V28 MCASP10_AXR1 MCASP Serial Data (Input/Output) IO V29 MCASP10_AXR2 MCASP Serial Data (Input/Output) IO U29 MCASP10_AXR3 MCASP Serial Data (Input/Output) IO U25 MCASP10_AXR4 MCASP Serial Data (Input/Output) IO V25 MCASP10_AXR5 MCASP Serial Data (Input/Output) IO W27 MCASP10_AXR6 MCASP Serial Data (Input/Output) IO W29 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-105. MCASP10 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP10_AXR7 MCASP Serial Data (Input/Output) IO W26 Table 5-106. MCASP11 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCASP11_ACLKR MCASP Receive Bit Clock IO W23 MCASP11_ACLKX MCASP Transmit Bit Clock IO V27 MCASP11_AFSR MCASP Receive Frame Sync IO W28 MCASP11_AFSX MCASP Transmit Frame Sync IO U28 MCASP11_AXR0 MCASP Serial Data (Input/Output) IO U27 MCASP11_AXR1 MCASP Serial Data (Input/Output) IO U24 MCASP11_AXR2 MCASP Serial Data (Input/Output) IO R23 MCASP11_AXR3 MCASP Serial Data (Input/Output) IO T23 MCASP11_AXR4 MCASP Serial Data (Input/Output) IO Y29 MCASP11_AXR5 MCASP Serial Data (Input/Output) IO Y27 MCASP11_AXR6 MCASP Serial Data (Input/Output) IO W24 MCASP11_AXR7 MCASP Serial Data (Input/Output) IO W25

5.3.25 DSS

5.3.25.1 MAIN Domain

Table 5-107. DSS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DSS_FSYNC0 Video Output Frame Sync 0 O AH27, Y26 DSS_FSYNC1 Video Output Frame Sync 1 O AD19, AH28 DSS_FSYNC2 Video Output Frame Sync 2 O AA27, AH29 DSS_FSYNC3 Video Output Frame Sync 3 O AG27, Y24 VOUT0_DE Video Output Data Enable O AC22 VOUT0_EXTPCLKIN Video Output External Pixel Clock Input I AH21 VOUT0_HSYNC Video Output Horizontal Sync O AJ26 VOUT0_PCLK Video Output Pixel Clock Output O AH22 VOUT0_VSYNC Video Output Vertical Sync O AJ22 VOUT0_DATA0 Video Output Data 0 O AE22 VOUT0_DATA1 Video Output Data 1 O AG23 VOUT0_DATA2 Video Output Data 2 O AF23 VOUT0_DATA3 Video Output Data 3 O AD23 VOUT0_DATA4 Video Output Data 4 O AH24 VOUT0_DATA5 Video Output Data 5 O AG21 VOUT0_DATA6 Video Output Data 6 O AE23 VOUT0_DATA7 Video Output Data 7 O AC21 VOUT0_DATA8 Video Output Data 8 O Y23 VOUT0_DATA9 Video Output Data 9 O AF21 VOUT0_DATA10 Video Output Data 10 O AB23 VOUT0_DATA11 Video Output Data 11 O AJ25 VOUT0_DATA12 Video Output Data 12 O AH25 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-107. DSS0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VOUT0_DATA13 Video Output Data 13 O AG25 VOUT0_DATA14 Video Output Data 14 O AH26 VOUT0_DATA15 Video Output Data 15 O AJ27 VOUT0_DATA16 Video Output Data 16 O AF24 VOUT0_DATA17 Video Output Data 17 O AJ24 VOUT0_DATA18 Video Output Data 18 O AG24 VOUT0_DATA19 Video Output Data 19 O AD24 VOUT0_DATA20 Video Output Data 20 O AC24 VOUT0_DATA21 Video Output Data 21 O AE24 VOUT0_DATA22 Video Output Data 22 O AJ20 VOUT0_DATA23 Video Output Data 23 O AG20 VOUT0_VP0_DE Video Output Data Enable O AC22 VOUT0_VP0_HSYNC Video Output Horizontal Sync O AJ26 VOUT0_VP0_VSYNC Video Output Vertical Sync O AJ22 VOUT0_VP2_DE Video Output Data Enable O AC22 VOUT0_VP2_HSYNC Video Output Horizontal Sync O AJ26 VOUT0_VP2_VSYNC Video Output Vertical Sync O AJ22 VOUT1_DE Video Output Data Enable O W26 VOUT1_EXTPCLKIN Video Output External Pixel Clock Input I W24 VOUT1_HSYNC Video Output Horizontal Sync O W27 VOUT1_PCLK Video Output Pixel Clock Output O W29 VOUT1_VSYNC Video Output Vertical Sync O V25 VOUT1_DATA0 Video Output Data 0 O U23 VOUT1_DATA1 Video Output Data 1 O U26 VOUT1_DATA2 Video Output Data 2 O V28 VOUT1_DATA3 Video Output Data 3 O V29 VOUT1_DATA4 Video Output Data 4 O V27 VOUT1_DATA5 Video Output Data 5 O U28 VOUT1_DATA6 Video Output Data 6 O U29 VOUT1_DATA7 Video Output Data 7 O U25 VOUT1_DATA8 Video Output Data 8 O U27 VOUT1_DATA9 Video Output Data 9 O U24 VOUT1_DATA10 Video Output Data 10 O R23 VOUT1_DATA11 Video Output Data 11 O T23 VOUT1_DATA12 Video Output Data 12 O Y28 VOUT1_DATA13 Video Output Data 13 O V23 VOUT1_DATA14 Video Output Data 14 O W23 VOUT1_DATA15 Video Output Data 15 O W28 VOUT1_VP0_DE Video Output Data Enable O W26 VOUT1_VP0_HSYNC Video Output Horizontal Sync O W27 VOUT1_VP0_VSYNC Video Output Vertical Sync O V25 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.3.26 DP

5.3.26.1 MAIN Domain

DP0_TX functionality is available on the SERDES pins. For more information, refer to Section 5.3.16, SERDES. Table 5-108. DP0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DP0_AUXN Display port differential auxiliary data (negative) IO G6 DP0_AUXP Display port differential auxiliary data (positive) IO F7 DP0_HPD Display Port Hot Plugged Display Detect I W2, Y4

5.3.27 Camera Streaming Interface Receiver (CSI_RX_IF) Subsystem

5.3.27.1 MAIN Domain

Table 5-109. CSI0 Signal Descriptions SIGNAL NAME [1] (2) DESCRIPTION [2] PIN TYPE [3] BALL [4] CSI0_RXCLKN CSI Differential Receive Clock Input (negative) I B20 CSI0_RXCLKP CSI Differential Receive Clock Input (positive) I A21 CSI0_RXRCALIB (1) CSI pin connected to external resistor for on-chip resistor calibration A F16 CSI0_RXN0 CSI Differential Receive Input (negative) I B19 CSI0_RXP0 CSI Differential Receive Input (positive) I A20 CSI0_RXN1 CSI Differential Receive Input (negative) I D18 CSI0_RXP1 CSI Differential Receive Input (positive) I C19 CSI0_RXN2 CSI Differential Receive Input (negative) I D17 CSI0_RXP2 CSI Differential Receive Input (positive) I C18 CSI0_RXN3 CSI Differential Receive Input (negative) I E16 CSI0_RXP3 CSI Differential Receive Input (positive) I E17 (1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused. (2) CSI TX functionally is available on the DSI pins. For more information, refer to Section 5.3.28, DSI_TX. Table 5-110. CSI1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CSI1_RXCLKN CSI Differential Receive Clock Input (negative) I B17 CSI1_RXCLKP CSI Differential Receive Clock Input (positive) I A18 CSI1_RXRCALIB (1) CSI pin connected to external resistor for on-chip resistor calibration A F15 CSI1_RXN0 CSI Differential Receive Input (negative) I B16 CSI1_RXP0 CSI Differential Receive Input (positive) I A17 CSI1_RXN1 CSI Differential Receive Input (negative) I D15 CSI1_RXP1 CSI Differential Receive Input (positive) I C16 CSI1_RXN2 CSI Differential Receive Input (negative) I D14 CSI1_RXP2 CSI Differential Receive Input (positive) I C15 CSI1_RXN3 CSI Differential Receive Input (negative) I E13 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-110. CSI1 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CSI1_RXP3 CSI Differential Receive Input (positive) I E14 (1) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.

5.3.28 DSI_TX

5.3.28.1 MAIN Domain

Table 5-111. DSI_TX0 Signal Descriptions SIGNAL NAME [1] (1) DESCRIPTION [2] PIN TYPE [3] BALL [4] DSI_TXCLKN DSI Differential Transmit Clock Output (positive) O E10 DSI_TXCLKP DSI Differential Transmit Clock Output (negative) O E11 DSI_TXN0 DSI Differential Transmit Output (negative) IO D11 DSI_TXP0 DSI Differential Transmit Output (positive) IO C12 DSI_TXN1 DSI Differential Transmit Output (negative) O D12 DSI_TXP1 DSI Differential Transmit Output (positive) O C13 DSI_TXN2 DSI Differential Transmit Output (negative) O B13 DSI_TXP2 DSI Differential Transmit Output (positive) O A14 DSI_TXN3 DSI Differential Transmit Output (negative) O B14 DSI_TXP3 DSI Differential Transmit Output (positive) O A15 DSI_TXRCALIB (2) DSI pin connected to external resistor for on-chip resistor calibration A F12 (1) The functionality of these pins is controlled by CTRLMMR_DPHY_TX0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = DSI PPI, 0x1 = CSI0 TX. (2) An external 500 Ω ±1% resistor must be connected between this pin and VSS, even when the pin is unused.

5.3.29 VPFE

5.3.29.1 MAIN Domain

Table 5-112. VPFE0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VPFE0_FIELD Video Input Field Indicator I AG23 VPFE0_HD Video Input Horizontal Sync I AE22 VPFE0_PCLK Video Input Pixel Clock I AH21 VPFE0_VD Video Input Vertical Sync I AF23 VPFE0_WEN Video Input Write Enable I AD23 VPFE0_DATA0 Video Input Data I AF24 VPFE0_DATA1 Video Input Data I AJ24 VPFE0_DATA2 Video Input Data I AG24 VPFE0_DATA3 Video Input Data I AD24 VPFE0_DATA4 Video Input Data I AC24 VPFE0_DATA5 Video Input Data I AE24 VPFE0_DATA6 Video Input Data I AJ21 VPFE0_DATA7 Video Input Data I AE21 VPFE0_DATA8 Video Input Data I AG25 VPFE0_DATA9 Video Input Data I AJ27 VPFE0_DATA10 Video Input Data I AC22 VPFE0_DATA11 Video Input Data I AD19 VPFE0_DATA12 Video Input Data I AD18 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 123 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-112. VPFE0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VPFE0_DATA13 Video Input Data I AH24 VPFE0_DATA14 Video Input Data I AE23 VPFE0_DATA15 Video Input Data I AC21

5.3.30 DMTIMER

5.3.30.1 MAIN Domain

Table 5-113. DMTIMER Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] TIMER_IO0 Timer Inputs and Outputs (not tied to single timer instance) IO P24, V6 TIMER_IO1 Timer Inputs and Outputs (not tied to single timer instance) IO R24, V5 TIMER_IO2 Timer Inputs and Outputs (not tied to single timer instance) IO AD23, P23 TIMER_IO3 Timer Inputs and Outputs (not tied to single timer instance) IO AH24, R28 TIMER_IO4 Timer Inputs and Outputs (not tied to single timer instance) IO AG21, T27 TIMER_IO5 Timer Inputs and Outputs (not tied to single timer instance) IO AE23, T24 TIMER_IO6 Timer Inputs and Outputs (not tied to single timer instance) IO AC2, T26 TIMER_IO7 Timer Inputs and Outputs (not tied to single timer instance) IO AB1, T25

5.3.30.2 MCU Domain

Table 5-114. DMTIMER Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_TIMER_IO0 Timer Inputs and Outputs (not tied to single timer instance) IO E22, E28 MCU_TIMER_IO1 Timer Inputs and Outputs (not tied to single timer instance) IO E25, H27 MCU_TIMER_IO2 Timer Inputs and Outputs (not tied to single timer instance) IO A28 MCU_TIMER_IO3 Timer Inputs and Outputs (not tied to single timer instance) IO A27 MCU_TIMER_IO4 Timer Inputs and Outputs (not tied to single timer instance) IO A25 MCU_TIMER_IO5 Timer Inputs and Outputs (not tied to single timer instance) IO D24 MCU_TIMER_IO6 Timer Inputs and Outputs (not tied to single timer instance) IO G27 MCU_TIMER_IO7 Timer Inputs and Outputs (not tied to single timer instance) IO G26 MCU_TIMER_IO8 Timer Inputs and Outputs (not tied to single timer instance) IO D26 MCU_TIMER_IO9 Timer Inputs and Outputs (not tied to single timer instance) IO D25 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.31 Emulation and Debug

5.3.31.1 MAIN Domain

Table 5-115. JTAG Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] EMU0 Emulation Control 0 IO C26 EMU1 Emulation Control 1 IO B29 TCK JTAG Test Clock Input I E29 TDI JTAG Test Data Input I V1 TDO JTAG Test Data Output OZ V3 TMS JTAG Test Mode Select Input I V2 TRSTn JTAG Reset I F24 Table 5-116. Trace Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] TRC_CLK Trace Clock O U23 TRC_CTL Trace Control O U26 TRC_DATA0 Trace Data 0 O V28 TRC_DATA1 Trace Data 1 O V29 TRC_DATA2 Trace Data 2 O V27 TRC_DATA3 Trace Data 3 O U28 TRC_DATA4 Trace Data 4 O U29 TRC_DATA5 Trace Data 5 O U25 TRC_DATA6 Trace Data 6 O U27 TRC_DATA7 Trace Data 7 O U24 TRC_DATA8 Trace Data 8 O R23 TRC_DATA9 Trace Data 9 O T23 TRC_DATA10 Trace Data 10 O Y28 TRC_DATA11 Trace Data 11 O V23 TRC_DATA12 Trace Data 12 O W23 TRC_DATA13 Trace Data 13 O W28 TRC_DATA14 Trace Data 14 O V25 TRC_DATA15 Trace Data 15 O W27 TRC_DATA16 Trace Data 16 O W29 TRC_DATA17 Trace Data 17 O W26 TRC_DATA18 Trace Data 18 O Y29 TRC_DATA19 Trace Data 19 O Y27 TRC_DATA20 Trace Data 20 O W24 TRC_DATA21 Trace Data 21 O W25 TRC_DATA22 Trace Data 22 O V26 TRC_DATA23 Trace Data 23 O V24 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 125 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.3.32 System and Miscellaneous

5.3.32.1 Boot Mode Configuration

5.3.32.1.1 MAIN Domain

BOOTMODE pins are latched on the rising edge of PORz_OUT. Table 5-117. Sysboot Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] BOOTMODE0 Bootmode pin 0 I AD20 BOOTMODE1 Bootmode pin 1 I AC22 BOOTMODE2 Bootmode pin 2 I AC29 BOOTMODE3 Bootmode pin 3 I Y25 BOOTMODE4 Bootmode pin 4 I V6 BOOTMODE5 Bootmode pin 5 I V5 BOOTMODE6 Bootmode pin 6 I AB27 BOOTMODE7 (1) Bootmode pin 7 I AB24 (1) These signals must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level.

5.3.32.1.2 MCU Domain

MCU_BOOTMODE pins are latched on the rising edge of MCU_PORz_OUT. Table 5-118. Sysboot Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_BOOTMODE00 Bootmode pin 00 I E27 MCU_BOOTMODE01 Bootmode pin 01 I E24 MCU_BOOTMODE02 Bootmode pin 02 I E28 MCU_BOOTMODE03 Bootmode pin 03 I F26 MCU_BOOTMODE04 Bootmode pin 04 I F25 MCU_BOOTMODE05 Bootmode pin 05 I F28 MCU_BOOTMODE06 Bootmode pin 06 I H29 MCU_BOOTMODE07 Bootmode pin 07 I J27 MCU_BOOTMODE08 Bootmode pin 08 I G29 MCU_BOOTMODE09 Bootmode pin 09 I H28

5.3.32.2 Clock

5.3.32.2.1 MAIN Domain

Table 5-119. Clock1 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] OSC1_XI High frequency oscillator input I P29 OSC1_XO High frequency oscillator output O P27 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.3.32.2.2 WKUP Domain

Table 5-120. Clock0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] WKUP_LFOSC0_XI Low frequency (32.768 KHz) oscillator input I N28 WKUP_LFOSC0_XO Low frequency (32.768 KHz) oscillator output O N26 WKUP_OSC0_XI High frequency oscillator input I M29 WKUP_OSC0_XO High frequency oscillator output O M27

5.3.32.3 System

5.3.32.3.1 MAIN Domain

Table 5-121. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] AUDIO_EXT_REFCLK0 External clock routed to ATL or MCASP as one of the selectable input clock sources, or as a output clock output for ATL or MCASP IO AD22 AUDIO_EXT_REFCLK1 External clock routed to ATL or MCASP as one of the selectable input clock sources, or as a output clock output for ATL or MCASP IO AE20 AUDIO_EXT_REFCLK2 External clock routed to ATL or MCASP as one of the selectable input clock sources, or as a output clock output for ATL or MCASP IO W26 AUDIO_EXT_REFCLK3 External clock routed to ATL or MCASP as one of the selectable input clock sources, or as a output clock output for ATL or MCASP IO W25 EXTINTn External Interrupt I AC18 EXT_REFCLK1 External clock input to MAIN domain, routed to Timer clock muxes as one of the selectable input clock sources for Timer/WDT modules, or as reference clock to MAIN_PLL2 (PER1 PLL) I U3 OBSCLK0 Observation clock output for test and debug purposes only O V5 OBSCLK1 Observation clock output for test and debug purposes only O AB24 OBSCLK2 Observation clock output for test and debug purposes only O AD21 PORz_OUT MAIN domain POR status output O U1 RESETSTATz MAIN domain warm reset status output O T6 SOC_SAFETY_ERRORn Error signal output from MAIN domain ESM IO U4 SYSCLKOUT0 SYSCLK0 output from MAIN PLL controller (divided by 6) for test and debug purposes only O V6 VMON_ER_VSYS Voltage Monitor for System supply, requires External Resistor divider A M26 VMON_IR_VEXT Voltage Monitor for External 1.8V supply, uses Internal Resistor divider A V19

5.3.32.3.2 WKUP Domain

Table 5-122. System0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_CLKOUT0 Reference clock output for Ethernet PHYs (50MHz or 25MHz) OZ H27 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 127 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-122. System0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] MCU_EXT_REFCLK0 External system clock input I H26 MCU_OBSCLK0 Observation clock output for test and debug purposes only O H27 MCU_PORz MCU Domain cold reset I H23 MCU_PORz_OUT MCU Domain POR status output O B28 MCU_RESETSTATz MCU Domain warm reset status output O C27 MCU_RESETz MCU Domain warm reset I D28 MCU_SAFETY_ERRORn Error signal output from MCU Domain ESM IO D27 MCU_SYSCLKOUT0 MCU Domain system clock output for test and debug purposes only O H26 PORz MAIN Domain cold reset I J24 RESET_REQz MAIN Domain external warm reset request input I C28 PMIC_POWER_EN0 Pin name retained for legacy purposes, not used for power enable NA E26 PMIC_POWER_EN1 Power enable output for MAIN Domain supplies O G23

5.3.32.4 EFUSE

Table 5-123. EFUSE Signal Description SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VPP_CORE (1) Programming voltage for MAIN Domain efuses PWR AB11 VPP_MCU (1) Programming voltage for MCU Domain efuses PWR F17 (1) This signal is valid only for High-Security devices. For more details, see Section 6.7, VPP Specification for One-Time Programmable (OTP) eFUSEs. For General-Purpose devices do not connect any signal, test point, or board trace to this signal.

5.3.33 Power Supply

All power balls must be supplied with the voltages specified in Section 6.4, Recommended Operating Conditions, unless otherwise specified in Section 5.3, Signal Descriptions. Table 5-124. Power Supply Signal Description SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] CAP_VDDS0 (1) External capacitor connection for CAP U7 CAP_VDDS0_MCU (1) External capacitor connection for CAP K23 CAP_VDDS1 (1) External capacitor connection for CAP AB21 CAP_VDDS1_MCU (1) External capacitor connection for CAP J18 CAP_VDDS2 (1) External capacitor connection for CAP Y18 CAP_VDDS2_MCU (1) External capacitor connection for CAP J19 CAP_VDDS3 (1) External capacitor connection for CAP W21 CAP_VDDS4 (1) External capacitor connection for CAP AA22 CAP_VDDS5 (1) External capacitor connection for CAP R22 CAP_VDDS6 (1) External capacitor connection for CAP V22 VDDAR_CORE MAIN domain RAM supply PWR L14, V13, V16, W19 VDDAR_CPU CPU RAM supply PWR L11, W12 VDDAR_MCU MCUSS RAM supply PWR K19, T19 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-124. Power Supply Signal Description (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VDDA_0P8_CSIRX CSIRX analog supply low PWR H17 VDDA_0P8_DP Displayport SERDES analog supply low PWR G12, J12 VDDA_0P8_DP_C Displayport SERDES clock supply PWR G14, H13 VDDA_0P8_DSITX DSITX clock supply PWR H15 VDDA_0P8_DSITX_C DSITX clock supply PWR J16 VDDA_0P8_UFS UFS analog supply low PWR AB9 VDDA_0P8_USB USB0-1 0.8 V analog supply PWR AA10 VDDA_0P8_SERDES0_1 SERDES0-1 analog supply low PWR AA15, Y14, Y16 VDDA_0P8_SERDES2_3 SERDES2-3 analog supply low PWR AA12, Y11, Y13 VDDA_0P8_SERDES_C0_1 SERDES0-1 clock supply PWR AB14, AB15 VDDA_0P8_SERDES_C2_3 SERDES2-3 clock supply PWR AB12, AB13 VDDA_1P8_CSIRX CSIRX analog supply high PWR G16 VDDA_1P8_DP Displayport SERDES analog supply high PWR H11 VDDA_1P8_DSITX DSITX analog supply high PWR J14 VDDA_1P8_UFS UFS analog supply high PWR AC8 VDDA_1P8_USB USB0-1 1.8 V analog supply PWR AC9 VDDA_1P8_SERDES0_1 SERDES0-1 analog supply high PWR AC14, AC15 VDDA_1P8_SERDES2_3 SERDES2-3 analog supply high PWR AC11, AC12 VDDA_3P3_USB USB0-1 3.3 V analog supply PWR AB10 VDDA_ADC0 ADC analog supply and high voltage reference (VREFP) PWR N22 VDDA_ADC1 ADC analog supply and high voltage reference (VREFP) PWR M23 VDDA_0P8_PLL_DDR DDR PLL analog supply PWR N9 VDDA_MCU_PLLGRP0 Analog supply for MCU PLL Group 0 PWR G18 VDDA_MCU_TEMP Analog supply for temperature sensor 0 in MCU domain PWR P21 VDDA_1P8_MLB MLB IO supply (6-pin interface) PWR W7 VDDA_PLLGRP0 Analog supply for MAIN PLL Group 0 PWR Y20 VDDA_PLLGRP1 Analog supply for MAIN PLL Group 1 PWR W17 VDDA_PLLGRP2 Analog supply for MAIN PLL Group 2 PWR M17 VDDA_PLLGRP3 Analog supply for MAIN PLL Group 3 PWR L12 VDDA_PLLGRP4 Analog supply for MAIN PLL Group 4 PWR R11 VDDA_PLLGRP5 Analog supply for MAIN PLL Group 5 (DDR) PWR P9 VDDA_PLLGRP6 Analog supply for MAIN PLL Group 6 PWR W18 VDDA_0P8_PLL_MLB MLB PLL analog supply PWR W8 VDDA_POR_WKUP WKUP domain analog supply PWR P22 VDDA_TEMP0_1 Analog supply for temperature sensor 0 and 1 PWR W15 VDDA_TEMP2_3 Analog supply for temperature sensor 2 and 3 PWR H9 VDDA_WKUP Oscillator supply for WKUP domain PWR H22 VDDSHV0 IO supply for MAIN domain general PWR U8, V7 VDDSHV0_MCU IO supply MCUSS general IO group, and MCU and MAIN domain warm reset pins PWR L22, M22 VDDSHV1 IO supply for MAIN domain IO group 1 PWR AA19, AA20, AC19, AC20 VDDSHV1_MCU IO supply for MCUSS IO group 1 PWR H19, H21, J20 VDDSHV2 IO supply for MAIN domain IO group 2 PWR AA17, AB16, AB18, AC17 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 129 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-124. Power Supply Signal Description (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VDDSHV2_MCU IO supply for MCUSS IO group 2 PWR J22, K21 VDDSHV3 IO supply for MAIN domain IO group 3 PWR V21, W22 VDDSHV4 IO supply for MAIN domain IO group 4 PWR AA21, Y22 VDDSHV5 IO supply for MAIN domain IO group 5 PWR T20, T22 VDDSHV6 IO supply for MAIN domain IO group 6 PWR U20, U22 VDDS_DDR DDR inteface power supply PWR A1, G8, J8, K7, L8, M7, N8, P7, R8, T1 VDDS_DDR_BIAS Bias supply for LPDDR4 PWR H7, J6, R6, T7 VDDS_DDR_C IO power for DDR Memory Clock Bit (MCB) macro PWR M9 VDDS_MMC0 MMC0 IO supply PWR AA8, AB7, Y7 VDDS_OSC1 HFOSC1 supply PWR R21 VDD_CORE MAIN domain core supply PWR J10, K11, K13, K15, K17, K9, L10, L16, L18, M15, N14, N16, N18, P13, P15, P17, R14, R16, R18, R20, T15, T17, T9, U14, U16, U18, V15, V17, V20, W14 VDD_CPU CPU core supply PWR N10, P11, R10, R12, U10, V11, V9, W10 VDDA_0P8_DLL_MMC0 MMC0 DLL analog supply PWR Y9 VDD_MCU MCUSS core supply PWR L20, M19, M21, N20, P19 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-124. Power Supply Signal Description (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] VSS Ground GND AA13, AC10, AC13, AD11, AD14, AD17, AE10, AE12, AE15, AE16, AE19, AE7, AF20, AF25, AF5, AG4, AG7, AH2, AH20, AH5, AJ4, AJ7, B3, B6, C1, C5, D2, D4, E1, E5, F4, G1, G7, H4, H6, K1, K4, L3, M1, M28, M4, M6, N27, N29, N3, P1, P28, P4, R3, U5 A10, A13, A16, A19, A22, A7, AA11, AA14, AA16, AA18, AA7, AA9, AB17, AB19, AB20, AB22, AB8, AC16, AF11, AF14, AF17, AF8, AG10, AG13, AG16, AG19, AH11, AH14, AH17, AH8, AJ10, AJ13, AJ16, AJ19, B12, B15, B18, B21, B9, C11, C14, C17, C20, C8, D10, D13, D16, D19, D7, E12, E15, E9, F14, F8, G11, G13, G15, G17, H10, H12, H14, H16, H18, H20, H8, J11, J13, J15, J17, J21, J23, J7, J9, K10, K12, K14, K16, K18, K20, K22, K8, L13, L15, L17, L19, L21, L23, L7, L9, M10, M14, M16, M18, M20, M8, N15, N17, N19, N21, N7, P10, P12, P14, P16, P18, P20, P8, R13, R15, R17, R19, R7, R9, T10, T14, T16, T18, T21, T8, U15, U17, U19, U21, U9, V10, V12, V14, V18, V8, W11, W13, W16, W20, W9, Y10, Y12, Y15, Y17, Y19, Y21, Y8 (1) This pin must always be connected via a 1-μF ±10% capacitor to VSS. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

5.4 Pin Multiplexing

Many device pins support multiple signal functions. Some signal functions are selected via a single layer of multiplexers associated with pins. Other signal functions are selected via two or more layers of multiplexers, where one layer is associated with the pins and other layers are associated with peripheral logic functions. Table 5-125, Pin Multiplexing only describes signal multiplexing at the pins. For more information, related to signal multiplexing at the pins, see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Refer to the respective peripheral chapter in the device TRM for information associated with peripheral signal multiplexing. Note When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided. Note Table 5-125, Pin Multiplexing does not include SerDes signal functions. For more information, refer to the Serializer/Deserializer (SerDes) chapter in the device TRM. Note Table 5-125, Pin Multiplexing does not include DPHY_TX signal functions. For more information, refer to the Shared D-PHY Transmitter (DPHY_TX) chapter in the device TRM. For more information on the I/O cell configurations, see Pad Configuration Registers section in Device Configuration chapter in the device TRM. Table 5-125. Pin Multiplexing ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C2 PADCONFIG165 AD1 MLB0_ML BSP GPIO1_30 0x00011C2 PADCONFIG167 AC3 MLB0_ML BDP GPIO1_32 0x00011C2 PADCONFIG164 U6 USB0_DR VVBUS USB1_DR VVBUS GPIO1_29 0x00011C2 PADCONFIG166 AC1 MLB0_ML BSN GPIO1_31 0x00011C2 PADCONFIG168 AD3 MLB0_ML BDN GPIO1_33 0x00011C2 PADCONFIG169 AD2 MLB0_ML BCP GPIO1_34 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C2 PADCONFIG170 AE2 MLB0_ML BCN GPIO1_35 0x00011C0 PADCONFIG0 AC18 EXTINTn GPIO0_0 0x00011C0 PADCONFIG1 AC23 PRG1_PR U0_GPO0 PRG1_PR U0_GPI0 PRG1_RG MII1_RD0 PRG1_PW M3_A0 RGMII1_R RMII1_RX GPIO0_1 GPMC0_B E1n RGMII7_R MCASP6_ ACLKX UART0_R XD 0x00011C0 PADCONFIG2 AG22 PRG1_PR U0_GPO1 PRG1_PR U0_GPI1 PRG1_RG MII1_RD1 PRG1_PW M3_B0 RGMII1_R RMII1_RX GPIO0_2 GPMC0_W AIT0 RGMII7_R MCASP6_ AFSX UART0_TX D 0x00011C0 PADCONFIG3 AF22 PRG1_PR U0_GPO2 PRG1_PR U0_GPI2 PRG1_RG MII1_RD2 PRG1_PW M2_A0 RGMII1_R RMII1_CR S_DV GPIO0_3 GPMC0_W AIT1 RGMII7_R MCASP6_ AXR0 UART1_R XD 0x00011C0 PADCONFIG4 AJ23 PRG1_PR U0_GPO3 PRG1_PR U0_GPI3 PRG1_RG MII1_RD3 PRG1_PW M3_A2 RGMII1_R RMII1_RX _ER GPIO0_4 GPMC0_DI R RGMII7_R MCASP6_ AXR1 UART1_TX D 0x00011C0 PADCONFIG5 AH23 PRG1_PR U0_GPO4 PRG1_PR U0_GPI4 PRG1_RG MII1_RX_ CTL PRG1_PW M2_B0 RGMII1_R X_CTL RMII1_TX GPIO0_5 GPMC0_C Sn2 RGMII7_R X_CTL MCASP6_ AXR2 MCASP6_ ACLKR UART2_R XD 0x00011C0 PADCONFIG6 AD20 PRG1_PR U0_GPO5 PRG1_PR U0_GPI5 PRG1_PW M3_B2 RMII1_TX_ EN GPIO0_6 GPMC0_W En MCASP3_ AXR0 BOOTMO DE0 0x00011C0 PADCONFIG7 AD22 PRG1_PR U0_GPO6 PRG1_PR U0_GPI6 PRG1_RG MII1_RXC PRG1_PW M3_A1 RGMII1_R XC RMII1_TX AUDIO_EX T_REFCLK GPIO0_7 GPMC0_C Sn3 RGMII7_R XC MCASP6_ AXR3 MCASP6_ AFSR UART2_TX D 0x00011C0 PADCONFIG8 AE20 PRG1_PR U0_GPO7 PRG1_PR U0_GPI7 PRG1_IEP 0_EDC_LA TCH_IN1 PRG1_PW M3_B1 AUDIO_EX T_REFCLK MCAN4_T X GPIO0_8 MCASP3_ AXR1 0x00011C0 PADCONFIG9 AJ20 PRG1_PR U0_GPO8 PRG1_PR U0_GPI8 PRG1_PW M2_A1 RMII5_RX MCAN4_R X GPIO0_9 GPMC0_O En_REn VOUT0_D ATA22 MCASP3_ AXR2 0x00011C0 PADCONFIG10 AG20 PRG1_PR U0_GPO9 PRG1_PR U0_GPI9 PRG1_UA RT0_CTSn PRG1_PW M3_TZ_IN SPI6_CS1 RMII5_RX GPIO0_10 GPMC0_A DVn_ALE PRG1_IEP 0_EDIO_D ATA_IN_O UT28 VOUT0_D ATA23 MCASP3_ ACLKX 0x00011C0 PADCONFIG11 AD21 PRG1_PR U0_GPO1 PRG1_PR U0_GPI10 PRG1_UA RT0_RTSn PRG1_PW M2_B1 SPI6_CS2 RMII5_CR S_DV GPIO0_11 GPMC0_B E0n_CLE PRG1_IEP 0_EDIO_D ATA_IN_O UT29 OBSCLK2 MCASP3_ AFSX 0x00011C0 PADCONFIG12 AF24 PRG1_PR U0_GPO11 PRG1_PR U0_GPI11 PRG1_RG MII1_TD0 PRG1_PW M3_TZ_O UT RGMII1_T MCAN4_T X GPIO0_12 RGMII7_T VOUT0_D ATA16 VPFE0_DA TA0 MCASP7_ ACLKX 0x00011C0 PADCONFIG13 AJ24 PRG1_PR U0_GPO1 PRG1_PR U0_GPI12 PRG1_RG MII1_TD1 PRG1_PW M0_A0 RGMII1_T MCAN4_R X GPIO0_13 RGMII7_T VOUT0_D ATA17 VPFE0_DA TA1 MCASP7_ AFSX 0x00011C0 PADCONFIG14 AG24 PRG1_PR U0_GPO1 PRG1_PR U0_GPI13 PRG1_RG MII1_TD2 PRG1_PW M0_B0 RGMII1_T MCAN5_T X GPIO0_14 RGMII7_T VOUT0_D ATA18 VPFE0_DA TA2 MCASP7_ AXR0 0x00011C0 PADCONFIG15 AD24 PRG1_PR U0_GPO1 PRG1_PR U0_GPI14 PRG1_RG MII1_TD3 PRG1_PW M0_A1 RGMII1_T MCAN5_R X GPIO0_15 RGMII7_T VOUT0_D ATA19 VPFE0_DA TA3 MCASP7_ AXR1 0x00011C0 PADCONFIG16 AC24 PRG1_PR U0_GPO1 PRG1_PR U0_GPI15 PRG1_RG MII1_TX_C TL PRG1_PW M0_B1 RGMII1_T X_CTL MCAN6_T X GPIO0_16 RGMII7_T X_CTL VOUT0_D ATA20 VPFE0_DA TA4 MCASP7_ AXR2 MCASP7_ ACLKR www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 133 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C0 PADCONFIG17 AE24 PRG1_PR U0_GPO1 PRG1_PR U0_GPI16 PRG1_RG MII1_TXC PRG1_PW M0_A2 RGMII1_T XC MCAN6_R X GPIO0_17 RGMII7_T XC VOUT0_D ATA21 VPFE0_DA TA5 MCASP7_ AXR3 MCASP7_ AFSR 0x00011C0 PADCONFIG19 AJ21 PRG1_PR U0_GPO1 PRG1_PR U0_GPI17 PRG1_IEP 0_EDC_SY NC_OUT1 PRG1_PW M0_B2 RMII5_TX MCAN5_T X GPIO0_18 VPFE0_DA TA6 MCASP3_ AXR3 0x00011C0 PADCONFIG20 AE21 PRG1_PR U0_GPO1 PRG1_PR U0_GPI18 PRG1_IEP 0_EDC_LA TCH_IN0 PRG1_PW M0_TZ_IN RMII5_RX _ER MCAN5_R X GPIO0_19 VPFE0_DA TA7 MCASP4_ ACLKX 0x00011C0 PADCONFIG21 AH21 PRG1_PR U0_GPO1 PRG1_PR U0_GPI19 PRG1_IEP 0_EDC_SY NC_OUT0 PRG1_PW M0_TZ_O UT RMII5_TX MCAN6_T X GPIO0_20 VOUT0_E XTPCLKIN VPFE0_PC LK MCASP4_ AFSX 0x00011C0 PADCONFIG22 AE22 PRG1_PR U1_GPO0 PRG1_PR U1_GPI0 PRG1_RG MII2_RD0 RGMII2_R RMII2_RX GPIO0_21 RGMII8_R VOUT0_D ATA0 VPFE0_H D MCASP8_ ACLKX 0x00011C0 PADCONFIG23 AG23 PRG1_PR U1_GPO1 PRG1_PR U1_GPI1 PRG1_RG MII2_RD1 RGMII2_R RMII2_RX GPIO0_22 RGMII8_R VOUT0_D ATA1 VPFE0_FI ELD MCASP8_ AFSX 0x00011C0 PADCONFIG24 AF23 PRG1_PR U1_GPO2 PRG1_PR U1_GPI2 PRG1_RG MII2_RD2 PRG1_PW M2_A2 RGMII2_R RMII2_CR S_DV GPIO0_23 RGMII8_R VOUT0_D ATA2 VPFE0_VD MCASP8_ AXR0 MCASP3_ ACLKR 0x00011C0 PADCONFIG25 AD23 PRG1_PR U1_GPO3 PRG1_PR U1_GPI3 PRG1_RG MII2_RD3 RGMII2_R RMII2_RX _ER GPIO0_24 RGMII8_R EQEP1_A VOUT0_D ATA3 VPFE0_W EN MCASP8_ AXR1 MCASP3_ AFSR TIMER_IO 0x00011C0 PADCONFIG26 AH24 PRG1_PR U1_GPO4 PRG1_PR U1_GPI4 PRG1_RG MII2_RX_ CTL PRG1_PW M2_B2 RGMII2_R X_CTL RMII2_TX GPIO0_25 RGMII8_R X_CTL EQEP1_B VOUT0_D ATA4 VPFE0_DA TA13 MCASP8_ AXR2 MCASP8_ ACLKR TIMER_IO 0x00011C0 PADCONFIG27 AG21 PRG1_PR U1_GPO5 PRG1_PR U1_GPI5 RMII5_TX_ EN MCAN6_R X GPIO0_26 GPMC0_W Pn EQEP1_S VOUT0_D ATA5 MCASP4_ AXR0 TIMER_IO 0x00011C0 PADCONFIG28 AE23 PRG1_PR U1_GPO6 PRG1_PR U1_GPI6 PRG1_RG MII2_RXC RGMII2_R XC RMII2_TX GPIO0_27 RGMII8_R XC VOUT0_D ATA6 VPFE0_DA TA14 MCASP8_ AXR3 MCASP8_ AFSR TIMER_IO 0x00011C0 PADCONFIG29 AC21 PRG1_PR U1_GPO7 PRG1_PR U1_GPI7 PRG1_IEP 1_EDC_LA TCH_IN1 SPI6_CS0 RMII6_RX _ER MCAN7_T X GPIO0_28 VOUT0_D ATA7 VPFE0_DA TA15 MCASP4_ AXR1 UART3_TX D 0x00011C0 PADCONFIG30 Y23 PRG1_PR U1_GPO8 PRG1_PR U1_GPI8 PRG1_PW M2_TZ_O UT RMII6_RX MCAN7_R X GPIO0_29 GPMC0_C Sn1 VOUT0_D ATA8 MCASP4_ AXR2 UART3_R XD 0x00011C0 PADCONFIG31 AF21 PRG1_PR U1_GPO9 PRG1_PR U1_GPI9 PRG1_UA RT0_RXD SPI6_CS3 RMII6_RX MCAN8_T X GPIO0_30 GPMC0_C Sn0 PRG1_IEP 0_EDIO_D ATA_IN_O UT30 VOUT0_D ATA9 MCASP4_ AXR3 0x00011C0 PADCONFIG32 AB23 PRG1_PR U1_GPO1 PRG1_PR U1_GPI10 PRG1_UA RT0_TXD PRG1_PW M2_TZ_IN RMII6_CR S_DV MCAN8_R X GPIO0_31 GPMC0_C LKOUT PRG1_IEP 0_EDIO_D ATA_IN_O UT31 VOUT0_D ATA10 GPMC0_F CLK_MUX MCASP5_ ACLKX 0x00011C0 PADCONFIG33 AJ25 PRG1_PR U1_GPO11 PRG1_PR U1_GPI11 PRG1_RG MII2_TD0 RGMII2_T RMII2_TX_ EN GPIO0_32 RGMII8_T EQEP1_I VOUT0_D ATA11 MCASP9_ ACLKX 0x00011C0 PADCONFIG34 AH25 PRG1_PR U1_GPO1 PRG1_PR U1_GPI12 PRG1_RG MII2_TD1 PRG1_PW M1_A0 RGMII2_T MCAN7_T X GPIO0_33 RGMII8_T VOUT0_D ATA12 MCASP9_ AFSX 0x00011C0 PADCONFIG35 AG25 PRG1_PR U1_GPO1 PRG1_PR U1_GPI13 PRG1_RG MII2_TD2 PRG1_PW M1_B0 RGMII2_T MCAN7_R X GPIO0_34 RGMII8_T VOUT0_D ATA13 VPFE0_DA TA8 MCASP9_ AXR0 MCASP4_ ACLKR DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C0 PADCONFIG36 AH26 PRG1_PR U1_GPO1 PRG1_PR U1_GPI14 PRG1_RG MII2_TD3 PRG1_PW M1_A1 RGMII2_T MCAN8_T X GPIO0_35 RGMII8_T VOUT0_D ATA14 MCASP9_ AXR1 MCASP4_ AFSR 0x00011C0 PADCONFIG37 AJ27 PRG1_PR U1_GPO1 PRG1_PR U1_GPI15 PRG1_RG MII2_TX_C TL PRG1_PW M1_B1 RGMII2_T X_CTL MCAN8_R X GPIO0_36 RGMII8_T X_CTL VOUT0_D ATA15 VPFE0_DA TA9 MCASP9_ AXR2 MCASP9_ ACLKR 0x00011C0 PADCONFIG38 AJ26 PRG1_PR U1_GPO1 PRG1_PR U1_GPI16 PRG1_RG MII2_TXC PRG1_PW M1_A2 RGMII2_T XC GPIO0_37 RGMII8_T XC VOUT0_V P2_HSYN C VOUT0_H SYNC MCASP9_ AXR3 MCASP9_ AFSR VOUT0_V P0_HSYN C 0x00011C0 PADCONFIG39 AC22 PRG1_PR U1_GPO1 PRG1_PR U1_GPI17 PRG1_IEP 1_EDC_SY NC_OUT1 PRG1_PW M1_B2 SPI6_CLK RMII6_TX_ EN PRG1_EC AP0_SYN C_OUT GPIO0_38 VOUT0_V P2_DE VOUT0_D E VPFE0_DA TA10 MCASP5_ AFSX VOUT0_V P0_DE BOOTMO DE1 0x00011C0 PADCONFIG40 AJ22 PRG1_PR U1_GPO1 PRG1_PR U1_GPI18 PRG1_IEP 1_EDC_LA TCH_IN0 PRG1_PW M1_TZ_IN SPI6_D0 RMII6_TX PRG1_EC AP0_SYN C_IN GPIO0_39 VOUT0_V P2_VSYN C VOUT0_V SYNC MCASP5_ AXR0 VOUT0_V P0_VSYN C 0x00011C0 PADCONFIG41 AH22 PRG1_PR U1_GPO1 PRG1_PR U1_GPI19 PRG1_IEP 1_EDC_SY NC_OUT0 PRG1_PW M1_TZ_O UT SPI6_D1 RMII6_TX PRG1_EC AP0_IN_A PWM_OUT GPIO0_40 VOUT0_P CLK MCASP5_ AXR1 0x00011C0 PADCONFIG42 AD19 PRG1_MDI O0_MDIO SPI1_CS2 I2C4_SCL GPIO0_41 DSS_FSY NC1 VPFE0_DA TA11 MCASP5_ AXR2 MCASP5_ ACLKR UART3_CT Sn 0x00011C0 AC PADCONFIG43 AD18 PRG1_MDI O0_MDC SPI1_CS3 I2C4_SDA RMII_REF _CLK GPIO0_42 VPFE0_DA TA12 MCASP5_ AXR3 MCASP5_ AFSR UART3_RT Sn 0x00011C0 PADCONFIG44 AF28 PRG0_PR U0_GPO0 PRG0_PR U0_GPI0 PRG0_RG MII1_RD0 PRG0_PW M3_A0 RGMII3_R RMII3_RX GPIO0_43 MCASP0_ AXR0 0x00011C0 PADCONFIG45 AE28 PRG0_PR U0_GPO1 PRG0_PR U0_GPI1 PRG0_RG MII1_RD1 PRG0_PW M3_B0 RGMII3_R RMII3_RX GPIO0_44 MCASP0_ AXR1 0x00011C0 PADCONFIG46 AE27 PRG0_PR U0_GPO2 PRG0_PR U0_GPI2 PRG0_RG MII1_RD2 PRG0_PW M2_A0 RGMII3_R RMII3_CR S_DV GPIO0_45 UART3_R XD MCASP0_ ACLKR 0x00011C0 BC PADCONFIG47 AD26 PRG0_PR U0_GPO3 PRG0_PR U0_GPI3 PRG0_RG MII1_RD3 PRG0_PW M3_A2 RGMII3_R RMII3_RX _ER GPIO0_46 UART3_TX D MCASP0_ AFSR 0x00011C0 PADCONFIG48 AD25 PRG0_PR U0_GPO4 PRG0_PR U0_GPI4 PRG0_RG MII1_RX_ CTL PRG0_PW M2_B0 RGMII3_R X_CTL RMII3_TX GPIO0_47 MCASP0_ AXR2 0x00011C0 PADCONFIG49 AC29 PRG0_PR U0_GPO5 PRG0_PR U0_GPI5 PRG0_PW M3_B2 RMII3_TX GPIO0_48 GPMC0_A MCASP0_ AXR3 BOOTMO DE2 0x00011C0 PADCONFIG50 AE26 PRG0_PR U0_GPO6 PRG0_PR U0_GPI6 PRG0_RG MII1_RXC PRG0_PW M3_A1 RGMII3_R XC RMII3_TX_ EN GPIO0_49 MCASP0_ AXR4 0x00011C0 CC PADCONFIG51 AC28 PRG0_PR U0_GPO7 PRG0_PR U0_GPI7 PRG0_IEP 0_EDC_LA TCH_IN1 PRG0_PW M3_B1 PRG0_EC AP0_SYN C_IN MCAN9_T X GPIO0_50 GPMC0_A MCASP0_ AXR5 0x00011C0 PADCONFIG52 AC27 PRG0_PR U0_GPO8 PRG0_PR U0_GPI8 PRG0_PW M2_A1 MCAN9_R X GPIO0_51 GPMC0_A MCASP0_ AXR6 UART6_R XD 0x00011C0 PADCONFIG53 AB26 PRG0_PR U0_GPO9 PRG0_PR U0_GPI9 PRG0_UA RT0_CTSn PRG0_PW M3_TZ_IN SPI3_CS1 PRG0_IEP 0_EDIO_D ATA_IN_O UT28 MCAN10_ TX GPIO0_52 GPMC0_A MCASP0_ ACLKX UART6_TX D 0x00011C0 PADCONFIG54 AB25 PRG0_PR U0_GPO1 PRG0_PR U0_GPI10 PRG0_UA RT0_RTSn PRG0_PW M2_B1 SPI3_CS2 PRG0_IEP 0_EDIO_D ATA_IN_O UT29 MCAN10_ RX GPIO0_53 GPMC0_A MCASP0_ AFSX www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C0 DC PADCONFIG55 AJ28 PRG0_PR U0_GPO11 PRG0_PR U0_GPI11 PRG0_RG MII1_TD0 PRG0_PW M3_TZ_O UT RGMII3_T GPIO0_54 CLKOUT MCASP0_ AXR7 0x00011C0 PADCONFIG56 AH27 PRG0_PR U0_GPO1 PRG0_PR U0_GPI12 PRG0_RG MII1_TD1 PRG0_PW M0_A0 RGMII3_T GPIO0_55 DSS_FSY NC0 MCASP0_ AXR8 0x00011C0 PADCONFIG57 AH29 PRG0_PR U0_GPO1 PRG0_PR U0_GPI13 PRG0_RG MII1_TD2 PRG0_PW M0_B0 RGMII3_T GPIO0_56 DSS_FSY NC2 MCASP0_ AXR9 0x00011C0 PADCONFIG58 AG28 PRG0_PR U0_GPO1 PRG0_PR U0_GPI14 PRG0_RG MII1_TD3 PRG0_PW M0_A1 RGMII3_T GPIO0_57 UART4_R XD MCASP0_ AXR10 0x00011C0 EC PADCONFIG59 AG27 PRG0_PR U0_GPO1 PRG0_PR U0_GPI15 PRG0_RG MII1_TX_C TL PRG0_PW M0_B1 RGMII3_T X_CTL GPIO0_58 UART4_TX D DSS_FSY NC3 MCASP0_ AXR11 0x00011C0 PADCONFIG60 AH28 PRG0_PR U0_GPO1 PRG0_PR U0_GPI16 PRG0_RG MII1_TXC PRG0_PW M0_A2 RGMII3_T XC GPIO0_59 DSS_FSY NC1 MCASP0_ AXR12 0x00011C0 PADCONFIG61 AB24 PRG0_PR U0_GPO1 PRG0_PR U0_GPI17 PRG0_IEP 0_EDC_SY NC_OUT1 PRG0_PW M0_B2 PRG0_EC AP0_SYN C_OUT GPIO0_60 GPMC0_A OBSCLK1 MCASP0_ AXR13 BOOTMO DE7 0x00011C0 PADCONFIG62 AB29 PRG0_PR U0_GPO1 PRG0_PR U0_GPI18 PRG0_IEP 0_EDC_LA TCH_IN0 PRG0_PW M0_TZ_IN PRG0_EC AP0_IN_A PWM_OUT GPIO0_61 GPMC0_A MCASP0_ AXR14 0x00011C0 FC PADCONFIG63 AB28 PRG0_PR U0_GPO1 PRG0_PR U0_GPI19 PRG0_IEP 0_EDC_SY NC_OUT0 PRG0_PW M0_TZ_O UT GPIO0_62 GPMC0_A MCASP0_ AXR15 0x00011C1 PADCONFIG64 AE29 PRG0_PR U1_GPO0 PRG0_PR U1_GPI0 PRG0_RG MII2_RD0 RGMII4_R RMII4_RX GPIO0_63 UART4_CT Sn MCASP1_ AXR0 UART5_R XD 0x00011C1 PADCONFIG65 AD28 PRG0_PR U1_GPO1 PRG0_PR U1_GPI1 PRG0_RG MII2_RD1 RGMII4_R RMII4_RX GPIO0_64 UART4_RT Sn MCASP1_ AXR1 UART5_TX D 0x00011C1 PADCONFIG66 AD27 PRG0_PR U1_GPO2 PRG0_PR U1_GPI2 PRG0_RG MII2_RD2 PRG0_PW M2_A2 RGMII4_R RMII4_CR S_DV GPIO0_65 GPMC0_A MCASP1_ ACLKR MCASP1_ AXR10 0x00011C1 PADCONFIG67 AC25 PRG0_PR U1_GPO3 PRG0_PR U1_GPI3 PRG0_RG MII2_RD3 RGMII4_R RMII4_RX _ER GPIO0_66 MCASP1_ AFSR MCASP1_ AXR11 0x00011C1 PADCONFIG68 AD29 PRG0_PR U1_GPO4 PRG0_PR U1_GPI4 PRG0_RG MII2_RX_ CTL PRG0_PW M2_B2 RGMII4_R X_CTL RMII4_TX GPIO0_67 GPMC0_A MCASP1_ AXR2 0x00011C1 PADCONFIG69 AB27 PRG0_PR U1_GPO5 PRG0_PR U1_GPI5 GPIO0_68 GPMC0_A MCASP1_ ACLKX BOOTMO DE6 0x00011C1 PADCONFIG70 AC26 PRG0_PR U1_GPO6 PRG0_PR U1_GPI6 PRG0_RG MII2_RXC RGMII4_R XC RMII4_TX GPIO0_69 GPMC0_A MCASP1_ AXR3 0x00011C1 PADCONFIG71 AA24 PRG0_PR U1_GPO7 PRG0_PR U1_GPI7 PRG0_IEP 1_EDC_LA TCH_IN1 SPI3_CS0 MCAN11_T X GPIO0_70 GPMC0_A MCASP1_ AXR4 UART2_TX D 0x00011C1 PADCONFIG72 AA28 PRG0_PR U1_GPO8 PRG0_PR U1_GPI8 PRG0_PW M2_TZ_O UT MCAN11_ RX GPIO0_71 GPMC0_A D10 MCASP1_ AFSX DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C1 PADCONFIG73 Y24 PRG0_PR U1_GPO9 PRG0_PR U1_GPI9 PRG0_UA RT0_RXD SPI3_CS3 PRG0_IEP 0_EDIO_D ATA_IN_O UT30 GPIO0_72 GPMC0_A D11 DSS_FSY NC3 MCASP1_ AXR5 UART8_R XD 0x00011C1 PADCONFIG74 AA25 PRG0_PR U1_GPO1 PRG0_PR U1_GPI10 PRG0_UA RT0_TXD PRG0_PW M2_TZ_IN PRG0_IEP 0_EDIO_D ATA_IN_O UT31 GPIO0_73 GPMC0_A D12 CLKOUT MCASP1_ AXR6 UART8_TX D 0x00011C1 PADCONFIG75 AG26 PRG0_PR U1_GPO11 PRG0_PR U1_GPI11 PRG0_RG MII2_TD0 RGMII4_T RMII4_TX_ EN GPIO0_74 GPMC0_A MCASP1_ AXR7 0x00011C1 PADCONFIG76 AF27 PRG0_PR U1_GPO1 PRG0_PR U1_GPI12 PRG0_RG MII2_TD1 PRG0_PW M1_A0 RGMII4_T GPIO0_75 MCASP1_ AXR8 UART8_CT Sn 0x00011C1 PADCONFIG77 AF26 PRG0_PR U1_GPO1 PRG0_PR U1_GPI13 PRG0_RG MII2_TD2 PRG0_PW M1_B0 RGMII4_T GPIO0_76 MCASP1_ AXR9 UART8_RT Sn 0x00011C1 PADCONFIG78 AE25 PRG0_PR U1_GPO1 PRG0_PR U1_GPI14 PRG0_RG MII2_TD3 PRG0_PW M1_A1 RGMII4_T GPIO0_77 MCASP2_ AXR0 UART2_CT Sn 0x00011C1 PADCONFIG79 AF29 PRG0_PR U1_GPO1 PRG0_PR U1_GPI15 PRG0_RG MII2_TX_C TL PRG0_PW M1_B1 RGMII4_T X_CTL GPIO0_78 MCASP2_ AXR1 UART2_RT Sn 0x00011C1 PADCONFIG80 AG29 PRG0_PR U1_GPO1 PRG0_PR U1_GPI16 PRG0_RG MII2_TXC PRG0_PW M1_A2 RGMII4_T XC GPIO0_79 MCASP2_ AXR2 0x00011C1 PADCONFIG81 Y25 PRG0_PR U1_GPO1 PRG0_PR U1_GPI17 PRG0_IEP 1_EDC_SY NC_OUT1 PRG0_PW M1_B2 SPI3_CLK GPIO0_80 GPMC0_A D13 MCASP2_ AXR3 BOOTMO DE3 0x00011C1 PADCONFIG82 AA26 PRG0_PR U1_GPO1 PRG0_PR U1_GPI18 PRG0_IEP 1_EDC_LA TCH_IN0 PRG0_PW M1_TZ_IN SPI3_D0 MCAN12_ TX GPIO0_81 GPMC0_A D14 MCASP2_ AFSX UART2_R XD 0x00011C1 PADCONFIG83 AA29 PRG0_PR U1_GPO1 PRG0_PR U1_GPI19 PRG0_IEP 1_EDC_SY NC_OUT0 PRG0_PW M1_TZ_O UT SPI3_D1 MCAN12_ RX GPIO0_82 GPMC0_A D15 MCASP2_ ACLKX 0x00011C1 PADCONFIG84 Y26 PRG0_MDI O0_MDIO I2C5_SCL MCAN13_ TX GPIO0_83 GPMC0_A DSS_FSY NC0 MCASP2_ AFSR MCASP2_ AXR4 0x00011C1 PADCONFIG85 AA27 PRG0_MDI O0_MDC I2C5_SDA MCAN13_ RX GPIO0_84 GPMC0_A DSS_FSY NC2 MCASP2_ ACLKR MCASP2_ AXR5 0x00011C1 PADCONFIG86 U23 RGMII5_T X_CTL RMII7_CR S_DV I2C2_SCL VOUT1_D ATA0 TRC_CLK EHRPWM0 _SYNCI GPIO0_85 GPMC0_A MCASP10 _ACLKX 0x00011C1 PADCONFIG87 U26 RGMII5_R X_CTL RMII7_RX _ER I2C2_SDA VOUT1_D ATA1 TRC_CTL EHRPWM0 _SYNCO GPIO0_86 GPMC0_A MCASP10 _AFSX 0x00011C1 PADCONFIG88 V28 RGMII5_T UART3_R XD SYNC2_O UT VOUT1_D ATA2 TRC_DATA EHRPWM_ TZn_IN0 GPIO0_87 GPMC0_A MCASP10 _AXR0 0x00011C1 PADCONFIG89 V29 RGMII5_T UART3_TX D SYNC3_O UT VOUT1_D ATA3 TRC_DATA EHRPWM0 GPIO0_88 GPMC0_A MCASP10 _AXR1 0x00011C1 PADCONFIG90 V27 RGMII5_T RMII7_TX I2C3_SCL VOUT1_D ATA4 TRC_DATA EHRPWM0 GPIO0_89 GPMC0_A MCASP11_ ACLKX 0x00011C1 PADCONFIG91 U28 RGMII5_T RMII7_TX I2C3_SDA VOUT1_D ATA5 TRC_DATA EHRPWM1 GPIO0_90 GPMC0_A MCASP11_ AFSX www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C1 PADCONFIG92 U29 RGMII5_T XC RMII7_TX_ EN I2C6_SCL VOUT1_D ATA6 TRC_DATA EHRPWM1 GPIO0_91 GPMC0_A MCASP10 _AXR2 0x00011C1 PADCONFIG93 U25 RGMII5_R XC I2C6_SDA VOUT1_D ATA7 TRC_DATA EHRPWM_ TZn_IN1 GPIO0_92 GPMC0_A MCASP10 _AXR3 EHRPWM_ SOCA 0x00011C1 PADCONFIG94 U27 RGMII5_R UART3_CT Sn UART6_R XD VOUT1_D ATA8 TRC_DATA EHRPWM2 GPIO0_93 GPMC0_A MCASP11_ AXR0 0x00011C1 PADCONFIG95 U24 RGMII5_R UART3_RT Sn UART6_TX D VOUT1_D ATA9 TRC_DATA EHRPWM2 GPIO0_94 GPMC0_A MCASP11_ AXR1 0x00011C1 PADCONFIG96 R23 RGMII5_R RMII7_RX UART6_CT Sn VOUT1_D ATA10 TRC_DATA EHRPWM_ TZn_IN2 GPIO0_95 GPMC0_A MCASP11_ AXR2 EHRPWM_ SOCB 0x00011C1 PADCONFIG97 T23 RGMII5_R RMII7_RX UART6_RT Sn VOUT1_D ATA11 TRC_DATA GPIO0_96 GPMC0_A MCASP11_ AXR3 0x00011C1 PADCONFIG98 Y28 RGMII6_T X_CTL RMII8_CR S_DV VOUT1_D ATA12 TRC_DATA GPIO0_97 GPMC0_A MCASP10 _ACLKR 0x00011C1 PADCONFIG99 V23 RGMII6_R X_CTL RMII8_RX _ER VOUT1_D ATA13 TRC_DATA EHRPWM3 GPIO0_98 GPMC0_A MCASP10 _AFSR 0x00011C1 PADCONFIG100 W23 RGMII6_T UART4_R XD SPI5_CS3 VOUT1_D ATA14 TRC_DATA EHRPWM3 GPIO0_99 GPMC0_A MCASP11_ ACLKR 0x00011C1 PADCONFIG101 W28 RGMII6_T UART4_TX D SPI5_CS2 VOUT1_D ATA15 TRC_DATA EHRPWM3 _SYNCI GPIO0_10 GPMC0_A MCASP11_ AFSR 0x00011C1 PADCONFIG102 V25 RGMII6_T RMII8_TX SPI5_D0 VOUT1_V SYNC TRC_DATA EHRPWM3 _SYNCO GPIO0_10 GPMC0_A VOUT1_V P0_VSYN C MCASP10 _AXR4 0x00011C1 PADCONFIG103 W27 RGMII6_T RMII8_TX SPI5_CS0 VOUT1_H SYNC TRC_DATA EHRPWM_ TZn_IN3 GPIO0_10 GPMC0_A VOUT1_V P0_HSYN C MCASP10 _AXR5 0x00011C1 PADCONFIG104 W29 RGMII6_T XC RMII8_TX_ EN SPI5_CLK VOUT1_P CLK TRC_DATA EHRPWM4 GPIO0_10 GPMC0_A MCASP10 _AXR6 0x00011C1 PADCONFIG105 W26 RGMII6_R XC AUDIO_EX T_REFCLK VOUT1_D E TRC_DATA EHRPWM4 GPIO0_10 GPMC0_A VOUT1_V P0_DE MCASP10 _AXR7 0x00011C1 PADCONFIG106 Y29 RGMII6_R UART4_CT Sn UART5_R XD CLKOUT TRC_DATA EHRPWM_ TZn_IN4 GPIO0_10 GPMC0_A MCASP11_ AXR4 0x00011C1 AC PADCONFIG107 Y27 RGMII6_R UART4_RT Sn UART5_TX D TRC_DATA EHRPWM5 GPIO0_10 GPMC0_A MCASP11_ AXR5 0x00011C1 PADCONFIG108 W24 RGMII6_R RMII8_RX SPI5_D1 VOUT1_E XTPCLKIN TRC_DATA EHRPWM5 GPIO0_10 GPMC0_B E1n MCASP11_ AXR6 0x00011C1 PADCONFIG109 W25 RGMII6_R RMII8_RX SPI5_CS1 AUDIO_EX T_REFCLK TRC_DATA EHRPWM_ TZn_IN5 GPIO0_10 GPMC0_DI R MCASP11_ AXR7 0x00011C1 PADCONFIG110 V26 MDIO0_M DIO TRC_DATA GPIO0_10 GPMC0_W AIT3 0x00011C1 BC PADCONFIG111 V24 MDIO0_M DC TRC_DATA GPIO0_11 GPMC0_W AIT2 0x00011C1 PADCONFIG112 AA2 SPI0_CS0 UART0_RT Sn GPIO0_111 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C1 PADCONFIG113 Y4 SPI0_CS1 CPTS0_TS _COMP I2C3_SCL DP0_HPD PRG1_IEP 0_EDIO_O UTVALID GPIO0_11 0x00011C1 PADCONFIG114 AA1 SPI0_CLK UART1_CT Sn I2C2_SCL GPIO0_11 0x00011C1 CC PADCONFIG115 AB5 SPI0_D0 UART1_RT Sn I2C2_SDA GPIO0_11 0x00011C1 PADCONFIG116 AA3 SPI0_D1 I2C6_SCL GPIO0_11 0x00011C1 PADCONFIG117 Y3 SPI1_CS0 UART0_CT Sn UART5_R XD PRG0_IEP 0_EDIO_O UTVALID GPIO0_11 PRG0_IEP 0_EDC_LA TCH_IN0 0x00011C1 PADCONFIG118 W4 SPI1_CS1 CPTS0_TS _SYNC I2C3_SDA UART5_TX D GPIO0_11 0x00011C1 DC PADCONFIG119 Y1 SPI1_CLK UART5_CT Sn I2C4_SDA UART2_R XD GPIO0_11 PRG0_IEP 0_EDC_SY NC_OUT0 0x00011C1 PADCONFIG120 Y5 SPI1_D0 UART5_RT Sn I2C4_SCL UART2_TX D GPIO0_11 PRG0_IEP 1_EDC_LA TCH_IN0 0x00011C1 PADCONFIG121 Y2 SPI1_D1 I2C6_SDA GPIO0_12 PRG0_IEP 1_EDC_SY NC_OUT0 0x00011C1 PADCONFIG122 AB2 UART0_R XD SPI2_CS1 GPIO0_12 0x00011C1 EC PADCONFIG123 AB3 UART0_TX D SPI2_CS2 SPI7_CS1 GPIO0_12 0x00011C1 PADCONFIG124 AC2 UART0_CT Sn TIMER_IO SPI0_CS2 MCAN2_R X SPI2_CS0 EQEP0_A GPIO0_12 MLB0_ML BSIG 0x00011C1 PADCONFIG125 AB1 UART0_RT Sn TIMER_IO SPI0_CS3 MCAN2_T X SPI2_CLK EQEP0_B GPIO0_12 0x00011C1 PADCONFIG126 AA4 UART1_R XD SPI7_CS2 GPIO0_12 0x00011C1 FC PADCONFIG127 AB4 UART1_TX D I3C0_SDA PULLEN SPI7_CS3 GPIO0_12 0x00011C2 PADCONFIG128 AC4 UART1_CT Sn MCAN3_R X SPI2_D0 EQEP0_S GPIO0_12 MLB0_ML BCLK 0x00011C2 PADCONFIG129 AD5 UART1_RT Sn MCAN3_T X SPI2_D1 EQEP0_I GPIO1_0 MLB0_ML BDAT 0x00011C2 PADCONFIG130 W5 MCAN0_R X I2C2_SCL GPIO1_1 0x00011C2 PADCONFIG131 W6 MCAN0_T X I2C2_SDA GPIO1_2 0x00011C2 PADCONFIG132 W3 MCAN1_R X UART6_CT Sn UART9_R XD USB0_DR VVBUS USB1_DR VVBUS GPIO1_3 0x00011C2 PADCONFIG133 V4 MCAN1_T X UART6_RT Sn UART9_TX D USB0_DR VVBUS USB1_DR VVBUS GPIO1_4 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 139 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C2 PADCONFIG134 W2 I3C0_SCL MMC2_SD CD UART9_CT Sn MCAN2_R X I2C6_SCL DP0_HPD PCIE0_CL KREQn GPIO1_5 UART6_R XD 0x00011C2 PADCONFIG135 W1 I3C0_SDA MMC2_SD WP UART9_RT Sn MCAN2_T X I2C6_SDA PCIE1_CL KREQn GPIO1_6 UART6_TX D 0x00011C2 PADCONFIG136 AC5 I2C0_SCL GPIO1_7 0x00011C2 PADCONFIG137 AA5 I2C0_SDA GPIO1_8 0x00011C2 PADCONFIG138 Y6 I2C1_SCL CPTS0_H W1TSPUS H GPIO1_9 0x00011C2 PADCONFIG139 AA6 I2C1_SDA CPTS0_H W2TSPUS H GPIO1_10 0x00011C2 PADCONFIG140 U2 ECAP0_IN _APWM_O UT SYNC0_O UT CPTS0_RF T_CLK SPI2_CS3 I3C0_SDA PULLEN SPI7_CS0 GPIO1_11 0x00011C2 PADCONFIG141 U3 EXT_REF CLK1 SYNC1_O UT SPI7_CLK GPIO1_12 0x00011C2 PADCONFIG142 V6 TIMER_IO ECAP1_IN _APWM_O UT SYSCLKO UT0 SPI7_D0 GPIO1_13 BOOTMO DE4 0x00011C2 PADCONFIG143 V5 TIMER_IO ECAP2_IN _APWM_O UT OBSCLK0 SPI7_D1 GPIO1_14 BOOTMO DE5 0x00011C2 PADCONFIG144 R26 MMC1_DA UART7_R XD GPIO1_15 0x00011C2 PADCONFIG145 R25 MMC1_DA UART7_TX D GPIO1_16 0x00011C2 PADCONFIG146 P24 MMC1_DA UART7_CT Sn ECAP0_IN _APWM_O UT TIMER_IO UART4_R XD GPIO1_17 0x00011C2 PADCONFIG147 R24 MMC1_DA UART7_RT Sn ECAP1_IN _APWM_O UT TIMER_IO UART4_TX D GPIO1_18 0x00011C2 PADCONFIG148 P25 MMC1_CL K UART8_R XD I2C4_SCL GPIO1_19 0x00011C2 PADCONFIG149 R29 MMC1_CM D UART8_TX D I2C4_SDA GPIO1_20 0x00011C2 PADCONFIG150 P23 MMC1_SD CD UART8_CT Sn UART0_D CDn TIMER_IO EQEP2_I PCIE2_CL KREQn GPIO1_21 PRG0_IEP 0_EDC_LA TCH_IN1 0x00011C2 PADCONFIG151 R28 MMC1_SD WP UART8_RT Sn UART0_D SRn TIMER_IO ECAP2_IN _APWM_O UT EQEP2_S PCIE3_CL KREQn GPIO1_22 PRG0_IEP 0_EDC_SY NC_OUT1 0x00011C2 PADCONFIG152 T28 MMC2_DA UART9_R XD CPTS0_H W1TSPUS H I2C5_SCL GPIO1_23 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x00011C2 PADCONFIG153 T29 MMC2_DA UART9_TX D CPTS0_H W2TSPUS H I2C5_SDA GPIO1_24 0x00011C2 PADCONFIG154 T27 MMC2_DA UART9_CT Sn UART0_DT Rn TIMER_IO UART6_R XD EQEP2_A GPIO1_25 PRG0_IEP 1_EDC_LA TCH_IN1 0x00011C2 PADCONFIG155 T24 MMC2_DA UART9_RT Sn UART0_RI n TIMER_IO UART6_TX D EQEP2_B GPIO1_26 PRG0_IEP 1_EDC_SY NC_OUT1 0x00011C2 PADCONFIG156 T26 MMC2_CL K USB0_DR VVBUS USB1_DR VVBUS TIMER_IO I2C3_SCL UART3_R XD GPIO1_27 0x00011C2 PADCONFIG157 T25 MMC2_CM D USB0_DR VVBUS USB1_DR VVBUS TIMER_IO I2C3_SDA UART3_TX D GPIO1_28 0x00011C2 PADCONFIG158 T6 RESETST ATz 0x00011C2 PADCONFIG159 U1 PORz_OU T 0x00011C2 PADCONFIG160 U4 SOC_SAF ETY_ERR ORn 0x00011C2 PADCONFIG161 V1 TDI 0x00011C2 PADCONFIG162 V3 TDO 0x00011C2 PADCONFIG163 V2 TMS 0x04301C0 WKUP_PADCON FIG0 E20 MCU_OSP I0_CLK MCU_HYP ERBUS0_ CK WKUP_GP IO0_16 0x04301C0 WKUP_PADCON FIG1 C21 MCU_OSP I0_LBCLK O MCU_HYP ERBUS0_ CKn WKUP_GP IO0_17 0x04301C0 WKUP_PADCON FIG2 D21 MCU_OSP I0_DQS MCU_HYP ERBUS0_ RWDS WKUP_GP IO0_18 0x04301C0 WKUP_PADCON FIG3 D20 MCU_OSP I0_D0 MCU_HYP ERBUS0_ DQ0 WKUP_GP IO0_19 0x04301C0 WKUP_PADCON FIG4 G19 MCU_OSP I0_D1 MCU_HYP ERBUS0_ DQ1 WKUP_GP IO0_20 0x04301C0 WKUP_PADCON FIG5 G20 MCU_OSP I0_D2 MCU_HYP ERBUS0_ DQ2 WKUP_GP IO0_21 0x04301C0 WKUP_PADCON FIG6 F20 MCU_OSP I0_D3 MCU_HYP ERBUS0_ DQ3 WKUP_GP IO0_22 0x04301C0 WKUP_PADCON FIG7 F21 MCU_OSP I0_D4 MCU_HYP ERBUS0_ DQ4 WKUP_GP IO0_23 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x04301C0 WKUP_PADCON FIG8 E21 MCU_OSP I0_D5 MCU_HYP ERBUS0_ DQ5 WKUP_GP IO0_24 0x04301C0 WKUP_PADCON FIG9 B22 MCU_OSP I0_D6 MCU_HYP ERBUS0_ DQ6 WKUP_GP IO0_25 0x04301C0 WKUP_PADCON FIG10 G21 MCU_OSP I0_D7 MCU_HYP ERBUS0_ DQ7 WKUP_GP IO0_26 0x04301C0 WKUP_PADCON FIG11 F19 MCU_OSP I0_CSn0 MCU_HYP ERBUS0_ CSn0 WKUP_GP IO0_27 0x04301C0 WKUP_PADCON FIG12 E19 MCU_OSP I0_CSn1 MCU_HYP ERBUS0_ RESETn WKUP_GP IO0_28 0x04301C0 WKUP_PADCON FIG13 F22 MCU_OSP I1_CLK WKUP_GP IO0_29 0x04301C0 WKUP_PADCON FIG14 A23 MCU_OSP I1_LBCLK O MCU_OSP I0_CSn2 MCU_HYP ERBUS0_ RESETOn MCU_OSP I0_RESET _OUT0 WKUP_GP IO0_30 0x04301C0 WKUP_PADCON FIG15 B23 MCU_OSP I1_DQS MCU_OSP I0_CSn3 MCU_HYP ERBUS0_I NTn MCU_OSP I0_ECC_F AIL WKUP_GP IO0_31 0x04301C0 WKUP_PADCON FIG16 D22 MCU_OSP I1_D0 WKUP_GP IO0_32 0x04301C0 WKUP_PADCON FIG17 G22 MCU_OSP I1_D1 MCU_UAR T0_RXD MCU_SPI1 _CS1 WKUP_GP IO0_33 0x04301C0 WKUP_PADCON FIG18 D23 MCU_OSP I1_D2 MCU_UAR T0_TXD MCU_SPI1 _CS2 WKUP_GP IO0_34 0x04301C0 WKUP_PADCON FIG19 C23 MCU_OSP I1_D3 MCU_UAR T0_CTSn MCU_SPI0 _CS1 WKUP_GP IO0_35 0x04301C0 WKUP_PADCON FIG20 C22 MCU_OSP I1_CSn0 WKUP_GP IO0_36 0x04301C0 WKUP_PADCON FIG21 E22 MCU_OSP I1_CSn1 MCU_HYP ERBUS0_ WPn MCU_TIM ER_IO0 MCU_HYP ERBUS0_ CSn1 MCU_UAR T0_RTSn MCU_SPI0 _CS2 MCU_OSP I0_RESET _OUT1 WKUP_GP IO0_37 0x04301C0 WKUP_PADCON FIG22 B27 MCU_RG MII1_TX_C TL MCU_RMII 1_CRS_D V WKUP_GP IO0_38 0x04301C0 WKUP_PADCON FIG23 C25 MCU_RG MII1_RX_ CTL MCU_RMII 1_RX_ER WKUP_GP IO0_39 0x04301C0 WKUP_PADCON FIG24 A28 MCU_RG MII1_TD3 MCU_TIM ER_IO2 MCU_ADC _EXT_TRI GGER0 WKUP_GP IO0_40 0x04301C0 WKUP_PADCON FIG25 A27 MCU_RG MII1_TD2 MCU_TIM ER_IO3 MCU_ADC _EXT_TRI GGER1 WKUP_GP IO0_41 0x04301C0 WKUP_PADCON FIG26 A26 MCU_RG MII1_TD1 MCU_RMII 1_TXD1 WKUP_GP IO0_42 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x04301C0 WKUP_PADCON FIG27 B25 MCU_RG MII1_TD0 MCU_RMII 1_TXD0 WKUP_GP IO0_43 0x04301C0 WKUP_PADCON FIG28 B26 MCU_RG MII1_TXC MCU_RMII 1_TX_EN WKUP_GP IO0_44 0x04301C0 WKUP_PADCON FIG29 C24 MCU_RG MII1_RXC MCU_RMII 1_REF_CL K WKUP_GP IO0_45 0x04301C0 WKUP_PADCON FIG30 A25 MCU_RG MII1_RD3 MCU_TIM ER_IO4 WKUP_GP IO0_46 0x04301C0 WKUP_PADCON FIG31 D24 MCU_RG MII1_RD2 MCU_TIM ER_IO5 WKUP_GP IO0_47 0x04301C0 WKUP_PADCON FIG32 A24 MCU_RG MII1_RD1 MCU_RMII 1_RXD1 WKUP_GP IO0_48 0x04301C0 WKUP_PADCON FIG33 B24 MCU_RG MII1_RD0 MCU_RMII 1_RXD0 WKUP_GP IO0_49 0x04301C0 WKUP_PADCON FIG34 E23 MCU_MDI O0_MDIO WKUP_GP IO0_50 0x04301C0 WKUP_PADCON FIG35 F23 MCU_MDI O0_MDC WKUP_GP IO0_51 0x04301C0 WKUP_PADCON FIG36 E27 MCU_SPI0 _CLK WKUP_GP IO0_52 MCU_BOO TMODE00 0x04301C0 WKUP_PADCON FIG37 E24 MCU_SPI0 _D0 WKUP_GP IO0_53 MCU_BOO TMODE01 0x04301C0 WKUP_PADCON FIG38 E28 MCU_SPI0 _D1 MCU_TIM ER_IO0 WKUP_GP IO0_54 MCU_BOO TMODE02 0x04301C0 WKUP_PADCON FIG39 E25 MCU_SPI0 _CS0 MCU_TIM ER_IO1 WKUP_GP IO0_55 0x04301C0 WKUP_PADCON FIG40 J29 WKUP_UA RT0_RXD WKUP_GP IO0_56 0x04301C0 WKUP_PADCON FIG41 J28 WKUP_UA RT0_TXD WKUP_GP IO0_57 0x04301C0 WKUP_PADCON FIG42 D29 MCU_MCA N0_TX WKUP_GP IO0_58 0x04301C0 AC WKUP_PADCON FIG43 C29 MCU_MCA N0_RX WKUP_GP IO0_59 0x04301C0 WKUP_PADCON FIG44 F26 MCU_SPI1 _CLK MCU_SPI1 _CLK WKUP_GP IO0_0 MCU_BOO TMODE03 0x04301C0 WKUP_PADCON FIG45 F25 MCU_SPI1 _D0 MCU_SPI1 _D0 WKUP_GP IO0_1 MCU_BOO TMODE04 0x04301C0 WKUP_PADCON FIG46 F28 MCU_SPI1 _D1 MCU_SPI1 _D1 WKUP_GP IO0_2 MCU_BOO TMODE05 0x04301C0 BC WKUP_PADCON FIG47 F27 MCU_SPI1 _CS0 MCU_SPI1 _CS0 WKUP_GP IO0_3 0x04301C0 WKUP_PADCON FIG48 G25 MCU_MCA N1_TX MCU_MCA N1_TX MCU_SPI0 _CS3 MCU_ADC _EXT_TRI GGER0 WKUP_GP IO0_4 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x04301C0 WKUP_PADCON FIG49 G24 MCU_MCA N1_RX MCU_MCA N1_RX MCU_SPI1 _CS3 MCU_ADC _EXT_TRI GGER1 WKUP_GP IO0_5 0x04301C0 WKUP_PADCON FIG50 F29 WKUP_UA RT0_CTSn WKUP_UA RT0_CTSn MCU_CPT S0_HW1T SPUSH MCU_I2C1 _SCL WKUP_GP IO0_6 0x04301C0 CC WKUP_PADCON FIG51 G28 WKUP_UA RT0_RTSn WKUP_UA RT0_RTSn MCU_CPT S0_HW2T SPUSH MCU_I2C1 _SDA WKUP_GP IO0_7 0x04301C0 WKUP_PADCON FIG52 G27 MCU_I2C1 _SCL MCU_I2C1 _SCL MCU_CPT S0_TS_SY NC MCU_I3C1 _SCL MCU_TIM ER_IO6 WKUP_GP IO0_8 0x04301C0 WKUP_PADCON FIG53 G26 MCU_I2C1 _SDA MCU_I2C1 _SDA MCU_CPT S0_TS_CO MP MCU_I3C1 _SDA MCU_TIM ER_IO7 WKUP_GP IO0_9 0x04301C0 WKUP_PADCON FIG54 H26 MCU_EXT _REFCLK0 MCU_EXT _REFCLK0 MCU_UAR T0_TXD MCU_ADC _EXT_TRI GGER0 MCU_CPT S0_RFT_C LK MCU_SYS CLKOUT0 WKUP_GP IO0_10 0x04301C0 DC WKUP_PADCON FIG55 H27 MCU_OBS CLK0 MCU_OBS CLK0 MCU_UAR T0_RXD MCU_ADC _EXT_TRI GGER1 MCU_TIM ER_IO1 MCU_I3C1 _SDAPULL EN MCU_CLK OUT0 WKUP_GP IO0_11 0x04301C0 WKUP_PADCON FIG56 G29 MCU_UAR T0_TXD MCU_SPI0 _CS1 WKUP_GP IO0_12 MCU_BOO TMODE08 0x04301C0 WKUP_PADCON FIG57 H28 MCU_UAR T0_RXD MCU_SPI1 _CS1 WKUP_GP IO0_13 MCU_BOO TMODE09 0x04301C0 WKUP_PADCON FIG58 H29 MCU_UAR T0_CTSn MCU_SPI0 _CS2 WKUP_GP IO0_14 MCU_BOO TMODE06 0x04301C0 EC WKUP_PADCON FIG59 J27 MCU_UAR T0_RTSn MCU_SPI1 _CS2 WKUP_GP IO0_15 MCU_BOO TMODE07 0x04301C0 WKUP_PADCON FIG60 D26 MCU_I3C0 _SCL MCU_UAR T0_CTSn MCU_TIM ER_IO8 WKUP_GP IO0_60 0x04301C0 WKUP_PADCON FIG61 D25 MCU_I3C0 _SDA MCU_UAR T0_RTSn MCU_TIM ER_IO9 WKUP_GP IO0_61 0x04301C0 WKUP_PADCON FIG62 J25 WKUP_I2C 0_SCL WKUP_GP IO0_62 0x04301C0 FC WKUP_PADCON FIG63 H24 WKUP_I2C 0_SDA WKUP_GP IO0_63 0x04301C1 WKUP_PADCON FIG64 J26 MCU_I2C0 _SCL WKUP_GP IO0_64 0x04301C1 WKUP_PADCON FIG65 H25 MCU_I2C0 _SDA WKUP_GP IO0_65 0x04301C1 WKUP_PADCON FIG66 E26 MCU_I3C0 _SDAPULL EN WKUP_GP IO0_66 0x04301C1 WKUP_PADCON FIG67 G23 PMIC_PO WER_EN1 MCU_I3C1 _SDAPULL EN WKUP_GP IO0_67 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x04301C1 WKUP_PADCON FIG68 D27 MCU_SAF ETY_ERR ORn 0x04301C1 WKUP_PADCON FIG69 D28 MCU_RES ETz 0x04301C1 WKUP_PADCON FIG70 C27 MCU_RES ETSTATz 0x04301C1 WKUP_PADCON FIG71 B28 MCU_POR z_OUT 0x04301C1 WKUP_PADCON FIG72 E29 TCK 0x04301C1 WKUP_PADCON FIG73 F24 TRSTn 0x04301C1 WKUP_PADCON FIG74 C26 EMU0 0x04301C1 WKUP_PADCON FIG75 B29 EMU1 0x04301C1 WKUP_PADCON FIG76 K25 MCU_ADC 0_AIN0 0x04301C1 WKUP_PADCON FIG77 K26 MCU_ADC 0_AIN1 0x04301C1 WKUP_PADCON FIG78 K28 MCU_ADC 0_AIN2 0x04301C1 WKUP_PADCON FIG79 L28 MCU_ADC 0_AIN3 0x04301C1 WKUP_PADCON FIG80 K24 MCU_ADC 0_AIN4 0x04301C1 WKUP_PADCON FIG81 K27 MCU_ADC 0_AIN5 0x04301C1 WKUP_PADCON FIG82 K29 MCU_ADC 0_AIN6 0x04301C1 WKUP_PADCON FIG83 L29 MCU_ADC 0_AIN7 0x04301C1 WKUP_PADCON FIG84 N23 MCU_ADC 1_AIN0 0x04301C1 WKUP_PADCON FIG85 M25 MCU_ADC 1_AIN1 0x04301C1 WKUP_PADCON FIG86 L24 MCU_ADC 1_AIN2 0x04301C1 WKUP_PADCON FIG87 L26 MCU_ADC 1_AIN3 0x04301C1 WKUP_PADCON FIG88 N24 MCU_ADC 1_AIN4 0x04301C1 WKUP_PADCON FIG89 M24 MCU_ADC 1_AIN5 0x04301C1 WKUP_PADCON FIG90 L25 MCU_ADC 1_AIN6 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 145 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-125. Pin Multiplexing (continued) ADDRESS REGISTER NAME BALL NUMB ER MUXMODE[14:0] SETTINGS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bootstrap 0x04301C1 WKUP_PADCON FIG91 L27 MCU_ADC 1_AIN7 0x04301C1 WKUP_PADCON FIG92 C28 RESET_R EQz 0x04301C1 WKUP_PADCON FIG93 J24 PORz DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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5.5 Pin Connectivity Requirements

This section describes the Unused/Reserved balls connection requirements. Note All power balls must be supplied with the voltages specified in Section 6.4, Recommended Operating Conditions, unless otherwise specified in Section 5.3, Signal Descriptions. Note MMC1_SDCD and MMC2_SDCD must be pulled down for respective MMC modules to work properly as a boot source. Table 5-126. Connectivity Requirements (ALF Package) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS M29 WKUP_OSC0_XI Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level if unused. P29 OSC1_XI N28 WKUP_LFOSC0_XI F24 TRSTn K25 MCU_ADC0_AIN0 K26 MCU_ADC0_AIN1 K28 MCU_ADC0_AIN2 L28 MCU_ADC0_AIN3 K24 MCU_ADC0_AIN4 K27 MCU_ADC0_AIN5 K29 MCU_ADC0_AIN6 L29 MCU_ADC0_AIN7 N23 MCU_ADC1_AIN0 M25 MCU_ADC1_AIN1 L24 MCU_ADC1_AIN2 L26 MCU_ADC1_AIN3 N24 MCU_ADC1_AIN4 M24 MCU_ADC1_AIN5 L25 MCU_ADC1_AIN6 L27 MCU_ADC1_AIN7 B2 DDR0_DQS0P E3 DDR0_DQS1P M3 DDR0_DQS2P R2 DDR0_DQS3P M26 VMON_ER_VSYS V19 VMON_IR_VEXT www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 147 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 5-126. Connectivity Requirements (ALF Package) (continued) BALL NUMBER BALL NAME CONNECTION REQUIREMENTS AE18 SERDES0_REXT Each of these balls must be connected to VSS through appropriate external pull resistor to ensure these balls are held to a valid logic low level if unused. The resistor value for the SERDES[4:0]_REXT pins is 3.01 kΩ ±1%, for the CSI[1:0]_RXRCALIB, USB[1:0]_RCALIB, and DSI_TXRCALIB pins is 500 Ω ±1%. This is the same connection as during functional mode. AE13 SERDES1_REXT AD13 SERDES2_REXT AE8 SERDES3_REXT F9 SERDES4_REXT F16 CSI0_RXRCALIB F15 CSI1_RXRCALIB AB6 USB0_RCALIB AD9 USB1_RCALIB F12 DSI_TXRCALIB D28 MCU_RESETz Each of these balls must be connected to the corresponding power supply through a separate external pull resistor to ensure these balls are held to a valid logic high level if unused. (1) H23 MCU_PORz J24 PORz E29 TCK V2 TMS J25 WKUP_I2C0_SCL H24 WKUP_I20_SDA H25 MCU_I2C0_SDA J26 MCU_I2C0_SCL Y6 I2C1_SCL AA6 I2C1_SDA AA5 I2C0_SDA AC5 I2C0_SCL AC18 EXTINTn V1 TDI V3 TDO B29 EMU1 C26 EMU0 B1 DDR0_DQS0N E2 DDR0_DQS1N M2 DDR0_DQS2N R1 DDR0_DQS3N AB11 VPP_CORE Each of these balls must be left unconnected if unused. F17 VPP_MCU AE1 MMC0_CALPAD AE2 MLB0_MLBCN AD2 MLB0_MLBCP AD3 MLB0_MLBDN AC3 MLB0_MLBDP AC1 MLB0_MLBSN AD1 MLB0_MLBSP (1) To determine which power supply is associated with any IO refer to Table 5-1, Pin Attributes. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 5-127. Reserved Balls Specific Connection Requirements BALLS CONNECTION REQUIREMENTS A29 / AJ1 / U11 / U12 / U13 / T11 / T12 / T13 / M11 / M12 / M13 / N11 / N12 / N13 These balls do not exist on the package. N25 / AJ29 / P26 / R27 / AD4 / E18 / F18 / G10 / F11 / N6 / L6 / F6 / E6 / G9 / F10 / AA23 / F13 These balls must be left unconnected. Note All other unused signal balls without Pad Configuration Register can be left unconnected. Note All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled. Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case where internal pull resistors are allowed as the only source/sink to hold a valid logic level. Any balls connected to a via, test point, or PCB trace are considered used and must not depend on the internal pull resistor to hold a valid logic level. Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This may be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be required to hold a valid logic level on balls with external connections. If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state which could damage the IO cell. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 149 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER MIN MAX UNIT VDD_CORE MAIN domain core supply –0.3 1.05 V VDD_MCU MCUSS core supply –0.3 1.05 V VDD_CPU CPU core supply –0.3 1.05 V VDDA_0P8_DLL_MMC0 MMC0 DLL analog supply –0.3 1.05 V VDDAR_CORE MAIN domain RAM supply –0.3 1.05 V VDDAR_MCU MCUSS RAM supply –0.3 1.05 V VDDAR_CPU CPU RAM supply –0.3 1.05 V VDDA_0P8_DP Displayport SERDES analog supply low –0.3 1.05 V VDDA_0P8_DP_C Displayport SERDES clock supply –0.3 1.05 V VDDA_0P8_DSITX DSITX clock supply –0.3 1.05 V VDDA_0P8_DSITX_C DSITX clock supply –0.3 1.05 V VDDA_0P8_CSIRX CSIRX analog supply low –0.3 1.05 V VDDA_0P8_SERDES0_1 SERDES0-1 analog supply low –0.3 1.05 V VDDA_0P8_SERDES2_3 SERDES2-3 analog supply low –0.3 1.05 V VDDA_0P8_SERDES_C0_1 SERDES0-1 clock supply –0.3 1.05 V VDDA_0P8_SERDES_C2_3 SERDES2-3 clock supply –0.3 1.05 V VDDA_0P8_USB USB0-1 0.8 V analog supply –0.3 1.05 V VDDA_0P8_UFS UFS analog supply low –0.3 1.05 V VDDA_0P8_PLL_MLB MLB PLL analog supply –0.3 1.05 V VDDA_0P8_PLL_DDR DDR PLL analog supply –0.3 1.05 V VDDA_1P8_USB USB0-1 1.8 V analog supply –0.3 2.2 V VDDA_1P8_UFS UFS analog supply high –0.3 2.2 V VDDA_1P8_DP Displayport SERDES analog supply high –0.3 2.2 V VDDA_1P8_DSITX DSITX analog supply high –0.3 2.2 V VDDA_1P8_CSIRX CSIRX analog supply high –0.3 2.2 V VDDA_1P8_SERDES0_1 SERDES0-1 analog supply high –0.3 2.2 V VDDA_1P8_SERDES2_3 SERDES2-3 analog supply high –0.3 2.2 V VDDA_3P3_USB USB0-1 3.3 V analog supply –0.3 3.8 V VDDA_MCU_PLLGRP0 Analog supply for MCU PLL Group 0 –0.3 2.2 V VDDA_PLLGRP0 Analog supply for Main PLL Group 0 –0.3 2.2 V VDDA_PLLGRP1 Analog supply for Main PLL Group 1 –0.3 2.2 V VDDA_PLLGRP2 Analog supply for Main PLL Group 2 –0.3 2.2 V VDDA_PLLGRP3 Analog supply for Main PLL Group 3 –0.3 2.2 V VDDA_PLLGRP4 Analog supply for Main PLL Group 4 –0.3 2.2 V VDDA_PLLGRP5 Analog supply for MAIN PLL Group 5 (DDR) –0.3 2.2 V VDDA_PLLGRP6 Analog supply for MAIN PLL Group 6 –0.3 2.2 V VDDA_WKUP Oscillator supply for WKUP domain –0.3 2.2 V VDDA_ADC0 ADC analog supply –0.3 2.2 V VDDA_ADC1 ADC analog supply –0.3 2.2 V VDDA_MCU_TEMP Analog supply for temperature sensor 0 in MCU domain –0.3 2.2 V VDDA_POR_WKUP WKUP domain analog supply –0.3 2.2 V VDDA_1P8_MLB MLB IO supply (6-pin interface) –0.3 2.2 V DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.1 Absolute Maximum Ratings (continued)

over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER MIN MAX UNIT VDDA_TEMP_0_1 Analog supply for temperature sensor 0 –0.3 2.2 V VDDA_TEMP_2_3 Analog supply for temperature sensor 2 –0.3 2.2 V VDDS_DDR DDR inteface power supply –0.3 1.2 V VDDS_DDR_BIAS Bias supply for LPDDR4 –0.3 1.2 V VDDS_DDR_C IO power for DDR Memory Clock Bit (MCB) macro –0.3 1.2 V VDDS_MMC0 MMC0 IO supply –0.3 2.2 V VDDS_OSC1 HFOSC1 supply –0.3 2.2 V VDDSHV0_MCU IO supply MCUSS general IO group, and MCU and MAIN domain warm reset pins 1.8 V –0.3 2.2 V3.3 V –0.3 3.8 VDDSHV0 IO supply for MAIN domain general 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV1_MCU IO supply for MCUSS IO group 1 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV1 IO supply for MAIN domain IO group 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV2_MCU IO supply for MCUSS IO group 2 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV2 IO supply for MAIN domain IO group 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV3 IO supply for MAIN domain IO group 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV4 IO supply for MAIN domain IO group 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV5 IO supply for MAIN domain IO group 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VDDSHV6 IO supply for MAIN domain IO group 1.8 V –0.3 2.2 V 3.3 V –0.3 3.8 VPP_CORE Supply voltage range for CORE EFUSE domain –0.3 1.89 V VPP_MCU Supply voltage range for MCU EFUSE domain –0.3 1.89 V USB0_VBUS(9) Voltage range for USB VBUS comparator input –0.3 3.6 V USB1_VBUS(9) Voltage range for USB VBUS comparator input –0.3 3.6 V Steady State Max. Voltage at all fail-safe IO pins I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn –0.3 3.8 V MCU_PORz, PORz –0.3 3.8 V VMON_IR_VEXT –0.3 2.2 V VMON_ER_VSYS(7) (8) –0.3 1.05 V Steady State Max. Voltage at all other IO pins(3) All other IO pins –0.3 IO supply voltage + 0.3 V www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 151 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER MIN MAX UNIT Transient Overshoot and Undershoot specification at IO pin 20% of IO supply voltage for up to 20% of signal period (see Figure 6-1, IO Transient Voltage Ranges) 0.2 × VDD(6) V Latch-up Performance, Class II (125°C)(4) I-Test –100 100 mA Over-Voltage (OV) Test NA 1.5 × VDD(6) V TSTG (5) Storage temperature –55 +150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.4, Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted. (3) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. (4) For current pulse injection: Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage. For overvoltage performance: Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection. (5) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning to ambient room temperature before usage. (6) VDD is the voltage on the corresponding power-supply pin(s) for the IO. (7) An external resistor divider is required to create the VMON input value that triggers with VTH = 0.45 when the VSYS level reaches the minimum allowed threshold. A series resistor R2 (VMON_ER_VSYS = VSYS × R1 / (R1 + R2)) of at least 10kΩ is recommended to limit current. (8) The VMON_ER_VSYS pin provides a way to monitor the system power supply. For more information, see Section 8.3.5 System Power Supply Monitor Design Guidelines. (9) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.3.4, USB VBUS Design Guidelines. Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, NMIn, VMON_ER_VSYS, and VMON_IR_VEXT are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 6.1. Tovershoot Tundershoot Tperiod Overshoot = 20% of nominal IO supply voltage Undershoot = 20% of nominal IO supply voltage A. Tovershoot + Tundershoot < 20% of Tperiod Figure 6-1. IO Transient Voltage Ranges DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002, Revision J(1) ±1000 VCharged-device model (CDM), per AEC Q100-011, Revision J All pins ±250 Corner pins (A1, AJ29) ±750 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Power-On-Hour (POH) Limits

IP(1) (2) (3) VOLTAGE DOMAIN VOLTAGE (V) (MAX) FREQUENCY (MHz) (MAX) Tj(°C) POH All 100% All All Supported OPPs Automotive -40°C to 125°C (4) 20000 All 100% All All Supported OPPs Extended -40°C to 105°C 100000 All 100% All All Supported OPPs Commercial 0°C to 90°C 100000 (1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. (2) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures. (3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH. (4) Automotive profile is defined as 20000 power on hours with a junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C, and 10%@125°C.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDD_CORE Boot/Active voltage for MAIN domain core supply 0.76 0.8 0.84 V VDD_MCU Boot/Active voltage for MCUSS core supply 0.76 0.8 0.89 V VDD_CPU Boot voltage for CPU core supply, applied at cold power up event 0.76 0.8 0.84 V Active voltage for CPU core supply, after AVS mode enabled in software AVS(4)-5% AVS(4) AVS(4)+5% V VDD_CPU AVS Range AVS valid voltage range for VDD_CPU 0.6 0.9 V VDDA_0P8_DLL_MMC0 MMC PLL analog supply 0.76 0.8 0.84 V VDDAR_CORE Main domain RAM supply 0.81 0.85 0.89 V VDDAR_MCU MCUSS RAM supply 0.81 0.85 0.89 V VDDAR_CPU CPU RAM supply 0.81 0.85 0.89 V VDDA_0P8_DP Displayport SERDES clock supply 0.76 0.8 0.84 V VDDA_0P8_DP_C Displayport SERDES clock supply 0.76 0.8 0.84 V VDDA_0P8_DSITX DSITX clock supply 0.76 0.8 0.84 V VDDA_0P8_DSITX_C DSITX clock supply 0.76 0.8 0.84 V VDDA_0P8_CSIRX CSIRX analog supply low 0.76 0.8 0.84 V VDDA_0P8_SERDES0_1 SERDES0-1 analog supply low 0.76 0.8 0.84 V VDDA_0P8_SERDES2_3 SERDES2-3 analog supply low 0.76 0.8 0.84 V VDDA_0P8_SERDES_C0_1 SERDES0-1 clock supply 0.76 0.8 0.84 V VDDA_0P8_SERDES_C2_3 SERDES2-3 clock supply 0.76 0.8 0.84 V VDDA_0P8_USB USB0-1 0.8v analog supply 0.76 0.8 0.84 V VDDA_0P8_UFS UFS analog supply low 0.76 0.8 0.84 V VDDA_1P8_USB USB0-1 1.8v analog supply 1.71 1.8 1.89 V VDDA_1P8_UFS UFS analog supply high 1.71 1.8 1.89 V www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.4 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDDA_1P8_DP Displayport SERDES analog supply high 1.71 1.8 1.89 V VDDA_1P8_DSITX DSITX analog supply high 1.71 1.8 1.89 V VDDA_1P8_CSIRX CSIRX analog supply high 1.71 1.8 1.89 V VDDA_1P8_SERDES0_1 SERDES0-1 analog supply high 1.71 1.8 1.89 V VDDA_1P8_SERDES2_3 SERDES2-3 analog supply high 1.71 1.8 1.89 V VDDA_3P3_USB USB0-1 3.3v analog supply 3.14 3.3 3.46 V VDDA_MCU_PLLGRP0 Analog supply for MCU PLL Group 0 1.71 1.8 1.89 V VDDA_PLLGRP0 Analog supply for Main PLL Group 0 1.71 1.8 1.89 V VDDA_PLLGRP1 Analog supply for MAIN PLL Group 1 1.71 1.8 1.89 V VDDA_PLLGRP2 Analog supply for MAIN PLL Group 2 1.71 1.8 1.89 V VDDA_PLLGRP3 Analog supply for MAIN PLL Group 3 1.71 1.8 1.89 V VDDA_PLLGRP4 Analog supply for MAIN PLL Group 4 1.71 1.8 1.89 V VDDA_PLLGRP5 Analog supply for MAIN PLL Group 5 (DDR) 1.71 1.8 1.89 V VDDA_PLLGRP6 Analog supply for MAIN PLL Group 6 1.71 1.8 1.89 V VDDA_0P8_PLL_MLB MLB PLL analog supply 0.76 0.8 0.84 V VDDA_WKUP Oscillator supply for wkup domain 1.71 1.8 1.89 V VDDA_ADC0 ADC analog supply 1.71 1.8 1.89 V VDDA_ADC1 ADC analog supply 1.71 1.8 1.89 V VDDA_0P8_PLL_DDR DDR PLL analog supply 0.76 0.8 0.84 V VDDA_MCU_TEMP Analog supply for temperature sensor 0 in MCU domain 1.71 1.8 1.89 V VDDA_POR_WKUP WKUP domain analog supply 1.71 1.8 1.89 V VDDA_1P8_MLB MLB IO supply (6-pin interface) 1.71 1.8 1.89 V VDDA_TEMP0_1 Analog supply for temperature sensor 0 and 1 1.71 1.8 1.89 V VDDA_TEMP2_3 Analog supply for temperature sensor 2 and 3 1.71 1.8 1.89 V VDDS_DDR (2) DDR inteface power supply 1.06 1.1 1.15 V VDDS_DDR_BIAS Bias supply for LPDDR4x 1.06 1.1 1.15 V VDDS_DDR_C IO power for DDR Memory Clock Bit (MCB) macro 1.06 1.1 1.15 V VDDS_MMC0 MMC0 IO supply 1.71 1.8 1.89 V VDDS_OSC1 HFOSC1 supply 1.71 1.8 1.89 V VDDSHV0 IO supply for main domain general 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV0_MCU IO supply MCUSS general IO group, and MCU and Main domain warm reset pins 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV1 IO supply for main domain IO group 1 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV1_MCU IO supply for MCUSS IO group 1 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV2 IO supply for main domain IO group 2 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV2_MCU IO supply for MCUSS IO group 2 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV3 IO supply for main domain IO group 3 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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over operating free-air temperature range (unless otherwise noted) SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT VDDSHV4 IO supply for main domain IO group 4 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV5 IO supply for main domain IO group 5 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V VDDSHV6 IO supply for main domain IO group 6 1.8-V operation 1.71 1.8 1.89 V 3.3-V operation 3.14 3.3 3.46 V USB0_VBUS Voltage range for USB VBUS comparator input 0 See (5) 3.46 V USB1_VBUS Voltage range for USB VBUS comparator input 0 See (5) 3.46 V USB0_ID Voltage range for the USB ID input See (3) V USB1_ID Voltage range for the USB ID input See (3) V VSS Ground 0 V TJ Operating junction temperature range Automotive –40 125 °C Extended –40 105 °C Commercial 0 90 °C (1) The voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth. (2) VDDS_DDR is required to still be powered with LPDDR4 voltage ranges, even If DDR interface is unused. (3) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source. (4) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry. (5) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 8.3.4, USB VBUS Design Guidelines. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 155 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each Operating Performance Point (OPP) for processor clocks and device core clocks. Table 6-1 describes the maximum supported frequency per speed grade for the device. Table 6-1. Speed Grade Maximum Frequency DEVICE MAXIMUM FREQUENCY (MHz) A72SS0 C66SS0 C71SS0 R5SS0/1 MCU_ R5SS0 GPU CBASS0 DMSC LPDDR4 DRA829xT 2000 1350 1000 1000 1000 750 500 333 4266 MT/s(1) (1) Maximum DDR Frequency is limited based on the specific memory type (vendor) used in a system and by PCB implementation. TI strongly recommends that all designs follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill, PCB material, and so forth) in order to achieve the full specified clock frequency. For details, see the Jacinto 7 LPDDR4 Board Design and Layout Guidelines. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.6 Electrical Characteristics

The interfaces or signals described in Section 6.6.1 through Section 6.6.9 correspond to the interfaces or signals available in multiplexing mode 0 (Primary Function). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions).

6.6.1 I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics

Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NAMES in Mode 0: WKUP_I2C0_SDA, WKUP_I2C0_SCL, MCU_I2C0_SDA, MCU_I2C0_SCL, I2C0_SDA, I2C0_SCL, I2C1_SDA, I2C1_SCL, EXTINTN BALL NUMBERS:H24 / J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 H24/ J25 / H25 / J26 / AA5 / AC5 / AA6 / Y6 / AC18 1.8-V MODE VIL Input low-level threshold 0.3 × VDDSHV(1) V VILSS Input low-level threshold steady state 0.3 × VDDSHV(1) V VIH Input high-level threshold 0.7 × VDDSHV(1) V VIHSS Input high-level threshold steady state 0.7 × VDDSHV(1) V VHYS Input Hysteresis Voltage 0.1 × VDDSHV(1) mV IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA VOL Output low-level voltage 0.2 × VDDSHV(1) V IOL (2) Low Level Output Current VOL(MAX) 6 mA SRI (4) Input Slew Rate 18f(3) or 1.8E+6 V/s 3.3-V MODE (5) VIL Input low-level threshold 0.3 × VDDSHV(1) V VILSS Input low-level threshold steady state 0.25 × VDDSHV(1) V VIH Input high-level threshold 0.7 × VDDSHV(1) V VIHSS Input high-level threshold steady state 0.7 × VDDSHV(1) V VHYS Input Hysteresis Voltage 0.05 × VDDSHV(1) mV IIN Input Leakage Current VI = 3.3 V or 0 V ±10 µA VOL Output low-level voltage 0.4(1) V IOL (2) Low Level Output Current VOL(MAX) 6 mA SRI (4) Input Slew Rate 33f(3) or 3.3E+6 8E + 7 V/s (1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

(2) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value. The value defined by this parameter should be considered the maximum current available to a system implementation which needs to maintain the specified VOL value for attached components. (3) f = toggle frequency of the input signal in Hz. (4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value. (5) I2C Hs-mode is not supported, when operating the IO in 3.3-V mode.

6.6.2 Fail-Safe Reset (FS Reset) Electrical Characteristics

Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NAMES in Mode 0: MCU_PORz, PORz BALL NUMBERS:H23 / J24 VIL Input low-level threshold 0.3 × VDDSHV(1) V VILSS Input low-level threshold steady state 0.3 × VDDSHV(1) V VIH Input high-level threshold 0.7 × VDDSHV(1) V VIHSS Input high-level threshold steady state 0.7 × VDDSHV(1) V VHYS Input Hysteresis Voltage 200 mV IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA (1) VDDSHV stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

6.6.3 HFOSC/LFOSC Electrical Characteristics

Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HIGH FREQUENCY OSCILLATOR BALL NAMES: WKUP_OSC0_XO, WKUP_OSC0_XI, OSC1_XO, OSC1_XI BALL NUMBERS:M27 / M29 / P27 / P29 VIH Input high-level threshold 0.65 × VDDSHV(1) V VIL Input low-level threshold 0.35 × VDDSHV(1) V VHYS Input Hysteresis Voltage 49 mV LOW FREQUENCY OSCILLATOR BALL NAMES: WKUP_LFOSC0_XO, WKUP_LFOSC0_XI BALL NUMBERS:N26 / N28 VIH Input high-level threshold 0.65 × VDDA_WKUP (1) V VIL Input low-level threshold 0.35 × VDDA_WKUP (1) V VHYS Input Hysteresis Voltage Active Mode 85 mV Bypass Mode 324 mV (1) VDDSHV stands for corresponding power supply. For WKUP_OSC0, the corresponding power supply is VDDA_WKUP. For OSC1_XI, the corresponding power supply is VDDS_OSC1. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.6.4 eMMCPHY Electrical Characteristics Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT BALL NAMES in Mode 0: MMC0_DAT[7:0], MMC0_CALPAD, MMC0_CMD, MMC0_DS, MMC0_CLK BALL NUMBERS:AG2 / AH1 / AG3 / AF4 / AE5 / AF3 / AG1 / AF2 / AE1 / AE3 / AE4 / AF1 VIL Input low-level threshold 0.35 × VDDSHV(1) V VILSS Input low-level threshold steady state 0.20 V VIH Input high-level threshold 0.65 × VDDSHV(1) V VIHSS Input high-level threshold steady state 1.4 V IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA IOZ Tri-state Output Leakage Current VO = 1.8 V or 0 V ±10 µA RPU Pull-up Resistor 15 20 25 kΩ RPD Pull-down Resistor 15 20 25 kΩ VOL Output low-level voltage 0.30 V VOH Output high-level voltage VDDSHV - 0.30(1) V IOL Low Level Output Current VOL(MAX) 2 mA IOH High Level Output Current VOH(MAX) 2 mA SRI Input Slew Rate 5E +8 V/s (1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column.

6.6.5 SDIO Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT BALL NAMES in Mode 0: MMC1_CLK, MMC1_CMD, MMC1_DAT[3:0], MMC2_CLK, MMC2_CMD, MMC2_DAT[3:0] BALL NUMBERS:P25 / R29 / R24 / P24 / R25 / R26 / T26 / T25 / T24 / T27 / T29 / T28 1.8-V MODE VIL Input low-level threshold 0.58 V VILSS Input low-level threshold steady state 0.58 V VIH Input high-level threshold 1.27 V VIHSS Input high-level threshold steady state 1.7 V VHYS Input Hysteresis Voltage 150 mV IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA RPU Pull-up Resistor 40 50 60 kΩ RPD Pull-down Resistor 40 50 60 kΩ VOL Output low-level voltage 0.45 V VOH Output high-level voltage VDDSHV- 0.45(1) V IOL Low Level Output Current VOL(MAX) 4 mA IOH High Level Output Current VOH(MAX) 4 mA SRI (3) Input Slew Rate 18f(2) or 1.8E+6 V/s 3.3-V Mode VIL Input low-level threshold 0.25 × VDDSHV(1) V www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VILSS Input low-level threshold steady state 0.15 × VDDSHV(1) V VIH Input high-level threshold 0.625 × VDDSHV(1) V VIHSS Input high-level threshold steady state 0.625 × VDDSHV(1) V VHYS Input Hysteresis Voltage 150 mV IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA RPU Pull-up Resistor 40 50 60 kΩ RPD Pull-down Resistor 40 50 60 kΩ VOL Output low-level voltage 0.125 × VDDSHV(1) V VOH Output high-level voltage 0.75 × VDDSHV(1) V IOL Low Level Output Current VOL(MAX) 6 mA IOH High Level Output Current VOH(MAX) 10 mA SRI (3) Input Slew Rate 33f(2) or 3.3E+6 V/s (1) VDDSHV stands for corresponding power supply (vddshv8). For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column. (2) f = toggle frequency of the input signal in Hz. (3) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

6.6.6 CSI-2/DSI D-PHY Electrical Characteristics

CSI-2/DSI (D-PHY) interfaces are compliant with MIPI D-PHY specifications v1.2 dated August 1, 2014, including ECNs and Errata as applicable.

6.6.7 ADC12B Electrical Characteristics

Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NAMES in Mode 0: MCU_ADC0_AIN[7:0], MCU_ADC1_AIN[7:0] BALL NUMBERS:K24 / K25 / K26 / K27 / K28 / K29 / L24 / L25 / L26 / L27 / L28 / L29 / M24 / M25 / N23 / N24 Analog Input VMCU_ADC 0/1_AIN[7:0] Full-scale Input Range VSS VDDA_ADC0/ V DNL Differential Non-Linearity -1 0.5 4 LSB INL Integral Non-Linearity ±1 ±4 LSB LSBGAIN- ERROR Gain Error ±2 LSB LSBOFFSE T-ERROR Offset Error ±2 LSB CIN Input Sampling Capacitance 5.5 pF SNR Signal-to-Noise Ratio Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 70 dB DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THD Total Harmonic Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 73 dB SFDR Spurious Free Dynamic Range Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 76 dB SNR(PLUS) Signal-to-Noise Plus Distortion Input Signal: 200 kHz sine wave at -0.5 dB Full Scale 69 dB RMCU_ADC 0/1_AIN[0:7] Input Impedance of MCU_ADC0/1_AIN[7:0] f = input frequency [1/((65.97 × 10–-12) × fSMPL_CLK)] Ω IIN Input Leakage MCU_ADC0/1_AIN[7 :0] = VSS -10 μA MCU_ADC0/1_AIN[7 :0] = VDDA_ADC0/1 24 μA Sampling Dynamics FSMPL_CLK SMPL_CLK Frequency 60 MHz tC Conversion Time 13 ADC0/1 SMPL_CL K Cycles tACQ Acquisition time 2 257 ADC0/1 SMPL_CL K Cycles TR Sampling Rate ADC0/1 SMPL_CLK = 60 MHz

4 MSPS

CCISO Channel to Channel Isolation 100 dB General Purpose Input Mode(1) VIL Input low-level threshold 0.35 × VDDA_ADC0/ V VILSS Input high-level threshold steady state 0.35 × VDDA_ADC0/ V VIH Input high-level threshold 0.65 × VDDA_ADC0/ V VIHSS Input high-level threshold steady state 0.65 × VDDA_ADC0/ V VHYS Input Hysteresis Voltage 200 mV IIN Input Leakage Current VI = 1.8 V or 0 V 6 µA (1) MCU_ADC0/1 can be configured to operate in General Purpose Input mode, where all MCU_ADC0/1_AIN[7:0] inputs are globally enabled to operate as digital inputs via the ADC0/1_CTRL register (gpi_mode_en = 1).

6.6.8 MLB LVCMOS Electrical Characteristics

Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NAMES in Mode 0: MLB0_MLBSN, MLB0_MLBDP, MLB0_MLBSP, MLB0_MLBCP, MLB0_MLBDN, MLB0_MLBCN BALL NUMBERS:AC1 / AC3 / AD1 / AD2 / AD3 / AE2 VIL Input Low Voltage 0.3 × VDD(1) V VILSS Input Low Voltage Steady State 0.3 × VDD(1) V www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Only GPIO mode supported. Over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH Input High Voltage 0.7 × VDD(1) V VIHSS Input High Voltage Steady State 0.75 × VDD(1) V VHYS Input Hysteresis Voltage 80 mV IIN Input Leakage Current VI = 1.8 V or 0 V ±10 µA RPD Pull-down Resistor 20 53 130 kΩ VOL Output Low Voltage 0.2 V VOH Output High Voltage VDD(1) - 0.2 V IOL Low Level Output Current VOL(MAX) 6 mA IOH High Level Output Current VOH(MIN) 6 mA SRI Input Slew Rate(2) fop > 100 MHz 1 V/ns fop < 1 MHz 10 V/ns (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes, POWER column. (2) Slew rate may be further limited, reference Section 6.9 for actual slew rate during operation.

6.6.9 LVCMOS Electrical Characteristics

Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BALL NAMES: ALL other IOs BALL NUMBERS: ALL other IOs 1.8-V MODE VIL Input Low Voltage 0.35 × VDD(1) V VILSS Input Low Voltage Steady State 0.3 × VDD(1) V VIH Input High Voltage 0.65 × VDD(1) V VIHSS Input High Voltage Steady State 0.85 × VDD(1) V VHYS Input Hysteresis Voltage 150 mV IIN Input Leakage Current. VI = 1.8 V or 0 V ±10 µA RPU Pull-up Resistor 15 22 30 kΩ RPD Pull-down Resistor 15 22 30 kΩ VOL Output Low Voltage 0.45 V VOH Output High Voltage VDD(1) - 0.45 V IOL (2) Low Level Output Current VOL(MAX) 3 mA IOH (2) High Level Output Current VOH(MIN) 3 mA SRI (4) Input Slew Rate 18f(3) or 1.8E+6 V/s 3.3-V MODE VIL Input Low Voltage 0.8 V VILSS Input Low Voltage Steady State 0.6 V VIH Input High Voltage 2.0 V VIHSS Input High Voltage Steady State 2.0 V VHYS Input Hysteresis Voltage 150 mV IIN Input Leakage Current. VI = 3.3 V or 0 V ±10 µA RPD Pull-down Resistor 15 22 30 kΩ VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 V DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOL (2) Low Level Output Current VOL(MAX) 5 mA IOH (2) High Level Output Current VOH(MIN) 6 mA SRI (4) Input Slew Rate 33f(3) or 3.3E+6 V/s (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see Section 5.2, Pin Attributes , POWER column. (2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current available to a system implementation which needs to maintain the specified VOL and VOH values for attached components. (3) f = toggle frequency of the input signal in Hz. (4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching Characteristics sections. Select the MIN parameter which results in the largest value.

6.6.10 USB2PHY Electrical Characteristics

USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable.

6.6.11 SerDes 4-L-PHY/2-L-PHY Electrical Characteristics

The PCIe interfaces are compliant with the electrical parameters specified in PCI Express ® Base Specification Revision 4.0, September 27, 2017. This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal termination enabled, as described by parameter V REFCLK_TERM in Table 6-2 , 4-L-PHY SERDES before applying a reference clock signal that exceeds the limits defined by V REFCLK_TERM. External termination should always be enabled on the source side. Table 6-2. 4-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT BALL NAMES in Mode 0: SERDES4_REFCLK_P, SERDES4_REFCLK_N BALL NUMBERS:E8 / E7 VREFCLK_TERM Single ended voltage threshold at the reference clock pin when internal termination is enabled 400 mV RTERM Internal termination 40 50 62.5 Ω Note The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013. Note The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3 Clause 70. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47. Note The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2. This Device imposes an additional limit on the 2-L-PHY SERDES REFCLK, as described by parameters V IDTH and VIDTL in Table 6-3, 2-L-PHY SERDES REFCLK Electrical Characteristics. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-3. 2-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT BALL NAMES in Mode 0: PCIE_REFCLK[3:0]P, PCIE_REFCLK[3:0]N BALL NUMBERS:AE9 / AD10 / AE11 / AD12 / AE14 / AD15 / AE17 / AD16 VIDTH Input Differential high-level threshold 200 mV VIDTL Input Differential low-level threshold –200 mV

6.6.12 UFS M-PHY Electrical Characteristics

The UFS interface electrical characteristics are compliant with MIPI M-PHY Specification v3.1, February 17, 2014. 6.6.13 eDP/DP AUX-PHY Electrical Characteristics Note The DP interface electrical characteristics are compliant with the VESA DisplayPort (DP) Standard v 1.4 February 23, 2016. Note The eDP interface electrical characteristics are compliant with the VESA Embedded DisplayPort (eDP) Standard v1.4b October 23, 2015.

6.6.14 DDR0 Electrical Characteristics

The DDR interface is compatible with JESD209-4B standard compliant LPDDR4 SDRAM devices.

6.7 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses and is applicable only for High-Security Devices.

6.7.1 Recommended Operating Conditions for OTP eFuse Programming

over operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION MIN NOM MAX UNIT VDD_CORE Supply voltage range for the core domain during OTP operation; OPP NOM (BOOT) See Section 6.4 V VDD_MCU Supply voltage range for the core domain during OTP operation; OPP NOM (BOOT) See Section 6.4 V VPP_CORE Supply voltage range for the eFuse ROM domain during normal operation N/A(2) Supply voltage range for the eFuse ROM domain during OTP programming(1) 1.71 1.8 1.89 V VPP_MCU Supply voltage range for the eFuse ROM domain during normal operation N/A(2) Supply voltage range for the eFuse ROM domain during OTP programming(1) 1.71 1.8 1.89 V (1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70018-Q1 from the TLV707x family meet the supply voltage range needed for VPP_CORE and VPP_MCU. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.7.1 Recommended Operating Conditions for OTP eFuse Programming (continued)

(2) N/A stands for Not Applicable.

6.7.2 Hardware Requirements

The following hardware requirements must be met when programming keys in the OTP eFuses:

• The VPP_CORE and VPP_MCU power supplies must be disabled when not programming OTP registers.
• The VPP_CORE and VPP_MCU power supplies must be ramped up after the proper device power-up sequence (for more details, see Section 6.9.2).

6.7.3 Programming Sequence

Programming sequence for OTP eFuses:

• Power on the board per the power-up sequencing. No voltage should be applied on the VPP_CORE and VPP_MCU terminals during power up and normal operation.
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP software package).
• Apply the voltage on the VPP_CORE and VPP_MCU terminals according to the specification in Section 6.7.1.
• Run the software that programs the OTP registers.
• After validating the content of the OTP registers, remove the voltage from the VPP_CORE and VPP_MCU terminals.

6.7.4 Impact to Your Hardware Warranty

You recognize and accept at your own risk that your use of eFuse permanently alters the TI device. You acknowledge that eFuse can fail due to incorrect operating conditions or programming sequence. Such a failure may render the TI device inoperable and TI will be unable to confirm the TI device conformed to TI device specifications prior to the attempted eFuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY FOR ANY TI DEVICES THAT HAVE BEEN eFUSED. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.8 Thermal Resistance Characteristics

This section provides the thermal resistance characteristics used on this device. For reliability and operability concerns, the maximum junction temperature of the device has to be at or below the TJ value identified in Section 6.4, Recommended Operating Conditions.

6.8.1 Thermal Resistance Characteristics for ALF Package

It is recommended to perform thermal simulations at the system level with the worst case device power consumption. NO. PARAMETER DESCRIPTION ALF PACKAGE °C/W (1)(3) AIR FLOW (m/s) (2) T1 RΘJC Junction-to-case 0.25 N/A T2 RΘJB Junction-to-board 2.1 N/A RΘJA Junction-to-free air 11.5 0 Junction-to-moving air 7.4 1 T5 6.5 2 T6 6 3 ΨJT Junction-to-package top 0.1 0 T8 0.1 1 T9 0.1 2 T10 0.1 3 T11 ΨJB Junction-to-board 1.6 0 T12 1.7 1 T13 1.6 2 T14 1.5 3 (1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Packages (2) m/s = meters per second. (3) °C/W = degrees Celsius per watt. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9 Timing and Switching Characteristics

The default SLEWRATE settings in each pad configuration register must be used to ensure timings, unless specific instructions are given otherwise.

6.9.1 Timing Parameters and Information

The timing parameter symbols used in Section 6.9 are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 6-4: Table 6-4. Timing Parameters Subscripts SYMBOL PARAMETER c Cycle time (period) d Delay time dis Disable time en Enable time h Hold time su Setup time START Start bit t Transition time v Valid time w Pulse duration (width) X Unknown, changing, or don't care level F Fall time H High L Low R Rise time V Valid IV Invalid AE Active Edge FE First Edge LE Last Edge Z High impedance DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.2 Power Supply Sequencing

This section describes power supply sequencing required to ensure proper device operation. The device can be operated using either an isolated or combined MCU & Main power distribution network (PDN). Two different primary power sequences are recommended based upon isolated and combined MCU & Main PDNs. In addition, the device can be operated in either MCU Only or DDR Retention low power modes. Two different desired device power supply sequences for entry and exit of low power modes are shown. The power supply names used in this section are specific to this device and align to names given in the Signal Descriptions section. Common power supply names may be used across different devices within the Jacinto 7 TM processor family. These common supply names will have very similar if not identical functions across devices. All power sequencing timing diagrams shown will use the following terminology:

• Primary = Essential power sequences of all voltage domains between off and full active states.
• VOPR MIN = Minimum operational voltage level that ensures functionality as specified in Recommended Operating Conditions
• Ramp-up = start of a voltage supply transition time from off condition to Vopr min.
• Ramp-down = start of a voltage supply transition time from Vopr to off condition
• Supply_“n” = multiple instances of similar power supplies (i.e. VDDSHVn = VDDSHV0, VDDSHV1, VDDSHV2 … VDDSHV6)
• Supply_“xxx” = multiple instances of similar power supplies used for different signal types (i.e. VDDA_1P8_xxx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)
• Time stamps = “T#” markers with descriptions and approximate elapsed times for general reference. Specific timing transitions are dependent upon PDN design (see PDN User Guide for details).

6.9.2.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the maximum slew rate of supplies to be less than 100 mV/us, as shown in Figure 6-2. For instance, a 1.8V supply should have a ramp time > 18 μs to ensure the slew rate < 100mV/us. Figure 6-2 describes the Power Supply Slew Rate Requirement in the device. t Supply value SPRSP08_ELCH_06 Slew Rate = ∆V / ∆T Max Slew Rate < 100 mV / µs or 0.1 V / 1E(-6)s = 1E(+5) V / s ∆Tmin > ∆V / Max Slew Rate or 1.8 V / 1E(+5) V / s ∆Tmin > 18 µs Figure 6-2. Power Supply Slew and Slew Rate

6.9.2.2 Combined MCU and Main Domains Power-Up Sequencing

Figure 6-3 describes the primary power-up sequencing when similar MCU and Main voltage domains are combined into common power rails. Combining MCU and Main voltage domains simplifies PDN design by reducing total number of power rails and sources while making MCU and Main processor sub-systems operational dependent on common power rails. Table 8-1 in Section 8.1, Power Supply Mapping captures recommended device power supply groups to power rail mapping summary. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_ELCH_01 T0 T1 T2 T3 T4 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) , VDDA_3P3_USB (4) (2) (5) (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDS_MMC0 (4) (3) (7) (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDS_MMC0 (4) (3) (7) VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0, VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP, VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3 VDD_CPU VDD_MCU , VDD_CORE, (VDDA_0P8_SERDES0_1, (8) VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C) (9) , VDDAR_CORE, VDDAR_CPU, VDDAR_MCU PORz, MCU_PORz (11)(12) WKUP_OSC0_XI, WKUP_OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) OSC1_XI, OSC1_XO (optional) VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB (10) MCU_BOOTMODE[9:0], BOOTMODE[7:0] (11) Valid Configuration (VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3) (6) VDD_MCU (8) Note 2 Figure 6-3. Combined MCU and Main Domains, Primary Power-Up Sequence 1. Time Stamp Markers T0 – 3.3V voltages start ramp-up to VOPR MIN. (0ms) T1 – 1.8V voltages start ramp-up to VOPR MIN. (2ms) T2 – Low voltage core supplies start ramp-up to VOPR MIN. (3ms) T3 – Low voltage RAM array voltages start ramp-up to VOPR MIN. (4ms) T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13ms) 2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces. A few supplies could have varying start times between T0 to T1 due to PDN designs using different power resources with varying turn-on & ramp-up time delays. 3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp-up aligned to T3 due to PDN designs grouping supplies with VDD_MMC0. 4. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant high-speed SD card operation is needed, then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-up to 3.3V will be same as other 3.3V domains as shown. If SD card is not needed or standard data DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail. 5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start of ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter. 6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed. 7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail with power up time stamp at T1. However, if MMC0 interface is needed, then VDD_MMC0 must not start ramp-up until time stamp T3 after VDD_CORE has reached VOPR MIN. Any MCU or Main dual voltage IO operating at 1.8V can be grouped with VDD_MMC0 into a common power rail with power up time stamp T3. 8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility, enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array domains (VDDAR_xxx) at time stamp T3. 9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance. It is not recommended to combine analog VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact jitter performance of clock, PLL and DLL signals. 10. VDDA_0P8_<dll/pll> are 0.8V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It is not recommended to combine these domains with any other 0.8V domains since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals. 11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power up sequence. 12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.

6.9.2.3 Combined MCU and Main Domains Power- Down Sequencing

Figure 6-4 describes the device power-down sequencing. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 171 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_ELCH_02 T0 T1 T2 T3 T4 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6) , VDDA_3P3_USB (2) (5) (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDS_MMC0 (4) (3) (7) (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDS_MMC0 (4) (3) (7) VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0, VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP, VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3 VDD_CPU VDD_MCU , VDD_CORE, (VDDA_0P8_SERDES0_1, (8) VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C) (9) VDD_MCU VDDAR_CORE, VDDAR_MCU, VDDAR_CPU (8) PORz, MCU_PORz (10) OSC1_XI, OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) WKUP_OSC0_XI, WKUP_OSC0_XO (optional) VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB MCU_BOOTMODE[9:0], BOOTMODE[7:0] (VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3) (6) TΔ1 Figure 6-4. Combined MCU and Main Domains, Primary Power-Down Sequence 1. Time Stamp Markers T0 – MCU_PORz & PORz assert low to put all processor resources in safe state. (0ms) T1 – Main DDR, SRAM Core & SRAM CPU power supplies start ramp-down. (0.5ms) T2 – Low voltage core supplies start supply ramp-down. (2.5ms) T3 - 1.8V voltages start supply ramp-down. (3.0ms) T4 – 3.3V voltages start supply ramp-down. (3.5ms) 2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces 3. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp- down aligned to T1 due to PDN designs grouping supplies with VDD_MMC0. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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1. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from 3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail. 5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter. 6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed. 7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down at time stamp T3. 8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility, enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array domains (VDDAR_xxx) at time stamp T1. 9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance. It is not recommended to combine analog VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact jitter performance of clock, PLL and DLL signals. 10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe state before any voltage begins to ramp down.

6.9.2.4 Isolated MCU and Main Domains Power- Up Sequencing

Isolated MCU and Main voltage domains enable an SoC’s MCU and Main processor sub-systems to operate independently. There are 2 reasons an SoC’s PDN design may need to support independent MCU and Main processor functionality. First is to provide flexibility to enable SoC low power modes that can significant reduce SoC power dissipation when processor operations are not needed. Second is to enable robustness to gain freedom from interference (FFI) of a single fault impacting both MCU and Main processor sub-systems which is especially beneficial if using the SoC’s MCU as the system safety monitoring processor. The number of additional PDN power rails needed is dependent upon number of different MCU IO signaling voltage levels. If only 1.8V IO signaling is used, the only 2 additional power rails could be required. If both 1.8 and 3.3V IO signaling is desired, then 4 additional power rails could be needed. Table 8-2 in Section 8.1, Power Supply Mapping captures recommended device power supplies to power rail mapping summary. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 173 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_ELCH_03 T0 T1 T2 T3 T4 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU) (2) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB (4) (2) (5) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) VDDS_MMC0 (4) (3) (7) VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0, VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP VDD_MCU , VDDAR_MCU (8) VDD_CORE, (VDD_MCU, VDDA_0P8_SERDES0_1, VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C) (9) VDDAR_CORE, VDDAR_CPU MCU_PORz (11)(12) PORz (11)(12) OSC1_XI, OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) WKUP_OSC0_XI, WKUP_OSC0_XO (optional) VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS MCU_BOOTMODE[9:0],BOOTMODE[7:0] (10) Valid Configuration (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU) (3) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) VDDS_MMC0 (4) (3) (7) VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3, VDD_CPU Note 2 (VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3) (6) VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB (10) Note 2 Figure 6-5. Isolated MCU and Main Domains, Primary Power-Up Sequence 1. Time Stamp Markers T0 – 3.3V voltages start ramp-up to VOPR MIN. (0ms) T1 – 1.8V voltages startramp-up to VOPR MIN. (2ms) T2 – Low voltage core supplies start ramp-up to VOPR MIN. (3ms) T3 – Low voltage RAM array voltages start ramp-up to VOPR MIN. (4ms) T4 – OSC1 is stable and PORz/MCU_PORz are de-asserted to release processor from reset. (13ms) 2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces. A few supplies could have varying start times between T0 to T1 due to PDN designs using different power resources with varying turn-on & ramp-up time delays. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have delayed start times that aligns to T3 due to PDN designs grouping supplies with VDD_MMC0. 4. VDDSHV5 supports MMC1 signaling for SD memory cards. If compliant UHS-I SD card operation is needed, then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-up to 3.3V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates with fixed 3.3V operation is acceptable, then supply can be grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then supply can be grouped with digital IO 1.8V power rail. 5. VDDA_3P3_USB is 3.3V analog supply used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start of ramp-up to 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit errors can be tolerated, then supply can be grouped with 3.3V digital IO power rail either directly or through a supply filter. 6. VDDA_1P8_<phy> are 1.8V analog supplies supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then supplies can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed. 7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp up at time stamp T3. Any MCU or Main dual voltage IO operating at 1.8V can be grouped with VDD_MMC0 into a common power rail with a ramp-up at time stamp T3. If MMC0 or eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail with ramp-up at time stamp T1. 8. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility, enabling it to be grouped and ramped-up with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array domains (VDDAR_xxx) at time stamp T3. 9. VDDA_1P8_<clk/pll/ana> are 1.8V analog supplies supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance. It is not recommended to combine analog VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact jitter performance of clock, PLL and DLL signals. 10. VDDA_0P8_<dll/pll> are 0.8V analog supplies supporting PLL and DLL circuitry needing a low noise supply for optimal performance. It is not recommended to combine these domains with any other 0.8V domains since high frequency switching noise could negatively impact jitter performance of PLL and DLL signals. 11. Minimum set-up and hold times shown with respect to MCU_PORz and PORz asserting high to latch MCU_BOOTMODEn (referenced to MCU_VDDSHV0) and BOOTMODEn (reference to VDDSHV2) settings into registers during power up sequence. 12. Minimum elapsed time from crystal oscillator circuitry being energized (VDDS_OSC1 at T1) until stable clock frequency is reached depends upon on crystal oscillator, capacitor parameters and PCB parasitic values. A conservative 10ms elapsed time defined by (T4 – T1) time stamps is shown. This could be reduced depending upon customer’s clock circuit (that is, crystal oscillator or clock generator) and PCB designs.

6.9.2.5 Isolated MCU and Main Domains, Primary Power- Down Sequencing

Figure 6-6 describes the device power-down sequencing. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 175 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_ELCH_04 T0 T1 T2 T3 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU) (2) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) ,VDDA_3P3_USB (4) (2) (5) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) VDDS_MMC0 (4) (3) (7) VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0, VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP (VDD_MCU , VDDAR_MCU) (8) VDD_CORE, (VDD_MCU, VDDA_0P8_SERDES0_1, VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C) (9) VDDAR_CORE, VDDAR_CPU MCU_PORz (10) PORz (10) OSC1_XI, OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) WKUP_OSC0_XI, WKUP_OSC0_XO (optional) VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU) (3) (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5 , VDDSHV6) VDDS_MMC0 (4) (3) (7) VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3, VDD_CPU (VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3) (6) VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB TΔ1 BOOTMODE[9:0],BOOTMODE[7:0] Figure 6-6. Isolated MCU and Main Domains, Primary Power- Down Sequencing 1. Time Stamp Markers T0 – MCU_PORz & PORz assert low to put all processor resources in safe state. (0ms) T1 – Main DDR, SRAM Core & SRAM CPU power supplies start ramp-down. (0.5ms) T2 – Low voltage core supplies start supply ramp-down. (2.5ms) T3 - 1.8V voltages start supply ramp-down. (3.0ms) T4 – 3.3V voltages start supply ramp-down. (3.5ms) 2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces. When eMMC memories are used, Main 1.8V supplies could have a ramp- down aligned to T1 due to PDN designs grouping supplies with VDD_MMC0. 4. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3V/1.8V) power rail is required for compliant, high-speed SD card operations. If compliant highspeed SD card operation is needed, then an independent, dual voltage (3.3V/1.8V) power source and rail are required. The start of ramp-down from 3.3V/1.8V will be same as other 3.3V domains as shown. If SD card is not needed or standard data rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail. 5. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. The start of ramp-down from 3.3V will be same as other 3.3V domains as shown. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter. 6. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed. 7. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface and must ramp-down at time stamp T1 before VDD_CORE starts ramp-down. Any MCU or Main dual voltage IO operating at 1.8V can be grouped with VDD_MMC0 into a common power rail with power down time stamp T1. If MMC0 or eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail and ramp-down at time stamp T3. 8. VDD_MCU is a digital voltage supply with a wide operating voltage range and power sequencing flexibility, enabling it to be grouped and ramped-down with either 0.8V VDD_CORE at time stamp T2 or 0.85V RAM array domains (VDDAR_xxx) at time stamp T1. 9. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL & analog circuitry needing a low noise supply for optimal performance. It is not recommended to combine analog VDDA_1P8_<phy> domains or digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency switching noise could negatively impact jitter performance of clock, PLL and DLL signals. 10. MCU_PORz and PORz must be asserted low for TΔ1 = 200us min to ensure SoC resources enter into safe state before any voltage begins to ramp down.

6.9.2.6 Entry and Exit of MCU Only State

Entry into MCU Only lower power state is accomplished by executing a power down sequence except for the 4 MCU supply groups (VDDSHVx_MCU at 3.3V, VDDSHVx_MCU at 1.8V, VDDA_MCU_PLLGRP0/ VDDA_MCU_TEMP analog supplies at 1.8V, VDD_MCU/VDDAR_MCU at 0.85V) that remain energized. Exit from MCU Only state is accomplished by executing a power up sequence with the 4 MCU supply groups remaining energized throughout the sequence. The example diagram shown is for an Isolated MCU & Main PDN type with eMMC support. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_ELCH_03 T0 T1 T2 T3 T4 Valid Configuration T0 T1 T2 T3 VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU (3)(5a) VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6 ,VDDA_3P3_USB (3)(5b) VDDS_MMC0 VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0, VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP VDD_MCU, VDDAR_MCU (7) VDDA_0P8_SERDES0_1, VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C VDD_CORE, VDD_MCU, VDDAR_CORE, VDDAR_MCUVDDAR_CPU, (7) MCU_PORz (9)(10) PORz (9)(10) OSC1_XI, OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) WKUP_OSC0_XI, WKUP_OSC0_XO (optional) VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU (4) VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6 (4) VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3, VDD_CPU VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3 (6) VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB SYSBOOT[17:0] (9) Active ActiveEntry into MCU only MCU only Exit from MCU only Figure 6-7. Entry and Exit of MCU Only Sequencing

6.9.2.7 Entry and Exit of DDR Retention State

Entry into DDR Retention (Suspend-to-RAM or S2R) state is accomplished by executing a power down sequence except for the 1 device DDR supply group (VDDS_DDR_BIAS, VDDS_DDR, and VDDS_DDR_C at 1.1V), and 1 additional discrete SDRAM supply (VDD_LPDDR4_1V8 at 1.8V; not shown in diagram below) that remain energized. Exit from DDR Retention state is accomplished by executing a power up sequence with these 2 DDR supply groups remaining energized throughout the sequence. The example diagram shown is for an Isolated MCU & Main PDN type with eMMC support. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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J7ES_ELCH_03 T0 T1 T2 T3 T4 Valid Configuration T0 T1 T2 T3 VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU (3)(5a) VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6 ,VDDA_3P3_USB (3)(5b) VDDS_MMC0 VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC0, VDDA_ADC1, VDDA_POR_WKUP, VDDA_WKUP VDD_MCU, VDDAR_MCU (7) VDDA_0P8_SERDES0_1, VDDA_0P8_SERDES2_3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2_3, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C VDD_CORE, VDD_MCU, VDDAR_CORE, VDDAR_MCUVDDAR_CPU, (7) MCU_PORz (9)(10) PORz (9)(10) OSC1_XI, OSC1_XO WKUP_LFOSC0_XI, WKUP_LFOSC0_XO (optional) WKUP_OSC0_XI, WKUP_OSC0_XO (optional) VDDS_DDR, VDDS_DDR_C, VDDS_DDR_BIAS VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU (4) VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV5, VDDSHV6 (4) VDDS_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP2, VDDA_PLLGRP3, VDDA_PLLGRP4, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_TEMP0_1, VDDA_TEMP2_3, VDD_CPU VDDA_1P8_CSIRX, VDDA_1P8_UFS, VDDA_1P8_USB, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2_3 (6) VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0, VDDA_0P8_PLL_MLB SYSBOOT[17:0] (9) Active ActiveEntry into MCU only DDR Retention Exit from MCU only Figure 6-8. Entry and Exit of DDR Retention Sequencing www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 179 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-5. System Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 2 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 30 pF

6.9.3.1 Reset Timing

Tables and figures provided in this section define timing requirements and switching characteristics for reset related signals. Table 6-6. MCU_PORz Timing Requirements see Figure 6-9 NO. MIN TYP MAX UNIT RST1 th(MCUD_SUPPLIES_VALID - MCU_PORz) Hold time, MCU_PORz active (low) at Power- up after all MCU DOMAIN supplies valid (using external crystal) N + 1200(2) 9500000 ns RST2 Hold time, MCU_PORz active (low) at Power- up after all MCU DOMAIN supplies(1) valid and external clock stable (using external LVCMOS oscillator) 1200 ns RST3 tw(MCU_PORzL) Pulse Width minimum, MCU_PORz low after Power-up (without removal of Power or system reference clock MCU_OSC0_XI/XO) 1200 ns (1) For definition of the MCU DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence. (2) N = oscillator start-up time MCU_PORz RST1 RST3 MCU_OSC0_XI, MCU_OSC0_XO RST2 MCU DOMAIN SUPPLIES VALID Figure 6-9. MCU_PORz Timing Requirements DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-7. PORz Timing Requirements see Figure 6-10 NO. MIN MAX UNIT RST4 th(MAIND_SUPPLIES_VALID - PORz) Hold time, PORz active (low) at Power-up after all MAIN DOMAIN supplies1 valid 1200 ns RST5 tw(PORzL) Pulse Width minimum, PORz low after Power-up 1200 ns 1. For definition of the MAIN DOMAIN supplies, see the Combined MCU and Main Domains Power-Up sequence. PORz RST4 RST5 MAIN DOMAIN SUPPLIES VALID Figure 6-10. PORz Timing Requirements Table 6-8. MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 6-11 NO. PARAMETER MODE MIN MAX UNIT RST6 td(MCU_PORzL-MCU_PORz_OUTL) Delay time, MCU_PORz active (low) to MCU_PORz_OUT active (low) 0 ns RST7 td(MCU_PORzH-MCU_PORz_OUTH) Delay time, MCU_PORz inactive (high) to MCU_PORz_OUT inactive (high) 0 ns RST8 td(MCU_PORzL-PORz_OUTL) Delay time, MCU_PORz active (low) to PORz_OUT active (low) 0 ns RST9 td(MCU_PORzH-PORz_OUTH) Delay time, MCU_PORz inactive (high) to PORz_OUT inactive (high) 1500 ns RST10 td(MCU_PORzL-MCU_RESETSTATzL) Delay time, MCU_PORz active (low) to MCU_RESETSTATz active (low) 0 ns RST11 td(MCU_PORzH-MCU_RESETSTATzH) Delay time, MCU_PORz inactive (high) to MCU_RESETSTATz inactive (high) POST bypass 12000*S(1) ns RST12 td(MCU_PORzL-RESETSTATzL) Delay time, MCU_PORz active (low) to RESETSTATz active (low) 0 ns RST13 td(MCU_PORzH-RESETSTATzH) Delay time, MCU_PORz inactive (high) to RESETSTATz inactive (high) 14500*S(1) ns RST14 tw(MCU_PORz_OUTL) Pulse width minimum, MCU_PORz_OUT active (low) 1200 ns RST15 tw(PORz_OUTL) Pulse Width Minimum PORz_OUT low 2550 ns RST16 tw(MCU_RESETSTATzL) Pulse Width Minimum MCU_RESETSTATz low 3900*S(1) ns RST17 tw(RESETSTATzL) Pulse Width Minimum RESETSTATz low 2650*S(1) ns (1) S = MCU_OSC0_XI/XO clock period. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 181 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

MCU_PORz RST17 MCU_RESETST A Tz MCU_PORz_OUT RESETST A Tz PORz_OUT RST16 RST15 RST14 RST13 RST12 RST1 1 RST7RST6 RST8 RST10 RST9 Figure 6-11. MCU_PORz initiates; MCU_PORz_OUT, PORz_OUT, MCU_RESETSTATz, and RESETSTATz Switching Characteristics DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-9. PORz Initiates; PORz_OUT and RESETSTATz Switching Characteristics see Figure 6-12 NO. PARAMETER MODE MIN MAX UNIT RST18 td(PORzL-PORz_OUTL) Delay time, PORz active (low) toPORz_OUT active (low) software control of POR_RST_ISO_DONE_Z T(1) CTRLMMR_WKUP_POR_RST _CTRL[0].POR_RST_ISO_ DONE_Z = 0 0 ns RST19 td(PORzH-PORz_OUTH) Delay time, PORz active (high) toPORz_OUT active (high) 1300 ns RST20 td(PORzL- RESETSTATzL) Delay time, PORz active (low) to RESETSTATz active (low) T(1) CTRLMMR_WKUP_POR_RST _CTRL[0].POR_RST_ISO_ DONE_Z = 0 0 ns RST21 td(PORzH- RESETSTATzH) Delay time, PORz active (high) to RESETSTATz active (high) 14500*S (2) ns (1) T = Reset Isolation Time (Software Dependent). (2) S = MCU_OSC0_XI/XO clock period. PORz RST18 RESETST A Tz RST20 RST21 PORz_OUT RST19 Figure 6-12. PORz initiates; PORz_OUT and RESETSTATz Switching Characteristics www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-10. MCU_RESETz Timing Requirements see Figure 6-13 NO. MIN MAX UNIT RST22 tw(MCU_RESETzL) (1) Pulse Width minimum, MCU_RESETz active (low) 1200 ns (1) Timing for MCU_RESETz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time. Table 6-11. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Switching Characteristics see Figure 6-13 NO. PARAMETER MIN MAX UNIT RST23 td(MCU_RESETzL-MCU_RESETSTATzL) Delay time, MCU_RESETz active (low) to MCU_RESETSTATz active (low) 800 ns RST24 td(MCU_RESETzH-MCU_RESETSTATzH) Delay time, MCU_RESETz inactive (high) to MCU_RESETSTATz inactive (high) 3900*S(1) ns RST25 td(MCU_RESETzL-RESETSTATzL) Delay time, MCU_RESETz active (low) to RESETSTATz active (low) 800 ns RST26 td(MCU_RESETzH-RESETSTATzH) Delay time, MCU_RESETz inactive (high) to RESETSTATz inactive (high) 3900*S(1) ns (1) S = MCU_OSC0_XI/XO clock period. MCU_RESETz RST23 RESETST A Tz RST25 RST26 MCU_RESETST A Tz RST24 RST22 Figure 6-13. MCU_RESETz initiates; MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching Characteristics DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-12. RESET_REQz Timing Requirements see Figure 6-14 NO. MIN MAX UNIT RST27 tw(RESET_REQzL) (1) Pulse Width minimum, RESET_REQz active (low) 1200 ns (1) Timing for RESET_REQz is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time. Table 6-13. RESET_REQz initiates; RESETSTATz Switching Characteristics see Figure 6-14 NO. PARAMETER MODE MIN MAX UNIT RST28 td(RESET_REQzL-RESETSTATzL) Delay time, RESET_REQz active (low) to RESETSTATz active (low) software control of SOC_WARMRST_ISO_DONE T(1) CTRLMMR_WKUP_MAIN_WA RM _RST_CTRL[0].SOC_ WARMRST_ISO_DONE_Z = 0 740 ns RST29 td(RESET_REQzH-RESETSTATzH) Delay time, RESET_REQz inactive (high) to RESETSTATz inactive (high) 2650*S (2) ns (1) T = Reset Isolation Time (Software Dependent). (2) S = MCU_OSC0_XI/XO clock period. RESET_REQz RST28 RST27 RESETST A Tz RST29 Figure 6-14. RESET_REQz initiates; RESETSTATz Timing Requirements and Switching Characteristics www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-14. EMUx Timing Requirements see Figure 6-15 NO. MIN MAX UNIT RST30 tsu(EMUx-MCU_PORz) Setup time, EMU[1:0] before MCU_PORz inactive (high) 3*S(1) ns RST31 th(MCU_PORz - EMUx) Hold time, EMU[1:0] after MCU_PORz inactive (high) 10 ns (1) S = MCU_OSC0_XI/XO clock period. EMU[1:0] MCU_PORz RST30 RST31 Figure 6-15. EMUx Timing Requirements Table 6-15. MCU_BOOTMODE Timing Requirements see Figure 6-16 NO. MIN MAX UNIT RST32 tsu(MCU_BOOTMODE-MCU_PORz_OUT) Setup time, MCU_BOOTMODE[09:00] before MCU_PORz_OUT high 3*S(1) ns RST33 th(MCU_PORz_OUT - MCU_BOOTMODE) Hold time, MCU_BOOTMODE[09:00] after MCU_ PORz_OUT high 0 ns (1) S = MCU_OSC0_XI/XO clock period. RST32 MCU_PORz_OUT MCU_BOOTMODE[09:00] RST33 Figure 6-16. MCU_BOOTMODE Timing Requirements DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-16. BOOTMODE Timing Requirements see Figure 6-17 NO. MIN MAX UNIT RST34 tsu(BOOTMODE-PORz_OUT) Setup time, BOOTMODE[7:0] before PORz_OUT high 3*S(1) ns RST35 th(PORz_OUT - BOOTMODE) Hold time, BOOTMODE[7:0] after PORz_OUT high 0 ns (1) S = MCU_OSC0_XI/XO clock period. RST34 PORz_OUT BOOTMODE[7:0] RST35 Figure 6-17. BOOTMODE Timing Requirements www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.3.2 Safety Signal Timing

Tables and figures provided in this section define switching characteristics for MCU_SAFETY_ERRORn and SOC_SAFETY_ERRORn. Table 6-17. MCU_SAFETY_ERRORn Switching Characteristics see Figure 6-18 NO. PARAMETER MIN MAX UNIT SFTY1 tw(MCU_SAFETY_ERRORn) Pulse width minimum, MCU_SAFETY_ERRORn active (PWM mode disabled) P*R(1) (2) ns SFTY2 td (ERROR_CONDITION-MCU_SAFETY_ERRORnL) Delay time, ERROR CONDITION to MCU_SAFETY_ERRORn active 50*P(1) ns (1) P = ESM functional clock (MCU_SYSCLK0 /6). (2) R = Error Pin Counter Pre-Load Register count value. MCU_SAFETY_ERRORn (PWM Mode Disabled) SFTY1 SFTY2 Internal Error Condition (Active High) Figure 6-18. MCU_SAFETY_ERRORn Switching Characteristics Table 6-18. SOC_SAFETY_ERRORn Switching Characteristics see Figure 6-19 NO. PARAMETER MIN MAX UNIT SFTY3 tw(SOC_SAFETY_ERRORn) Pulse width minimum,SOC_SAFETY_ERRORn active (PWM mode disabled) P*R(1) (2) ns SFTY4 td (ERROR_CONDITION-SOC_SAFETY_ERRORnL) Delay time, ERROR CONDITION to SOC_SAFETY_ERRORn active 50*P(1) ns SOC_SAFETY_ERRORn (PWM Mode Disabled) SFTY3 SFTY4 Internal Error Condition (Active High) Figure 6-19. SOC_SAFETY_ERRORn Switching Characteristics DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.3.3 Clock Timing

Tables and figures provided in this section define timing requirements and switching characteristics for clock signals. Table 6-19. Clock Timng Requiements see Figure 6-20 NO. MIN MAX UNIT CLK1 tc(EXT_REFCLK1) Cycle time minimum, EXT_REFCLK1 10 ns CLK2 tw(EXT_REFCLK1H) Pulse Duration minimum, EXT_REFCLK1 high E*0.45(1) E*0.55(1) ns CLK3 tw(EXT_REFCLK1L) Pulse Duration minimum, EXT_REFCLK1 low E*0.45(1) E*0.55(1) ns (1) E = EXT_REFCLK1 cycle time. EXT_REFCLK1 CLK1 CLK2 CLK3 CLK19 CLK20 CLK21 MCU_EXT_REFCLK0 Figure 6-20. Clock Timing Requirements Table 6-20. Clock Switching Characteristics see Figure 6-21 NO. PARAMETER MIN MAX UNIT CLK4 tc(SYSCLKOUT0) Cycle time minimum,SYSCLKOUT0 8 ns CLK5 tw(SYSCLKOUT0H) Pulse Duration minimum, SYSCLKOUT0 high A*0.4(1) A*0.6(1) ns CLK6 tw(SYSCLKOUT0L) Pulse Duration minimum, SYSCLKOUT0 low A*0.4(1) A*0.6(1) ns CLK7 tc(OBSCLK0) Cycle time minimum, OBSCLK0 5 ns CLK8 tw(OBSCLK0H) Pulse Duration minimum, OBSCLK0 high B*0.4(2) B*0.6(2) ns CLK9 tw(OBSCLK0L) Pulse Duration minimum,OBSCLK0 low B*0.4(2) B*0.6(2) ns CLK10 tc(CLKOUT0) Cycle time minimum, CLKOUT0 20 ns CLK11 tw(CLKOUT0H) Pulse Duration minimum, CLKOUT0 high C*0.4(3) C*0.6(3) ns CLK12 tw(CLKOUT0L) Pulse Duration minimum,CLKOUT0 low C*0.4(3) C*0.6(3) ns (1) A = SYSCLKOUT0 cycle time. (2) B = OBSCLK0 cycle time. (3) C = CLKOUT0 cycle time. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

MCU_SYSCLKOUT0 CLK13 CLK14 CLK15 MCU_OBSCLK0 CLK16 CLK17 CLK18 Figure 6-21. Clock Switching Characteristics

6.9.4 Clock Specifications

6.9.4.1 Input and Output Clocks / Oscillators

Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as follows:

• OSC1_XO/OSC1_XI — Еxternal main crystal interface pins connected to internal oscillator which sources reference clock and provides reference clock to PLLs within MAIN domain. Also, for audio applications, high-frequency oscillator 0 is used to provide audio clock frequencies to MCASPs.
• High frequency oscillators inputs – OSC1_XO/OSC1_XI — external main crystal interface pins connected to internal oscillator which sources reference clock. Provides reference clock to PLLs within MCU domain and MAIN domain. This high- frequency oscillator is used to provide audio clock frequencies to MCASPs. – WKUP_OSC0_XO/WKUP_OSC0_XI — external main crystal interface pins connected to internal oscillator which sources reference clock. Provides reference clock to PLLs within WKUP and MAIN domain.
• Low frequency oscillator input – WKUP_LFOSC_XO/WKUP_LFOSC_XI — external main crystal interface pins connected to internal oscillator which sources reference clock provides a clock for low power operation in deeper sleep modes.
• General purpose clock inputs – MCU_EXT_REFCLK0 — optional external. Provides system clock input (MCU domain). – EXT_REFCLK1 — optional external System clock input (MAIN domain). Optionally PLL2 (PER1) and MCASP can be sourced by EXT_REFCLK1 (sourced externally). – SERDES4_REFCLK_P/N — SerDes reference clock input for PCIe or Optional USB3 and SGMII interfaces. – PCIE_REFCLK[3:0]N/P — There are 4 differential clock input/output pins to support PCIe devices.
• External video pixel clock inputs – VOUT0_EXTPCLKIN — optional for the DPI0 port of DSS. – VOUT1_EXTPCLKIN — optional for the DPI1 port of DSS.
• External CPTS reference clock inputs DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the device TRM.

6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source

Figure 6-23 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit should be placed as close as possible to the WKUP_OSC0_XI and WKUP_OSC0_XO pins. Device WKUP_OSC0_XOWKUP_OSC0_XI Cf1 Crystal Rd Cf2 (Optional) J7ES_WKUP_OSC_INT_02 Rbias(Optional) PCB Ground Figure 6-23. WKUP_OSC0 Crystal Implementation The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-21 summarizes the required electrical constraints. Table 6-21. WKUP_OSC0 Crystal Electrical Characteristics PARAMETER MIN TYP MAX UNIT Fxtal Crystal Parallel Resonance Frequency 19.2, 20, 24, 25, 26, 27 MHz Fxtal Crystal Frequency Stability and Tolerance Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 CL1+PCBXI Capacitance of CL1 + CPCBXI 12 24 pF CL2+PCBXO Capacitance of CL2 + CPCBXO 12 24 pF CL Crystal Load Capacitance 6 12 pF Cshunt Crystal Circuit Shunt Capacitance ESRxtal = 30 Ω 19.2 MHz, 20 MHz,

24 MHz, 25 MHz, 26 MHz,

27 MHz

ESRxtal = 40 Ω 19.2 MHz, 20 MHz, ESRxtal = 50 Ω 19.2 MHz, 20 MHz, ESRxtal = 60 Ω 19.2 MHz, 20 MHz, 24 MHz 5 pF ESRxtal = 80 Ω 19.2 MHz, 20 MHz 5 pF

25 MHz 3 pF

ESRxtal = 100 Ω 19.2 MHz, 20 MHz 3 pF DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-21. WKUP_OSC0 Crystal Electrical Characteristics (continued) PARAMETER MIN TYP MAX UNIT ESRxtal Crystal Effective Series Resistance 100 Ω When selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. Table 6-22 details the switching characteristics of the oscillator and the requirements of the input clock. Table 6-22. WKUP_OSC0 Switching Characteristics – Crystal Mode PARAMETER MIN TYP MAX UNIT CXI XI Capacitance 1.55 pF CXO XO Capacitance 1.35 pF CXIXO XI to XO Mutual Capacitance 0.1 pF ts Maximum Start-up Time 9.5(1) ms (1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum startup and operation over temperature/voltage extremes. VDDA_WKUP WKUP_OSC0_XO tsX Time Voltage VSS VDDA_WKUP (min.) VDD_WKUP (min.) VSS VDD_WKUP J7ES_WKUP_OSC_ST ARTUP_04 Figure 6-24. WKUP_OSC0 Start-up Time The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined by the crystal manufacturer. The capacitive load, C L, of this circuit is a combination of discrete capacitors CL1, C L2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to WKUP_OSC0_XI and WKUP_OSC0_XO have parasitic capacitance to ground, C PCBXI and C PCBXO, where the PCB designer should be able to extract parasitic capacitance for each signal trace. The WKUP_OSC0 circuits and device package have combined parasitic capacitance to ground, C PCBXI and CPCBXO, where these parasitic capacitance values are defined in Table 6-22. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 193 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_WKUP_OSC_CC_05 CPCBXI CPCBXO CL1 CL2 PCB Signal Traces Crystal Circuit Components WKUP_OSC0_XO WKUP_OSC0_XI CXI CXO Device Figure 6-25. Load Capacitance Load capacitors, C L1 and C L2 in Figure 6-23, should be chosen such that the below equation is satisfied. C L in the equation is the load specified by the crystal manufacturer. CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)] To determine the value of CL1 and CL2, multiply the capacitive load value C L by 2. Using this result, subtract the combined values of C PCBXI + C XI to determine the value of C L1 and the combined values of C PCBXO + C XO to determine the value of C L2. For example, if C L = 10 pF, C PCBXI = 2.9 pF, C XI = 0.5 pF, C PCBXO = 3.7 pF, C XO = 0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and C L2 = [(2CL) - (CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for WKUP_OSC0 operating conditions defined in Table 6-21. Shunt capacitance, C shunt, of the crystal circuit is a combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal circuit components to WKUP_OSC0 have mutual parasitic capacitance to each other, C PCBXIXO, where the PCB designer should be able to extract mutual parasitic capacitance between these signal traces. The device package also has mutual parasitic capacitance, C XIXO, where this mutual parasitic capacitance value is defined in Table 6-22. PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can also be minimized by placing a ground trace between these signals when the layout requires them to be routed in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as possible when selecting a crystal. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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J7ES_WKUP_OSC_SC_06 Device WKUP_OSC0_XO WKUP_OSC0_XI CPCBXIXO PCB Signal Traces Crystal Circuit Components CXIXOCO Figure 6-26. Shunt Capacitance A crystal should be chosen such that the below equation is satisfied. C O in the equation is the maximum shunt capacitance specified by the crystal manufacturer. Cshunt ≥ CO + CPCBXIXO + CXIXO For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω, CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.

6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source

Figure 6-27 shows the recommended oscillator connections when WKUP_OSC0_XI is connected to a 1.8-V LVCMOS square-wave digital clock source. Note A DC steady-state condition is not allowed on WKUP_OSC0_XI when the oscillator is powered up. This is not allowed because WKUP_OSC0_XI is internally AC coupled to a comparator that may enter a unknown state when DC is applied to the input. Therefore, application software should power down WKUP_OSC0 any time WKUP_OSC0_XI is not toggling between logic states. Device WKUP_OSC0_XOWKUP_OSC0_XI PCB Ground Figure 6-27. 1.8-V LVCMOS-Compatible Clock Input

6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source

Figure 6-28 shows the recommended crystal circuit. All discrete components used to implement the oscillator circuit should be placed as close as possible to the OSC1_XI and OSC1_XO pins. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 195 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

OSC1_XOOSC1_XI Cf1 Crystal Rd Cf2 (Optional) J7ES_AUX_OSC_INT_07 Rbias(Optional) PCB Ground Figure 6-28. OSC1 Crystal Implementation DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-23 summarizes the required electrical constraints. Table 6-23. OSC1 Crystal Electrical Characteristics PARAMETER MIN TYP MAX UNIT Fxtal Crystal Parallel Resonance Frequency 19.2 27 MHz Fxtal Crystal Frequency Stability and Tolerance Ethernet RGMII and RMII not used ±100 ppm Ethernet RGMII and RMII using derived clock ±50 CL1+PCBXI Capacitance of CL1 + CPCBXI 12 24 pF CL2+PCBXO Capacitance of CL2 + CPCBXO 12 24 pF CL Crystal Load Capacitance 6 12 pF Cshunt Crystal Circuit Shunt Capacitance ESRxtal = 30 Ω 19.2 MHz, 20 MHz, ESRxtal = 40 Ω 19.2 MHz, 20 MHz, ESRxtal = 50 Ω 19.2 MHz, 20 MHz, ESRxtal = 60 Ω 19.2 MHz, 20 MHz, 24 MHz 5 pF ESRxtal = 80 Ω 19.2 MHz, 20 MHz 5 pF ESRxtal = 100 Ω 19.2 MHz, 20 MHz 3 pF ESRxtal Crystal Effective Series Resistance 100 Ω When selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. Table 6-24 details the switching characteristics of the oscillator and the requirements of the input clock. Table 6-24. OSC1 Switching Characteristics – Crystal Mode PARAMETER MIN TYP MAX UNIT CXI XI Capacitance 1.55 pF CXO XO Capacitance 1.35 pF CXIXO XI to XO Mutual Capacitance 0.9 fF ts Maximum Start-up Time 9.5(1) ms (1) TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum startup and operation over temperature/voltage extremes. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

VDDS_OSC1 OSC1_XO tsX Time Voltage VSS VDDS_OSC1 (min.) VDD_CORE (min.) VSS VDD_CORE J7ES_AUX_OSC_STARTUP_08 Figure 6-29. OSC1 Start-up Time The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined by the crystal manufacturer. The capacitive load, C L, of this circuit is a combination of discrete capacitors C L1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to OSC1_XI and OSC1_XO have parasitic capacitance to ground, C PCBXI and C PCBXO, where the PCB designer should be able to extract parasitic capacitance for each signal trace. The OSC1 circuits and device package have combined parasitic capacitance to ground, C PCBXI and C PCBXO, where these parasitic capacitance values are defined in Table 6-24. J7ES_AUX_OSC_CC_05 CPCBXI CPCBXO CL1 CL2 PCB Signal Traces Crystal Circuit Components OSC1_XO OSC1_XI CXI CXO Device Figure 6-30. Load Capacitance Load capacitors, C L1 and C L2 in Figure 6-28, should be chosen such that the below equation is satisfied. C L in the equation is the load specified by the crystal manufacturer. CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)] To determine the value of CL1 and CL2, multiply the capacitive load value C L by 2. Using this result, subtract the combined values of C PCBXI + C XI to determine the value of C L1 and the combined values of C PCBXO + C XO to determine the value of C L2. For example, if C L = 10 pF, C PCBXI = 2.9 pF, C XI = 0.5 pF, C PCBXO = 3.7 pF, C XO = 0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and C L2 = [(2CL) - (CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for OSC1 operating conditions defined in Table 6-23 . Shunt capacitance, C shunt, of the crystal circuit is a combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal circuit components to OSC1 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB designer should be able to extract mutual parasitic capacitance between these signal traces. The device package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined in Table 6-24. PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can also be minimized by placing a ground trace between these signals when the layout requires them to be routed in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as possible when selecting a crystal. J7ES_AUX_OSC_SC_06 Device OSC1_XO OSC1_XI CPCBXIXO PCB Signal Traces Crystal Circuit Components CXIXOCO Figure 6-31. Shunt Capacitance A crystal should be chosen such that the below equation is satisfied. C O in the equation is the maximum shunt capacitance specified by the crystal manufacturer. Cshunt ≥ CO + CPCBXIXO + CXIXO For example, the equation would be satisfied when the crystal being used is 25 MHz with an ESR = 30 Ω, CPCBXIXO = 0.04 pF, CXIXO = 0.01 pF, and shunt capacitance of the crystal is less than or equal to 6.95 pF.

6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source

Figure 6-32 shows the recommended oscillator connections when OSC1 is connected to a 1.8-V LVCMOS square-wave digital clock source. Note A DC steady-state condition is not allowed on OSC1_XI when the oscillator is powered up. This is not allowed because OSC1_XI is internally AC coupled to a comparator that may enter a unknown state when DC is applied to the input. Therefore, application software should power down OSC1 any time OSC1_XI is not toggling between logic states. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 199 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

OSC1_XOOSC1_XI J7ES_AUX_OSC_EXT_09 PCB Ground Figure 6-32. 1.8-V LVCMOS-Compatible Clock Input

6.9.4.1.5 Auxiliary OSC1 Not Used

Figure 6-33 shows the recommended oscillator connections when OSC1 is not used. OSC1_XI must be connected to VSS through an external pull resistor (R pd) to ensure this input is held to a valid low level when unused since the internal pull-down resistor is disabled by default. Device OSC1_XOOSC1_XI Rpd PCB Ground NC Figure 6-33. OSC1 Not Used

6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source

Figure 6-34 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board (PCB) designs include the two optional resistors R bias and R d in case they are required for proper oscillator operation when combined with production crystal circuit components. In most cases, R bias is not required and Rd is a 0- Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator performance with production crystal circuit components installed on preproduction PCBs. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-26 summarizes the required electrical constraints. Table 6-26. WKUP_LFOSC0 Crystal Electrical Characteristics NAME DESCRIPTION MIN TYP MAX UNIT fp Parallel resonance crystal frequency 32768 Hz Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF Cshunt Shunt capacitance ESRxtal – 40 Ω 4 pF ESRxtal – 60 Ω 3 pF ESRxtal – 80 Ω 2 pF ESRxtal – 100 Ω 1 pF ESR Crystal effective series resistance 100 kΩ When selecting a crystal, the system design must consider the temperature and aging characteristics of a based on the worst case environment and expected life expectancy of the system. Table 6-27 details the switching characteristics of the oscillator and the requirements of the input clock. Table 6-27. WKUP_LFOSC0 Switching Characteristics – Crystal Mode NAME DESCRIPTION MIN TYP MAX UNIT fxtal Oscillation frequency 32768 Hz tsX Start-up time 96.5 ms VDDA_WKUP WKUP_LFOSC0_XO tsX Time Voltage VSS VDDA_WKUP (min.) VDD_WKUP (min.) VSS VDD_WKUP J7ES_LF_OSC_ST ARTUP_13 Figure 6-36. WKUP_LFOSC0 Start-up Time Figure 6-37 shows the recommended oscillator connections when WKUP_LFOSC0 is not used. WKUP_LFOSC0 may be a no-connect while the oscillator remains disabled since the internal pull-down resistor is enabled by default. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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WKUP_LFOSC0_XOWKUP_LFOSC0_XI NC NC Figure 6-37. WKUP_LFOSC0 Not Used

6.9.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

• MCU_CLKOUT0 – Reference clock output for Ethernet PHYs (50 MHz or 25 MHz)
• MCU_SYSCLKOUT0 – SYSCLK0 of WKUP_PLLCTRL0 is divided by 6 and then sent out of the device as a LVCMOS clock signal (MCU_SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
• MCU_OBSCLK0 – On the clock output MCU_OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug.
• SYSCLKOUT0 – SYSCLK0 from the MAIN_PLL controller is divided by 6 and then sent out of the device as a LVCMOS clock signal (SYSCLKOUT0). This signal can be used to test if the main chip clock is functioning or not.
• CLKOUT – Reference clock output
• OBSCLK[2:0] – On the clock output OBSCLK0, oscillators and PLLs clocks can be observed for tests and debug. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive power from the off-chip power-supply. There are total of three PLLs in the device in WKUP and MCU domains:

• MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0
• MCU_PLL1 (MCU PERIPHERAL PLL)
• MCU_PLL2 (MCU CPSW PLL) There are total of twenty PLLs in the device in MAIN domain:
• PLL0 (MAIN PLL) with PLLCTRL0
• PLL1 (PER0 PLL)
• PLL2 (PER1 PLL)
• PLL3 (CPSW9G PLL)
• PLL4 (AUDIO0 PLL)
• PLL5 (VIDEO PLL)
• PLL6 (GPU PLL)
• PLL7 (C7x PLL)
• PLL8 (ARM0 PLL)
• PLL12 (DDR PLL)
• PLL13 (C66 PLL)
• PLL14 (R5F PLL)
• PLL15 (AUDIO1 PLL)
• PLL16 (DSS PLL0)
• PLL17 (DSS PLL1)
• PLL18 (DSS PLL2)
• PLL19 (DSS PLL3)
• PLL23 (DSS PLL7)
• PLL24 (MLB PLL)
• PLL25 (VISION PLL) Note For more information, see:
• Device Configuration / Clocking / PLLs section in the device TRM.
• Peripherals / Display Subsystem Overview section in the device TRM. Note The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.

6.9.4.4 Module and Peripheral Clocks Frequencies

Section 6.9.5, Peripherals section documents the maximum frequency associated with the peripheral clocks of the device. For more details on the clocking structure of each module, reference Device Configurations chapter in the device TRM. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5 Peripherals

6.9.5.1 ATL

The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock using cycle stealing via software. Note For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM. Table 6-28 represents ATL timing conditions. Table 6-28. ATL Timing Conditions PARAMETER MODE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate External reference CLK 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance Internal reference CLK 1 10 pF switching characteristics for ATL.

6.9.5.1.1 ATL_PCLK Timing Requirements

NO. PARAMETER MODE MIN MAX UNIT D1 tc(pclk) Cycle time, ATL_PCLK External reference CLK 5 ns D2 tw(pclkL) Pulse Duration, ATL_PCLK low External reference CLK 0.45 × M (1) + 2.5 ns D3 tw(pclkH) Pulse Duration, ATL_PCLK high External reference CLK 0.45 × M (1) + 2.5 ns (1) M = ATL_CLK[x] period

6.9.5.1.2 ATL_AWS[x] Timing Requirements

NO. MODE MIN MAX UNIT D4 tc(aws) Cycle Time, ATL_AWSx External reference CLK 2 × M(1) ns D5 tw(awsL) Pulse Duration, ATL_AWSx low External reference CLK 0.45 × A(2) + 2.5 ns D6 tw(awsH) Pulse Duration, ATL_AWSx high External reference CLK 0.45 × A(2) + 2.5 ns (1) M = ATL_CLK[x] period (2) A = ATL_AWS[x] period (3) x = 0 to 3

6.9.5.1.3 ATL_BWS[x] Timing Requirements

NO. MODE MIN MAX UNIT D7 tc(bws) Cycle Time, ATL_BWSx External reference clock 2 × M(1) ns D8 tw(bwsL) Pulse Duration, ATL_BWS[x] low(3) External reference clock 0.45 × B(2) + 2.5 ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

NO. MODE MIN MAX UNIT D9 tw(bwsH) Pulse Duration, ATL_BWS[x] high(3) External reference clock 0.45 × B(2) + 2.5 ns (1) M = ATL_CLK[x] period (2) B = ATL_BWS[x] period (3) x = 0 to 3

6.9.5.1.4 ATCLK[x] Switching Characteristics

NO. PARAMETER MODE MIN MAX UNIT D10 tc(atclk) Cycle time, ATCLKx Internal reference CLK 20 ns D11 tw(atclkL) Pulse Duration, ATCLK[x] low(3) Internal reference D12 tw(atclkH) Pulse Duration, ATCLK[x] high(3) Internal reference (1) M = ATL_CLK[x] period (2) P = ATCLK[x] period (3) x = 0 to 3 A TCLK[x] D12 D11 D10 atl_01 Figure 6-38. ATCLK[x] Timing DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.2 VPFE

Table 6-29 represents VPFE timnig conditions. Table 6-29. VPFE Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1.3 2.64 V/ns PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces 50 ps Table 6-30, Figure 6-39, and Figure 6-40 represent timing requirements for VPFE0. Table 6-30. Timing Requirements for VPFE0 NO.(1) MIN MAX UNIT V1 tc(pclk) Cycle time, VPFE0_PCLK 6.06(1) ns V2 tw(pclkH) Pulse duration, VPFE0_PCLK high 0.45 × P(2) ns V3 tw(pclkL) Pulse duration, VPFE0_PCLK low 0.45 × P(2) ns V4 tsu(ctrlV-pclkV) Setup time, control signals (VPFE0_HD, VPFE0_VD, VPFE0_WEN, VPFE0_FIELD) valid before VPFE0_PCLK transition 2.12 ns V5 tsu(dataV-pclkV) Setup time, VPFE0_DATA[15:0] valid before VPFE0_PCLK transition 2.38 ns V6 th(pclkV-ctrlV/dataV) Hold time, control signals (VPFE0_HD, VPFE0_VD, VPFE0_WEN, VPFE0_FIELD) and VPFE0_DATA[15:0] valid after VPFE0_PCLK transition -0.05 ns (1) For maximum frequency of 165 MHz. (2) P = VPFE0_PCLK period. VPFE0_TIMING_01 VPFE0_PCLK V2 V1 V3 Figure 6-39. VPFE0 Clock Signal Requirement VPFE0_PCLK (Negative-edge clocking) VPFE0_HD, VPFE0_VD, VPFE0_WEN, VPFE0_FIELD V4 V6 VPFE0_PCLK (Positive-edge clocking) VPFE0_TIMING_02 V5 V6 VPFE0_DATA[15:0] Figure 6-40. VPFE0 Timing Requirements For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 207 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.5.3 CPSW2G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description.

6.9.5.3.1 CPSW2G MDIO Interface Timings

Table 6-31 represents CPSW2G timing conditions. Table 6-31. CPSW2G MDIO Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input signal slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF Table 6-32, Table 6-33, and Figure 6-41 present timing requirements for MDIO. Table 6-32. CPSW2G MDIO Timing Requirements NO. MIN MAX UNIT MDIO1 tsu(mdioV-mdcH) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns MDIO2 th(mdcH-mdioV) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 6-33. CPSW2G MDIO Switching Characteristics NO. PARAMETER MIN MAX UNIT MDIO3 tc(mdc) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(mdcH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(mdcL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(mdcL-mdioV) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -150 150 ns MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 6-41. CPSW2G MDIO Timing Requirements and Switching Characteristics Note x = 0 in MCU domain DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.3.2 CPSW2G RMII Timings

requirements, and switching characteristics for CPSW2G RMII. Table 6-34. CPSW2G RMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input signal slew rate VDDSHVx(1) = 1.8V 0.2 0.54 V/ns VDDSHVx(1) = 3.3V 0.8 1.2 V/ns OUTPUT CONDITIONS CL Output load capacitance 3 25 pF (1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information on IO power rail assinments. see Figure 6-42 NO. MIN MAX UNIT RMII1 tc(ref_clk) Cycle time, RMII[x]_REF_CLK 19.999 20.001 ns RMII2 tw(ref_clkH) Pulse Duration, RMII[x]_REF_CLK high 7 13 ns RMII3 tw(ref_clkL) Pulse Duration, RMII[x]_REF_CLK low 7 13 ns RMII[x]_REF_CLK RMII2 RMII3 RMII1 A. x = 1 in MCU domain. Figure 6-42. CPSW2G RMII[x]_REFCLK Timing Requirements – RMII Mode NO. MIN MAX UNIT RMII4 tsu(rxdV-ref_clkH) Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising edge 4 ns tsu(crs_dvV-ref_clkH) Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising edge 4 ns tsu(rx_erV-ref_clkH) Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising edge 4 ns RMII5 th(ref_clkH-rxdV) Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising edge 2 ns th(ref_clkH-crs_dvV) Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising edge 2 ns th(ref_clkH-rx_erV) Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge 2 ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

RMII[x]_ _REF CLK RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Figure 6-43. CPSW2G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII Mode see Figure 6-44 NO. PARAMETER MIN MAX UNIT RMII6 td(ref_clkH-txdV) Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TXD[1:0] valid 2 13 ns td(ref_clkH-tx_enV) Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TX_EN valid 2 13 ns RMII[x]_TXD[1:0], RMII[x]_TX_EN RMII6 RMII[x]_REF_CLK Figure 6-44. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode

6.9.5.3.3 CPSW2G RGMII Timings

operation. For more information, see Gigabit Ethernet MAC (MCU_CPSW0) section in Peripherals chapter in the device TRM. Table 6-35. CPSW2G RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2.64 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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NO. MODE MIN MAX UNIT RGMII1 tc(rxc) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(rxcH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(rxcL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns see Figure 6-45 NO. MODE MIN MAX UNIT RGMII4 tsu(rdV-rxcV) Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(rx_ctlV-rxcV) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII5 th(rxcV-rdV) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(rxcV-rx_ctlV) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII[x] RD 3_ [ :0] (B) RGMII[x] RX_CTL_ (B) RGMII[x] RXC_ (A) RGMII4 RXERRRXDV 2nd Half-byte1st Half-byte RGMII2 RGMII3 RGMII1 RGMII5 A. RGMII_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC. Figure 6-45. CPSW2G Receive Interface Timing, RGMII Operation Mbps, and 1000 Mbps. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

NO. PARAMETER MODE MIN MAX UNIT RGMII6 tc(txc) Cycle time, RGMII[x]_TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII7 tw(txcH) Pulse duration, RGMII[x]_TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII8 tw(txcL) Pulse duration, RGMII[x]_TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns see Figure 6-46 NO. PARAMETER MODE MIN MAX UNIT RGMII9 tosu(tdV-txcV) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns tosu(tx_ctlV-txcV) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns RGMII10 toh(tdV-txcV) Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns toh(tx_ctlV-txcV) Output hold time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL_ (B) RGMII9 1st Half-byte TXERRTXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 6-46. CPSW2G Transmit Interface Timing RGMII Mode

6.9.5.4 CPSW9G

For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-36 represents CPSW9G timing conditions. Table 6-36. CPSW9G Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input signal slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF

6.9.5.4.1 CPSW9G MDIO Interface Timings

Table 6-37, Table 6-38, and Figure 6-47 present timing requirements and switching characteristics for MDIO. Table 6-37. CPSW9G MDIO Timing Requirements NO. PARAMETER(1) MIN MAX UNIT MDIO1 tsu(mdioV-mdcH) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns MDIO2 th(mdcH-mdioV) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 6-38. CPSW9G MDIO Switching Characteristics NO. PARAMETER(1) MIN MAX UNIT MDIO3 tc(mdc) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(mdcH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(mdcL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(mdcL-mdioV) Delay time, MDIO[x]_MDC falling edge to MDIO[x]_MDIO valid -150 150 ns (1) x = 0 MDIO3 MDIO1 MDIO2 MDIO7 MDIO4 MDIO5 MDIO[x]_MDC MDIO[x]_MDIO (input) MDIO[x]_MDIO (output) CPSW2G_MDIO_TIMING_01 Figure 6-47. CPSW9G MDIO Diagrams Receive and Transmit

6.9.5.4.2 CPSW9G RMII Timings

RMII receive. Table 6-39. CPSW9G RMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate VDDSHVx(1) = 1.8V 0.108 0.54 V/ns VDDSHVx(1) = 3.3V 0.4 1.2 V/ns OUTPUT CONDITIONS www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-39. CPSW9G RMII Timing Conditions (continued) PARAMETER MIN MAX UNIT CL Output load capacitance 3 25 pF (1) x = 0 - 5, where x indicates the respective IO power rail. Refer to Pin Attributes for more information on IO power rail assinments. see Figure 6-48 NO. MIN TYP MAX UNIT RMII1 tc(ref_clk) Cycle time, RMII[x]_REF_CLK 19.999 20.001 ns RMII2 tw(ref_clkH) Pulse Duration, RMII[x]_REF_CLK high 7 13 ns RMII3 tw(ref_clkL) Pulse Duration, RMII[x]_REF_CLK low 7 13 ns RMII[x]_REF_CLK RMII2 RMII3 RMII1 Figure 6-48. RMII[x]_REF_CLK Timing Requirements – RMII Mode NO. PARAMETER DESCRIPTION MIN TYP MAX UNIT RMII4 tsu(rxdV-ref_clkH) Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK rising edge 4 ns tsu(crs_dvV-ref_clkH) Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK rising edge 4 ns tsu(rx_erV-ref_clkH) Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK rising edge 4 ns RMII5 th(ref_clkH-rxdV) Hold time, RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK rising edge 2 ns th(ref_clkH-crs_dvV) Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK rising edge 2 ns th(ref_clkH-rx_erV) Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK rising edge 2 ns RMII4 RMII5 RMII[x]_ _REF CLK RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Figure 6-49. CPSW9G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RXER Timing Requirements – RMII Mode DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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NO. PARAMETER MIN TYP MAX UNIT RMII6 td(ref_clkH-txdV) Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TXD[1:0] valid 2 13 ns td(ref_clkH-tx_enV) Delay time, RMII[x]_REF_CLK rising edge to RMII[x]_TX_EN valid 2 13 ns RMII[x]_TXD[1:0], RMII[x]_TX_EN RMII6 RMII[x]_REF_CLK Figure 6-50. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode

6.9.5.4.3 CPSW9G RGMII Timings

RGMII operation. For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM. Table 6-40. CPSW9G RGMII Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2.64 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 20 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL 50 ps RGMII[x]_TXC, RGMII[x]_TD[3:0], RGMII[x]_TX_CTL 50 ps NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT RGMII1 tc(rxc) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII2 tw(rxcH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns RGMII3 tw(rxcL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 215 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

NO. MODE MIN MAX UNIT RGMII4 tsu(rdV-rxcV) Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns tsu(rx_ctlV-rxcV) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII5 th(rxcV-rdV) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns th(rxcV-rx_ctlV) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC transition 10Mbps 1 ns 100Mbps 1 ns 1000Mbps 1 ns RGMII[x] RD 3_ [ :0] (B) RGMII[x] RX_CTL_ (B) RGMII[x] RXC_ (A) RGMII4 RXERRRXDV 2nd Half-byte1st Half-byte RGMII2 RGMII3 RGMII1 RGMII5 A. RGMII_RXC must be externally delayed relative to the data and control pins. B. Data and control information is received using both edges of the clocks. RGMII_RXD[3:0] carries data bits 3-0 on the rising edge of RGMII_RXC and data bits 7-4 on the falling edge of RGMII_RXC. Similarly, RGMII_RXCTL carries RXDV on rising edge of RGMII_RXC and RXERR on falling edge of RGMII_RXC. Figure 6-51. CPSW9G RGMII[x]_RXC, RGMII[x]_RD[3:0] and RGMII[x]_RCTL Timing Requirements – RGMII Mode for 10 Mbps, 100 Mbps, and 1000 Mbps. see Figure 6-52 NO. PARAMETER MODE MIN TYP MAX UNIT RGMII6 tc(txc) Cycle time, RGMII[x]_TXC 10Mbps 360 440 ns 100Mbps 36 44 ns 1000Mbps 7.2 8.8 ns RGMII7 tw(txcH) Pulse duration, RGMII[x]_TXC high 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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NO. PARAMETER MODE MIN TYP MAX UNIT RGMII8 tw(txcL) Pulse duration, RGMII[x]_TXC low 10Mbps 160 240 ns 100Mbps 16 24 ns 1000Mbps 3.6 4.4 ns see Figure 6-52 NO. PARAMETER MODE MIN MAX UNIT RGMII9 tosu(tdV-txcV) Output setup time, RGMII[x]_TD[3:0] valid to RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns tosu(tx_ctlV-txcV) Output setup time, RGMII[x]_TX_CTL valid to RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns RGMII1 toh(tdV-txcV) Output hold time, RGMII[x]_TD[3:0] valid after RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns toh(tx_ctlV-txcV) Output hold time, RGMII[x]_TX_CTL valid after RGMII[x]_TXC transition 10Mbps 1.2 ns 100Mbps 1.2 ns 1000Mbps 1.05 ns RGMII[x]_TXC (A) RGMII[x]_TD[3:0] (B) RGMII[x] TX_CTL_ (B) RGMII9 1st Half-byte TXERRTXEN 2nd Half-byte RGMII7 RGMII8 RGMII6 RGMII10 A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled. B. Data and control information is received using both edges of the clocks. RGMII_TD[3:0] carries data bits 3-0 on the rising edge of RGMII_TXC and data bits 7-4 on the falling edge of RGMII_TXC. Similarly, RGMII_TX_CTL carries TXDV on rising edge of RGMII_TXC and RTXERR on falling edge of RGMII_TXC. Figure 6-52. CPSW9G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics - RGMII Mode

6.9.5.5 CSI-2

For more information, see the Camera Streaming Interface Receiver (CSI_RX_IF) chapter in the device TRM. The CSI_RX_IF deals with the processing of the pixel data coming from an external image sensor and data from memory. It is a key component for the following multimedia applications: camera viewfinder, video record, and still image capture. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

The CSI_RX_IF has a primary serial interface (CSI-2 port) compliant with the MIPI D-PHY RX specification v1.2 and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock lane in synchronous mode, double data rate. Refer to the specification for timing details.

• 2.5 Gbps (1.25 GHz) for each lane.

6.9.5.6 DDRSS

For more details about features and additional description information on the device LPDDR4 Memory Interfaces, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices with the following features:

• 32-bit data path to external SDRAM memory
• Memory device capacity: Up to 8GB address space available over two chip selects (4GB per rank)
• No support for byte mode, or memories with more than 17 row address bits Table 6-41 and Figure 6-53 present switching characteristics for DDRSS. Table 6-41. Switching Characteristics for DDRSS NO. PARAMETER DDR TYPE MIN MAX UNIT 1 tc(DDR_CKP/DDR_CKN) Cycle time, DDR0_CKP and DDR0_CKN LPDDR4 0.536 3.003 ns DDR0_CKP DDR0_CKN Figure 6-53. DDRSS Memory Interface Clock Timing For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.

6.9.5.7 DSS

For more details about features and additional description information on the device Display Subsystem – Video Output Ports, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-42 represents DPI timing conditions. Table 6-42. DPI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1.44 26.4 V/ns OUTPUT CONDITIONS CL Output load capacitance 1.5 5 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps Table 6-43, Table 6-44, Figure 6-54 and Figure 6-55 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-43. DPI Video Output Switching Characteristics NO.(2) PARAMETER MIN MAX UNIT D1 tc(pclk) Cycle time, VOUT(x)_PCLK 6.06 ns DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-43. DPI Video Output Switching Characteristics (continued) NO.(2) PARAMETER MIN MAX UNIT D2 tw(pclkL) Pulse duration, VOUT(x)_PCLK low 0.475×P(1) ns D3 tw(pclkH) Pulse duration, VOUT(x)_PCLK high 0.475×P(1) ns D4 td(pclkV-dataV) Delay time, VOUT(x)_PCLK transition to VOUT(x)_DATA[23:0] transition -0.68 1.78 ns D5 td(pclkV-ctrlL) Delay time, VOUT(x)_PCLK transition to control signals VOUT(x)_VSYNC, VOUT(x)_HSYNC, VOUT(x)_DE falling edge -0.68 1.78 ns (1) P = output VOUT(x)_PCLK period in ns. (2) x in VOUT(x) = 1 or 2 VOUT(x)_PCLK VOUT(x)_VSYNC VOUT(x)_HSYNC VOUT(x)_DA T A[23:0] VOUT(x)_DE data_1 data_2 data_n DPI_TIMING_01 VOUT _PCLK(x) Falling-edge Clock Reference Rising-edge Clock Reference A. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock. B. The polarity and the pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS) section in Peripherals chapter in the device TRM. C. The VOUT(x)_PCLK frequency can be configured, refer to Display Subsystem section in Peripherals chapter in the device TRM. D. x in VOUT(x) = 1 or 2. Figure 6-54. DPI Video Output www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-44. DPI External Pixel Clock Timing Requirements NO.(2) MIN MAX UNIT D6 tc(extpclkin) Cycle time, VOUT(x)_EXTPCLKIN 6.06 ns D7 tw(extpclkinL) Pulse duration, VOUT(x)_EXTPCLKIN low 0.45×P (1) ns D8 tw(extpclkinH) Pulse duration, VOUT(x)_EXTPCLKIN high 0.45×P (1) ns (1) P = output VOUT(x)_PCLK period in ns. (2) x in VOUT(x) = 1 or 2 VOUT(x)_EXTPCLKIN DPI_TIMING_02 Falling-edge Clock Reference Rising-edge Clock Reference VOUT(x)_EXTPCLKIN Figure 6-55. DPI External Pixel Clock Input For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter in the device TRM. 6.9.5.8 eCAP The supported features by the device ECAP are:

• 32-bit time base counter
• 4-event time-stamp registers (each 32 bits)
• Independent edge polarity selection for up to four sequenced time-stamp capture events
• Interrupt capabilities on any of the four capture events
• Input capture signal pre-scaling (from 1 to 16)
• Support of different capture modes (single shot capture, continuous mode capture, absolute timestamp capture or difference mode time-stamp capture) Table 6-45 represents ECAP timing conditions. Table 6-45. ECAP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF and Figure 6-57). DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.8.1 Timing Requirements for eCAP

NO. PARAMETER DESCRIPTION MIN MAX UNIT CAP1 tw(cap) Pulse duration, CAP (asynchronous) 2 + 2P (1) ns (1) P = sysclk CAP CAP1 EPERIPHERALS_TIMNG_01 Figure 6-56. eCAP Input Timings

6.9.5.8.2 Switching Characteristics for eCAP

NO. PARAMETER DESCRIPTION MIN MAX UNIT CAP2 tw(apwm) Pulse duration, APWM -2 + 2P (1) ns (1) P = sysclk APWM CAP2 EPERIPHERALS_TIMNG_02 Figure 6-57. eCAP Output Timings For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.

6.9.5.9 EPWM

The supported features by the device EPWM are:

• Dedicated 16-bit time-base counter with period and frequency control
• Two independent PWM outputs which can be used in different configurations (with single-edge operation, with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation)
• Asynchronous override control of PWM signals during fault conditions
• Programmable phase-control support for lag or lead operation relative to other EPWM modules
• Dead-band generation with independent rising and falling edge delay control
• Programmable trip zone allocation of both latched and un-latched fault conditions
• Events enabling to trigger both CPU interrupts and start of ADC conversions Table 6-46 represents EPWM timing conditions. Table 6-46. EPWM Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF 6-59, Figure 6-60, Figure 6-61, and Figure 6-58). www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 221 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.5.9.1 Timing Requirements for eHRPWM

NO. PARAMETER DESCRIPTION MIN MAX UNIT PWM6 tw(synci) Pulse duration, EHRPWM_SYNCI 2 + 2P (1) ns PWM7 tw(tz) Pulse duration, EHRPWM_TZn_IN low 2 + 3P (1) ns (1) P = sysclk EHRPWM_TZn_IN PWM7 EPERIPHERALS_TIMNG_07 EHRPWM_SYNCI PWM6 Figure 6-58. ePWM_SYNCI and ePWM_TZn_IN Output Timings For more information, see Camera Subsystem section in Peripherals chapter in the device TRM.

6.9.5.9.2 Switching Characteristics for eHRPWM

NO. PARAMETER DESCRIPTION MIN MAX UNIT PWM1 tw(pwm) Pulse duration, EHRPWM_A/B, high or low P-3 (1) ns PWM2 tw(syncout) Pulse duration, EHRPWM_SYNCO P-3 (1) ns PWM3 td(tzL-pwmV) Delay time, EHRPWM_TZn_IN falling edge to EHRPWM_A/B valid 11 ns PWM4 td(tzL-pwmZ) Delay time, EHRPWM_TZn_IN falling edge to EHRPWM_A/B Hi-Z 11 ns DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-47. EQEP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 1 4 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 7 pF (see Figure 6-62).

6.9.5.10.1 Timing Requirements for eQEP

NO. MIN MAX UNIT QEP1 tw(qep) Pulse duration, QEP_A/B 2 + 2P(1) ns QEP2 tw(qepiH) Pulse duration, QEP_I high 2 + 2P(1) ns QEP3 tw(qepiL) Pulse duration, QEP_I low 2 + 2P(1) ns QEP4 tw(qepsH) Pulse duration, QEP_S high 2 + 2P(1) ns QEP5 tw(qepsL) Pulse duration, QEP_S low 2 + 2P(1) ns (1) P = sysclk QEP_S QEP4 EPERIPHERALS_TIMNG_03 QEP_I QEP2 QEP_A/B QEP1 QEP3 QEP5 Figure 6-62. eQEP Input Timings

6.9.5.10.2 Switching Characteristics for eQEP

NO. PARAMETER MIN MAX UNIT QEP6 td(QEP-CNTR) Delay time, external clock to counter increment 24 ns For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter in the device TRM.

6.9.5.11 GPIO

The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.

• Group one: WKUP_GPIO0 and WKUP_GPIO1
• Group two: GPIO0, GPIO2, GPIO4, and GPIO6
• Group three: GPIO1, GPIO3, GPIO5, and GPIO7 Within each group, exactly one module is selected to control the corresponding I/O pins and pin interrupts. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1), GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general purpose interface supports up to 248 I/O pins. For more details about features and additional description information on the device General-Purpose Interface, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Note The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi. Table 6-48 represents GPIO timing conditions. Table 6-48. GPIO Timing Conditions PARAMETER BUFFER TYPE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate LVCMOS LVCMOS I2C OD FS I2C OD FS OUTPUT CONDITIONS CL Output load capacitance LVCMOS 3 10 pF I2C OD FS 3 100 pF (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see POWER column of the Pin Attributes table.

6.9.5.11.1 GPIO Timing Requirements

NO. PARAMETER DESCRIPTION MIN MAX UNIT GPIO1 tw(GPIO_IN) Pulse width, GPIOn_x 2P + 30(1) ns (1) P = functional clock period in ns.

6.9.5.11.2 GPIO Switching Characteristics

NO. PARAMETER DESCRIPTION BUFFER TYPE MIN MAX UNIT GPIO2 tw(GPIO_OUT) Pulse width, GPIOn_x LVCMOS 0.975P(1) - 3.6 ns I2C OD FS 160 ns (1) P = functional clock period in ns. For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

6.9.5.12 GPMC

For more details about features and additional description information on the device General-Purpose Memory Controller, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-49 represents GPMC timing conditions. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 225 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

The IO timings provided in this section are applicable for all combinations of signals for GPMC0. However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs Table 6-49. GPMC Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT Input Conditions tSR Input slew rate 1.65 4 V/ns Output Conditions CLOAD Output load capacitance 5 20 pF

6.9.5.12.1 GPMC and NOR Flash — Synchronous Mode

electrical characteristic conditions below (see Figure 6-63 through Figure 6-67). NO. PARAMETER DESCRIPTION (2) MODE (3) MIN MAX MIN MAX UNIT

100 MHz

(4)

133 MHz

(4) F12 tsu(dV-clkH) Setup time, input data GPMC_AD[15:0] valid before output clock GPMC_CLK high div_by_1_mode; 1.81 1.11 ns not_div_by_1_mode; 1.06 ns F13 th(clkH-dV) Hold time, input data GPMC_AD[15:0] valid after output clock GPMC_CLK high div_by_1_mode; 1.78 2.28 ns not_div_by_1_mode; 1.78 ns F21 tsu(waitV-clkH) Setup time, input wait GPMC_WAIT[j] valid before output clock GPMC_CLK high (1) div_by_1_mode; 1.81 1.11 ns not_div_by_1_mode; 1.06 ns F22 th(clkH-waitV) Hold time, input wait GPMC_WAIT[j] valid after output clock GPMC_CLK high (1) div_by_1_mode; 1.78 2.28 ns not_div_by_1_mode; 1.78 ns (1) In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. (2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General- Purpose Memory Controller (GPMC) section in the device TRM. (3) For div_by_1_mode:

• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h: – GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4) (4) For 100 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3 For 133 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT NO.(2) PARAMETER DESCRIPTION MODE(19) MIN MAX MIN MAX UNI T100 MHz(20) 133 MHz(20) F0 tc(clk) Period, output clock GPMC_CLK(18) div_by_1_mode; 10 7.52 ns F1 tw(clkH) Typical pulse duration, output clock GPMC_CLK high div_by_1_mode 0.475*P (15)- 0.3 0.475*P (15)- 0.3 ns DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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NO.(2) PARAMETER DESCRIPTION MODE(19) MIN MAX MIN MAX UNI T100 MHz(20) 133 MHz(20) F1 tw(clkL) Typical pulse duration, output clock GPMC_CLK low div_by_1_mode 0.475*P (15)- 0.3 0.475*P (15)- 0.3 ns F2 td(clkH-csnV) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] transition(14) div_by_1_mode no extra_delay F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK rising edge to output chip select GPMC_CSn[i] invalid(14) div_by_1_mode no extra_delay (5)+3.75 ns F4 td(aV-clk) Delay time, output address GPMC_A[27:1] valid to output clock GPMC_CLK first edge div_by_1_mode B(2)-2.3 B(2)+4.5 B(2)-2.3 B(2)+4.5 ns F5 td(clkH-aIV) Delay time, output clock GPMC_CLK rising edge to output address GPMC_A[27:1] invalid div_by_1_mode; -2.3 4.5 -2.3 4.5 ns F6 td(be[x]nV-clk) Delay time, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n valid to output clock GPMC_CLK first edge div_by_1_mode B(2)-2.3 B(2)+1.9 B(2)-2.3 B(2)+1.9 ns F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n invalid(11) div_by_1_mode D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) div_by_1_mode D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(13) div_by_1_mode D(4)-2.3 D(4)+1.9 D(4)-2.3 D(4)+1.9 ns F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition div_by_1_mode no extra_delay F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode; no extra_delay F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition div_by_1_mode no extra_delay F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid div_by_1_mode no extra_delay F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition div_by_1_mode no extra_delay F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(11) div_by_1_mode J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) div_by_1_mode J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns F15 td(clkL-do). Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(13) div_by_1_mode J(10)-2.3 J(10)+2.7 J(10)-2.3 J(10)+2.7 ns F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(11) div_by_1_mode J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) div_by_1_mode J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 227 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

NO.(2) PARAMETER DESCRIPTION MODE(19) MIN MAX MIN MAX UNI T100 MHz(20) 133 MHz(20) F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(13) div_by_1_mode J(10)-2.3 J(10)+1.9 J(10)-2.3 J(10)+1.9 ns F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[i] low(14) Read A(1) A(1) ns Write A(1) A(1) ns F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C(3) C(3) ns Write C(3) C(3) ns F20 tw(advnV) Pulse duration, output address valid and address latch enable GPMC_ADVn_ALE low Read K(16) K(16) ns Write K(16) K(16) ns (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) With n being the page burst access number. (2) B = ClkActivationTime × GPMC_FCLK(17) (3) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) With n being the page burst access number. (4) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (5) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (6) For csn falling edge (CS activated):

• Case GPMCFCLKDIVIDER = 0: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – F = 0.5 × CSExtraDelay × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime) is a multiple of 3) – F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3) – F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(17) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3) (7) For ADV falling edge (ADV activated):
• Case GPMCFCLKDIVIDER = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode:
• Case GPMCFCLKDIVIDER = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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– G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise

• Case GPMCFCLKDIVIDER = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Writing mode:
• Case GPMCFCLKDIVIDER = 0: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – G = 0.5 × ADVExtraDelay × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3) – G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3) – G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(17) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3) (8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
• Case GPMCFCLKDIVIDER = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3) For OE rising edge (OE deactivated):
• Case GPMCFCLKDIVIDER = 0: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – H = 0.5 × OEExtraDelay × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime) is a multiple of 3) – H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3) – H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(17) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3) (9) For WE falling edge (WE activated):
• Case GPMCFCLKDIVIDER = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17)
• Case GPMCFCLKDIVIDER = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3) For WE rising edge (WE deactivated): www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 229 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

• Case GPMCFCLKDIVIDER = 0: – I = 0.5 × WEExtraDelay × GPMC_FCLK (17)
• Case GPMCFCLKDIVIDER = 1: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) otherwise
• Case GPMCFCLKDIVIDER = 2: – I = 0.5 × WEExtraDelay × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime) is a multiple of 3) – I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3) – I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(17) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3) (10) J = GPMC_FCLK(17) (11) First transfer only for CLK DIV 1 mode. (12) Half cycle; for all data after initial transfer for CLK DIV 1 mode. (13) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK. (14) In GPMC_CSn[i], i is equal to 0, 1, 2, or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. (15) P = GPMC_CLK period in ns (16) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(17) (17) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (18) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER. (19) For div_by_1_mode:
• GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency For no extra_delay:
• GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
• GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
• GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
• GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed (20) For 100 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3 For 133 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address D 0 F12 F13 F11 F19 F18 F20 F10 F19 F12 F12 GPMC_01 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. Figure 6-63. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0) www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 231 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

GPMC_CLK GPMC_CSn[i] GPMCA[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address D 0 D 1 D 2 F12 F13 F13 F12 F8 F8 F9 F10 F11 F21 F21 D 3 GPMC_02 F22F22 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. Figure 6-64. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0) GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[j] D 0 D 1 D 2 D 3 F15 F15 F15 F8F8 F14F14 F17 F17 F17 F9F6 F17 F17 F17 Valid Address GPMC_03 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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GPMC_CLK GPMC_CSn[i] GPMC_A[27:17] GPMC_BE1n BPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_WEn GPMC_WAIT[j] Address (LSB) D 0 D 1 D 2 D 3 F15 F15 F15 F8F8 F17 F17 F17 F6 F17 F17 F17 F18 F20 F21 F21 GPMC_AD[15:0] F14 GPMC_05 F22 F22 Address (MSB) F14 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. B. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. Figure 6-67. GPMC and Multiplexed NOR Flash — Synchronous Burst Write

6.9.5.12.2 GPMC and NOR Flash — Asynchronous Mode

electrical characteristic conditions below (see Figure 6-68 through Figure 6-73). NO. MODE(7) MIN MAX UNIT FA5(1) tacc(d) Data access time div_by_1_mode H(5) ns FA20(2) tacc1-pgmode(d) Page mode successive data access time div_by_1_mode P(4) ns FA21(3) tacc2-pgmode(d) Page mode first data access time div_by_1_mode H(5) ns (1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. (2) The FA20 prameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. (3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field. (4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6) (6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (7) For div_by_1_mode:

• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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NO. PARAMETER DESCRIPTION MODE (15) MIN MAX UNIT (16) FA0 tw(be[x]nV) Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time Read N(12) ns Write N(12) FA1 tw(csnV) Pulse duration, output chip select GPMC_CSni low Read A(1) ns Write A(1) FA3 td(csnV-advnIV) Delay time, output chip select GPMC_CSni valid to output address valid and address latch enable GPMC_ADVn_ALE invalid Read B(2)-2.55 B(2)+2.65 ns Write B(2)-2.55 B(2)+2.65 FA4 td(csnV-oenIV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn invalid (Single read) div_by_1_mode; ns FA9 td(aV-csnV) Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSni valid div_by_1_mode; J(9)-2.55 J(9)+2.65 ns FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSni valid div_by_1_mode; ns FA12 td(csnV-advnV) Delay time, output chip select GPMC_CSni valid to output address valid and address latch enable GPMC_ADVn_ALE valid div_by_1_mode; K(10)-2.55 K (10)+2.65 ns FA13 td(csnV-oenV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn valid div_by_1_mode; L(11)-2.55 L(11)+2.65 ns FA16 tw(aIV) Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses div_by_1_mode; G(7) ns FA18 td(csnV-oenIV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn invalid (Burst read) div_by_1_mode; ns FA20 tw(aV) Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses div_by_1_mode; D(4) ns FA25 td(csnV-wenV) Delay time, output chip select GPMC_CSni valid to output write enable GPMC_WEn valid div_by_1_mode; E(5)-2.55 E(5)+2.65 ns FA27 td(csnV-wenIV) Delay time, output chip select GPMC_CSni valid to output write enable GPMC_WEn invalid div_by_1_mode; F(6)-2.55 F(6)+2.65 ns FA28 td(wenV-dV) Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid div_by_1_mode; 2.65 ns FA29 td(dV-csnV) Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSni valid div_by_1_mode; J(9)-2.55 J(9)+2.65 ns FA37 td(oenV-aIV) Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end div_by_1_mode; 2.65 ns (1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) with n being the page burst access number (2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) (5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (7) G = Cycle2CycleDelay × GPMC_FCLK(14) www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 235 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14) (10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) (13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (15) For div_by_1_mode:

• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency (16) For 133 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address Valid Valid Data IN 0 Data IN 0 FA0 FA9 FA10 FA3 FA1 FA4 FA12 FA13 FA0 FA10 FA5 GPMC_06 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-68. GPMC and NOR Flash — Asynchronous Read — Single Word DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADCn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Address 0 Address 1 Valid Valid Valid Valid Data Upper FA9 FA10 FA3 FA9 FA3 FA13 FA13 FA1 FA1 FA4 FA4 FA12 FA12 FA10 FA0 FA0 FA16 FA0 FA0 FA10 FA10 FA5 FA5 GPMC_07 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-69. GPMC and NOR Flash — Asynchronous Read — 32–Bit www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 237 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_AD[15:0] GPMC_WAIT[j] Add0 Add1 Add2 Add3 Add4 D0 D1 D2 D3 D3 FA1 FA0 FA18 FA13 FA12 FA0 FA9 FA10 FA10 FA21 FA20 FA20FA20 GPMC_08 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field. C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bits field. D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-70. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[MSB:1] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[j] Valid Address Data OUT FA0 FA1 FA10 FA3 FA25 FA29 FA9 FA12 FA27 FA0 FA10 GPMC_09 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. Figure 6-71. GPMC and NOR Flash — Asynchronous Write — Single Word www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 239 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WAIT[j] Address (MSB) Valid Valid Address (LSB) Data IN Data IN FA0 FA9 FA10 FA3 FA13 FA29 FA1 FA37 FA12 FA4 FA10 FA0 FA5 GPMC_A[27:17] GPMC_AD[15:0] GPMC_10 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field. C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. Figure 6-72. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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GPMC_FCLK GPMC_CLK GPMC_CSn[i] GPMC_A[27:17] GPMC_BE0n_CLE GPMC_BE1n GPMC_ADVn_ALE GPMC_WEn GPMC_AD[15:0] GPMC_WAIT[j] Address (MSB) Valid Address (LSB) Data OUT FA0 FA1 FA9 FA10 FA3 FA25 FA29 FA12 FA27 FA28 FA0 FA10 GPMC_11 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. Figure 6-73. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 241 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.5.12.3 GPMC and NAND Flash — Asynchronous Mode

electrical characteristic conditions below (see Figure 6-74 through Figure 6-77). NO. MODE(4) MIN MAX UNIT

133 MHz(5)

GNF12(1) tacc(d) Access time, input data GPMC_AD15:0 div_by_1_mode; J(2) ns (1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3) (3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (4) For div_by_1_mode:

• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency (5) For 133 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT NO. PARAMETER MODE (15) MIN MAX UNIT

(16) GNF0 tw(wenV) Pulse duration, output write enable GPMC_WEn valid div_by_1_mode; A(1) ns GNF1 td(csnV-wenV) Delay time, output chip select GPMC_CSni valid to output write enable GPMC_WEn valid div_by_1_mode; B(2)-2.55 B(2)+2.65 ns GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE high to output write enable GPMC_WEn valid div_by_1_mode; C(3)-2.55 C(3)+2.65 ns GNF3 tw(wenV-dV) Delay time, output data GPMC_AD[15:0] valid to output write enable GPMC_WEn valid div_by_1_mode; D(4)-2.55 D(4)+2.65 ns GNF4 tw(wenIV-dIV) Delay time, output write enable GPMC_WEn invalid to output data GPMC_AD[15:0] invalid div_by_1_mode; E(5)-2.55 E(5)+2.65 ns GNF5 tw(wenIV-cleIV) Delay time, output write enable GPMC_WEn invalid to output lower-byte enable and command latch enable GPMC_BE0n_CLE invalid div_by_1_mode; F(6)-2.55 F(6)+2.65 ns GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn invalid to output chip select GPMC_CSni invalid div_by_1_mode; G(7)-2.55 G(7)+2.65 ns GNF7 tw(aleH-wenV) Delay time, output address valid and address latch enable GPMC_ADVn_ALE high to output write enable GPMC_WEn valid div_by_1_mode; C(3)-2.55 C(3)+2.65 ns GNF8 tw(wenIV-aleIV) Delay time, output write enable GPMC_WEn invalid to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode; F(6)-2.55 F(6)+2.65 ns GNF9 tc(wen) Cycle time, write div_by_1_mode; H(8) ns GNF10 td(csnV-oenV) Delay time, output chip select GPMC_CSni valid to output enable GPMC_OEn_REn valid div_by_1_mode; I(9)-2.55 I(9)+2.65 ns GNF13 tw(oenV) Pulse duration, output enable GPMC_OEn_REn valid div_by_1_mode; K(10) ns GNF14 tc(oen) Cycle time, read div_by_1_mode; L(11) ns GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn invalid to output chip select GPMC_CSni invalid div_by_1_mode; M(12)-2.55 M (12)+2.65 ns (1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14) DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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(2) B = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (3) C = ((WEOnTime - ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - ADVExtraDelay)) × GPMC_FCLK(14) (4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay) × GPMC_FCLK(14) (5) E = ((WrCycleTime - WEOffTime) × (TimeParaGranularity + 1) - 0.5 × WEExtraDelay) × GPMC_FCLK(14) (6) F = ((ADVWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (7) G = ((CSWrOffTime - WEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - WEExtraDelay)) × GPMC_FCLK(14) (8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) (9) I = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14) (10) K = (OEOffTime - OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK(14) (11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK(14) (12) M = ((CSRdOffTime - OEOffTime) × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay - OEExtraDelay)) × GPMC_FCLK(14) (13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. (14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns. (15) For div_by_1_mode:

• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h: – GPMC_CLK frequency = GPMC_FCLK frequency (16) For 133 MHz:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT GPMC_FCLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADCn_ALE GPMC_OEn_REn GPMC_WEn GPMC_AD[15:0] Command GNF0 GNF1 GNF2 GNF3 GNF4 GNF5 GNF6 GPMC_12 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. Figure 6-74. GPMC and NAND Flash — Command Latch Cycle www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 243 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

GPMC_FCLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WEn GPMC_AD[15:0] Address GNF0 GNF1 GNF7 GNF3 GNF4 GNF6 GNF8 GNF9 GPMC_13 A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. Figure 6-75. GPMC and NAND Flash — Address Latch Cycle GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_FCLK GPMC_WAIT[j] GNF10 GNF14 GNF15 GNF12 GNF13 DA T AGPMC_AD[15:0] GPMC_14 A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional clock edge. GNF12 value must be stored inside AccessTime register bits field. B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0, 1, 2, or 3. Figure 6-76. GPMC and NAND Flash — Data Read Cycle DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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GPMC_FCLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WEn DA T A GNF0 GNF1 GNF4 GNF9 GNF3 GNF6 GPMC_AD[15:0] GPMC_15 A. \`In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. Figure 6-77. GPMC and NAND Flash — Data Write Cycle For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in the device TRM.

6.9.5.12.4 GPMC0 IOSET

Table 6-50 present the specific groupings of signals (IOSET) for use with GPMC0. Table 6-50. GPMC0 IOSET Signals IOSET1 IOSET2 BALL NAME MUX BALL NAME MUX GPMC0_WAIT2 MDIO0_MDC 8 MDIO0_MDC 8 GPMC0_BE1n PRG1_PRU0_GPO0 8 RGMII6_RD1 8 GPMC0_WAIT0 PRG1_PRU0_GPO1 8 PRG1_PRU0_GPO1 8 GPMC0_WAIT1 PRG1_PRU0_GPO2 8 PRG1_PRU0_GPO2 8 GPMC0_DIR PRG1_PRU0_GPO3 8 PRG1_PRU0_GPO3 8 GPMC0_CSn2 PRG1_PRU0_GPO4 8 PRG1_PRU0_GPO4 8 GPMC0_WEn PRG1_PRU0_GPO5 8 PRG1_PRU0_GPO5 8 GPMC0_CSn3 PRG1_PRU0_GPO6 8 PRG1_PRU0_GPO6 8 GPMC0_OEn_REn PRG1_PRU0_GPO8 8 PRG1_PRU0_GPO8 8 GPMC0_ADVn_ALE PRG1_PRU0_GPO9 8 PRG1_PRU0_GPO9 8 GPMC0_BE0n_CLE PRG1_PRU0_GPO10 8 PRG1_PRU0_GPO10 8 GPMC0_WPn PRG1_PRU1_GPO5 8 PRG1_PRU1_GPO5 8 GPMC0_CSn1 PRG1_PRU1_GPO8 8 PRG1_PRU1_GPO8 8 GPMC0_CSn0 PRG1_PRU1_GPO9 8 PRG1_PRU1_GPO9 8 GPMC0_CLKOUT PRG1_PRU1_GPO10 8 PRG1_PRU1_GPO10 8 GPMC0_AD0 PRG0_PRU0_GPO5 8 PRG0_PRU0_GPO5 8 GPMC0_AD1 PRG0_PRU0_GPO7 8 PRG0_PRU0_GPO7 8 GPMC0_AD2 PRG0_PRU0_GPO8 8 PRG0_PRU0_GPO8 8 GPMC0_AD3 PRG0_PRU0_GPO9 8 PRG0_PRU0_GPO9 8 GPMC0_AD4 PRG0_PRU0_GPO10 8 PRG0_PRU0_GPO10 8 GPMC0_AD5 PRG0_PRU0_GPO17 8 PRG0_PRU0_GPO17 8 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 245 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-50. GPMC0 IOSET (continued) Signals IOSET1 IOSET2 BALL NAME MUX BALL NAME MUX GPMC0_AD6 PRG0_PRU0_GPO18 8 PRG0_PRU0_GPO18 8 GPMC0_AD7 PRG0_PRU0_GPO19 8 PRG0_PRU0_GPO19 8 GPMC0_AD8 PRG0_PRU1_GPO5 8 PRG0_PRU1_GPO5 8 GPMC0_AD9 PRG0_PRU1_GPO7 8 PRG0_PRU1_GPO7 8 GPMC0_AD10 PRG0_PRU1_GPO8 8 PRG0_PRU1_GPO8 8 GPMC0_AD11 PRG0_PRU1_GPO9 8 PRG0_PRU1_GPO9 8 GPMC0_AD12 PRG0_PRU1_GPO10 8 PRG0_PRU1_GPO10 8 GPMC0_AD13 PRG0_PRU1_GPO17 8 PRG0_PRU1_GPO17 8 GPMC0_AD14 PRG0_PRU1_GPO18 8 PRG0_PRU1_GPO18 8 GPMC0_AD15 PRG0_PRU1_GPO19 8 PRG0_PRU1_GPO19 8 GPMC0_A0 PRG0_MDIO0_MDC 8 PRG0_MDIO0_MDC 8 GPMC0_A1 RGMII5_TX_CTL 8 RGMII5_TX_CTL 8 GPMC0_A2 RGMII5_RX_CTL 8 RGMII5_RX_CTL 8 GPMC0_A3 RGMII5_TD3 8 RGMII5_TD3 8 GPMC0_A4 RGMII5_TD2 8 RGMII5_TD2 8 GPMC0_A5 RGMII5_TD1 8 RGMII5_TD1 8 GPMC0_A6 RGMII5_TD0 8 RGMII5_TD0 8 GPMC0_A7 RGMII5_TXC 8 RGMII5_TXC 8 GPMC0_A8 RGMII5_RXC 8 RGMII5_RXC 8 GPMC0_A9 RGMII5_RD3 8 RGMII5_RD3 8 GPMC0_A10 RGMII5_RD2 8 RGMII5_RD2 8 GPMC0_A11 RGMII5_RD1 8 RGMII5_RD1 8 GPMC0_A12 RGMII5_RD0 8 RGMII5_RD0 8 GPMC0_A13 RGMII6_TX_CTL 8 RGMII6_TX_CTL 8 GPMC0_A14 RGMII6_RX_CTL 8 RGMII6_RX_CTL 8 GPMC0_A15 RGMII6_TD3 8 RGMII6_TD3 8 GPMC0_A16 RGMII6_TD2 8 RGMII6_TD2 8 GPMC0_A17 RGMII6_TD1 8 RGMII6_TD1 8 GPMC0_A18 RGMII6_TD0 8 RGMII6_TD0 8 GPMC0_A19 RGMII6_TXC 8 RGMII6_TXC 8 GPMC0_A20 RGMII6_RXC 8 RGMII6_RXC 8 GPMC0_A21 RGMII6_RD3 8 RGMII6_RD3 8 GPMC0_A22 RGMII6_RD2 8 RGMII6_RD2 8 GPMC0_A23 PRG0_PRU1_GPO2 8 PRG0_PRU1_GPO2 8 GPMC0_A24 PRG0_PRU1_GPO4 8 PRG0_PRU1_GPO4 8 GPMC0_A25 PRG0_PRU1_GPO6 8 PRG0_PRU1_GPO6 8 GPMC0_A26 PRG0_PRU1_GPO11 8 PRG0_PRU1_GPO11 8 GPMC0_A27 PRG0_MDIO0_MDIO 8 PRG0_MDIO0_MDIO 8 GPMC0_WAIT3 MDIO0_MDIO 8 MDIO0_MDIO 8

6.9.5.13 HyperBus

For more details about features and additional description information on the device HyperBus, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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conditions and electrical characteristic conditions (see Figure 6-78, Figure 6-79, and Figure 6-80). Table 6-51 represents HyperBus timing conditions. Table 6-51. HyperBus Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1.5 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch between traces CK and CKn; RWDS and DQ[7:0] 10 ps CK/CKn and RWDS; CK/CKn and CSn 200 ps CK/CKn and DQ[7:0] 35 ps RESETn and CSn[1:0] 340 ps

6.9.5.13.1 Timing Requirements for HyperBus

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT D1 tw(resetnL) Pulse duration, HYPERBUS0_RESETn low 200 ns D2 tw(csnL) Pulse duration, HYPERBUS0_CSn[1:0] low 1000 ns D3 td(resetnH-csnL) Delay time, HYPERBUS0_RESETn rising edge to HYPERBUS0_CSn[1:0] falling edge 200.34 ns td(csnL-rwdsL) Delay time, HYPERBUS0_CSn[1:0] falling edge to HYPERBUS0_RWDS falling edge

166 MHz 186 ns

100 MHz 182 ns

D5 tskn(rwdsV-dV) Input skew, HYPERBUS0_RWDS transition to HYPERBUS0_DQ[7:0] valid 166 MHz -0.46 0.46 ns LFD5 100 MHz -0.81 0.81 ns

6.9.5.13.2 HyperBus 166 MHz Switching Characteristics

NO. PARAMETER DESCRIPTION MIN MAX UNIT D6 tc(ck/ckn) Cycle time, HYPERBUS0_CK/CKn 6 ns D7 tw(ck/ckn) Pulse duration, HYPERBUS0_CK/CKn high or low 2.85 ns D8 tw(csnH) Pulse duration, HYPERBUS0_CSn[1:0] invalid between operations 6 ns D9 td(csnL-ckH/cknL) Delay time, HYPERBUS0_CSn[1:0] falling edge to first HYPERBUS0_CK rising (HYPERBUS0_CKn falling) edge -3.28 ns D10 td(ckL/cknH-csnH) Delay time, last falling HYPERBUS0_CK (rising HYPERBUS0_Ckn) edge to HYPERBUS0_CSn[1:0] rising 0.28 ns D11 td(ckV/cknV-rwdsV) Delay time, HYPERBUS0_CK/CKn transition to HYPERBUS0_RWDS valid 0.68 2.14 ns D12 td(ckV-dV) Delay time, HYPERBUS0_CK/CKn transition to HYPERBUS0_DQ[7:0] valid 0.71 2.3 ns

6.9.5.13.3 HyperBus 100 MHz Switching Characteristics

NO. PARAMETER DESCRIPTION MIN MAX UNIT LFD6 tc(ck/ckn) Cycle time, HYPERBUS0_CK/CKn 10 ns LFD7 tw(ck/ckn) Pulse duration, HYPERBUS0_CK/CKn high or low 4.88 ns LFD8 tw(csnH) Pulse duration, HYPERBUS0_CSn[1:0] invalid between operations 10 ns LFD9 td(csnL-ckH/cknL) Delay time, HYPERBUS0_CSn[1:0] falling edge to first HYPERBUS0_CK rising (HYPERBUS0_CKn falling) edge -3.33 ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 247 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

NO. PARAMETER DESCRIPTION MIN MAX UNIT LFD10 td(ckL/cknH-csnH) Delay time, last falling HYPERBUS0_CK (rising HYPERBUS0_Ckn) edge to HYPERBUS0_CSn[1:0] rising 0.33 ns LFD11 td(ckV/cknV-rwdsV) Delay time, HYPERBUS0_CK/CKn transition to HYPERBUS0_RWDS valid 1.13 3.68 ns LFD12 td(ckV/cknV-dV) Delay time, HYPERBUS0_CK/CKn transition to HYPERBUS0_DQ[7:0] valid 1.16 3.84 ns HYPERBUS_TIMING_01 CK, CKn D8/LFD8 D2 RWDS DQ[7:0] D9/LFD9 Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:047:40 Dn Dn Dn+1 Dn+1 A B A B D6/LFD6 D7/LFD7 D11/LFD11 D10/LFD10 D12/LFD12 D12/LFD12 CSn Figure 6-78. HyperBus Timing Diagrams – Transmitter Mode HYPERBUS_TIMING_02 RWDS DQ[7:0] Command-Address Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS 39:32 31:24 23:16 15:8 7:047:40 Dn Dn Dn+1 Dn+1 A B A B CK, CKn D8/LFD8 D2 D9/LFD9 D6/LFD6 D7/LFD7 D10/LFD10 D12/LFD12 D5/LFD5 D5/LFD5 CSn Figure 6-79. HyperBus Timing Diagrams – Receiver Mode RESETn HYPERBUS_TIMING_03 CSn Figure 6-80. HyperBus Timing Diagrams – Reset For more information, see HyperBus Interface section in Peripherals chapter in the device TRM. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.14 I2C

The Inter-IC module is compliant with the Philips I2C Bus Specification, revision 2.1. Refer to the specification for timing details for all but rise/fall time parameters. Philips I2C specification rise/fall timings apply only to MCU_I2C0, WKUP_I2C0, and I2C[0-1]. All other instances of I2C use standard LVCMOS buffers to emulate open-drain buffers, and their rise/fall times should be referenced using the device IBIS model. For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 249 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.5.15 I3C

For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-52, Table 6-53 , Table 6-54, Figure 6-81, Table 6-56, Figure 6-82, and Figure 6-83 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-52. I3C Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.2276 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 50 pF Table 6-53. I3C Open Drain Timing Requirements see Figure 6-81 NO. MODE MIN MAX UNIT OD4 tsu(sdaV-sclH) Setup time, SDA valid before SCL rising edge Master 3 ns Table 6-54. I3C Open Drain Switching Characteristics see Figure 6-81 NO. PARAMETER MODE MIN MAX UNIT OD1 tw(sclL_od) Pulse duration, SCL low Master 200 ns tw(sclL_od_dig) tw(sclL_od) + tf(sda_od), min ns OD2 tw(sclH_od) Pulse duration, SCL high Master 41 ns tw(sclH_od_dig) tw(sclH_od) + tf(scl) ns OD3 tf(sda_od) Fall time, SDA Master tf(scl) 12 ns OD5 td(sclL-START) Delay time, SCL low after START (S) condition Master, ENTAS0 38.4 1000 ns Master, ENTAS1 38.4 100000 ns Master, ENTAS2 38.4 2000000 ns Master, ENTAS3 38.4 50000000 ns OD6 td(sclH-STOP) Delay time, SCL high before STOP (P) condition Master td(sclV), min / 2 ns OD7 tw(mmoverlap) Pulse duration, current master to secondary master overlap time during handoff Master tw(sclL_od_dig) ns OD8 tw(aval) Pulse duration, Bus Available condition Master 1000 ns OD9 tw(idle) Pulse duration, Bus Idle condition Master 1000000 ns OD10 tw(mmlock) Pulse duration, new master not driving SDA low Master tw(aval) ns DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.16 MCAN

For more details about features and additional description information on the device Controller Area Network Interface, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Note The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names, where n represents the specific MCAN module. Table 6-57. MCAN Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 15 V/ns OUTPUT CONDITIONS CL Output load capacitance 5 20 pF Table 6-58. MCAN Switching Characteristics NO. PARAMETER MIN MAX UNIT M1 td(MCAN_TX) Delay time, transmit shift register to MCANn_TX pin(1) 10 ns M2 td(MCAN_RX) Delay time, MCANn_RX pin to receive shift register(1) 10 ns (1) n is [0:13] in MCANn_* or [0:1] in MCU_MCANn_* For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.17 MCASP

For more details about features and additional description information on the device Multichannel Audio Serial Port, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-60 and Figure 6-84 present timing requirements for MCASP0 to MCASP11. Table 6-59 represents MCASP timing conditions. Table 6-59. MCASP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.7 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 100 1100 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps Table 6-60. MCASP Timing Requirements NO. MODE(1) MIN MAX UNIT ASP1 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X 15.26 ns ASP2 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X high or low 0.5P(2) - 1.53 ns ASP3 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X 15.26 ns ASP4 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X high or low 0.5R(3) - 1.53 ns ASP5 tsu(AFSRX-ACLKRX) Setup time, MCASP[x]_AFSR/X input valid before MCASP[x]_ACLKR/X ACLKR/X int 12.3 ns ACLKR/X ext in/out 4 ASP6 th(ACLKRX-AFSRX) Hold time, MCASP[x]_AFSR/X input valid after MCASP[x]_ACLKR/X ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 ASP7 tsu(AXR-ACLKRX) Setup time, MCASP[x]_AXR input valid before MCASP[x]_ACLKR/X ACLKR/X int 12.3 ns ACLKR/X ext in/out 4 ASP8 th(ACLKRX-AXR) Hold time, MCASP[x]_AXR input valid after MCASP[x]_ACLKR/X ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 253 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

A0A1B0B1A30A31B30B31C0C1C2C3C31 MCASP[x]_AHCLKR/X (Falling Edge Priority)MCASP[x]_AHCLKR/X (Rising Edge Polarity) MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)MCASP[x]_AXR[x] (Data In/Receive) ASP6ASP5MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(A)MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(B) A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured for falling edge (to shift data in). B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured for rising edge (to shift data in). Figure 6-84. MCASP Input Timing DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-61 and Figure 6-85 present switching characteristics over recommended operating conditions for MCASP0 to MCASP11. Table 6-61. MCASP Switching Characteristics NO. PARAMETER DESCRIPTION MODE(1) MIN MAX UNIT ASP9 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X 20 ns ASP10 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X high or low 0.5P(2) - 2 ns ASP11 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X 20 ns ASP12 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X high or low 0.5R(3) - 2 ns ASP13 td(ACLKRX-AFSRX) Delay time, MCASP[x]_ACLKR/X transmit edge to MCASP[x]_AFSR/X output valid ACLKR/X int 0 7.25 ns ACLKR/X ext in/out -15.28 12.84 ASP14 td(ACLKX-AXR) Delay time, MCASP[x]_ACLKX transmit edge to MCASP[x]_AXR output valid ACLKR/X int 0 7.25 ns ACLKR/X ext in/out -15.28 12.84 ASP15 tdis(ACLKX-AXR) Disable time, MCASP[x]_ACLKX transmit edge to MCASP[x]_AXR output high impedance ACLKR/X int 0 7.25 ns ACLKR/X ext in/out -14.9 14 (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. (3) R = ACLKR/X period in ns. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 255 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

A0A1B0B1A30A31B30B31C0C1C2C3C31 ASP13ASP13 ASP13ASP13ASP13 MCASP[x]_AHCLKR/X (Falling Edge Priority)MCASP[x]_AHCLKR/X (Rising Edge Polarity) MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay) MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay) MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)MCASP[x]_AXR[x] (Data Out/Transmit) MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)(A)MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)(B) A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured for rising edge (to shift data in). B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured for falling edge (to shift data in). Figure 6-85. MCASP Output Timing For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device TRM. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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6.9.5.18 MCSPI

For more details about features and additional description information on the device Serial Port Interface, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the device TRM. Table 6-62 represents MCSPI timing conditions. Note The IO timings provided in this section are applicable for all combinations of signals for MCU_SPI0 and MCU_SPI1. However, the timings are only valid for MCU_SPI0 and MCU_SPI1 if signals within a single IOSET are used. The IOSETs are defined in the Table 6-67 and Table 6-68 tables. Table 6-62. MCSPI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 2 8.5 V/ns OUTPUT CONDITIONS CL Output load capacitance CLK 6 24 pF D[x], CSi 6 12 pF

6.9.5.18.1 MCSPI — Master Mode

Table 6-63, Figure 6-86, Table 6-64, and Figure 6-87 present timing requirements and switching characteristics for MCSPI – Master Mode. Table 6-63. MCSPI Timing Requirements - Master Mode see Figure 6-86 NO. MIN MAX UNIT SM4 tsu(misoV- spiclkV) Setup time, SPI_D[x] valid before SPI_CLK active edge 2.8 ns SM5 th(spiclkV- misoV) Hold time, SPI_D[x] valid after SPI_CLK active edge 3 ns Table 6-64. MCSPI Switching Characteristics - Master Mode see Figure 6-87 NO. PARAMETER MODE MIN MAX UNIT SM1 tc(spiclk) Cycle time, SPI_CLK 20.8 ns SM2 tw(spiclkL) Pulse duration, SPI_CLK low 0.5P - 1(1) ns SM3 tw(spiclkH) Pulse duration, SPI_CLK high 0.5P - 1(1) ns SM6 td(spiclkV-simoV) Delay time, SPI_CLK active edge to SPI_D[x] transition -3 2.5 ns SM7 td(csV-simoV) Delay time, SPI_CSi active edge to SPI_D[x] transition 5 ns SM8 td(csV-spiclk) Delay time, SPI_CSi active to SPI_CLK first edge PHA = 0(2) B - 4(3) ns PHA = 1 (2) A - 4(4) ns SM9 td(spiclkV-csV) Delay time, SPI_CLK last edge to SPI_CSi inactive PHA = 0(2) A - 4(4) ns PHA = 1(2) B - 4(3) ns (1) P = SPI_CLK period in ns (2) SPI_CLK phase is programmable with the PHA bit of the MCSPI_CHCONF_0/1/2/3 register (3) B = (TCS + .5) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register and Fratio = Even >= 2. (4) When P = 20.8 ns, A = (TCS + 1) * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 257 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

When P > 20.8 ns, A = (TCS + 0.5) * Fratio * TSPICLKREF, where TCSns a bit field of the MCSPI_CHCONF_0/1/2/3 register. SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 PHA=1 EPOL=1 POL=0 POL=1 POL=0 POL=1 SM8 SM9 SM3 SM1 SM2 SM1 SM8 SM9SM3 SM1 SM2 SM1 SM2 SM3 SM2 SM3 SM4 SM5 SM4 SM5 SM4 SM4 SM5 SM5 SPRSP08_TIMING_McSPI_02 Figure 6-86. SPI Master Mode Receive Timing DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) SPI_CS[i] (OUT) SPI_SCLK (OUT) SPI_SCLK (OUT) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM8 SM9 SM6 SM3 SM1 SM2 SM1 SM8 SM9SM3 SM1 SM2 SM1 SM6 SM7 SM6 SM2 SM3 SM2 SM3 SM6 SM6 SM6 SPRSP08_TIMING_McSPI_01 Figure 6-87. MCSPI Master Mode Transmit Timing

6.9.5.18.2 MCSPI — Slave Mode

Table 6-65, Table 6-66, Figure 6-88, and Figure 6-89 present timing requirements and switching characteristics for MCSPI – Slave Mode. Table 6-65. MCSPI Timing Requirements - Slave Mode NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT SS1 tc(spiclk) Cycle time, SPI_CLK 20.8 ns SS2 tw(spiclkL) Pulse duration, SPI_CLK low 0.45P (1) ns SS3 tw(spiclkH) Pulse duration, SPI_CLK high 0.45P (1) ns SS4 tsu(simoV-spiclkV) Setup time, SPI_D[x] valid before SPI_CLK active edge 5 ns SS5 th(spiclkV-simoV) Hold time, SPI_D[x] valid after SPI_CLK active edge 5 ns SS8 tsu(csV-spiclkV) Setup time, SPI_CSi valid before SPI_CLK first edge 5 ns SS9 th(spiclkV-csV) Hold time, SPI_CSi valid after SPI_CLK last edge 5 ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 259 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-66. MCSPI Switching Characteristics - Slave Mode NO. PARAMET ER DESCRIPTION MIN MAX UNIT SS6 td(spiclkV- somiV) Delay time, SPI_CLK active edge to SPI_D[x] transition 2 17.12 ns SS7 tsk(csV-somiV) Delay time, SPI_CSi active edge to SPI_D[x] transition 20.95 ns (1) P = SPI_CLK period in ns. SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS8 SS9 SS8 SS9 SS2 SS3 SS2 SS2 SS4 SS5 SS5 SS4 SS4 SS5 SS4 SS5 SPRSP08_TIMING_McSPI_04 Figure 6-88. SPI Slave Mode Receive Timing DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (OUT) SPI_CS[i] (IN) SPI_SCLK (IN) SPI_SCLK (IN) SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS6 SS3 SS1 SS3 SS1 SS3 SS1 SS2 SS1 SS6 SS6 SS8 SS9 SS7 SS8 SS2 SS3 SS2 SS2 SS6 SS6SS6 SS9 SPRSP08_TIMING_McSPI_03 Figure 6-89. MCSPI Slave Mode Transmit Timing Table 6-67 and Table 6-68 present the specific groupings of signals (IOSET) for use with MCU_SPI0 and MCU_SPI1. Table 6-67. MCU_SPI0 IOSETs Signals IOSET1 IOSET2 BALL NAME MUX BALL NAME MUX MCU_SPI0_CLK MCU_SPI0_CLK 0 MCU_SPI0_CLK 0 MCU_SPI0_D0 MCU_SPI0_D0 0 MCU_SPI0_D0 0 MCU_SPI0_D1 MCU_SPI0_D1 0 MCU_SPI0_D1 0 MCU_SPI0_CS0 MCU_SPI0_CS0 0 MCU_SPI0_CS0 0 MCU_SPI0_CS1 MCU_OSPI1_D3 5 WKUP_GPIO0_12 1 MCU_SPI0_CS2 MCU_OSPI1_CSn1 5 WKUP_GPIO0_14 1 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 261 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-68. MCU_SPI1 IOSET Signals IOSET1 IOSET2 BALL NAME MUX BALL NAME MUX MCU_SPI1_CLK MCU_SPI1_CLK 0 MCU_SPI1_CLK 0 MCU_SPI1_D0 MCU_SPI1_D0 0 MCU_SPI1_D0 0 MCU_SPI1_D1 MCU_SPI1_D1 0 MCU_SPI1_D1 0 MCU_SPI1_CS0 MCU_SPI1_CS0 0 MCU_SPI1_CS0 0 MCU_SPI1_CS1 MCU_OSPI1_D1 5 WKUP_GPIO0_13 1 MCU_SPI1_CS2 MCU_OSPI1_D2 5 WKUP_GPIO0_15 1 For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the device TRM.

6.9.5.19 MMCSD

The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD), and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking for syntactical correctness. For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Note Some operating modes require software configuration of the MMC DLL delay settings, as shown in Table 6-69 and Table 6-78. For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in the device TRM.

6.9.5.19.1 MMC0 - eMMC Interface

MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the following eMMC applications:

• Legacy speed
• High speed SDR
• High speed DDR
• HS200 Table 6-69 presents the required DLL software configuration settings for MMC0 timing modes. Table 6-69. MMC0 DLL Delay Mapping for All Timing Modes REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL SELDLYTXCLK SELDLYRXCLK FRQSEL CLKBUFSEL MODE DESCRIPTION STROBE DELAY OUTPUT DELAY ENABLE OUTPUT DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DLL/ DELAY CHAIN SELECT DLL REF FREQUENCY DELAY BUFFER DURATION Legacy SDR 8-bit PHY operating 1.8 V,

25 MHz

0x0 0x0 NA 0x1 0x10 0x1 0x0 0x7 High Speed SDR 8-bit PHY operating 1.8 V,

50 MHz

0x0 0x0 NA 0x1 0xA 0x1 0x0 0x7 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-69. MMC0 DLL Delay Mapping for All Timing Modes (continued) REGISTER NAME MMCSD0_SS_PHY_CTRL_4_REG MMCSD0_SS_PHY_CTRL_5_REG BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL SELDLYTXCLK SELDLYRXCLK FRQSEL CLKBUFSEL MODE DESCRIPTION STROBE DELAY OUTPUT DELAY ENABLE OUTPUT DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DLL/ DELAY CHAIN SELECT DLL REF FREQUENCY DELAY BUFFER DURATION High Speed DDR 8-bit PHY operating 1.8 V, 0x0 0x1 0x5 0x1 0x3 0x0 0x4 0x7 HS200 8-bit PHY operating 1.8 V,

200 MHz

0x0 0x1 0x6 0x1 Tuning 0x0 0x0 0x7 Table 6-70 presents timing conditions for MMC0. Table 6-70. MMC0 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Legacy SDR 0.14 1.44 V/ns High Speed SDR 0.3 0.9 V/ns High Speed DDR (CMD) 0.3 0.9 V/ns High Speed DDR (DAT[7:0]) 0.45 0.9 V/ns OUTPUT CONDITIONS CL Output load capacitance HS200 1 6 pF All other modes 1 12 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace All modes 126 756 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces Legacy SDR, High Speed SDR, High Speed DDR 100 ps HS200 8 ps www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 263 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-71, Figure 6-90, Table 6-72, and Figure 6-91 present timing requirements and switching characteristics for MMC0 – Legacy SDR Mode. Table 6-71. MMC0 Timing Requirements – Legacy SDR Mode see Figure 6-90 NO. MIN MAX UNIT LSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 9.69 ns LSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 9.65 ns LSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge 9.69 ns LSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge 9.65 ns Figure 6-90. MMC0 – Legacy SDR – Receive Mode Table 6-72. MMC0 Switching Characteristics – Legacy SDR Mode see Figure 6-91 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 25 MHz LSDR5 tc(clk) Cycle time, MMC0_CLK 40 ns LSDR6 tw(clkH) Pulse duration, MMC0_CLK high 18.7 ns LSDR7 tw(clkL) Pulse duration, MMC0_CLK low 18.7 ns LSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition -2.74 5.07 ns LSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition -2.74 5.07 ns Figure 6-91. MMC0 – Legacy SDR – Transmit Mode DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-73, Figure 6-92, Table 6-74, and Figure 6-93 present timing requirements and switching characteristics for MMC0 – High Speed SDR Mode. Table 6-73. MMC0 Timing Requirements – High Speed SDR Mode see Figure 6-92 NO. MIN MAX UNIT HSSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 2.99 ns HSSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 2.67 ns HSSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge 2.99 ns HSSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge 2.67 ns Figure 6-92. MMC0 – High Speed SDR Mode – Receive Mode Table 6-74. MMC0 Switching Characteristics – High Speed SDR Mode see Figure 6-93 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 50 MHz HSSDR5 tc(clk) Cycle time, MMC0_CLK 20 ns HSSDR6 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns HSSDR7 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns HSSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition -0.84 3.65 ns HSSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition -0.84 3.65 ns Figure 6-93. MMC0 – High Speed SDR Mode – Transmit Mode www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 265 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-75, Figure 6-94, Table 6-76, and Figure 6-95 present timing requirements and switching characteristics for MMC0 – High Speed DDR Mode. Table 6-75. MMC0 Timing Requirements – High Speed DDR Mode see Figure 6-94 NO. MIN MAX UNIT HSDDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 2 ns HSDDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 2.5 ns HSDDR3 tsu(dV-clkV) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition 0.74 ns HSDDR4 th(clkV-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition 1.67 ns Figure 6-94. MMC0 – High Speed DDR Mode – Receive Mode Table 6-76. MMC0 Switching Characteristics – High Speed DDR Mode see Figure 6-95 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 50 MHz HSDDR5 tc(clk) Cycle time, MMC0_CLK 20 ns HSDDR6 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns HSDDR7 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns HSDDR8 td(clkH-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 3.4 9.72 ns HSDDR9 td(clkV-dV) Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition 2.9 6.6 ns Figure 6-95. MMC0 – High Speed DDR Mode – Transmit Mode DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-77 and Figure 6-96 present switching characteristics for MMC0 – HS200 Mode. Table 6-77. MMC0 Switching Characteristics – HS200 Mode see Figure 6-96 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 200 MHz HS2005 tc(clk) Cycle time, MMC0_CLK 5 ns HS2006 tw(clkH) Pulse duration, MMC0_CLK high 2.08 ns HS2007 tw(clkL) Pulse duration, MMC0_CLK low 2.08 ns HS2008 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.12 3.16 ns HS2009 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition 1.12 3.16 ns Figure 6-96. MMC0 – HS200 Mode – Transmit Mode

6.9.5.19.2 MMC1/2 - SD/SDIO Interface

MMC1 and MMC2 interfaces are compliant with the SD Host Controller Standard Specification 4.10 and SD Physical Layer Specification v3.01 as well as SDIO Specification v3.00 and they support the following SD Card applications:

• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I SDR104
• UHS–I DDR50 Table 6-78 presents the required DLL software configuration settings for MMC1 timing modes. Table 6-78. MMC1/2 DLL Delay Mapping for All Timing Modes REGISTER NAME MMCSD12_SS_PHY_CTRL_4_REG MMCSD12_SS_PHY_CTRL_5_REG BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION Default Speed 4-bit PHY operating

3.3 V, 25 MHz 0x1 0x1 0x0 0x0 0x7

3.3 V, 50 MHz 0x1 0x1 0x0 0x0 0x7

1.8 V, 25 MHz 0x1 0xF 0x0 0x0 0x7

1.8 V, 50 MHz 0x1 0xF 0x0 0x0 0x7

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Table 6-78. MMC1/2 DLL Delay Mapping for All Timing Modes (continued) REGISTER NAME MMCSD12_SS_PHY_CTRL_4_REG MMCSD12_SS_PHY_CTRL_5_REG BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL MODE DESCRIPTION DELAY ENABLE DELAY VALUE INPUT DELAY ENABLE INPUT DELAY VALUE DELAY BUFFER DURATION UHS-I SDR50 4-bit PHY operating

1.8 V, 100 MHz 0x1 0xC 0x1 Tuning 0x7

1.8 V, 50 MHz 0x1 0xC 0x1 0x2 0x7

1.8, V 200 MHz 0x1 0x5 0x1 Tuning 0x7 Table 6-79 presents timing conditions for MMC1. Table 6-79. MMC1/2 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Default Speed, High Speed 0.69 2.06 V/ns UHS–I SDR12, UHS–I SDR25 0.34 1.34 V/ns OUTPUT CONDITIONS CL Output load capacitance All modes 1 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace UHS–I DDR50 240 1134 ps All other modes 126 1386 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces UHS–I DDR50, UHS–I SDR104 20 ps All other modes 100 ps DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-80, Figure 6-97, Table 6-81, and Figure 6-98 present timing requirements and switching characteristics for MMC1/2 – Default Speed Mode. Table 6-80. MMC1/2 Timing Requirements – Default Speed Mode see Figure 6-97 NO. MIN MAX UNIT DS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.55 ns DS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 4.65 ns DS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.55 ns DS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 4.65 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLKx M [ ]_MC CMDx MMC DA T[ ]_ [3:0]x DS1 DS2 DS3 DS4 Figure 6-97. MMC1/2 – Default Speed – Receive Mode Table 6-81. MMC1/2 Switching Characteristics – Default Speed Mode see Figure 6-98 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 25 MHz DS5 tc(clk) Cycle time, MMC[x]_CLK 40 ns DS6 tw(clkH) Pulse duration, MMC[x]_CLK high 18.7 ns DS7 tw(clkL) Pulse duration, MMC[x]_CLK low 18.7 ns DS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition -2.93 3.63 ns DS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition -2.93 3.63 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ _ [3:0]x] D 5 S D 7 S D 8 S D 9 S DS6 Figure 6-98. MMC1/2 – Default Speed – Transmit Mode www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 269 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-82, Figure 6-99, Table 6-83, and Figure 6-100 present timing requirements and switching characteristics for MMC1/2 – High Speed Mode. Table 6-82. MMC1/2 Timing Requirements – High Speed Mode see Figure 6-99 NO. MIN MAX UNIT HS1 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.55 ns HS2 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 2.67 ns HS3 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.55 ns HS4 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 2.67 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLKx MMC[ ]_CMDx MMC DA T[ ]_ [3:0]x H 1 S H 2 S H 3 S H 4 S Figure 6-99. MMC1 /2– High Speed – Receive Mode Table 6-83. MMC1/2 Switching Characteristics – High Speed Mode see Figure 6-100 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 50 MHz HS5 tc(clk) Cycle time. MMC[x]_CLK 20 ns HS6 tw(clkH) Pulse duration, MMC[x]_CLK high 9.2 ns HS7 tw(clkL) Pulse duration, MMC[x]_CLK low 9.2 ns HS8 td(clkL-cmdV) Delay time, MMC[x]_CLK falling edge to MMC[x]_CMD transition -1.77 2.35 ns HS9 td(clkL-dV) Delay time, MMC[x]_CLK falling edge to MMC[x]_DAT[3:0] transition -1.77 2.35 ns MMC[x]_CLK MMC CMD[ ]_ x MMC DA T[ ]_ [3:0]x H 5 S H 7 S H 8 S H 9 S HS6 Figure 6-100. MMC1/2 – High Speed – Transmit Mode DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-84 , Figure 6-101 , Table 6-85 , and Figure 6-102 present timing requirements and switching characteristics for MMC1/2 – UHS-I SDR12 Mode. Table 6-84. MMC1/2 Timing Requirements – UHS-I SDR12 Mode see Figure 6-101 NO. MIN MAX UNIT SDR121 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 21.65 ns SDR122 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 1.67 ns SDR123 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 21.65 ns SDR124 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 1.67 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CMDx MMC DA T[ ]_ [3:0]x SDR121 SDR122 SDR123 SDR124 MMC[ ]_CLKx Figure 6-101. MMC1/2 – UHS-I SDR12 – Receive Mode Table 6-85. MMC1/2 Switching Characteristics – UHS-I SDR12 Mode see Figure 6-102 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 25 MHz SDR125 tc(clk) Cycle time, MMC[x]_CLK 40 ns SDR126 tw(clkH) Pulse duration, MMC[x]_CLK high 18.7 ns SDR127 tw(clkL) Pulse duration, MMC[x]_CLK low 18.7 ns SDR128 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.2 13.69 ns SDR129 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 1.2 13.69 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ ]_ [3:0]x SDR125 SDR127SDR126 SDR128 SDR129 SDR128 SDR129 Figure 6-102. MMC1/2 – UHS-I SDR12 – Transmit Mode www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 271 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-86 , Figure 6-103 , Table 6-87 , and Figure 6-104 present timing requirements and switching characteristics for MMC1/2 – UHS-I SDR25 Mode. Table 6-86. MMC1/2 Timing Requirements – UHS-I SDR25 Mode see Figure 6-103 NO. MIN MAX UNIT SDR251 tsu(cmdV-clkH) Setup time, MMC[x]_CMD valid before MMC[x]_CLK rising edge 2.15 ns SDR252 th(clkH-cmdV) Hold time, MMC[x]_CMD valid after MMC[x]_CLK rising edge 1.67 ns SDR253 tsu(dV-clkH) Setup time, MMC[x]_DAT[3:0] valid before MMC[x]_CLK rising edge 2.15 ns SDR254 th(clkH-dV) Hold time, MMC[x]_DAT[3:0] valid after MMC[x]_CLK rising edge 1.67 ns A. x = 1, 2 for MMC1 and MMC2 B. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLKx MMC[ ]_CMDx MMC DA T[ ]_ [3:0]x SDR251 SDR252 SDR253 SDR254 Figure 6-103. MMC1/2 – UHS-I SDR25 – Receive Mode Table 6-87. MMC1/2 Switching Characteristics – UHS-I SDR25 Mode see Figure 6-104 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 50 MHz SDR255 tc(clk) Cycle time, MMC[x]_CLK 20 ns SDR256 tw(clkH) Pulse duration, MMC[x]_CLK high 9.2 ns SDR257 tw(clkL) Pulse duration, MMC[x]_CLK low 9.2 ns SDR258 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 2.4 9.8 ns SDR259 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 2.4 9.8 ns MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ _ [3:0]x] SDR255 SDR257SDR256 SDR258 SDR259 SDR258 SDR259 Figure 6-104. MMC1/2 – UHS-I SDR25 – Transmit Mode DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-88, and Figure 6-105 presents switching characteristics for MMC1/2 – UHS-I SDR50 Mode. Table 6-88. MMC1/2 Switching Characteristics – UHS-I SDR50 Mode see Figure 6-105 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 100 MHz SDR505 tc(clk) Cycle time, MMC[x]_CLK 10 ns SDR506 tw(clkH) Pulse duration, MMC[x]_CLK high 4.45 ns SDR507 tw(clkL) Pulse duration, MMC[x]_CLK low 4.45 ns SDR508 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.2 6.35 ns SDR509 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 1.2 6.35 ns A. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[x]_ [3:0] SDR505 SDR507SDR506 SDR508 SDR509 SDR508 SDR509 Figure 6-105. MMC1/2 – UHS-I SDR50 – Transmit Mode www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 273 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-89 and Figure 6-106 present switching characteristics for MMC1/2 – UHS-I DDR50 Mode. Table 6-89. MMC1/2 Switching Characteristics – UHS-I DDR50 Mode see Figure 6-106 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 50 MHz DDR505 tc(clk) Cycle time, MMC[x]_CLK 20 ns DDR506 tw(clkH) Pulse duration, MMC[x]_CLK high 9.2 ns DDR507 tw(clkL) Pulse duration, MMC[x]_CLK low 9.2 ns DDR508 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.2 9.8 ns DDR509 td(clk-dV) Delay time, MMC[x]_CLK transition to MMC[x]_DAT[3:0] transition 1.2 6.35 ns A. x = 1, 2 for MMC1 and MMC2 MMC[x] CLK_ MMC[x] CMD_ MMC[x] DAT□3_ [ :0] DDR508 DDR509 DDR509 DDR505 DDR506 DDR507 Figure 6-106. MMC1/2 – UHS-I DDR50 – Transmit Mode DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-90, and Figure 6-107 present switching characteristics for MMC1/2 – UHS-I SDR104 Mode. Table 6-90. MMC1/2 Switching Characteristics – UHS-I SDR104 Mode see Figure 6-107 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC[x]_CLK 200 MHz SDR1045 tc(clk) Cycle time, MMC[x]_CLK 5 ns SDR1046 tw(clkH) Pulse duration, MMC[x]_CLK high 2.08 ns SDR1047 tw(clkL) Pulse duration, MMC[x]_CLK low 2.08 ns SDR1048 td(clkH-cmdV) Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition 1.12 3.16 ns SDR1049 td(clkH-dV) Delay time, MMC[x]_CLK rising edge to MMC[x]_DAT[3:0] transition 1.12 3.16 ns A. x = 1, 2 for MMC1 and MMC2 MMC[ ]_CLKx MMC CMD[ ]_ x MMC DA T[ ]_ [3:0]x SDR1045 SDR1047SDR1046 SDR1048 SDR1049 SDR1048 SDR1049 Figure 6-107. MMC1/2 – UHS-I SDR104 – Transmit Mode

6.9.5.20 CPTS

Table 6-91 represents CPTS timing conditions. Table 6-91. CPTS Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 2 10 pF switching characteristics of the CPTS interface.

6.9.5.20.1 CPTS Timing Requirements

NO. MIN MAX UNIT T1 tw(HWnTSPUSHH) Pulse duration, HWnTSPUSH(2) high 12P + 2(1) ns T2 tw(HWnTSPUSHL) Pulse duration, HWnTSPUSH(2) low 12P + 2(1) ns T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45 * T(3) ns T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45 * T(3) ns (1) P = functional clock period in ns. (2) In HWnTSPUSH, n = 1 to 2. (3) T = RFT_CLK period in ns. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 275 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

RFT_CLK T3 T4 T5 HWn_TSPUSH T1 T2 Figure 6-108. CPTS Timing Requirements

6.9.5.20.2 CPTS Switching Characteristics

NO. PARAMETER SOURCE MIN MAX UNIT T6 tw(TS_COMPH) Pulse duration, TS_COMP high 36P - 2(1) ns T7 tw(TS_COMPL) Pulse duration, TS_COMP low 36P - 2(1) ns T8 tw(TS_SYNCH) Pulse duration, TS_SYNC high 36P - 2(1) ns T9 tw(TS_SYNCL) Pulse duration, TS_SYNC low 36P - 2(1) ns T10 tw(SYNC_OUTH) Pulse duration, SYNCn_OUT(2) high TS_SYNC 36P - 2(1) ns TS_GENF 5P - 2(1) ns T11 tw(SYNC_OUTL) Pulse duration, SYNCn_OUT(2) low TS_SYNC 36P - 2(1) ns TS_GENF 5P - 2(1) ns (1) P = functional clock period in ns. (2) n = 0 to 3 in SYNCn_OUT TS_COMP T6 T7 TS_SYNC T8 T9 SYNCn_OUT T10 T1 1 Figure 6-109. CPTS Switching Characteristics For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter in the device TRM.

6.9.5.21 OSPI

For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-92 represents OSPI timing conditions. Table 6-92. OSPI Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 3.3 V 2 6 V/ns All other modes 1 6 V/ns OUTPUT CONDITIONS DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-92. OSPI Timing Conditions (continued) PARAMETER MIN MAX UNIT CL Output load capacitance All modes 3 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay OSPI_CLK trace No Loopback; Internal Pad Loopback 450 ps Propagation delay OSPI_LBCLKO trace External Board Loopback 2*L-30(2) 2*L+30(2) ps Propagation delay OSPI_DQS trace DQS L-30(2) L+30(2) ps td(Trace Mismatch Delay) Propagation delay mismatch OSPI_Di:0, OSPI_CSn relative to OSPI_CLK All modes ps (1) i in D[i:0] = 0 to 7 for OSPI0; i in [i:0] = 3 for OSPI1 (2) L = Propagation delay of OSPI_CLK trace www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 277 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.5.21.1 OSPI PHY Mode

I/O timing requirements and switching characteristics are not applicable when OSPI is used with data training. Follow the Section 8.3.2, OSPI and QSPI Board Design and Layout Guidelines section to ensure proper operation. PARAMETER DESCRIPTION MODE MIN MAX UNIT tc(CLK) Cycle time, CLK DDR, 1.8V 6 ns DDR, 3.3V 7.5 ns tc(CLK) Cycle time, CLK SDR, 1.8V 6 ns SDR, 3.3V 7.5 ns Note The I/O Timings provided in this section are only applicable when data training is not implemented. Additionally, the I/O Timings are valid only for some OSPI usage modes when the corresponding DLL Delays are configured as described in Table 6-93 found in this section. characteristics for OSPI DDR and SDR Mode. Table 6-93. OSPI DLL Delay Mapping - SDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE All modes PHY_CONFIG_TX_DLL_DELAY_FLD 0x0 PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, D[i:0] valid before active CLK edge(1) 1.8V, Internal Loopback -2.19 ns 3.3V, Internal Loopback -1.71 ns O20 th(CLK-D) Hold time, D[i:0] valid after active CLK edge(1) 1.8V, Internal Loopback 7.62 ns 3.3V, Internal Loopbacl 8.1 ns O21 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK input (DQS) edge(1) 1.8V, External Board Loopback -3.1 ns 3.3V, External Board Loopback -2.72 ns O22 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK input (DQS) edge(1) 1.8V, External Board Loopback 3.81 ns 3.3V, External Board Loopback 4.33 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 6-110. OSPI Timing Requirements – SDR, Internal Clock and Internal Pad Loopback Clock OSPI_DQS OSPI_TIMING_06 O21 O 2 2 OSPI_D[i:0] Figure 6-111. OSPI Timing Requirements – SDR, External Loopback Clock NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O7 tc(CLK) Cycle time, CLK 1.8V 7 ns 3.3V 7.5 ns O8 tw(CLKL) Pulse duration, CLK low -0.3+0.475*P (2) ns O9 tw(CLKH) Pulse duration, CLK high -0.3+0.475*P (2) ns O10 td(CLK-CSn) Delay time, CLK rising edge to CSn active edge 1.8V 0.475 * P + 0.975 * N * R (2) (3) (5) 0.475 * P + 0.975 * N * R + 1 (3) (3) (5) ns 3.3V 0.475 * P + 0.975 * N * R (2) (3) (5) 0.475 * P + 0.975 * N * R + 1 (2) (3) (5) ns O11 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V 0.475 * P + 0.975 * N * R - 1 (2) (4) (5) 0.475 * P + 0.975 * N * R + 1 (2) (4) (5) ns 3.3V -1+0.475 * P + 0.975 * N * R (2) (4) (5) 1+0.475 * P + 0.975 * N * R (2) (4) (5) ns O12 td(CLK-D) Delay time, CLK active edge to D[i:0] transition(1) 1.8V -1.16 1.25 ns 3.3V -1.33 1.51 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time = SCLK period (3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (5) R = refclk www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 279 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

OSPI_CLK OSPI_TIMING_02 OSPI_CSn O10 O1 1 O9 O8 O12 OSPI_D[i:0] Figure 6-112. OSPI Switching Characteristics – SDR presents timing requirements for OSPI DDR and SDR Mode. Table 6-94. OSPI DLL Delay Mapping - DDR Timing Modes MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE OSPI0 OSPI1 Transmit 1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x40 0x41 3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x3C 0x3E Receive 1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x13 0x15 3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x1E 0x1E All other modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0 0x0 NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, D[i:0] valid before active LBCLK (DQS) edge(1) 1.8V, External Board Loopback 0.52 ns 3.3V, External Board Loopback 1.97 ns O16 th(LBCLK-D) Hold time, D[i:0] valid after active LBCLK (DQS) edge(1) 1.8V, External Board Loopback 1.24 (2) ns 3.3V, External Board Loopback 1.44 (2) ns O17 tsu(D-DQS) Setup time, DQS edge to D[i:0] transition(1) 1.8V, DQS -0.46 ns 3.3V, DQS -0.66 ns O18 th(DQS-D) Hold time, DQS edge to D[i:0] transition(1) 1.8V, DQS 3.59 ns 3.3V, DQS 8.89 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to Section 8.3.2 for more details. OSPI_DQS O16O15 OSPI_TIMING_04 OSPI_D[i:0] Figure 6-113. OSPI Timing Requirements – DDR, External Loopback Clock and DQS DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, CLK 1.8V 19 ns 3.3V 19 ns O2 tw(CLKL) Pulse duration, CLK low 0.475*P - 0.3 (2) ns O3 tw(CLKH) Pulse duration, CLK high 0.475*P - 0.3 (2) ns O4 td(CLK-CSn) Delay time, CSn active edge to CLK rising edge 1.8V 0.475 * P + 0.975 * N * R (2) (3) (5) 0.475 * P + 0.975 * N * R + 1 (2) (3) (5) ns 3.3V 0.475 * P + 0.975 * N * R (2) (3) (5) 0.475 * P + 0.975 * N * R + 1(2) (3) (5) ns O5 td(CLK-CSn) Delay time, CLK rising edge to CSn inactive edge 1.8V 0.475 * P + 0.975 * N * R - 7(2) (4) (5) 0.475 * P + 0.975 * N * R (2) (4) (5) ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX 0.475 * P + 0.975 * N * R - 7(2) (4) (5) 0.475 * P + 0.975 * N * R (2) (4) (5) ns O6 td(CLK-D) Delay time, CLK active edge to D[i:0] transition(1) 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX -7.71 -1.56 ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX -7.71 -1.56 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time = SCLK period (3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (5) R = refclk OSPI_CLK OSPI_TIMING_01 OSPI_CSn O6 O6 O4 O3 OSPI_D[i:0] Figure 6-114. OSPI Switching Characteristics – DDR www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 281 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.5.21.2 OSPI Tap Mode

Table 6-95, Figure 6-115, Table 6-96, and Figure 6-116 present timing requirements and switching characteristics for OSPI0 Tap SDR Mode. Table 6-95. OSPI Timing Requirements – Tap SDR Mode see Figure 6-115 NO. MODE MIN MAX UNIT O19 tsu(D-CLK) Setup time, OSPI_D[7:0] valid before active OSPI_CLK edge No Loopback (10.4 - O20 th(CLK-D) Hold time, OSPI_D[7:0] valid after active OSPI_CLK edge No Loopback (–0.2 + (1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] (2) R = reference clock cycle time in ns OSPI_CLK OSPI_D[i:0] OSPI_TIMING_05 O 9 1 O20 Figure 6-115. OSPI Timing Requirements – Tap SDR, No Loopback DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-96. OSPI0/1 Switching Characteristics – Tap SDR Mode see Figure 6-116 NO. PARAMETER MODE MIN MAX UNIT O7 tc(CLK) Cycle time, OSPI0/1_CLK 20 ns O8 tw(CLKL) Pulse duration, OSPI0/1_CLK low ((0.475P(1)) - 0.3) ns O9 tw(CLKH) Pulse duration, OSPI0/1_CLK high ((0.475P(1)) - 0.3) ns O10 td(CSn-CLK) Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge ((0.475P(1)) + (0.975M(2)R(4)) - 1.5) ((0.525P(1)) + (1.025M(2)R(4)) + 1.5) ns O11 td(CLK-CSn) Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge ((0.475P(1)) + (0.975N(3)R(4)) - 1.5) ((0.525P(1)) + (1.025N(3)R(4)) + 1.5) ns O12 td(CLK-D) Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition –2 2 ns (1) P = SCLK cycle time in ns = OSPI0/1_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = reference clock cycle time in ns OSPI_CLK OSPI_TIMING_02 OSPI_CSn O10 O1 1 O9 O8 O12 OSPI_D[i:0] Figure 6-116. OSPI Switching Characteristics – Tap SDR, No Loopback www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 283 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-97, Figure 6-117, Table 6-98, and Figure 6-118 present timing requirements and switching characteristics for OSPI0 Tap DDR Mode. Table 6-97. OSPI Timing Requirements – Tap DDR Mode see Figure 6-117 NO. MODE MIN MAX UNIT O13 tsu(D-CLK) Setup time, OSPI0/1_D[7:0] valid before active OSPI0/1_CLK edge No Loopback (12.04 - O14 th(CLK-D) Hold time, OSPI0/1_D[7:0] valid after active OSPI0/1_CLK edge No Loopback (1.84 + (1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD] (2) R = reference clock cycle time in ns OSPI_CLK O14O13 OSPI_TIMING_03 OSPI_D[i:0] O14O13 Figure 6-117. OSPI Timing Requirements – Tap DDR, No Loopback DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-98. OSPI0/1 Switching Characteristics – Tap DDR Mode see Figure 6-118 NO. PARAMETER MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI0/1_CLK 40 ns O2 tw(CLKL) Pulse duration, OSPI0/1_CLK low ((0.475P(1)) - 0.3) ns O3 tw(CLKH) Pulse duration, OSPI0/1_CLK high ((0.475P(1)) - 0.3) ns O4 td(CSn-CLK) Delay time, OSPI0/1_CSn[3:0] active edge to OSPI0/1_CLK rising edge ((0.475P(1)) + ((0.975M(2)R(5)) - 1.5) ((0.525P(1)) + ( 1.025M(2)R(5)) + 1.5) ns O5 td(CLK-CSn) Delay time, OSPI0/1_CLK rising edge to OSPI0/1_CSn[3:0] inactive edge ((0.475P(1)) + ((0.525P(1)) + (1.025N(3)R(5)) + 1.5) ns O6 td(CLK-D) Delay time, OSPI0/1_CLK active edge to OSPI0/1_D[7:0] transition (–17.94 + (–1.56 + (1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD] (5) R = reference clock cycle time in ns OSPI_CLK OSPI_TIMING_01 OSPI_CSn OSPI_D[i:0] Figure 6-118. OSPI Switching Characteristics – Tap DDR, No Loopback

6.9.5.22 PCIE

The PCI-Express Subsystem is compliant with the PCIe ® Base Specification, Revision 4.0. Refer to the specification for timing details. For more details about features and additional description information on the device Peripheral Component Interconnect Express, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description. For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals chapter in the device TRM.

6.9.5.23 Timers

For more details about features and additional description information on the device Timers, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-99 represents Timers timing conditions. Table 6-99. Timers Timing Conditions PARAMETER DESCRIPTION MODE MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate CAPTURE 0.5 5 V/ns www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 285 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 6-99. Timers Timing Conditions (continued) PARAMETER DESCRIPTION MODE MIN MAX UNIT OUTPUT CONDITIONS CL Output load capacitance PWM 2 10 pF Timers.

6.9.5.23.1 Timing Requirements for Timers

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T1 tw(TINPH) Pulse duration, high CAPTURE 2.5 + (1) ns T2 tw(TINPL) Pulse duration, low CAPTURE 2.5 + (1) ns (1) P = functional clock period in ns.

6.9.5.23.2 Switching Characteristics for Timers

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT T3 tw(TOUTH) Pulse duration, high PWM -2.5 + (1) ns T4 tw(TOUTL) Pulse duration, low PWM -2.5 + (1) ns (1) P = functional clock period in ns. T1 T2 TIMER_IOx (inputs) TIMER_01 T3 T4 TIMER_IOx (outputs) Figure 6-119. Timer Timing For more information, see Timers section in Peripherals chapter in the device TRM.

6.9.5.24 UART

For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within , Section 5.3, Signal Descriptions and Section 7, Detailed Description. Table 6-100 represents UART timing conditions. Table 6-100. UART Timing Conditions PARAMETER DESCRIPTION MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 30 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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characteristics for UART interface.

6.9.5.24.1 Timing Requirements for UART

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT 4 tw(rxd) Pulse width, receive data bit, high or low 0.95U (1) 1.05U (1) ns 5 tw(rxdS) Pulse width, receive start bit, low 0.95U (1) ns (1) U = UART baud time = 1/Programmed baud rate

6.9.5.24.2 UART Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT fop(baud) Maximum programmable baud rate 15 pF 12 MHz 30 pF 0.115 1 td(ctsnL-txdV) Delay time, receive CTSn bit to transmit data 30 ns 2 tw(txd) Pulse width, transmit data bit, high or low U - 2 (1) U + 2 (1) ns 3 tw(txdS) Pulse width, transmit start bit, low U - 2 (1) ns (1) U = UART baud time = 1/Programmed baud rate Figure 6-120. UART Timing For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter in the device TRM.

6.9.5.25 USB

The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0. Refer to the specification for timing details. For more details about features and additional description information on the device Universal Serial Bus Subsystem (USB), see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 287 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

6.9.6 Emulation and Debug

6.9.6.1 Trace

Table 6-101. Trace Timing Conditions PARAMETER MIN MAX UNIT OUTPUT CONDITIONS CL Output load capacitance 2 5 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Mismatch) Propagation delay mismatch across all traces 200 ps Table 6-102 and Figure 6-121 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-102. Trace Switching Characteristics NO. PARAMETER MIN MAX UNIT

1.8 V Mode

DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 6.50 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 2.50 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 2.50 ns DBTR4 tosu(TRC_DATAV-TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 0.81 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 0.81 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 0.81 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 0.81 ns

3.3 V Mode

DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 9.75 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 4.13 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 4.13 ns DBTR4 tosu(TRC_DATAV-TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.22 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.22 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.22 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.22 ns TRC_DATA TRC_CTL TRC_CLK ( ) ( ) (Ideal) Worst Case 1 Worst Case 2 DBTR1 DBTR2 DBTR3 DBTR4 DBTR6 DBTR5 DBTR7 DBTR4 DBTR6 DBTR5 DBTR7 SPRSP08_Debug_01 Figure 6-121. Trace Switching Characteristics

6.9.6.2 JTAG

For more details about features and additional description information on the device IEEE 1149.1 Standard– Test–Access Port, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 6-103. JTAG Timing Conditions PARAMETER MIN MAX UNIT Input Conditions SRI Input slew rate 0.25 2.00 V/ns Output Conditions CL Output load capacitance 5 15 pF

6.9.6.2.1 JTAG Electrical Data and Timing

conditions and electrical characteristic conditions. See Figure 6-122 NO. MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 100 ns J2 tw(TCKH) Pulse width minimum, TCK high 40 ns J3 tw(TCKL) Pulse width minimum, TCK low 40 ns tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 13 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 13 ns th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 7.7 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 7.7 ns 1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in this table only apply when the two IO power domains are operating at the same voltage. Values for these timing parameters are not defined when operating the two IO power domains at different voltages since propagation delay through the device IO buffers differ when some are operating at 1.8V while others are operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG interface is still expected to function when the two IO power domains are operated at different voltages, assuming the system designer has implemented appropriate level shifters and the operating frequency is reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different voltages. See Figure 6-122 NO. PARAMETER MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 37.75 ns 1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in this table only apply when the two IO power domains are operating at the same voltage. Values for these timing parameters are not defined when operating the two IO power domains at different voltages since propagation delay through the device IO buffers differ when some are operating at 1.8V while others are operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG interface is still expected to function when the two IO power domains are operated at different voltages, assuming the system designer has implemented appropriate level shifters and the operating frequency is reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different voltages. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 289 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Figure 6-122. JTAG Timing Requirements and Switching Characteristics DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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7 Detailed Description

7.1 Overview

DRA829 Jacinto™ 7 processors, based on the Arm®v8 64-bit architecture, provide advanced system integration to enable lower system costs of applications such as Infotainment, Cluster, Premium Audio, and Gateway . The integrated diagnostics and functional safety features are targeted to ASIL-B/C certification/requirements. The integrated microcontroller (MCU) island eliminates the need for an external system MCU. The device features a Gigabit Ethernet switch and a PCIe hub which enables networking use cases that require heavy data bandwidth. The hardware accelerators allow for vision pre-processing, distance and motion processing with minimal impact on system performance. Up to six Arm ® Cortex®-R5F subsystems manage low level, timing critical processing tasks leaving the Arm ® Cortex®-A72’s unencumbered for applications. A dual-core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Note For more information on features, subsystems, and architecture of superset device System on Chip (SoC), see the device TRM. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 291 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

7.2 Processor Subsystems

7.2.1 Arm Cortex-A72

The device implements one dual-core Arm® Cortex®-A72 MPU, which is integrated inside the Compute Cluster, along with other modules. The Cortex-A72 cores are general-purpose processors that can be used for running customer applications. The A72SS is built around the Arm Cortex-A72 MPCore (A72 cluster), which is provided by Arm and configured by TI. It is based on the symmetric multiprocessor (SMP) architecture, and thus it delivers high performance and optimal power management and debug capabilities. The A72 processor is a multi-issue out-of-order superscalar execution engine with integrated L1 instruction and data caches, compatible with Armv8-A architecture. The Armv8-A architecture brings a number of new features. These include 64-bit data processing, extended virtual addressing and 64-bit general purpose registers. For more information, see Dual-A72 MPU Subsystem section in Processors and Accelerators chapter in the device TRM.

7.2.2 Arm Cortex-R5F

The MCU_ARMSS is a dual-core implementation of the Arm ® Cortex®-R5F processor configured for split/lock operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm ® CoreSight™ debug and trace architecture, integrated Vectored Interrupt Manager (VIM), ECC Aggregators, and various wrappers for protocol conversion and address translation for easy integration into the SoC. For more information, see Dual-R5F MCU Subsystem section in Processors and Accelerators chapter in the device TRM.

7.2.3 DSP C71x

The TMS320C71x is the next-generation fixed and floating-point DSP platform. The C71x DSP is a new core in the Texas Instruments' DSP family. The C71x DSP supports vector signal processing, providing significant lift in DSP processing power over a broad range of general signal processing tasks in comparison to the C6x DSP family. In addition, the C71x provides several specialized functions which accelerate targeted functions by more than 30 times. Besides expanding vector processing capabilities, the new C71x core also incorporates advanced techniques to improve control code efficiency and ease of programming such as branch prediction, protected pipeline, precise exception and virtual memory management. For more information, see C71x DSP Subsystem section in Processors and Accelerators chapter in the device TRM.

7.2.4 DSP C66x

The C66x subsystem is based on the TI's standard TMS320C66x ™ DSP CorePac module. It includes subsystem logic to ease the C66x CorePac integration into the SoC, while maximizing software reuse from previous devices. The C66x DSP extends the performance of the C64x+ and C674x DSPs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data. On C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. The C66x DSP can execute instructions that operate on 128-bit vectors. For example, the QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (for example, execution of up to eight instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler. For more information, see C66x DSP Subsystem section in Processors and Accelerators chapter in the device TRM. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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7.3 Accelerators and Coprocessors

7.3.1 GPU

The Graphics Processing Unit (GPU) accelerates 3-dimensional (3D) and 2-dimensional (2D) graphics and compute applications. The GPU module is a scalable architecture which efficiently processes a number of different workload concurrently:

• 3D Graphic Workload, which involves vertex data and pixel data processing for rendering of 3D scenes.
• 2D Graphic Workload, which involves pixel data processing for rendering 2D objects.
• Compute Applications Workload, which involves general purpose data processing. For more information, see Graphics Accelerator (GPU) section in Processors and Accelerators chapter in the device TRM.

7.3.2 D5520MP2

The DECODER module is a D5520MP2 dual-core PowerVR® VPU (video processor unit). The D5520MP2 is capable of supporting:

• 1x 4kp60 decode or
• 2x 4kp30 decodes or
• 4x 1080p60 decodes or
• 8x 1080p30 decodes For more information, see Multi-Standard HD Video Decoder (D5520MP2) section in Processors and Accelerators chapter in the device TRM.

7.3.3 VXE384MP2

The ENCODER module is a VXE384MP2 core PowerVR® VPU (video processor unit). The VXE384MP2 is capable of supporting:

• 1x 1080p60 video stream encoding or
• 2x or 3x 1080p30 video stream encodings For more information, see Multi-Standard HD Video Encoder (VXE384MP2) section in Processors and Accelerators chapter in the device TRM. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 293 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

7.4 Other Subsystems

7.4.1 MSMC

The Multicore Shared Memory Controller (MSMC) forms the heart of the compute cluster (COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected processing elements and the rest of the system. MSMC serves as the data-movement backbone of the compute cluster. For more information, see Multicore Shared Memory Controller (MSMC) section in Device Configuration chapter in the device TRM.

7.4.2 NAVSS

7.4.2.1 NAVSS0

Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA and Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), Virtualization translation (VirtSS), and a North Bridge (NBSS).

7.4.2.2 MCU_NAVSS

MCU Navigator Subsystem (MCU NAVSS) has a subset of the modules of the main NAVSS and is instantiated in the MCU domain. MCU Navigator Subsystem consists of DMA/Queue Management components – UDMA and Ring Accelerator (UDMASS), and Peripherals (Module subsystem [MODSS]). For more information, see Main Navigator Subsystem (NAVSS) and MCU Navigator Subsystem (MCU NAVSS) sections in Data Movement Architecture (DMA) chapter in the device TRM.

7.4.3 PDMA Controller

The Peripheral DMA is a simple DMA which has been architected to specifically meet the data transfer needs of peripherals, which perform data transfers using memory mapped registers accessed via a standard non-coherent bus fabric. The PDMA module is intended to be located close to one or more peripherals which require an external DMA for data movement and is architected to reduce cost by using VBUSP interfaces and supporting only statically configured Transfer Request (TR) operations. The PDMA is only responsible for performing the data movement transactions which interact with the peripherals themselves. Data which is read from a given peripheral is packed by a PDMA source channel into a PSI-L data stream which is then sent to a remote peer UDMA-P destination channel which then performs the movement of the data into memory. Likewise, a remote UDMA-P source channel fetches data from memory and transfers it to a peer PDMA destination channel over PSI-L which then performs the writes to the peripheral. The PDMA architecture is intentionally heterogeneous (UDMA-P + PDMA) to right size the data transfer complexity at each point in the system to match the requirements of whatever is being transferred to or from. Peripherals are typically FIFO based and do not require multi-dimensional transfers beyond their FIFO dimensioning requirements, so the PDMA transfer engines are kept simple with only a few dimensions (typically for sample size and FIFO depth), hardcoded address maps, and simple triggering capabilities. Multiple source and destination channels are provided within the PDMA which allow multiple simultaneous transfer operations to be ongoing. The DMA controller maintains state information for each of the channels and employs round-robin scheduling between channels in order to share the underlying DMA hardware. For more information, see PDMA Controller section in DMA Controllers chapter in the device TRM.

7.4.4 Power Supply

The device requires 6 power supply types and 1 internal LDO connection type, see Power Supply Signal Descriptions:

• Digital IO Voltages
• Digital Low Voltages DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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• Digital AVS Voltage
• Analog PHY & CLK Voltages
• Analog Low Voltages
• Efuse Programming Voltages
• LDO Bulk Filter Capacitors Common device power supply input types can be grouped together into power rails. All power rails must be supplied by power resources designed to support the most strigent power supply voltage specification and total load current demands. Two recommended Power Distribution Networks (PDNs) have been defined that either combine or isolate MCU and Main domains, (refer to Section 8.1, Power Supply Mapping). It is possible that a few power supply inputs may not be needed in some systems. In such cases, all unused supply inputs, other than VPP_CORE & VPP_MCU, must be connected to a valid power rail with a proper voltage level in order to ensure device reliability (refer to Section 6.4, Recommended Operating Conditions). The following examples are given for reference: 1. If MCU Island safety monitor or MCU Only low power processing are not used, then VDD_MCU supply can be combined with the VDD_CORE supply with compatible operating voltage specification. 2. If UHS-I SD Card or USB2.0 interface is not needed, then VDDSHV5 (MMC1 interface) and VDDA_USB_3P3 (USB PHY interface) can be combined with VDD_IO_3V3 digital IO power rail. 3. If General Purpose device type is used, then Efuse programming voltages VPP_CORE & VPP_MCU are not needed and should be left unconnected.

7.4.5 Peripherals

7.4.5.1 ADC

The Analog-to-Digital Converter (ADC) module contains a single 12-bit ADC which can be multiplexed to any 1 of 8 analog inputs (channels). For more information, see Analog-to-Digital Converter (ADC) section in Peripherals chapter in the device TRM.

7.4.5.2 ATL

The Audio Tracking Logic (ATL) is used by HD Radio ™ applications to synchronize the digital audio output to the baseband clock. This same IP can also be used generically to track errors between two reference signals (such as frame syncs) and generate a modulated clock output (using software-controlled cycle stealing) which averages to some desired frequency. This process can be used as a hardware assist for asynchronous sample rate conversion algorithms. For more information, see Audio Tracking Logic (ATL) section in Peripherals chapter in the device TRM.

7.4.5.3 CSI

7.4.5.3.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)

The integration of the CSI_RX_IF module allows the device to stream video inputs from multiple cameras to internal memory. The video input may also be retransmitted via the transmitter CSI (CSI_TX_IF) for debug and test purposes. For more information, see Camera Streaming Interface (CSI) section in Peripherals chapter in the device TRM.

7.4.5.3.2 Camera Streaming Interface Transmitter (CSI_TX_IF)

The integration of the CSI_TX_IF module allows the device to stream out video data from memory, or retransmit from the CSI receivers as an optional loopback output for diagnostics, debug, and test purposes. For more information, see Camera Streaming Interface (CSI) section in Peripherals chapter in the device TRM.

7.4.5.4 CPSW2G

The two-port Gigabit Ethernet MAC (MCU_CPSW0) subsystem provides Ethernet packet communication for the device and is configured in a similar manner as an Ethernet switch. MCU_CPSW0 features the Reduced Gigabit www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 295 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.

7.4.5.5 CPSW9G

The 9-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the device and can be configured as an Ethernet switch. CPSW0 features the Serial Gigabit Media Independent Interface (SGMII), Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII) and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management. For more information, see Gigabit Ethernet Switch (MCU_CPSW0) section in Peripherals chapter in the device TRM.

7.4.5.6 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency. The desired accuracy can be programed based on calculation for each application. The DCC measures the frequency of a selectable clock source using another input clock as a reference. For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.

7.4.5.7 DDRSS

The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC, and not directly through the system interconnect. For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.

7.4.5.8 DSS

The DSS is a flexible composition-enabled display subsystem, that supports multiple high resolution display outputs. It consists of one Display Controller (DISPC) and one Frame Buffer Decompression Core (FBDC). The DISPC supports a multi-layer blending and transparency for each of its display outputs. The DISPC also supports a write-back pipeline with scaling to enable memory-to-memory composition and/or to capture a display output for Ethernet video encoding. For more information, see Display Subsystem (DSS) section in Peripherals chapter in the device TRM.

7.4.5.8.1 DSI

The MIPI DSI v1.3.1 Controller (DSITX) implements the stream arbitration and low-level protocol layer functionalities required by MIPI DSI 1.3 standard. It supports up to 4 x 2.5 Gbps D-PHY data lanes in a single- link configuration and handles the byte lane mapping per use case (1, 2, 3, or 4-lanes). The accompaning DSI (Physical Layer) D-PHY module (DPHYTX) provides the video output interfacing by implementing a four-lane MIPI D-PHY transmitter. For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in the device TRM. 7.4.5.8.2 eDP The VESA DP1.4/eDP1.4 Compliant Transmitter Host Controller (EDP) can output up to 4 video streams (through Multiple Stream Transport / MST) and one audio stream through the 4-lane accompaning SerDes module. It provides up to 25.92 Gbps of application bandwidth. An additional eDP (Physical Layer) auxiliary PHY (AUXPHY) module implements a doubly-terminated differential pair required for 1 Mbps data rates over a long (15m) cable. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in the device TRM.

7.4.5.9 VPFE

The Video Processing Front End (VPFE) is an input interface module that receives raw (unprocessed) image/ video data or YUV digital video data from external imaging peripherals (such as image sensors, video decoders, etc) and performs DMA transfers to store the captured data in the system DDR memory. For more information, see Video Processing Front End (VPFE) section in Peripherals chapter in the device TRM. 7.4.5.10 eCAP The enhanced Capture (ECAP) module can be used for:

• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors. For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.

7.4.5.11 EPWM

An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention. It needs to be highly programmable and very flexible while being easy to understand and use. The EPWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided; instead, the EPWM is built up from smaller single channel modules with separate resources and that can operate together as required to form a system. This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand its operation quickly. In the further description the letter x within a signal or module name is used to indicate a generic EPWM instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the EPWM_x instance. Thus, EPWM1A and EPWM1B belong to EPWM1, EPWM2A and EPWM2B belong to EPWM2, and so forth. Additionally, the EPWM integration allows this synchronization scheme to be extended to the capture peripheral modules (ECAP). The number of modules is device-dependent and based on target application needs. Modules can also operate stand-alone. For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in the device TRM.

7.4.5.12 ELM

The Error Location Module (ELM) is used with the GPMC. Syndrome polynomials generated on-the-fly when reading a NAND flash page and stored in GPMC registers are passed to the ELM. A host processor can then correct the data block by flipping the bits to which the ELM error-location outputs point. When reading from NAND flash memories, some level of error-correction is required. In the case of NAND modules with no internal correction capability, sometimes referred to as bare NANDs, the correction process is delegated to the memory controller. ELM can be also used to support parallel NOR flash or NAND flash. For more information, see Error Location Module (ELM) section in Peripherals chapter in the device TRM.

7.4.5.13 ESM

The Error Signaling Module (ESM) aggregates safety-related events and/or errors from throughout the device into one location. It can signal both low and high priority interrupts to a processor to deal with a safety event and/or manipulate an I/O error pin to signal an external hardware that an error has occurred. Therefore an external controller is able to reset the device or keep the system in safe, known state. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 297 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

For more information, see Error Signaling Module (ESM) section in Peripherals chapter in the device TRM. 7.4.5.14 eQEP The Enhnanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary incremental encoder to get position, direction and speed information from a rotating machine for use in high performance motion and position control system. The disk of an incremental encoder is patterned with a single track of slots patterns. These slots create an alternating pattern of dark and light lines. The disk count is defined as the number of dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an absolute position. Encoder manufacturers identify the index pulse using different terms such as index, marker, home position and zero reference. For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter in the device TRM.

7.4.5.15 GPIO

The General-Purpose Input/Output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an output, the user can write to an internal register to control the state driven on the output pin. When configured as an input, user can obtain the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce host CPU interrupts and DMA synchronization events in different interrupt/event generation modes. For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

7.4.5.16 GPMC

The General-Purpose Memory Controller is a unified memory controller dedicated for interfacing with external memory devices like:

• Asynchronous SRAM-like memories and application-specific integrated circuit (ASIC) devices
• Asynchronous, synchronous, and page mode (available only in non-multiplexed mode) burst NOR flash devices
• NAND flash
• Pseudo-SRAM devices For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the device TRM.

7.4.5.17 Hyperbus

The Hyperbus module is a part of the device Flash Subsystem (FSS). The Hyperbus module is low pin count memory interface that provides high read/write performance. The Hyperbus module connects to hyperbus memory (HyperFlash or HyperRAM) and uses simple hyperbus protocol for read and write transactions. There is one Hyperbus ™ module inside the device. The Hyperbus module includes one Hyperbus Memory Controller (HBMC). For more information, see Hyperbus Interface section in Peripherals chapter in the device TRM.

7.4.5.18 I2C

The device contains ten multimaster Inter-Integrated Circuit (I2C) controllers each of which provides an interface between a local host (LH), such as an Arm or a Digital Signal Processor (DSP), and any I 2C-bus-compatible device that connects via the I 2C serial bus. External components attached to the I 2C bus can serially transmit and receive up to 8 bits of data to and from the LH device through the 2-wire I2C interface. Each multimaster I2C module can be configured to act like a slave or master I2C-compatible device. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I 2C compliant open drain buffers, and support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1, I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate open drain, and support fast mode (up to 400 kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1. For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device TRM.

7.4.5.19 I3C

The device contains three Improved Inter-Integrated Circuit (I3C) controllers each of which provides an interface between a local host (LH), such as an Arm, and any I3C-bus-compatible device that connects via the I3C serial bus. For more information, see Improved Inter-Integrated Circuit (I3C) Interface section in Peripherals chapter in the device TRM.

7.4.5.20 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are broadcast to the entire network, which provides for data consistency in every node of the system. The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices can coexist on the same network without any conflict. For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.

7.4.5.21 MCASP

The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as for an inter-component digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component. Although inter-component digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows an easy connection to external DIR components (for example, S/PDIF to I2S format converters). For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device TRM.

7.4.5.22 MCRC Controller

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the integrity of a memory system. A signature representing the contents of the memory is obtained when the contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate the signature for a set of data and then compare the calculated signature value against a predetermined good signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC controller compresses each data being read through CPU read data bus. For more information, see MCRC Controller section in Interprocessor Communication chapter in the device TRM.

7.4.5.23 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 299 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

There are total of eleven MCSPI modules in the device. For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the device TRM.

7.4.5.24 MMC/SD

The MMCSD Host Controller provides an interface to eMMC 5.1 (embedded MultiMedia Card), SD 4.10 (Secure Digital), and SDIO 4.0 (Secure Digital IO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking for syntactical correctness. For more information, see Multimedia Card/Secure Digital (MMC/SD) Interface section in Peripherals chapter in the device TRM.

7.4.5.25 OSPI

The Octal Serial Peripheral Interface (OSPI ™) module is a kind of Serial Peripheral Interface (SPI) module which allows single, dual, quad or octal read and write access to external flash devices. The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor wishing to execute code directly from external flash memory), or in an indirect mode where the module is set-up to silently perform some requested operation, signaling its completion via interrupts or status registers. For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device TRM.

7.4.5.26 PCIE

The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps per lane for serial links on backplanes and printed wiring boards. For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals chapter in the device TRM.

7.4.5.27 SerDes

SerDes'es goal is to convert device (SoC) parallel data into serialized data that can be output over a highspeed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can be processed by the device. To this end, the SerDes contains a variety of functional blocks to handle both the external analog interface as well as the internal digital logic. For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.

7.4.5.28 WWDT

The Windowed Watchdog Timer provides timer functionality for operating systems and for benchmarking code. The module incorporates several counters, which define the timebases needed for scheduling in the operating system. The module is implemented with an RTI module, but only WWDT is supported. This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for Automotive Electronics”) as well as OSEK/Time compliant operating systems. For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.

7.4.5.29 Timers

All timers include specific functions to generate accurate tick interrupts to the operating system. Each timer can be clocked from several different independent clocks. The selection of clock source is made from registers in the MCU_CTRL_MMR0/CTRL_MMR0. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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In the MCU domain the device provides 10 timer pins to be used as MCU Timer Capture inputs or as MCU Timer PWM outputs. In order to provide maximum flexibility, these 10 pins may be used with any of MCU_TIMER0 through MCU_TIMER9 instances. System level muxes are used to control the capture source pin for each MCU_TIMER[9-0] and the MCU_TIMER[9-0] source for each MCU_TIMER_IO[1-0] PWM output. In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER19 instances. System level muxes are used to control the capture source pin for each TIMER[19-0] and the TIMER[19-0] source for each TIMER_IO[7-0] PWM output. Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc. When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-bit prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter. For more information, see Timers section in Peripherals chapter in the device TRM.

7.4.5.30 UART

The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There are twelve UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral devices or interprocessor communication between devices. For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter in the device TRM.

7.4.5.31 USB

Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange between a host device and a wide range of simultaneously accessible peripherals. The device supports two identical USB subsystems:

• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY and HS/FS/LS (1) (USB2.0) PHY
• USB3SS1 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY and HS/FS/LS (USB2.0) PHY For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device TRM.

7.4.5.32 UFS

The Universal Flash Storage (UFS) interface is a standard-based serial interface engine. There is one UFS module inside the device - UFS0. The UFS module includes one UFS 2.1 host controller (HC) with an integrated M-PHY. The UFS module complies with the standards as listed in Table 7-1. Table 7-1. UFS Standards DOCUMENT VERSION DESCRIPTION JESD220-1A v1.1 Universal Flash Storage (UFS) Unified Memory Extension JESD220-2 v1.0 Universal Flash Storage (UFS) Card Extension JESD220C v2.1, March 2016 Universal Flash Storage (UFS) JESD223-1B v1.1A Universal Flash Storage Host Controller Interface (UFSHCI) Unified Memory Extension JESD223C v2.1, March 2016 Universal Flash Storage Host Controller Interface (UFSHCI) www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 301 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 7-1. UFS Standards (continued) DOCUMENT VERSION DESCRIPTION JESD224 March 2013 Universal Flash Storage (UFS) Test November, 2001 Federal Information Processing Standards (FIPS) 197 Advanced Encryption Standard (AES) v3.1, 2014 MIPI® Alliance Specification for M-PHY v1.60, 2013 MIPI Alliance Specification for Unified Protocol (UniProSM) Revision 24, August 2010 Small Computer System Interface (SCSI) Block Commands - 3 Revision 27, October 2010 SCSI Primary Commands - 4 For more information, see Universal Flash Storage (UFS) Interface section in Peripherals chapter in the device TRM. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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8 Applications and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Power Supply Mapping

This Jacinto 7TM processor device can be operated in several different modes of operation depending upon the number of power resources, power supply groups (i.e. power rails) and control signals available:

• Full Active
• MCU Only low power mode
• DDR Retention (Suspend-to-RAM or S2R) low power mode
• MCU Island safety monitor
• Extended MCU safety monitor Two power distribution networks (PDNs) that support these different operational modes are recommended and provide optional end product features. To name a few:
• Dual Voltage (1.8V & 3.3V) IO Interfaces
• Compliant UHS-I SD Card
• Compliant USB2.0
• High Security device type Efuse programming on-board for in-field updates An Isolated PDN provides independent MCU & Main power resources & rails (see Table 8-2) to support power rail Freedom From Interference (FFI) as desired to reach end product system functional safety targets. An isolated PDN is needed to support MCU Only lower power mode or MCU Island safety monitoring. MCU ONLY can significantly reduce device power by disabling all Main processing while only keeping MCU processor resources active. A Combined PDN reduces total number of power resources & rails by grouping MCU & Main supplies into common power rails (see Table 8-1). This PDN can be used for Extended MCU safety processing but does not allow for MCU Island safety monitor or MCU Only low power modes. The DDR Retention low power mode can be supported with either an Isolated or Combined PDN scheme. The TPS6594x & LP8764x Power Management ICs (PMICs) are key power components in the two recommended PDNs. Additional discrete power components may be added as desired to support optional system features. TI has optimized recommended PDNs using these PMICs for the following reasons:
• Full device performance entitlement as validated on TI Evalution boards
• Enable all system functional safety features and analysis captured in device safety manual
• Support power rail load steps, supply voltage accuracies and maximum load currents with margins
• Meet device primary & low power mode supply sequencing requirements (refer to Section 6.9.2, Power Supply Sequencing)
• Provide Adaptive Voltage Scaling (AVS) Class 0 device requirements with TI validated software For full PDN design and operational details, refer to either 1. “Dual TPS6594-Q1 PMIC User Guide for Jacinto 7TM DRA829 and TDA4VM Automotived PDN-0B (SLVUC32)” for legacy designs aligned to original EVM PDN-0A wishing to minimize SCH & PCB updates 2. “Dual TPS6594-Q1 PMIC User Guide for Jacinto 7TM DRA829 and TDA4VM Automotived PDN-0C (SLVUC99)" for all new designs www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 303 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 8-1. Combined MCU and Main Voltage Domain Power Rail Mapping TYPES VOLTAGE [V] DOMAIN NAMES DOMAIN GROUPS POWER RAILS # Digital IO 3.3 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0,VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV53, VDDSHV6)1, VDDA_3P3_USB4 VDDSHVn_MC U,VDDSHVn, VDDA_3P3_US VDD_IO_3V3 1 Digital IO 1.8 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU, VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV, VDDSHV4, VDDSHV53, VDDSHV6)2 VDDSHVn_MC U2 VDDSHVn3 2 VDD_IO_1V8 2 Digital IO 1.8 VDDS_MMC06 VDDS_MMC06 VDDS_MMC0_1V86 3 Analog PHY 1.8 (VDDA_1P8_CSIRX, VDDA_1P8_USB, VDDA_1P8_UFS, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES) VDDA_1P8_<p hy>5 VDD_PHY_1V85 4 Analog Clk, Meas 1.8 VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP VDDS_OSC1, VDDA_PLLGRP6:0, VDDA_TEMP3:0 VDDA_1P8_<cl k/meas> VDA_LN_1V8 5 Analog, low voltage 0.80 VDDA_0P8_PLL_MLB, VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0 VDDA_0P8_DP LL VDA_DPLL_0V8 6 Digital, AVS low voltage 0.77 – 0.84 VDD_CPU VDD_CPU VDD_CPU_AVS 7 Digital, low voltage 0.80 VDD_MCU7, VDD_CORE, (VDDA_0P8_SERDES, VDDA_0P8_SERDES_C, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB) 8 VDD_MCU VDD_CORE VDDA_0P8_<p hy>8 VDD_PROC_0V8 8 Digital, low voltage 0.85 VDDAR_MCU, VDDAR_CORE, VDDAR_CPU VDDAR VDD_RAM_0V85 9 Digital, low voltage 1.1 VDDS_DDR_BIAS, VDDS_DDR, VDDS_DDR_C VDDS_DDR VDD_DDR_1V1 10 1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces 2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces 3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail. 4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter. 5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed. 6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0 interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached Vopr min. 7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility, enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains (VDDAR_xxx). 8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance. Table 8-2. Isolated MCU and Main Voltage Domain Power Rail Mapping TYPES VOLTAGE [V] DOMAIN NAMES DOMAIN GROUPS POWER RAILS # Digital IO 3.3 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)1 VDDSHVn_MC U VDD_MCUIO_3V3 1 Digital IO 3.3 (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV53, VDDSHV6)1, VDDA_3P3_USB4 VDDSHVn, VDDA_3P3_US VDD_IO_3V3 2 Digital IO 1.8 (VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2_MCU)2 VDDSHVn_MC U2 VDD_MCUIO_1V8 3 Digital IO 1.8 (VDDSHV0, VDDSHV1, VDDSHV2, VDDSHV3, VDDSHV4, VDDSHV53, VDDSHV6)2 VDDSHVn2 3 VDD_IO_1V8 4 Digital IO 1.8 VDDS_MMC06 VDDS_MMC06 VDDS_MMC0_1V86 5 Analog Clk, Meas 1.8 VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_ADC_MCU, VDDA_POR_WKUP, VDDA_WKUP VDDA_MCU1P 8_<clk/meas> VDA_MCU_1V8 6 Analog Clk, Meas 1.8 VDDS_OSC1, VDDA_PLLGRP6:0, VDDA_TEMP3:0 VDDA_1P8_<cl k/meas> VDA_DPLL_1V8 7 Analog PHY 1.8 (VDDA_1P8_CSIRX, VDDA_1P8_USB, VDDA_1P8_UFS, VDDA_1P8_DP, VDDA_1P8_DSITX, VDDA_1P8_MLB, VDDA_1P8_SERDES)5 VDDA_1P8_<p hy>5 VDA_PHY_1V85 8 Analog, low voltage 0.80 VDDA_0P8_PLL_MLB, VDDA_0P8_PLL_DDR, VDDA_0P8_DLL_MMC0 VDDA_0P8_DP LL VDA_DPLL_0V8 9 Digital, low voltage 0.80 VDD_MCU, VDDAR_MCU VDD_MCU, VDDAR_MCU VDD_MCU_0V85 10 Digital, AVS low voltage 0.77 – 0.84 vdd_cpu VDD_CPU VDD_CPU_AVS 11 www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 305 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Table 8-2. Isolated MCU and Main Voltage Domain Power Rail Mapping (continued) TYPES VOLTAGE [V] DOMAIN NAMES DOMAIN GROUPS POWER RAILS # Digital, low voltage

0.80 VDD_CORE,

(VDDA_0P8_SERDES, VDDA_0P8_SERDES_C, VDDA_0P8_DP, VDDA_0P8_DP_C, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C, VDDA_0P8_CSIRX, VDDA_0P8_UFS, VDDA_0P8_USB)8 VDD_CORE, VDDA_0P8_<p hy>8 VDD_CORE_0V8 12 Digital, low voltage

0.85 VDDAR_CORE, VDDAR_CPU VDDAR VDD_RAM_0V85 13

Digital, low voltage

1.1 VDDS_DDR_BIAS,VDDS_DDR,

VDDS_DDR_C VDDS_DDR VDD_DDR_1V1 14 1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to support 3.3V digital interfaces 2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to support 1.8V digital interfaces 3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed 3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail. 4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO power rail either directly or through a supply filter. 5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed. 6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0 interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0 interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached VOPR MIN. 7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility, enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains (VDDAR_xxx). 8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply for optimal performance.

8.2 Device Connection and Layout Fundamentals

8.2.1 Power Supply Decoupling and Bulk Capacitors

8.2.1.1 Power Distribution Network Implementation Guidance

The Jacinto 7 Processor Power Distribution Networks: Implementation and Analysis (SPRACN5) provides guidance for successful implementation of the power distribution network. This includes PCB stackup guidance as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only designs that follow the board design guidelines contained in the application report.

8.2.2 External Oscillator

For more information, see Section 6.9.4.1, Input and output Clocks/Oscillators. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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8.2.3 JTAG and EMU

Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target Connection Guide. For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual

8.2.4 Reset

The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESET_REQz) and four reset status pins (MCU_PORz_OUT, MCU_RESETSTATz, PORz_OUT, and RESETSTATz). These pins can be driven by an external power good circuitry or Power Management IC (PMIC). MCU_PORz and Main PORz pins should be held active low during the entire power-up phase, and until all power supplies as well as the HFOSC0 clock are stable. All MCU domain resets act as master resets to the whole device, whereas Main domain resets only reset Main domain (MCU domain is reset isolated from all Main domain resets).

8.2.5 Unused Pins

For more information about Unused Pins, see Connections for Unused Pins

8.2.6 Hardware Design Guide for JacintoTM 7 Devices

The Hardware Design Guide for JacintoTM 7 Devices document describes hardware system design considerations for the JacintoTM 7 family of processors.This design guide is intended to be used as an aid during the development of application hardware. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 307 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

8.3 Peripheral- and Interface-Specific Design Information

8.3.1 LPDDR4 Board Design and Layout Guidelines

The goal of the Jacinto 7 LPDDR4 Board Design and Layout Guidelines is to make the LPDDR4 system implementation straightforward for all designers. Requirements have been distilled down to a set of layout and routing rules that allow designers to successfully implement a robust design for the topologies that TI supports. TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.

8.3.2 OSPI and QSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI and QSPI interfaces.

8.3.2.1 No Loopback and Internal Pad Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm as stripline or ~8cm as microstrip)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-1
• Propagation delays and matching: – A to B < 450 ps – Matching skew: < 60 ps A B MCU_OSPI[x]_CLK OSPI/QSPI/SPI device clock input OSPI/QSPI/SPI device IOy, CS# MCU_OSPI[x]_D[y], MCU_OSPI[x]_CSn[z] 0 * Ω OSPI_Board_01 * 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed. Figure 8-1. OSPI Interface High Level Schematic

8.3.2.2 External Board Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must be approximately equal to the signal propagation delay of the control and data signals between the flash device and the SoC device (E to F, or F to E)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-2
• Propagation delays and matching: – A to B = E to F = (C to D) / 2 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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– Matching skew: < 60 ps Note The OSPI Board Loopback Hold time requirement (described in Section 6.9.5.21, OSPI) is larger than the Hold time provided by a typical flash device. Therefore, the length of MCU_OPSI[x]_LBCLKO pin to the MCU_OSPI[x]_DQS pin (C to D) can be shortened to compensate. A B E F MCU_OSPI[x]_CLK OSPI/QSPI/SPI device clock input OSPI/QSPI/SPI device IOy, CS# MCU_OSPI[x]_D[y], MCU_OSPI[x]_CSn[z] 0 * Ω OSPI_Board_02 C D MCU_OSPI[x]_LBCLKO MCU_OSPI[x]_DQS 0 * Ω * 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK and MCU_OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if needed. Figure 8-2. OSPI Interface High Level Schematic

8.3.2.3 DQS (only available in Octal Flash devices)

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device
• The DQS pin of the flash devices must be connected to MCU_OSPI[x]_DQS signal
• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) should be approximately equal to the signal propagation delay from the MCU_OSPI[x]_DQS pin to the DQS output pin (C to D)
• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-3
• Propagation delays and matching: – A to B = C to D – Matching skew: < 60 ps www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 309 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

MCU_OSPI[x]_CLK OSPI/QSPI/SPI device clock input 0 * Ω J7ES_OSPI_Board_03 C D MCU_OSPI[x]_DQS OSPI device DQS E F OSPI/QSPI/SPI device IOy, CS# MCU_OSPI[x]_D[y], MCU_OSPI[x]_CSn[z] * 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed. Figure 8-3. OSPI Interface High Level Schematic

8.3.3 SERDES REFCLK Design Guidelines

The following section details the routing guidelines that must be observed when terminating the SERDES REFCLK and is applicable only when SERDES REFCLK is configured to input mode. 1. 50 Ω to GND is recommended on each leg. 2. Internal AC coupling is always enabled, so external biasing is not needed.

8.3.4 USB VBUS Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as 20 V when the Power Delivery addendum is supported. Some applications require a max voltage to be 30 V. The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the Figure 8-4), which limits the voltage applied to the actual device pin (USB0_VBUS, USB1_VBUS). The tolerance of these external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V should be less than 100 nA. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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USBn_VBUS J7ES_USB_VBUS_01 VSS VSS 16.6 k Ω 10 k Ω 3.4 k Ω VBUS signal (BZX84C6V8 or equivalent) 6.8V A. USBn_VBUS, where n = 0 or 1. Figure 8-4. USB VBUS Detect Voltage Divider / Clamp Circuit The USB0_VBUS and USB1_VBUS pins can be considered to be fail-safe because the external circuit in Figure 8-4 limits the input current to the actual device pin in a case where VBUS is applied while the device is powered off.

8.3.5 System Power Supply Monitor Design Guidelines

The VMON_ER_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a single pre-regulated power source for the entire system. This supply is monitored by comparing the output of an external voltage divider circuit sourced by this supply with an internal voltage reference, with a power fail event being triggered when the voltage applied to VMON_ER_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point is determined by the system designer when selecting component values used to implement the external resistor voltage divider circuit. When designing the resistor divider circuit it is important to understand various factors which contribute to variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of the VMON_ER_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider. This minimizes variability contributed by resistor value tolerances. Input leakage current associated with VMON_ER_VSYS must also be considered since any current flowing into the pin creates a loading error on the voltage divider output. The VMON_ER_VSYS input leakage current may be in the range of 10 nA to 2.5 μA when applying 0.45 V. Note The resistor voltage divider shall be designed such that its output voltage never exceeds themaximum value defined in Section 6.4 , Recommended Operating Conditions during normal operating conditions. Figure 8-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger threshold is 5 V - 10%, or 4.5 V. For this example, it is important to understand which variables effect the maximum trigger threshold when selecting resistor values. It is obvious a device which has a VMON_ER_VSYS input threshold of 0.45 V + 3% needs to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The effect of resistor tolerance and input leakage also needs to be considered, but how these contributions effect the maximum trigger point may not be obvious. When selecting component values which produce a maximum trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high combined with a condition where input leakage current for the VMON_ER_VSYS pin is 2.5 μA. When implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold of 4.523 V. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 311 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

Once component values have been selected to satisfy the maximum trigger voltage as described above, the system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result is a minimum trigger threshold of 4.008 V. This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V. Approximately 250 mV of this range is introduced by VMON_ER_VSYS input threshold accuracy of ±3%, approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this range is introduced by loading error when VMON_ER_VSYS input leakage current is 2.5 μA. The resistor values selected in this example produces approximately 100 μA of bias current through the resistor divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor divider bias current vs loading error is something the system designer needs to consider when selecting component values. The system designer should also consider implementing a noise filter on the voltage divider output since VMON_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done by installing a capacitor across R1 as shown in Figure 8-5. However, the system designer must determine the response time of this filter based on system supply noise and expected response to transient events. Figure 8-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger threshold is -10% or 4.5 V. Device VMON_VSYS SPRSP56_VMON_ER_MON_01 VSS 4.81 k Ω 40.2 k 1%Ω ± VSYS Value = Determined by system designer (System Power Supply) Figure 8-5. System Supply Monitor Voltage Divider Circuit

8.3.6 High Speed Differential Signal Routing Guidance

The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and spacing limits. TI supports only designs that follow the board design guidelines contained in the application report.

8.3.7 Thermal Solution Guidance

The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful implementation of a thermal solution for system designs containing this device. This document provides background information on common terms and methods related to thermal solutions. TI only supports designs that follow system design guidelines contained in the application report. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, DRA829). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully-qualified development-support product. X and P devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. For orderable part numbers of DRA829 devices in the ALF package type, see the Package Option Addendum of this document, the TI website (ti.com), or contact your TI sales representative.

9.1.1 Standard Package Symbolization

Some devices may have a cosmetic circular marking visible on the top of the device package which results from the production test process. In addition, some devices may also show a color variation in the package substrate which results from the substrate manufacturer. These differences are cosmetic only with no reliability impact. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 313 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

J7ES_SPRSP35_PACK_01 xBBBBBBBBzYrPPPcQ1 PIN ONE INDICATOR O G1YYY ZZZ XXXXXXX Figure 9-1. Printed Device Reference

9.1.2 Device Naming Convention

Table 9-1. Nomenclature Description FIELD PARAMETER FIELD

DESCRIPTION

x Device evolution stage X Prototype P Preproduction (production test flow, no reliability data) BLANK Production BBBBBBBB(1) Base production part number J721E(1) Preproduction superset device DRA829VM See Table 4-1, Device Comparison DRA829JM See Table 4-1, Device Comparison z Device Speed T See Table 6-1, Speed Grade Maximum Frequency) OTHER Alternate speed grade Y Device Type G General purpose (Prototype and Production) C General purpose, R5F Lockstep capable

0 High Security(2) capable

5 High Security (2)capable, R5F Lockstep capable

R High Security Prime(2) capable, R5F Lockstep capable D High Security(2) capable, R5F Lockstep capable, Customer Dev Keys. Only available on preproduction J721E devices. P High Security Prime(2) capable, R5F Lockstep capable, Customer Dev Keys. Only available on preproduction J721E devices. r Device revision A or BLANK SR 1.0 B SR 1.1 C SR 2.0 DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Table 9-1. Nomenclature Description (continued) FIELD PARAMETER FIELD c Carrier Designator N/A BLANK Tray N/A R Tape and Reel Q1 Automotive Designator BLANK Not automotive qualified. Supports TJ = –40°C to 105°C Meet AEC-Q100 qualification requirements, with exceptions as specified in this document (data sheet). Supports TJ = –40°C to 125°C XXXXXXX Lot Trace Code As Marked N/A Lot Trace Code (LTC) YYY Production Code As Marked N/A Production Code, for TI use only ZZZ Production Code As Marked N/A Production Code, for TI use only O Pin One As Marked N/A Pin one designator G1 ECAT As Marked N/A ECAT—Green package designator (1) J721E is the base part number for the preproduction superset device. Software should constrain the features used to match the intended production device. (2) For HS device support, TI recommends the 0, 5, or D device types. The R and P (HS “prime”) device types are not recommended for most applications, as they require extra steps in the manufacturing process and have a higher cost. Note BLANK in the symbol or part number is collapsed so there are no gaps between characters.

9.2 Tools and Software

The following products support development for DRA829 platforms: Development Tools Code Composer Studio ™ Integrated Development Environment Code Composer Studio (CCS) Integrated Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment for embedded developers. Pin mux tool The Pin MUX Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDKs) or used to configure customer's custom software. Version 4 of the Pin Mux utility adds the capability of automatically selecting a mux configuration that satisfies the entered requirements. Power Estimation Tool (PET) Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be applied to further reduce overall power consumption. For a complete listing of development-support tools for the processor platform, visit the Texas Instruments website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 315 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

9.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The following documents describe the DRA829 devices. Technical Reference Manual J721E DRA829/TDA4VM/AM752x Processors Silicon Revisions 2.0, 1.1, and 1.0 Technical Reference Manual Details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the DRA829 family of devices. Errata J721E DRA829/TDA4VM/AM752x Processors Silicon Revisions 2.0, 1.1, and 1.0 Silicon Errata Describes the known exceptions to the functional specifications for the device.

9.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.5 Trademarks

eMMC™ is a trademark of MultiMediaCard Association. HyperBus™ is a trademark of Mobiveil Inc. CoreSight™ is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Code Composer Studio™ and TI E2E™ are trademarks of Texas Instruments. Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. PowerVR® is a registered trademark of Imagination Technologies Limited. PCI-Express® and PCIe® are registered trademarks of PCI-SIG. Secure Digital® is a registered trademark of SD Card Association. MIPI® is a registered trademark of MIPI Alliance, Inc. All trademarks are the property of their respective owners.

9.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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Changes from August 28, 2021 to April 22, 2024 (from Revision J (August 2021) to Revision K (April 2024)) Page

• Global:: Deleted the "Power Consumption Summary" section (was after Section 6.5, Operating Performance
• (Package Information): Updated/Changed the "Device Information" table to "Package Information" table and
• (Device Comparison): Updated/Changed the MSMC capacity for DRA829VM to "8MB". Now both DRA829JM
• (Device Comparison): Moved the "Security Accelerators" row to be group sequenced with the other
• (Pin Attributes): Added the secondary pin multiplexing functions for the DSI and controlled by CTRLMMR
• (Pin Attributes): Added the secondary pin multiplexing functions for the MCU_ADC and controlled by
• (Pin Attributes): Added "The MUXMODE field is not used to select …" footnote for the WKUP_GPIO0_[68:83]
• (Pin Attributes): Added reset states to the BALL RESET STATE column for mmc0_* pins in the Pin Attributes
• (Power Supply Signal Description): Added "±10%" to the "This pin must always be … capacitor to
• (Connections for Unused Pins): Added the "VMON_ER_VSYS" (M26) and "VMON_IR_VEXT" (V19) signals
• (Connections for Unused Pins): Updated/Changed "All VMON and power balls must be …" Note deleting
• (Pin Connectivity Requirements): Updated/Changed the section title (was "Connections for Unused Pins") 147
• (Connectivity Requirements (ALF Package)): Updated/Changed the table title (was "Unused Balls Specific
• (Pin Connectivity Requirements): Added "as a boot source" to the Note specifying MMC1_SDCD and
• (Absolute Maximum Ratings): Moved "VMON_IR_VEXT" and "VMON_ER_VSYS"signals from "Steady State
• Added the "VMON_IR_VEXT" and "VMON_ER_VSYS"signals to the "Fail-safe IO terminals are designed …"
• (Absolute Maximum Ratings): Updated/Changed "JESD78D (Class II)" to " JESD78E (Class II)" in the "For
• (Recommended Operating Conditions): Deleted the "Refer to Power-On-Hour (POH) Limits for limitations."
• (I2C, Open-Drain, Fail-Safe (I2C OD FS) Electrical Characteristics): Updated/Changed the VOL, Output low- www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 317 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

• (I2C OD FS Electrical Characteristics): Defined MAX VIH values for 1.8-V mode and 3.3-V mode and included
• (I2C OD FS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes
• (I2C OD FS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added
• (I2C OD FS Electrical Characteristics): Added associated "I2C Hs-mode is not supported …" footnote to the
• (I2C OD FS Electrical Characteristics): Added associated "The IOL parameter defines …" footnote to the IOL,
• (SDIO Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to
• (SDIO Electrical Characteristics): Added both the MIN and MAX input slew rate value and added associated
• (CSI-2/DSI D-PHY Electrical Characteristics): Deleted the Electrical Characteristics table and added a Note for the CSI-2/DSI D-PHY interfaces electrical characteristics compliance with MIPI D-PHY specifications v1.2
• (LVCMOS Electrical Characteristics): Added the MIN input slew rate value and added associated footnotes to
• (LVCMOS Electrical Characteristics): Added both the MIN and MAX input slew rate value and added
• (LVCMOS Electrical Characteristics): Defined the minimum input slew rate value and added notes to describe
• (WKUP_OSC0 Switching Characteristics – Crystal Mode): Updated/Changed CXIXO, XI to XO Mutual
• (WKUP_LFOSC0 Internal Oscillator Clock Source): Updated/Changed the ESR row UNIT column from "Ω" to
• (LFXOSC Modes of Operation table): Updated/Changed the value of PD_C for BYPASS mode from "X" to
• (DDRSS): Added a bullet below the JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices
• (MMC1/2 - SD/SDIO Interface): Updated/Changed the "OTAPDLYENA, DELAY ENABLE" and
• (OSPI DLL Delay Mapping - DDR Timing Modes): Updated/Changed the DELAY VALUES for both OSPI0
• (Device Naming Convention): Added content to the "Base production part number" Values plus Description DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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• (Documentation Support): Updated/Changed the document titles for both the TRM and Errata to include www.ti.com DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 319 Product Folder Links: DRA829J DRA829J-Q1 DRA829V DRA829V-Q1

11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 SPRSP35K – FEBRUARY 2019 – REVISED APRIL 2024 www.ti.com

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www.ti.com 20-Feb-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRA829JMTGBALFR NRND FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 105 DRA829JMTGBALF 942 DRA829JMTGBALFRQ1 NRND FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 DRA829JMTGBALFQ1 942 DRA829JMTGCALFR ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR DRA829JMTGCALF 942 Samples DRA829JMTGCALFRQ1 ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR DRA829JMTGCALFQ1 942 Samples DRA829VMTGBALFR NRND FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 105 DRA829VMTGBALF 942 DRA829VMTGBALFRQ1 NRND FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 DRA829VMTGBALFQ1 942 DRA829VMTGCALFR ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR DRA829VMTGCALF 942 Samples DRA829VMTGCALFRQ1 ACTIVE FCBGA ALF 827 250 RoHS & Green Call TI Level-3-250C-168 HR DRA829VMTGCALFQ1 942 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

www.ti.com 20-Feb-2025 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DRA829J, DRA829J-Q1, DRA829V, DRA829V-Q1 :

• Catalog : DRA829J , DRA829V
• Automotive : DRA829J-Q1 , DRA829V-Q1 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRA829JMTGBALFR FCBGA ALF 827 250 336.6 336.6 53.2 DRA829JMTGBALFRQ1 FCBGA ALF 827 250 336.6 336.6 53.2 DRA829JMTGCALFR FCBGA ALF 827 250 336.6 336.6 53.2 DRA829JMTGCALFRQ1 FCBGA ALF 827 250 336.6 336.6 53.2 DRA829VMTGBALFR FCBGA ALF 827 250 336.6 336.6 53.2 DRA829VMTGBALFRQ1 FCBGA ALF 827 250 336.6 336.6 53.2 DRA829VMTGCALFR FCBGA ALF 827 250 336.6 336.6 53.2 DRA829VMTGCALFRQ1 FCBGA ALF 827 250 336.6 336.6 53.2 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 22.4 TYP

22.4 TYP

0.8 TYP

835X 0.45-0.55

2.8 MAX

0.5

0.3 TYP

B 24.1 23.9 A 24.1 23.9 (0.8) TYP (0.8) TYP ( 20) ( 18) FCBGA - 2.8 mm max heightALF0827A PLASTIC BALL GRID ARRAY 4224732/B 02/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Pb-Free die bump and Pb-Free solder ball. BALL A1 CORNER SEATING PLANE BALL TYP 0.15 C C E G J L N R U W AA AC AE AG

0.15 C A B

0.08 C SYMM SYMM BALL A1 CORNER D F H K M P T V Y AB AD AF A AJ B AH SCALE 0.650

www.ti.com EXAMPLE BOARD LAYOUT (0.8) TYP ( 0.4) METAL

0.07 MAX

( 0.4) SOLDER MASK OPENING

0.07 MIN

FCBGA - 2.8 mm max heightALF0827A PLASTIC BALL GRID ARRAY 4224732/B 02/2019 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811). SYMM SYMM LAND PATTERN EXAMPLE SCALE:5X AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 B A 26 27 28 29 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.8) TYP FCBGA - 2.8 mm max heightALF0827A PLASTIC BALL GRID ARRAY 4224732/B 02/2019 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:5X AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 B A 26 27 28 29

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