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DRA64x,DRA65x www.ti.com SPRT656 –JANUARY 2013 DRA64x/DRA65xOMAP™ AutomotiveApplicationsProcessorsTechnicalBrief

1 High-PerformanceSystem-on-Chip (SoC)

11.1 Features

– 256K-Byte L2 UnifiedMapped RAM/Caches• High-PerformanceAutomotive Media With ECCApplicationsProcessors

  • DSP/EDMA Memory Management Unit– Up to1-GHz ARM ® Cortex™ -A8 RISC Core (DEMMU)– Up to600-MHz C674x ™ VLIW DSP – Maps C674x DSP and EDMA TC Memory– Up to4800/3600C674x ™ MIPS/MFLOPS Accesses toSystem Addresses– FullySoftware-CompatiblewithC67x+ ™ , • 128K-Bytes On-Chip Memory ControllerC64x+ ™ (OCMC) RAM• ARM ® Cortex™ -A8 Core • General-PurposeM3 Subsystem– ARMv7 Architecture – ARM ® Cortex™ -M3 Processor• In-Order,Dual-Issue,Superscalar • 128K-Byte Instruction/DataMemoryProcessor Core
  • 16K-Byte Data Memory• NEON ™ MultimediaArchitecture – General-PurposeDMA• Supports Integerand FloatingPoint – FiveGeneral-PurposeTimers• Jazelle® RCT ExecutionEnvironment
  • Programmable High-DefinitionVideo Image• ARM ® Cortex™ -A8 Memory Architecture Coprocessing (HDVICP v2)Engine– 32K-Byte Instructionand Data Caches – Encode, Decode, Transcode Operations– 512K-Byte L2 Cache – H.264,MPEG2, VC1, MPEG4, SP/ASP,– 64K-Byte RAM, 48K-Byte Boot ROM JPEG/MJPEG• TMS320C674x ™ Floating-PointVLIW DSP • Media Controller– 64 General-PurposeRegisters(32-Bit) – ControlstheHDVPSS and HDVICP2– SixALU (32-/40-Bit)FunctionalUnits • SGX530 3D Graphics Engine• Supports 32-BitInteger,SP (IEEESingle – Deliversup to23 MPoly/secPrecision/32-Bit)and DP (IEEEDouble – UniversalScalableShader EnginePrecision/64-Bit)FloatingPoint – Direct3DMobile,OpenGLES 1.1and 2.0,• Supports up toFour SP Adds Per Clock OpenVG 1.0,OpenMax API Supportand Four DP Adds Every Two Clocks – Advanced Geometry DMA DrivenOperation• Supports up toTwo Floating-Point(SP or – Programmable HQ Image Anti-AliasingDP) Approximate Reciprocalor Square Root OperationsPer Cycle • ViterbiCoprocessor (VCP2) – Two MultiplyFunctionalUnits • Endianness
  • Mixed-PrecisionIEEE Floating-Point – ARM/DSP Instructions/Data– LittleEndian MultiplySupported up to: • HD Video ProcessingSubsystem (HDVPSS) – 2 SP x SP → SP Per Clock – Two 165 MHz HD Video Capture Inputs – 2 SP x SP → DP Every Two Clocks • One 16/24-bitInput,SplittableintoDual 8- – 2 SP x DP → DP Every Three Clocks bitSD Capture Ports – 2 DP x DP → DP Every Four Clocks • One 8/16/24-bitInput
  • Fixed-PointMultiplySupports Two 32 x • One 8-bitOnly Input

32 Multiplies,Four 16 x 16-bitMultiplies – Two 165 MHz HD Video DisplayOutput

includingComplex Multiplies,or Eight8 x • One 16/24/30-bitand one 16/24-bitOutput8-BitMultipliesper Clock Cycle – Composite or S-VideoAnalog Output• C674x ™ Two-Level Memory Architecture – MacroVision® Support Available– 32K-Byte L1P RAM/Cache With EDC – DigitalHDMI 1.3transmitterWith Integrated– 32K-Byte L1D RAM/Cache PHY Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2OMAP isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2013,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

DRA64x,DRA65x SPRT656 –JANUARY 2013 www.ti.com – Advanced Video ProcessingFeaturesSuch • One System Watchdog Timer (WDT 0) as Scan/Format/RateConversion • SixConfigurableUART/IrDA/CIR Modules – Three Graphics Layers and Compositors – UART0 With Modem ControlSignals

  • Dual 32-bitDDR2/DDR3 SDRAM Interfaces – Supports up to3.6864Mbps UART0/1/2 – Supports up toDDR2-800 and DDR3-800 – Supports up to12 Mbps UART3 – Up toEightx 8 Devices Total2 GB Total – SIR,MIR, FIR (4.0MBAUD), and CIR Address Space • Four SerialPeripheralInterfaces(SPIs)[up to – Dynamic Memory Manager (DMM) 48-MHz]
  • Programmable Multi-ZoneMemory – Each With Four Chip-Selects Mapping and Interleaving • Three MMC/SD/SDIO SerialInterfaces[up to48-
  • Enables Efficient2D Block Accesses MHz]
  • Supports TiledObjectsin0°,90°,180°,or – Three Supportingup to1-/4-/8-BitModes 270° Orientationand Mirroring • Dual ControllerArea Network (DCAN) Modules
  • OptimizesInterlacedAccesses – CAN Version2 PartA, B
  • GeneralPurpose Memory Controller(GPMC) • Four Inter-IntegratedCircuit(I2CBus ™ )Ports – 8-/16-bitMultiplexedAddress/DataBus • SixMulti-ChannelAudio SerialPorts(McASP) – 512M-Byte TotalAddress Space Divided – Dual Ten SerializerTransmit/ReceivePortsAmong up to8 Chip Selects – Quad Four SerializerTransmit/ReceivePorts– GluelessInterfacetoNOR Flash,NAND – DIT-CapableFor S/PDIF (AllPorts)Flash(BCH/Hamming ErrorCode Detection), • Multi-ChannelBufferedSerialPort(McBSP)SRAM and Pseudo-SRAM – Transmit/ReceiveClocks up to48 MHz– ErrorLocatorModule (ELM) Outsideof – Two Clock Zones and Two SerialData PinsGPMC toProvideUpto 16-Bit/512-Bytes – Supports TDM, I2S,and SimilarFormatsHardware ECC forNAND
  • SerialATA (SATA) 3.0Gbps ControllerWith– FlexibleAsynchronous ProtocolControlfor IntegratedPHYInterfacetoFPGA, CPLD, ASICs, and so Forth – DirectInterfacetoOne Hard Disk Drive
  • Enhanced Direct-Memory-Access(EDMA) – Hardware-AssistedNativeCommand Controller Queuing (NCQ) from up to32 Entries – Four TransferControllers – Supports PortMultiplierand Command- Based Switching– 64/8IndependentDMA/QDMA Channels
  • ParallelATA/ATAPI I/F(ATA/ATAPI-6• Dual PortEthernet(10/100/1000Mb/s)With Specification)OptionalSwitch – PIO,MultiwordDMA, and UDMA– IEEE 802.3Compliant (3.3VI/OOnly)
  • Real-TimeClock (RTC)– MII/RMII/GMII/RGMIIMedia IndependentI/Fs – One-Time or PeriodicInterruptGeneration– Management Data I/O(MDIO) Module
  • Up to128 General-PurposeI/O(GPIO)Pins– Reset Isolation
  • One Spin Lock Module withup to128 Hardware– IEEE-1588Time-Stamping,AVB, and SemaphoresIndustrialEthernetProtocols
  • One MailboxModule with12 Mailboxes• Dual USB 2.0PortsWith IntegratedPHYs
  • On-Chip ARM ROM Bootloader(RBL)– USB2.0 High-/Full-SpeedClients
  • Power, Reset,and Clock Management– USB2.0 High-/Full-/Low-SpeedHosts,or OTG – MultipleIndependentCore Power Domains– Supports End Points0-15 – MultipleIndependentCore VoltageDomains• One PCI Express 2.0PortWith IntegratedPHY – Support forThree OperatingPoints– SinglePortWith 1 Lane at5.0GT/s (OPP166/120/100)per VoltageDomain– Configurableas Root Complex or Endpoint – Clock Enable/DisableControlfor• MLB Subsystem (MLBSS) Subsystems and Peripherals– MLB 3-pinor 6-pininterfaces
  • 32KB Embedded Trace Buffer™ (ETB™ )and 5-– Enables Connection toMOST OpticalRings pinTrace InterfaceforDebug– MOST25/50/150 (up to100Mbps) • IEEE-1149.1(JTAG) Compatible• Audio TrackingLogic (ATL) • 684-PinPb-FreeBGA Package (CYE Suffix),– Asyncronous SRC Assist 0.8-mm BallPitchWith ViaChannel™• Eight32-bitGeneral-PurposeTimers (Timer1–8) Technology toReduce PCB Cost

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  • 45-nm CMOS Technology • 3.3-VBuffersforGeneralI/Oand 1.8V/3.3VDual VoltageBuffersforMMC/SD/SDIO interface Copyright© 2013,Texas InstrumentsIncorporated High-PerformanceSystem-on-Chip(SoC) 3 SubmitDocumentationFeedback

DRA64x,DRA65x SPRT656 –JANUARY 2013 www.ti.com

1.2 Applications

  • Automotive Navigation
  • InCar Media/Radio/DTVReceiver
  • Automotive ConnectivityBox
  • Automotive Vision
  • Rear Seat Entertainment

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1.3 Description

DRA64x/DRA65x OMAP AutomotiveApplicationsProcessorsare a highly-integrated,programmable platformthatleveragesTI’s technologyto meet the processingneeds of the followingautomotive applications:automotivenavigation,Media/Radio/DTVreception,connectivity,automotivevisionand rear seatentertainment. The device enables Original-EquipmentManufacturers(OEMs) and Original-DesignManufacturers (ODMs) toquicklybringtomarketdevicesfeaturingrobustoperatingsystemssupport,richuserinterfaces, and highprocessingperformancethroughthe maximum flexibilityof a fullyintegratedmixed processor solution.The devicealsocombinesprogrammableprocessingwitha highlyintegratedperipheralset. Programmabilityisprovidedby an ARM Cortex™ -A8 RISC CPU withNeon ™ extension,TI C674x VLIW floating-pointDSP core,and high-definitionvideo/imagingcoprocessors.The ARM allowsdevelopersto keep controlfunctionsseparatefrom algorithmsprogrammed on the DSP and coprocessors,thus reducingthe complexityof the system software.The ARM Cortex™ -A8 32-bitRISC Core withNeon ™ floating-pointextensionincludes:32 Kbytes(KB) ofInstructioncache;32KB ofData cache;512KB ofL2 Cache;48KB ofBootROM; and 64KB ofRAM. The richperipheralsetprovidesthe abilityto controlexternalperipheraldevicesand communicate with externalprocessors.For detailson each oftheperipherals,see therelatedsectionsinthisdocument and the associatedperipheralreferenceguides. The peripheralset includes:HD Video Processing Subsystem;General-PurposeM3 Subsystem;TransportPacket ProcessorSubsystem;Dual PortGigabit EthernetMACs (10/100/1000Mbps) [EthernetSwitch]withMII/RMII/GMII/RGMIIand MDIO interface supportingIEEE-1588 Time-Stamping,AVB, and IndustrialEthernetProtocols;two USB portswith integrated2.0PHY; PCIe x1 GEN2 Compliantinterface;two 10-serializerMcASP audioserialports(with DIT mode); fourquad-serilaizerMcASP audio serialports(withDIT mode); one McBSP multichannel bufferedserialport;sixUARTs withIrDAand CIR support;fourSPI serialinterfaces;threeMMC/SD/SDIO serialinterfaces;fourI2C master/slaveinterfaces;a ParallelCamera Interface(CAM); up to128 General- Purpose IOs (GPIOs);eight32-bitgeneral-purposetimers;System watchdog timer;Dual DDR2/DDR3 SDRAM interfaces;flexible8/16-bitasynchronousmemory interface;two ControllerArea Network(DCAN) modules;a SpinLock;Mailbox;ParallelHard DiskDriveInterface(PATA/ATAPI);MLBSS 3-Pinand 6-Pin Interfaces;AudioTrackingLogic(ATL);and ParallelATA. DRA64x/DRA65x OMAP AutomotiveApplicationsProcessorsalsoincludea high-definitionvideo/imaging coprocessor2 (HDVICP2), and an SGX530 3D graphicsengine to off-loadmany videoand imaging processingtasksfrom theDSP core,making more DSP MIPS availableforcommon videoand imaging algorithms.Additionally,ithas a completesetof developmenttoolsforboth the ARM and DSP which includeC compilers,a DSP assemblyoptimizertosimplifyprogrammingand scheduling,and a Microsoft® Windows ™ debuggerinterfaceforvisibilityintosourcecode execution. The C674x DSP coreisthehigh-performancefloating-pointDSP generationintheTMS320C6000 ™ DSP platformand iscode-compatiblewithpreviousgenerationC64x Fixed-Pointand C67x Floating-PointDSP generation.The C674x Floating-PointDSP processoruses 32KB ofL1 program memory withEDC and 32KB of L1 data memory. Up to 32KB of L1P can be configuredas program cache.The remainingis noncacheableno-wait-stateprogram memory. Up to32KB ofL1D can be configuredas datacache.The remainingisnon-cacheableno-wait-statedatamemory. The DSP has 256KB ofL2 RAM withECC, which can be definedas SRAM, L2 cache, or a combinationof both.AllC674x L3 and off-chipmemory accessesareroutedthroughan MMU. Copyright© 2013,Texas InstrumentsIncorporated High-PerformanceSystem-on-Chip(SoC) 5 SubmitDocumentationFeedback

Cortex™-M3 SGX530 GPU C674x DSP with floating point IVA HD 1080p Video Coprocessor Radio Coprocessors Display Subsystem Connectivity High Speed Interconnect SystemPeripherals Serial Interfaces Program/Data Storage Video in Ports eDMA MMU DMM 2x 32b DDR2/3 MMC /SD NAND/ NOR/ Async SATAPATAMcBSP I C 2CAN McSPI UART Dual USB 2.0 (with PHY) USB Host Security Timers, PLLs, GPIO PCIe MOST 150/MLB Gig EMAC AVB ARM Cortex™-A8 DRA64x,DRA65x SPRT656 –JANUARY 2013 www.ti.com

1.4 DRA64x/DRA65x FunctionalBlock Diagram

Note:Not allperipheralsareavailableatthesame timedue topinmultiplexing.

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