DR805X

DR805X DCD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 79

Technical content

Datasheet sections

8-bit RISC Microcontroller Instructions set details ver 3.10

DR805x Instructions set details - 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

DR805x Instructions set details - 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. software assembler, compiler and debugger tools. relative addressing mode is used for jump instructions. microcontroller core. One cycle is equal to one clock period. instruction takes to execute. Table 1. Notes on data addressing modes program memory address space. program memory as the first byte of the following instruction. Table 2. Notes on program addressing modes

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Table 3. Arithmetic operations

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Table 4. Logic operations Table 5. Boolean manipulation

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Table 6. Data transfer

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Table 7. Program branches

DR805x Instructions set details - 1 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 2.3. I NSTRUCTION SET BRIEF – HEXADECIMAL ORDER Opcode Mnemonic Opcode Mnemonic 00 H NOP 30 H JNB bit.rel

01 H AJMP addr11 31 H ACALL addr11

02 H LJMP addr16 32 H RETI

03 H RR A 33 H RLC A

04 H INC A 34 H ADDC A,#data

05 H INC direct 35 H ADDC A,direct

06 H INC @R0 36 H ADDC A,@R0

07 H INC @R1 37 H ADDC A,@R1

08 H INC R0 38 H ADDC A,R0

09 H INC R1 39 H ADDC A,R1

0A H INC R2 3A H ADDC A,R2 0B H INC R3 3B H ADDC A,R3 0C H INC R4 3C H ADDC A,R4 0D H INC R5 3D H ADDC A,R5 0E H INC R6 3E H ADDC A,R6 0F H INC R7 3F H ADDC A,R7

10 H JBC bit,rel 40 H JC rel

11 H ACALL addr11 41 H AJMP addr11

12 H LCALL addr16 42 H ORL direct,A

13 H RRC A 43 H ORL direct,#data

14 H DEC A 44 H ORL A,#data

15 H DEC direct 45 H ORL A,direct

16 H DEC @R0 46 H ORL A,@R0

17 H DEC @R1 47 H ORL A,@R1

18 H DEC R0 48 H ORL A,R0

19 H DEC R1 49 H ORL A,R1

1A H DEC R2 4A H ORL A,R2 1B H DEC R3 4B H ORL A,R3 1C H DEC R4 4C H ORL A,R4 1D H DEC R5 4D H ORL A,R5 1E H DEC R6 4E H ORL A,R6 1F H DEC R7 4F H ORL A,R7 20 H JB bit.rel 50 H JNC rel

21 H AJMP addr11 51 H ACALL addr11

22 H RET 52 H ANL direct,A

23 H RL A 53 H ANL direct,#data

24 H ADD A,#data 54 H ANL A,#data

25 H ADD A,direct 55 H ANL A,direct

26 H ADD A,@R0 56 H ANL A,@R0

27 H ADD A,@R1 57 H ANL A,@R1

28 H ADD A,R0 58 H ANL A,R0

29 H ADD A,R1 59 H ANL A,R1

2A H ADD A,R2 5A H ANL A,R2 2B H ADD A,R3 5B H ANL A,R3 2C H ADD A,R4 5C H ANL A,R4 2D H ADD A,R5 5D H ANL A,R5 2E H ADD A,R6 5E H ANL A,R6 2F H ADD A,R7 5F H ANL A,R7

DR805x Instructions set details - 1 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Opcode Mnemonic Opcode Mnemonic

60 H JZ rel 90 H MOV DPTR,#data16

61 H AJMP addr11 91 H ACALL addr11

62 H XRL direct,A 92 H MOV bit,C

63 H XRL direct,#data 93 H MOVC A,@A+DPTR

64 H XRL A,#data 94 H SUBB A,#data

65 H XRL A,direct 95 H SUBB A,direct

66 H XRL A,@R0 96 H SUBB A,@R0

67 H XRL A,@R1 97 H SUBB A,@R1

68 H XRL A,R0 98 H SUBB A,R0

69 H XRL A,R1 99 H SUBB A,R1

6A H XRL A,R2 9A H SUBB A,R2 6B H XRL A,R3 9B H SUBB A,R3 6C H XRL A,R4 9C H SUBB A,R4 6D H XRL A,R5 9D H SUBB A,R5 6E H XRL A,R6 9E H SUBB A,R6 6F H XRL A,R7 9F H SUBB A,R7

70 H JNZ rel A0 H ORL C,bit

71 H ACALL addr11 A1 H AJMP addr11

72 H ORL C,direct A2 H MOV C,bit

73 H JMP @A+DPTR A3 H INC DPTR

74 H MOV A,#data A4 H MUL AB

75 H MOV direct,#data A5 H -

76 H MOV @R0,#data A6 H MOV @R0,direct

77 H MOV @R1,#data A7 H MOV @R1,direct

78 H MOV R0.#data A8 H MOV R0,direct 79 H MOV R1.#data A9 H MOV R1,direct 7A H MOV R2.#data AA H MOV R2,direct 7B H MOV R3.#data AB H MOV R3,direct 7C H MOV R4.#data AC H MOV R4,direct 7D H MOV R5.#data AD H MOV R5,direct 7E H MOV R6.#data AE H MOV R6,direct 7F H MOV R7.#data AF H MOV R7,direct

80 H SJMP rel B0 H ANL C,bit

81 H AJMP addr11 B1 H ACALL addr11

82 H ANL C,bit B2 H CPL bit

83 H MOVC A,@A+PC B3 H CPL C

84 H DIV AB B4 H CJNE A,#data,rel

85 H MOV direct,direct B5 H CJNE A,direct,rel

86 H MOV direct,@R0 B6 H CJNE @R0,#data,rel

87 H MOV direct,@R1 B7 H CJNE @R1,#data,rel

88 H MOV direct,R0 B8 H CJNE R0,#data,rel

89 H MOV direct,R1 B9 H CJNE R1,#data,rel

8A H MOV direct,R2 BA H CJNE R2,#data,rel 8B H MOV direct,R3 BB H CJNE R3,#data,rel 8C H MOV direct,R4 BC H CJNE R4,#data,rel 8D H MOV direct,R5 BD H CJNE R5,#data,rel 8E H MOV direct,R6 BE H CJNE R6,#data,rel 8F H MOV direct,R7 BF H CJNE R7,#data,rel

Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Table 8. Instruction set brief in hexadecimal order

DR805x Instructions set details - 1 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3. I NSTRUCTIONS SET DETAILS 3.1. ACALL Instruction: ACALL addr11 Function: Absolute call Description: ACALL unconditionally calls a s ubroutine located at the indicated address. The instruction increments t he PC twice to obt ain the address of the following instruct ion, then pushes the 16-bit result onto the stack (low-order byte first) and increm ents the stack pointer twice. The destination address is obtained by su ccessively concatenating the five high-order bits of the incremented PC, op code bits 7-5, and the second byte of the instruction. The subroutine called must therefore start within the same 2K block of program me mory as the first byte of the instruction following ACALL. No flags are affected. Operation: (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ← (PC7-0) (SP) ← (SP) + 1 ((SP)) ← (PC15-8) (PC10-0) ← page address Bytes: 2 Cycles: 6 Encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

DR805x Instructions set details - 1 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.2. ADD Instruction: ADD A, <src-byte> Function: Adds A to the source operand and returns the result to A. Description: ADD adds the byte variable indicat ed to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integer s, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are allowed: register, direct, register- indirect, or immediate. 3.2.1. ADD A, R N Operation: (PC) ← (PC) + 1 (A) ← (A) + (Rn) Bytes: 1 Cycles: 2 Encoding: 0 0 1 0 1 r r r 3.2.2. ADD A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (A) + (direct) Bytes: 2 Cycles: 3 Encoding: 0 0 1 0 0 1 0 1 direct address

DR805x Instructions set details - 1 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.2.3. ADD A, @R I Operation: (PC) ← (PC) + 1 (A) ← (A) + ((Ri)) Bytes: 1 Cycles: 3 Encoding: 0 0 1 0 0 1 1 i 3.2.4. ADD A, # DATA Operation: (PC) ← (PC) + 2 (A) ← (A) + #data Bytes: 2 Cycles: 2 Encoding: 0 0 1 0 0 1 0 0 immediate data

DR805x Instructions set details - 1 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.3. ADDC Instruction: ADDC A, < src-byte> Function: Adds A and the sour ce operand, then adds one (1) if CY is set, and puts the result in A. Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags ar e set, respectively, if there is a carry out of bit 7 or bit 3, and cl eared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise OV is clear ed. When adding signed integers, OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. Four source operand-addressing modes ar e allowed: register= direct, register- indirect, or immediate. 3.3.1. ADDC A, R N Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 2 Encoding: 0 0 1 1 1 r r r 3.3.2. ADDC A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (A) + (C) + (direct) Bytes: 2 Cycles: 3 Encoding: 0 0 1 1 0 1 0 1 direct address

DR805x Instructions set details - 1 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.3.3. ADDC A, @R I Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 3 Encoding: 0 0 1 1 0 1 1 i 3.3.4. ADDC A, # DATA Operation: (PC) ← (PC) + 2 (A) ← (A) + (C) + #data Bytes: 2 Cycles: 2 Encoding: 0 0 1 1 0 1 0 0 immediate data

DR805x Instructions set details - 1 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.4. AJMP Instruction: AJMP addr11 Function: Absolute jump Description: AJMP transfers program execution to the indicated address, which is formed at run- time by concatenating t he high-order five bits of the PC (after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the firs t byte of the instruction following AJMP. Operation: (PC) ← (PC) + 2 (PC10-0) ← page address Bytes: 2 Cycles: 3 Encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0

DR805x Instructions set details - 2 0 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.5. ANL Instruction: ANL <dest-byte>, <src-byte> Function: Logical AND for byte operands Description: ANL performs the bit wise logica l AND operation betw een the variables indicated and stores the results in the destination variable. No flags are affected (except P, if <dest-byte > = A). The two operands allow six addressing mode combinations. When the destination is a accumulator, the source can use register, direc t, register-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. Note: When this instruction is used to modi fy an output port, the value used as the original port data will be read from the output dat a latch, not the input pins. 3.5.1. ANL A, R N Operation: (PC) ← (PC) + 1 (A) ← (A) and (Rn) Bytes: 1 Cycles: 2 Encoding: 0 1 0 1 1 r r r 3.5.2. ANL A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (A) and (direct) Bytes: 2 Cycles: 3 Encoding: 0 1 0 1 0 1 0 1 direct address

DR805x Instructions set details - 2 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.5.3. ANL A, @R I Operation: (PC) ← (PC) + 1 (A) ← (A) and ((Ri)) Bytes: 1 Cycles: 3 Encoding: 0 1 0 1 0 1 1 i 3.5.4. ANL A, # DATA Operation: (PC) ← (PC) + 2 (A) ← (A) and #data Bytes: 2 Cycles: 2 Encoding: 0 1 0 1 0 1 0 0 immediate data 3.5.5. ANL DIRECT, A Operation: (PC) ← (PC) + 2 (direct) ← (direct) and (A) Bytes: 2 Cycles: 4 Encoding: 0 1 0 1 0 0 1 0 direct address 3.5.6. ANL DIRECT, #DATA Operation: (PC) ← (PC) + 3 (direct) ← (direct) and #data Bytes: 3 Cycles: 4 Encoding: 0 1 0 1 0 0 1 1 direct address immediate data Instruction: ANL C, <src-bit>

DR805x Instructions set details - 2 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Function: Logical AND for bit operands Description: If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash (“/” preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected . No other flags are affected. Only direct bit addressing is allowed for the source operand. 3.5.7. ANL C, BIT Operation: (PC) ← (PC) + 2 (C) ← (C) and (bit) Bytes: 2 Cycles: 3 Encoding: 1 0 0 0 0 0 1 0 bit address 3.5.8. ANL C, / BIT Operation: (PC) ← (PC) + 2 (C) ← (C) and / (bit) Bytes: 2 Cycles: 3 Encoding: 1 0 1 1 0 0 0 0 bit address

DR805x Instructions set details - 2 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.6. CJNE Instruction: CJNE <dest-byte >, < src-byte >, rel Function: Compare and jump if not equal. Description: CJNE compares the magnitudes of the first two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relati ve displacement in the last instruction byte to the PC, after incr ementing the PC to the start of the next instruction. The carry flag is se t if the unsigned integer value of <dest-byte> is less than the unsigne d integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected. The first two operands allow four addre ssing mode combinations: the accumulator may be compared with any directly addr essed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate constant. 3.6.1. CJNE A, DIRECT, REL Operation: (PC) ← (PC) + 3 if (A) < > (direct) then (PC) ← (PC) + relative offset if (A) < (direct) then (C) ← 1 else (C) ← 0 Bytes: 3 Cycles: 5 Encoding: 1 0 1 1 0 1 0 1 direct address relative address

DR805x Instructions set details - 2 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.6.2. CJNE A, # DATA, REL Operation: (PC) ← (PC) + 3 if (A) < > data then (PC) ← (PC) + relative offset if (A) < data then (C) ← 1 else (C) ← 0 Bytes: 3 Cycles: 4 Encoding: 1 0 1 1 0 1 0 0 immediate data relative address 3.6.3. CJNE RN, # DATA, REL Operation: (PC) ← (PC) + 3 if (Rn) < > data then (PC) ← (PC) + relative offset if (Rn) < data then (C) ← 1 else (C) ← 0 Bytes: 3 Cycles: 4 Encoding: 1 0 1 1 1 r r r immediate data relative address

DR805x Instructions set details - 2 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.6.4. CJNE @R I, #DATA, REL Operation: (PC) ← (PC) + 3 if ((Ri)) < > data then (PC) ← (PC) + relative offset if ((Ri)) < data then (C) ← 1 else (C) ← 0 Bytes: 3 Cycles: 5 Encoding: 1 0 1 1 0 1 1 i immediate data relative address

DR805x Instructions set details - 2 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.7. CLR 3.7.1. CLR A Function: Clear accumulator Description: The accumulator is cleared (all bits set to zero). No flags are affected. Operation: (PC) ← (PC) + 1 (A) ← 0 Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 0 0 3.7.2. CLR BIT Function: Clear bit Description: The indicated bit is cleared (reset to zero). No other flags are affected. Operation: (PC) ← (PC) + 2 bit ← 0 Bytes: 2 Cycles: 4 Encoding: 1 1 0 0 0 0 1 0 bit address

DR805x Instructions set details - 2 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.7.3. CLR C Function: Clear carry Description: The carry flag is cleared (reset to zero). No other flags are affected. Operation: (PC) ← (PC) + 1 (C) ← 0 Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 0 1 1

DR805x Instructions set details - 2 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.8. CPL 3.8.1. CPL A Function: Complement accumulator Description: Each bit of the accumulator is logically complemented (one’s complement). Bits which previous ly contained a one are changed to zero and vice versa. No flags are affected. Operation: (PC) ← (PC) + 1 (A) ← / (A) Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 0 1 0 0 3.8.2. CPL BIT Function: Complement bit Description: The bit variable specified is co mplemented. A bit which had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit. Note: When this instruction is used to modi fy an output pin, the value used as the original data will be r ead from the output data latch, not the input pin. Operation: (PC) ← (PC) + 2 (C) ← (bit) Bytes: 2 Cycles: 4 Encoding: 1 0 1 1 0 0 1 0 bit address

DR805x Instructions set details - 2 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.8.3. CPL C Function: Complement carry Description: The carry flag is complemented. A bit which had been a one is changed to zero and vice versa. Operation: (PC) ← (PC) + 1 (C) ← / (C) Bytes: 1 Cycles: 1 Encoding: 1 0 1 1 0 0 1 1

DR805x Instructions set details - 3 0 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.9. DA Instruction: DA A Function: Decimal adjust a ccumulator for addition Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variable s (each in packed BCD format), producing two four-bit digits. Any A DD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the low- order nibble. This internal addition would set the ca rry flag if a carry-out of the low- order four-bit field propagated through all high-order bits , but it would not clear the carry flag otherwise. If the carry flag is now set, or if the four high-order bits now exceed nine (1010xxxx-1111xxxx), these high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble. Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear the carry. The carry flag thus indicates if the sum of the original two BCD va riables is greater than 100, allowing multiple precision decimal addition. OV is not affected. All of this occurs during the one instruction cycle. Essentially; this instruction performs the decimal conv ersion by adding 00 H , 06 H , 60 H , or 66 H to the accumulator, depending on initial accumulator and PSW conditions. Note: DA A cannot simply convert a hexadecimal number in the accumulator to BCD notation, nor does DA A apply to decimal subtraction. Operation: (PC) ← (PC) + 1 if [[(A3-0) > 9] ^ [(AC) = 1]] then next Bytes: 1 Cycles: 4 Encoding: 1 1 0 1 0 1 0 0

DR805x Instructions set details - 3 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.10. DEC Instruction: DEC byte Function: Decrement byte Description: The variable indicated is decremented by 1. An original value of 00 H will underflow to 0FF H. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modi fy an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.10.1. DEC A Operation: (PC) ← (PC) + 1 (A) ← (A) - 1 Bytes: 1 Cycles: 2 Encoding: 0 0 0 1 0 1 0 0 3.10.2. DEC R N Operation: (PC) ← (PC) + 1 (Rn) ← (Rn) - 1 Bytes: 1 Cycles: 3 Encoding: 0 0 0 1 1 r r r

DR805x Instructions set details - 3 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.10.3. DEC DIRECT Operation: (PC) ← (PC) + 2 (direct) ← (direct) - 1 Bytes: 2 Cycles: 4 Encoding: 0 0 0 1 0 1 0 1 direct address 3.10.4. DEC @R I Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 4 Encoding: 0 0 0 1 0 1 1 i

DR805x Instructions set details - 3 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.11. DIV Instruction: DIV AB Function: Divide Description: DIV AB divides the unsigned eight-bi t integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared. Exception: If B had originally contained 00 H, the values returned in the accumulator and B register will be undefined and the overflow flag will be set. The carry flag is cleared in any case. Operation: (PC) ← (PC) + 1 – result’s bits 15..8 (B7-0) ← (A) / (B) – result’s bits 7..0 Bytes: 1 Cycles: 5 Encoding: 1 0 0 0 0 1 0 0

DR805x Instructions set details - 3 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.12. DJNZ Instruction: DJNZ <byte>, <rel-addr> Function: Decrement and jump if not zero Description: DJNZ decrements the location i ndicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00 H wil l underflow to 0FF H. No flags are affected. The branch destination woul d be computed by adding the signed relative-displacement value in the last instruction byte to the PC, after incrementing the PC to the firs t byte of the follo wing instruction. The location decremented may be a register or directly addressed byte. Note: When this instruction is used to modi fy an output port, the value used as the original port data will be read from the output dat a latch, not the input pins. 3.12.1. DJNZ R N, REL Operation: (PC) ← (PC) + 2 (Rn) ← (Rn) - 1 if (Rn) ≠ 0 then (PC) ← (PC) + rel Bytes: 2 Cycles: 4 Encoding: 1 1 0 1 1 r r r relative address

DR805x Instructions set details - 3 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.12.2. DJNZ DIRECT, REL Operation: (PC) ← (PC) + 3 (direct) ← (direct) - 1 if (direct) ≠ 0 then (PC) ← (PC) + rel Bytes: 3 Cycles: 5 Encoding: 1 1 0 1 0 1 0 1 direct address relative address

DR805x Instructions set details - 3 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.13. INC Instruction: INC operand Function: Increment Description: INC increments the indi cated variable by 1. An original value of 0FFh will overflow to 00h. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modi fy an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.13.1. INC A Operation: (PC) ← (PC) + 1 (A) ← (A) + 1 Bytes: 1 Cycles: 2 Encoding: 0 0 0 0 0 1 0 0 3.13.2. INC R N Operation: (PC) ← (PC) + 1 (Rn) ← (Rn) + 1 Bytes: 1 Cycles: 3 Encoding: 0 0 0 0 1 r r r

DR805x Instructions set details - 3 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.13.3. INC DIRECT Operation: (PC) ← (PC) + 2 (direct) ← (direct) + 1 Bytes: 2 Cycles: 4 Encoding: 0 0 0 0 0 1 0 1 direct address 3.13.4. INC @R I Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 4 Encoding: 0 0 0 0 0 1 1 i 3.13.5. INC DPTR Function: Increment data pointer Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 16) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00 H will increment the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Operation: (PC) ← (PC) + 1 (DPTR) ← (DPTR) + 1 Bytes: 1 Cycles: 1 Encoding: 1 0 1 0 0 0 1 1

DR805x Instructions set details - 3 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.14. JB Instruction: JB bit, rel Function: Jump if bit is set Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. T he branch destination is computed by adding the signed relative-displacem ent in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Operation: (PC) ← (PC) + 3 if (bit) = 1 then (PC) ← (PC) + rel Bytes: 3 Cycles: 4 Encoding: 0 0 1 0 0 0 0 0 bit address relative address

DR805x Instructions set details - 3 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.15. JBC Instruction: JBC bit, rel Function: Jump if bit is set and clear bit Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected. Note: When this instruction is used to test an output pin, the value used as the original data will be read from the output data latch, not the input pin. Operation: (PC) ← (PC) + 3 if (bit) = 1 then (bit) ← 0 (PC) ← (PC) + rel Bytes: 3 Cycles: 4 Encoding: 0 0 0 1 0 0 0 0 bit address relative address

DR805x Instructions set details - 4 0 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.16. JC Instruction: JC rel Function: Jump if carry is set Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. T he branch destination is computed by adding the signed relative- displa cement in the second instruction byte to the PC, after incrementing the PC twice. No flags are affected. Operation: (PC) ← (PC) + 2 if (C) = 1 then (PC) ← (PC) + rel Bytes: 2 Cycles: 3 – C=1 2 – C=0 Encoding: 0 1 0 0 0 0 0 0 relative address

DR805x Instructions set details - 4 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.17. JMP Instruction: JMP @A + DPTR Function: Jump indirect Description: Add the eight-bit unsigned contents of the accumulator with the sixteen- bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent inst ruction fetches. Sixteen-bit addition is performed (modulo 2 16): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the accumulator nor the data pointer is altered. No flags are affected. Operation: (PC) ← (A) + (DPTR) Bytes: 1 Cycles: 3 Encoding: 0 1 1 1 0 0 1 1

DR805x Instructions set details - 4 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.18. JNB Instruction: JNB bit,rel Function: Jump if bit is not set Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. T he branch destination is computed by adding the signed relative-displacem ent in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The bit tested is not modified. No flags are affected. Operation: (PC) ← (PC) + 3 if (bit) = 0 then (PC) ← (PC) + rel. Bytes: 3 Cycles: 4 Encoding: 0 0 1 1 0 0 0 0 bit address relative address

DR805x Instructions set details - 4 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.19. JNC Instruction: JNC rel Function: Jump if carry is not set Description: If the carry flag is a zero, branc h to the address indicated; otherwise proceed with the next instruction. T he branch destination is computed by adding the signed relative-displ acement in the second instruction byte to the PC, after incrementing t he PC twice to point to the next instruction. The carry flag is not modified. Operation: (PC) ← (PC) + 2 if (C) = 0 then (PC) ← (PC) + rel Bytes: 2 Cycles: 3 – C=0 2 – C=1 Encoding: 0 1 0 1 0 0 0 0 relative address

DR805x Instructions set details - 4 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.20. JNZ Instruction: JNZ rel Function: Jump if accumulator is not zero Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instru ction. The branch destination is computed by adding the signed relati ve-displacement in the second instruction byte to the PC, afte r incrementing the PC twice. The accumulator is not modified. No flags are affected. Operation: (PC) ← (PC) + 2 if (A) ≠ 0 then (PC) ← (PC) + rel. Bytes: 2 Cycles: 3 Encoding: 0 1 1 1 0 0 0 0 relative address

DR805x Instructions set details - 4 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.21. JZ Instruction: JZ rel Function: Jump if accumulator is zero Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instru ction. The branch destination is computed by adding the signed relati ve-displacement in the second instruction byte to the PC, afte r incrementing the PC twice. The accumulator is not modified. No flags are affected. Operation: (PC) ← (PC) + 2 if (A) = 0 then (PC) ← (PC) + rel Bytes: 2 Cycles: 3 Encoding: 0 1 1 0 0 0 0 0 relative address

DR805x Instructions set details - 4 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.22. LCALL Instruction: LCALL addr16 Function: Long call Description: LCALL calls a subroutine locat ed at the indicated address. The instruction adds three to the prog ram counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the st ack pointer by two. The high-order and low-order bytes of t he PC are then loaded, respectively, with the second and third bytes of the LCAL L instruction. Program execution continues with the instruction at this address. The subroutine may therefore begin anywhere in the fu ll 64 Kbyte program memory address space. No flags are affected. Operation: (PC) ← (PC) + 3 (SP) ← (SP) + 1 ((SP)) ← (PC7-0) (SP) ← (SP) + 1 ((SP)) ← (PC15-8) (PC) ← addr15-0 Bytes: 3 Cycles: 6 Encoding: 0 0 0 1 0 0 1 0 address 15..8 address 7..0

DR805x Instructions set details - 4 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.23. LJMP Instruction: LCALL addr16 Function: Long jump Description: LJMP causes an unconditional br anch to the indicated address, by loading the high- order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program me mory address space. No flags are affected. Operation: (PC) ← addr15... addr0 Bytes: 3 Cycles: 4 Encoding: 0 0 0 0 0 0 1 0 address 15..8 address 7..0

DR805x Instructions set details - 4 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.24. MOV Instruction: MOV <dest-byte>, <src-byte> Function: Move byte variable Description: The byte variable indicated by t he second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation. Fifteen combinat ions of source and destination addressing modes are allowed. 3.24.1. MOV A, R N Operation: (PC) ← (PC) + 1 (A) ← (Rn) Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 1 r r r 3.24.2. MOV A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (direct) Note: MOV A, ACC is a valid instruction. Bytes: 2 Cycles: 2 Encoding: 1 1 1 0 0 1 0 1 direct address

DR805x Instructions set details - 4 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.24.3. MOV A, @R I Operation: (PC) ← (PC) + 1 (A) ← ((Ri)) Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 1 1 i 3.24.4. MOV A, # DATA Operation: (PC) ← (PC) + 2 (A) ← #data Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 0 1 0 0 immediate data 3.24.5. MOV R N, A Operation: (PC) ← (PC) + 1 (Rn) ← (A) Bytes: 1 Cycles: 2 Encoding: 1 1 1 1 1 r r r 3.24.6. MOV R N, DIRECT Operation: (PC) ← (PC) + 2 (Rn) ← (direct) Bytes: 2 Cycles: 4 Encoding: 1 0 1 0 1 r r r direct address

DR805x Instructions set details - 5 0 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.24.7. MOV R N, #DATA Operation: (PC) ← (PC) + 2 (Rn) ← #data Bytes: 2 Cycles: 2 Encoding: 0 1 1 1 1 r r r immediate data 3.24.8. MOV DIRECT, A Operation: (PC) ← (PC) + 2 (direct) ← (A) Bytes: 2 Cycles: 2 – destination inside SFR 3 – destination inside RAM Encoding: 1 1 1 1 0 1 0 1 direct address 3.24.9. MOV DIRECT, RN Operation: (PC) ← (PC) + 2 (direct) ← (Rn) Bytes: 2 Cycles: 2 – destination inside SFR 3 – destination inside RAM Encoding: 1 0 0 0 1 r r r direct address 3.24.10. MOV DIRECT, DIRECT Operation: (PC) ← (PC) + 3 (direct) ← (direct) Bytes: 3 Cycles: 3 – destination inside SFR 4 – destination inside RAM Encoding: 1 0 0 0 0 1 0 1 direct address (source) direct address (destination)

DR805x Instructions set details - 5 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.24.11. MOV DIRECT, @RI Operation: (PC) ← (PC) + 2 (direct) ← ((Ri)) Bytes: 2 Cycles: 3 – direct inside SFR 4 – direct inside RAM Encoding: 1 0 0 0 0 1 1 i direct address 3.24.12. MOV DIRECT, #DATA Operation: (PC) ← (PC) + 2 (direct) ← #data Bytes: 3 Cycles: 3 Encoding: 0 1 1 1 0 1 0 1 direct address (source) immediate data 3.24.13. MOV @R I, A Operation: (PC) ← (PC) + 1 ((Ri)) ← (A) Bytes: 1 Cycles: 3 Encoding: 1 1 1 1 0 1 1 i 3.24.14. MOV @R I, DIRECT Operation: (PC) ← (PC) + 2 ((Ri)) ← (direct) Bytes: 2 Cycles: 4 Encoding: 1 0 1 0 0 1 1 i direct address

DR805x Instructions set details - 5 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.24.15. MOV @R I, #DATA Operation: (PC) ← (PC) + 2 ((Ri)) ← #data Bytes: 2 Cycles: 3 Encoding: 0 1 1 1 0 1 1 i immediate data 3.24.16. MOV C, BIT Function: Move bit data Description: The Boolean variable indicat ed by the second operand (directly addressable bit) is copied into carry flag. No other register or flag is affected. Operation: (PC) ← (PC) + 2 (C) ← (bit) Bytes: 2 Cycles: 3 Encoding: 1 0 1 0 0 0 1 0 bit address 3.24.17. MOV BIT, C Function: Move carry flag Description: The carry flag is copied into the B oolean variable indicated by the first operand (directly addressable bit). No other register or flag is affected. Operation: (PC) ← (PC) + 2 (bit) ← (C) Bytes: 2 Cycles: 4 Encoding: 1 0 0 1 0 0 1 0 bit address

DR805x Instructions set details - 5 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.24.18. MOV DPTR, # DATA16 Function: Load data pointer wit h a 16-bit constant Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once. Operation: (PC) ← (PC) + 3 DPH ← immediate data15...8 DPL ← immediate data7..0 Bytes: 3 Cycles: 3 Encoding: 1 0 0 0 0 1 0 1 immediate data 15...8 immediate data 7...0

DR805x Instructions set details - 5 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.25. MOVC Instruction: MOVC A, @A + <base-reg> Function: Move code byte Description: The MOVC instructions load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accu mulator contents and the contents of a sixteen-bit base regist er, which may be either the data pointer or the PC. In the latter ca se, the PC is incremented to the address of the following instruction before being added to the accumulator; otherwise the base regist er is not alter ed. Sixteen-bit addition is performed so a carry-out from the low-order eight bits may propagate through higher-order bits. No flags are affected. 3.25.1. MOVC A, @A + DPTR Operation: (PC) ← (PC) + 1 (A) ← ((A) + (DPTR)) Bytes: 1 Cycles: 4 Encoding: 1 0 0 1 0 0 1 1 3.25.2. MOVC A, @A + PC Operation: (PC) ← (PC) + 1 (A) ← ((A) + (PC)) Bytes: 1 Cycles: 4 Encoding: 1 0 0 0 0 0 1 1

DR805x Instructions set details - 5 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.26. MOVX Instruction: MOVX <dest-byte>, <src-byte> Function: Move external Description: The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the X appended to MOV. There are two types of instructions, differi ng in whether they provide an eight- bit or sixteen-bit indirect address to the external data RAM. In the first type, the c ontents of R0 or R1 in the current register bank provide an eight-bit address, in t he second type of MOVX instructions, the data pointer generates a sixteen- bit address. Please refer to the section “External Data Memory” of core specification for more information. 3.26.1. MOVX A, @R I Operation: (PC) ← (PC) + 1 (A) ← ((Ri)) Bytes: 1 Cycles: 3 Encoding: 1 1 1 0 0 0 1 i 3.26.2. MOVX A, @DPTR Operation: (PC) ← (PC) + 1 (A) ← ((DPTR)) Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 0 0

DR805x Instructions set details - 5 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.26.3. MOVX @R I, A Operation: (PC) ← (PC) + 1 ((Ri)) ← (A) Bytes: 1 Cycles: 4 Encoding: 1 1 1 1 0 0 1 i 3.26.4. MOVX @DPTR, A Operation: (PC) ← (PC) + 1 ((DPTR)) ← (A) Bytes: 1 Cycles: 3 Encoding: 1 1 1 1 0 0 0 0

DR805x Instructions set details - 5 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.27. MUL Instruction: MUL AB Function: Multiply Description: MUL AB multiplies t he unsigned eight-bit int egers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FF H) the overflow flag is set; otherwise it is cleared. The carry flag is always cleared. Operation: (PC) ← (PC) + 1 (A) ← (A) x (B) – result’s bits 7..0 (B) ← (A) x (B) – result’s bits 15..8 Bytes: 1 Cycles: 4 Encoding: 1 0 1 0 0 1 0 0

DR805x Instructions set details - 5 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.28. NOP Function: No operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 0 0

DR805x Instructions set details - 5 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.29. ORL Instruction: ORL <dest-byte>, <src-byte> Function: Logical OR for byte variables Description: ORL performs the bit wise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected (except P, if <dest-byte> = A). The two operands allow six addre ssing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addr essing; when the destination is a direct address, the source can be the accumulator or immediate data. Note: When this instruction is used to modi fy an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.29.1. ORL A, R N Operation: (PC) ← (PC) + 1 (A) ← (A) or (Rn) Bytes: 1 Cycles: 2 Encoding: 0 1 0 0 1 r r r 3.29.2. ORL A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (A) or (direct) Bytes: 2 Cycles: 3 Encoding: 0 1 0 0 0 1 0 1 direct address

DR805x Instructions set details - 6 0 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.29.3. ORL A, @R I Operation: (PC) ← (PC) + 1 (A) ← (A) or ((Ri)) Bytes: 1 Cycles: 3 Encoding: 0 1 0 0 0 1 1 i 3.29.4. ORL A, # DATA Operation: (PC) ← (PC) + 1 (A) ← (A) or #data Bytes: 2 Cycles: 2 Encoding: 0 1 0 0 0 1 0 0 immediate data 3.29.5. ORL DIRECT, A Operation: (PC) ← (PC) + 1 (direct) ← (direct) or (A) Bytes: 2 Cycles: 4 Encoding: 0 1 0 0 0 0 1 0 direct address 3.29.6. ORL DIRECT, #DATA Operation: (PC) ← (PC) + 1 (direct) ← (direct) or #data Bytes: 3 Cycles: 4 Encoding: 0 1 0 0 0 0 1 1 direct address Immediate data Instruction: ORL C, <src-bit>

DR805x Instructions set details - 6 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. Function: Logical OR for bit variables Description: Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state otherwise. A slash (“/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected. No other flags are affected. 3.29.7. ORL C, BIT Operation: (PC) ← (PC) + 2 (C) ← (C) or (bit) Bytes: 2 Cycles: 3 Encoding: 0 1 1 1 0 0 1 0 bit address 3.29.8. ORL C, / BIT Operation: (PC) ← (PC) + 2 (C) ← (C) or /(bit) Bytes: 2 Cycles: 3 Encoding: 1 0 1 0 0 0 0 0 bit address

DR805x Instructions set details - 6 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.30. POP Instruction: POP direct Function: Pop from stack Description: The contents of the internal RA M location addressed by the stack pointer are read, and t he stack pointer is decremented by one. The value read is the transfer to the di rectly addressed byte indicated. No flags are affected. Operation: (PC) ← (PC) + 2 (direct) ← ((SP)) (SP) ← (SP) - 1 Bytes: 2 Cycles: 2 – direct inside SFR 3 – direct inside RAM Encoding: 1 1 0 1 0 0 0 0 direct address

DR805x Instructions set details - 6 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.31. PUSH Instruction: PUSH direct Function: Push onto stack Description: The stack pointer is incremented by one. The contents of the indicated variable are then copied into the in ternal RAM location addressed by the stack pointer. Otherwise no flags are affected. Operation: (PC) ← (PC) + 2 (SP) ← (SP) + 1 ((SP)) ← (direct) Bytes: 2 Cycles: 4 Encoding: 1 1 0 0 0 0 0 0 direct address

DR805x Instructions set details - 6 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.32. RET Function: Return from subroutine Description: RET pops the high and low-order by tes of the PC successively from the stack, decrementing the stack point er by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. Operation: (PC15-8) ← ((SP)) (SP) ← (SP) - 1 (PC7-0) ← ((SP)) (SP) ← (SP) - 1 Bytes: 1 Cycles: 4 Encoding: 0 0 1 0 0 0 1 0

DR805x Instructions set details - 6 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.33. RETI Function: Return from interrupt Description: RETI pops the high and low-order by tes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected; the PSW is not automatically restored to its pre-interrupt stat us. Program execution continues at the resulting address, which is generally the instruction immediately after the poi nt at which the interr upt request was detected. If a lower or same-level interrupt is pending when the RETI instruction is executed, that one instruction wil l be executed before the pending interrupt is processed. Operation: (PC15-8) ← ((SP)) (SP) ← (SP) - 1 (PC7-0) ← ((SP)) (SP) ← (SP) - 1 Bytes: 1 Cycles: 4 Encoding: 0 0 1 1 0 0 1 0

DR805x Instructions set details - 6 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.34. RL Instruction: RL A Function: Rotate accumulator left Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Operation: (PC) ← (PC) + 1 (An + 1) ← (An) n = 0-6 (A0) ← (A7) Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 0 1 1

DR805x Instructions set details - 6 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.35. RLC Instruction: RLC A Function: Rotate accumulato r left through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags are affected. Operation: (PC) ← (PC) + 1 (An + 1) ← (An) n = 0-6 (A0) ← (C) (C) ← (A7) Bytes: 1 Cycles: 1 Encoding: 0 0 1 1 0 0 1 1

DR805x Instructions set details - 6 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.36. RR Instruction: RR A Function: Rotate accumulator right Description: The eight bits in the accumulator ar e rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Operation: (PC) ← (PC) + 1 (An) ← (An + 1) n = 0-6 (A7) ← (A0) Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 1 1

DR805x Instructions set details - 6 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.37. RRC Instruction: RRC A Function: Rotate accumulator right through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into t he carry flag; the original value of the carry flag moves into the bit 7 position. No other flags are affected. Operation: (PC) ← (PC) + 1 (An) ← (An + 1) n=0-6 (A7) ← (C) (C) ← (A0) Bytes: 1 Cycles: 1 Encoding: 0 0 0 1 0 0 1 1

DR805x Instructions set details - 7 0 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.38. SETB Instruction: SETB <bit> Function: Set bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. 3.38.1. SETB C Operation: (PC) ← (PC) + 1 (C) ← 1 Bytes: 1 Cycles: 1 Encoding: 1 1 0 1 0 0 1 1 3.38.2. SETB BIT Operation: (PC) ← (PC) + 2 (bit) ← 1 Bytes: 2 Cycles: 4 Encoding: 1 1 0 1 0 0 1 0 bit address

DR805x Instructions set details - 7 1 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.39. SJMP Instruction: SJMP rel Function: Short jump Description: Program control branches uncondition ally to the address indicated. The branch destination is computed by addi ng the signed displacement in the second instruction byte to the PC, after incrementi ng the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it. Note: Under the above conditions the inst ruction following SJMP will be at 102 H. Therefore, the di splacement byte of t he instruction will be the relative offset (0123 H - 0102 H ) = 21 H . In other words, an SJMP with a displacement of 0FE H would be a one-instruction infinite loop. Operation: (PC) ← (PC) + 2 (PC) ← (PC) + rel Bytes: 2 Cycles: 3 Encoding: 1 0 0 0 0 0 0 0 relative address

DR805x Instructions set details - 7 2 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.40. SUBB Instruction: SUBB A, <src-byte> Function: Subtract with borrow Description: SUBB subtracts the indicated va riable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand). AC is set if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. When subtracting signed integers OV indicates a negative number produced when a negative va lue is subtracted from a positive value, or a positive result when a positive num ber is subtracted from a negative number. The source operand allows four addressing modes: register, direct, register-indirect, or immediate. 3.40.1. SUBB A, R N Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 2 Encoding: 1 0 0 1 1 r r r 3.40.2. SUBB A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (A) - (C) - (direct) Bytes: 2 Cycles: 3 Encoding: 1 0 0 1 0 1 0 1 direct address

DR805x Instructions set details - 7 3 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.40.3. SUBB A, @R I Operation: (PC) ← (PC) + 1 Bytes: 1 Cycles: 3 Encoding: 1 0 0 1 0 1 1 i 3.40.4. SUBB A, # DATA Operation: (PC) ← (PC) + 2 (A) ← (A) - (C) - #data Bytes: 2 Cycles: 2 Encoding: 1 0 0 1 0 1 0 0 immediate data

DR805x Instructions set details - 7 4 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.41. SWAP Instruction: SWAP A Function: Swap nibbles withi n the accumulator Description: SWAP A interchanges the low and high-order nibble s (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four-bit rotate instruction. No flags are affected. Operation: (PC) ← (PC) + 1 (A3-0) ↔ (A7-4), (A7-4) ↔ (A3-0) Bytes: 1 Cycles: 1 Encoding: 1 1 0 0 0 1 0 0

DR805x Instructions set details - 7 5 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.42. XCH Instruction: XCH A, <byte> Function: Exchange accumulator with byte variable Description: XCH loads the accumulator with the contents of the indicated variable, at the same time writ ing the original accumulator contents to the indicated variable. The source/ destination operand can use register, direct, or register-indirect addressing. 3.42.1. XCH A, R N Operation: (PC) ← (PC) + 1 (A) ↔ (Rn) Bytes: 1 Cycles: 2 Encoding: 1 1 0 0 1 r r r 3.42.2. XCH A, DIRECT Operation: (PC) ← (PC) + 2 (A) ↔ (direct) Bytes: 2 Cycles: 3 Encoding: 1 1 0 0 0 1 0 1 direct address 3.42.3. XCH A, @R I Operation: (PC) ← (PC) + 1 (A) ↔ ((Ri)) Bytes: 1 Cycles: 3 Encoding: 1 1 0 0 0 1 1 i

DR805x Instructions set details - 7 6 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.43. XCHD Instruction: XCHD A, @Ri Function: Exchange digit Description: XCHD exchanges the low-order nibbl e of the accumulator (bits 3-0, generally representing a hex adecimal or BCD digi t), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7- 4) of each register ar e not affected. No flags are affected. Operation: (PC) ← (PC) + 1 (A3-0) ↔ ((Ri)3-0) Bytes: 1 Cycles: 3 Encoding: 1 1 0 1 0 1 1 i

DR805x Instructions set details - 7 7 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.44. XRL Instruction: XRL <dest-byte>, <src-byte> Function: Logical Exclusive OR for byte variables Description: XRL performs the bit wise logica l Exclusive OR operation between the indicated variables, storing the result s in the destination. No flags are affected (except P, if <dest-byte> = A). The two operands allow six addre ssing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addr essing; when the destination is a direct address, the source can be accumulator or immediate data. Note: When this instruction is used to modi fy an output port, the value used as the original port data will be read from the output data latch, not the input pins. 3.44.1. XRL A, R N Operation: (PC) ← (PC) + 1 (A) ← (A) xor (Rn) Bytes: 1 Cycles: 2 Encoding: 0 1 1 0 1 r r r 3.44.2. XRL A, DIRECT Operation: (PC) ← (PC) + 2 (A) ← (A) xor (direct) Bytes: 2 Cycles: 3 Encoding: 0 1 1 0 0 1 0 1 direct address

DR805x Instructions set details - 7 8 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 3.44.3. XRL A, @ R I Operation: (PC) ← (PC) + 1 (A) ← (A) xor ((Ri)) Bytes: 1 Cycles: 3 Encoding: 0 1 1 0 0 1 1 i 3.44.4. XRL A, # DATA Operation: (PC) ← (PC) + 2 (A) ← (A) xor #data Bytes: 2 Cycles: 2 Encoding: 0 1 1 0 0 1 0 0 immediate data 3.44.5. XRL DIRECT, A Operation: (PC) ← (PC) + 2 (direct) ← (direct) xor (A) Bytes: 2 Cycles: 4 Encoding: 0 1 1 0 0 0 1 0 direct address 3.44.6. XRL DIRECT, #DATA Operation: (PC) ← (PC) + 3 (direct) ← (direct) xor #data Bytes: 3 Cycles: 4 Encoding: 0 1 1 0 0 0 1 1 direct address immediate data

DR805x Instructions set details - 7 9 - All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. 4. C ONTACTS If any problems are encountered please contact Digital Core Design. Headquarters: Wroclawska 94 41-902 Bytom POLAND e-mail: iiinnnfffooo@@@dddcccddd...ppplll tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iiinnnfffoooUUUSSS@@@dddcccddd...ppplll tel. : +1 210 422 8268 fax : +1 210 679 7511 Distributors: