DR8051CPU DCD | Alldatasheet

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All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. DDRR88005511CCPPUU High Performance 8-bit Microcontroller ver 3.10 OVERVIEW DR8051CPU is a high performance, area optimized soft core of a single-chip 8-bit em- bedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about low power consump- tion. Additionally an advanced power man- agement unit makes DR8051CPU core perfect for portable equipment where low power consumption is mandatory. DR8051CPU soft core is 100% binary- compatible with the industry standard 8051 8- bit microcontroller. There are two configura- tions of DR8051CPU: Harward where external data and program buses are separated, and von Neumann with common program and ex- ternal data bus. DR8051CPU has RISC archi- tecture 6.7 times faster compared to standard architecture and executes 65-200 million in- structions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty. DR8051CPU is delivered with fully auto- mated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES

  • 100% software compatible with industry standard 8051
  • RISC architecture enables to execute in- structions 6.7 times faster compared to standard 8051
  • 12 times faster multiplication
  • 9.6 times faster division
  • Up to 256 bytes of internal (on-chip) Data Memory
  • Up to 64K bytes of Program Memory
  • Up to 16M bytes of external (off-chip) Data Memory
  • User programmable Program Memory Wait States solution for wide range of memories speed
  • User programmable External Data Memory Wait States solution for wide range of memories speed
  • De-multiplexed Address/Data bus to allow easy connection to memory
  • Interface for additional Special Function Registers
  • Fully synthesizable, static synchronous de- sign with positive edge clocking and no in- ternal tri-states

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

  • Scan test ready
  • 1.3 GHz virtual clock frequency in a 0.35u technological process PERIPHERALS
  • DoCD™ debug unit ○ Processor execution control ○ Run ○ Halt ○ Step into instruction ○ Skip instruction ○ Read-write all processor contents ○ Program Counter (PC) ○ Program Memory ○ Internal (direct) Data Memory ○ Special Function Registers (SFRs) ○ External Data Memory ○ Hardware execution breakpoints ○ Program Memory ○ Internal (direct) Data Memory ○ Special Function Registers (SFRs) ○ External Data Memory ○ Hardware breakpoints activated at a certain ○ Program address (PC) ○ Address by any write into memory ○ Address by any read from memory ○ Address by write into memory a required data ○ Address by read from memory a required data ○ Three wire communication interface
  • Power Management Unit ○ Power management mode ○ Switchback feature ○ Stop mode
  • Interrupt Controller ○ 2 priority levels ○ 2 external interrupt sources CONFIGURATION The following parameters of the DR8051CPU core can be easy adjusted to requirements of dedicated application and technology. Configu- ration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. - Harward • Memory style - von Neumann - synchronous • Program Memory type - asynchronous - used (0-7) • Program Memory wait- states - unused - used • Program Memory writes - unused - synchronous • Internal Data Memory type - asynchronous - used (0-7) • External Data Memory wait-states - unused
  • Interrupts - subroutines location - used • Power Management Mode - unused - used • Stop mode - unused - used • DoCD debug unit - unused DELIVERABLES ♦ Source code: ◊ VHDL Source Code or/and ◊ VERILOG Source Code or/and ◊ Encrypted, or plain text EDIF netlist ♦ VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses ♦ Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet ♦ Synthesis scripts ♦ Example application ♦ Technical support ◊ IP Core implementation support ◊ 3 months maintenance
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.

  • Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementa- tion. Unlimited Designs , One Year licenses allow use IP Core in unlimited number of FPGA bit- streams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months.
  • Single Design license for ○ VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist
  • One Year license for ○ Encrypted Netlist only
  • Unlimited Designs license for ○ HDL Source ○ Netlist
  • Upgrade from ○ HDL Source to Netlist ○ Single Design to Unlimited Designs SYMBOL prgdatai(7:0) xramdatai(7:0) prgdatao(7:0) prgrd xramdatao(7:0) xramaddr(23:0) xramrd xramwr sfroe sfrwe sfrdatao(7:0) sfraddr(7:0) ramoe ramwe ramdatai(7:0) sfrdatai(7:0) int0 int1 clk reset ramdatao(7:0) ramaddr(7:0) stop pmm xramdataz docddatao docdclk docddatai prgwr prgaddr(15:0) prgdataz BLOCK DIAGRAM ramdatai(7:0) int0 int1 clk reset ramdatao(7:0) ALU Control Unit Interrupt Controller Opcode Decoder Program Memory Interface External Memory Interface Power Management Unit Internal Data Memory Interface User SFR Interface DoCD™ Debug Unit sfrdatai(7:0) xramdatai(7:0) prgdatai(7:0) prgaddr(15:0) docddatai docddatao docdclk prgrd xramwr xramrd xramaddr(23:0) xramdatao(7:0) ramwe ramoe sfrwe sfroe sfraddr(7:0) sfrdatao(7:0) pmm stop xramdataz ramaddr(7:0) prgwr prgdatao(7:0) prgdataz

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock reset input Global synchronous reset ramdatai[7:0] input Data bus from Internal Data Memory sfrdatai[7:0] input Data bus from user SFRs prgdatai[7:0] input Input data bus from Program Memory xramdatai[7:0] input Data bus from External Data Memory int0 input External interrupt 0 line int1 input External interrupt 1 line docddatai input DoCD™ data input ramdatao[7:0] output Data bus for Internal Data Memory ramaddr[7:0] output Internal Data Memory address bus ramoe output Internal Data Memory output enable ramwe output Internal Data Memory write enable sfrdatao[7:0] output Data bus for user SFRs sfraddr[7:0] output User SFRs address bus sfroe output User SFRs output enable sfrwe output User SFRs write enable prgaddr[15:0] output Program Memory address bus prgdatao[7:0] output Output data bus for Program Memory prgdataz output PRGDATA tri-state buffers control line prgrd output Program Memory read prgwr output Program Memory write xramdatao[7:0] output Data bus for External Data Memory xramdataz output XDATA tri-state buffers control line xramaddr[23:0] output External Data Memory address bus xramrd output External Data Memory read xramwr output External Data Memory write docddatao output DoCD™ data output docdclk output DoCD™ clock line pmm output Power management mode indicator stop output Stop mode indicator UNITS SUMMARY ALU – Arithmetic Logic Unit performs the arithmetic and logic operations during execu- tion of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) regis- ters and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder – Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit – Performs the core synchroniza- tion and data flow control. This module is di- rectly connected to Opcode Decoder and manages execution of all microcontroller tasks. Program Memory Interface – Contains Pro- gram Counter (PC) and related logic. It per- forms the instructions code fetching. Program Memory can be also written. This feature al- lows usage of a small boot loader loading new program into RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and al- lows core to work with different speed program memories. External Memory Interface – Contains mem- ory access related registers such as Data Pointer High (DPH0), Data Pointer Low (DPL0), Data Page Pointer (DPP0), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. Allows applications soft- ware to access up to 16 MB of external data memory. The DPP0 register is used for seg- ments swapping. STRETCH register allows flexible timing management while accessing different speed system devices by program- ming XRAMWR and XRAMRD pulse width between 1 – 8 clock periods. Internal Data Memory Interface – Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8-bit Stack Pointer (SP) register and related logic. User SFRs Interface – Special Function Reg- isters interface controls access to the special registers. It contains standard and used de- fined registers and related logic. User defined external devices can be quickly accessed (read, written, modified) using all direct ad- dressing mode instructions. Interrupt Controller – Interrupt control module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers. Power Management Unit – Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Man- agement Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. microcontroller is planned to use in portable and power critical applications. DoCD™ Debug Unit – it’s a real-time hard- ware debugger provides debugging capability of a whole SoC system. In contrast to other on- chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memo- ries, all SFRs including user defined peripher- als. Hardware breakpoints can be set and con- trolled on program memory, internal and exter- nal data memories, as well as on SFRs. Hard- ware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCD™ system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A spe- cial care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when de- bug option is no longer used. PERFORMANCE The following tables give a survey about the Core area and performance in ASICs Devices (all CPU features and peripherals have been included): Device Optimization Fmax 0.25u typical area 100 MHz 0.25u typical speed 250 MHz Core performance in ASIC devices For a user the most important is application speed improvement. The most commonly used arithmetic functions and their improvements are shown in table below. An improvement was computed as {80C51 clock periods} divided by {DR8051CPU clock periods} required to exe- cute an identical function. More details are available in core documentation. Function Improvement 8-bit addition (immediate data) 7,20 8-bit addition (direct addressing) 6,00 8-bit addition (indirect addressing) 6,00 8-bit addition (register addressing) 7,20 8-bit subtraction (immediate data) 7,20 8-bit subtraction (direct addressing) 6,00 8-bit subtraction (indirect addressing) 6,00 8-bit subtraction (register addressing) 7,20 8-bit multiplication 10,67 8-bit division 9,60 16-bit addition 7,20 16-bit subtraction 7,64 16-bit multiplication 9,75 32-bit addition 7,20 32-bit subtraction 7,43 32-bit multiplication 9,04 Average speed improvement: 7,58 Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following ta- ble gives a survey about the DR8051CPU per- formance in terms of Dhrystone/sec and VAX MIPS rating. Device Target Clock frequency Dhry/sec (VAX MIPS) 80C51 - 12 MHz 268 (0.153) 80C310 - 33 MHz 1550 (0.882) DR8051CPU 0.25u 250 MHz 40325 (22.951) Core performance in terms of Dhrystones 268 1550 40325 5000 10000 15000 20000 25000 30000 35000 40000 45000 80C51 (12MHz) 80C310 (33MHz) DR8051CPU (250MHz) Area utilized by the each unit of DR8051CPU core in vendor specific technologies is summa- rized in table below. Area Component [Gates] [FFs] CPU* 4850 220 Interrupt Controller 400 40 Power Management Unit 50 5 Total area 5300 265 *CPU – consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface Core components area utilization

All trademarks mentioned in this document http://www.DigitalCoreDesign.com are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved. The main features of each DR8051 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Design Architecture speed grade Program Memory space Stack space size Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Interrupt sources Interrupt levels Data Pointers Timer/Counters UART I\\O Ports Program Memory Wait States Compare/Capture Watchdog Master I2C Bus Controller Slave I2C Bus Controller SPI Fixed Point Coprocessor Floating Point Coprocessor DR8051CPU 6.7 64k 256 256 16M DR8051 6.7 64k 256 256 16M DR8051XP 6.7 64k 256 256 16M 15 2 2 3 2 4 DR8051 family of High Performance Microcontroller Cores The main features of each DR80390 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Design Architecture speed grade Program Memory space Stack space size Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Interrupt sources Interrupt levels Data Pointers Timer/Counters UART I\\O Ports Program Memory Wait States Compare/Capture Watchdog Master I2C Bus Controller Slave I2C Bus Controller SPI Fixed Point Coprocessor Floating Point Coprocessor DR80390CPU 6.7 16M 256 256 16M DR80390 6.7 16M 256 256 16M DR80390XP 6.7 16M 256 256 16M 15 2 2 3 2 4 DR80390 family of High Performance Microcontroller Cores

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