DMC80C49

DMC80C49 DAEWOO | Alldatasheet

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CMOS SINGLE-COMPONENT | oor ttm | 8-BIT MICROCOMPUTER 1] FEATURES . Fi ai © Pin-to-pin compatible with intel’s 80C48/80C35/ | al] 80C49/80C39 : 7 ~~ © 80C48/80C49 Low power mask programmable ROM. © 80C35/80C39 Low power, CPU only. © 1.36 psec instruction cycle. eu All instruction 1 or 2 cycles. re © Ability to maintain operation during AC power ine | ARPRRRTRUOTT ITY =f: © Exit idle mode with an external or internal interrupt | °""" 2) wth signal. © Battery operation. © 3 power consumption selections ~ Normal operation : 12mA @ 11MHz @5V — Idle mode 1 4.8mA @ 11mHz @5V ~ Power down — : 2uA @2V © 80C49 is also available as a standard cell, © 11MHz operation @5V + 10% (7 MAXIMUM RATINGS © Ambient temperature under bias 10C~+70C © Storage temperature 5 -65C~+150C © Voltage on any pin with respect to ground 2 -0.5V~Vee+1V © Maximum voltage on any pin with respect to ground: 7V © Power dissipation 21.5 Watt. S71

80C39 have been designed to provide low power consumption and high performance. the equivalent of the 80C48/80C49 without program memory on-board. Figure 1. Figure 2. Figure 3.

(1 PIN DESCRIPTION [ SvmterPnNel—Funcson | Syinbo Pino ‘nation [vx [20 [Grout GND exerci | «STH | 88 put iv testable wang ta) [Voo____|26 _ |Low Power standby pin JT1, and JNT1 instructions. Vee Main power supply ; +5V dur- Can be designated the timer/ pe eee bet Fo ‘expander. . INT 6 | Interrupt input. Initiates an in- P10-P17 127-34 terrupt if interrupt is enabled. PP areoean | etter [P20-P23_| 21-24 -bit quasi-bidrectional port _| reset. Also testable with cond P24-P27 P20-P23 contain the four high | tional jump instruction.( Active Port 2 order program counter bits ee ot rust remain low fo during an external_program at least 3 machine cycles for memory fetch and serve as a proper éperation. 4-bit 1/O expander bus for Output strobe activated during 8243. _ : a BUS read. Can be used to 0B0-D87 | 12-19|True bidirectional port which enable data onto toe bus from BUS can on or read an external device. synehr using the RD, WR strobes. The port can also ae read Strobe 0 ox be statically latched. (Active low) Contains the 8 low order pro- RESET Input which is used to initialize gram counter bits during an ee ec ‘external program memory (Active low) (Non TTL Vix) fetch, and receives the WR 10 ]Ouput strobe during a bus addressed instruction under write.(Active low) the control of PSEN. Also con- Used as write strobe to exter- ‘tains the address and data dur- nal data memory. ing an external RAM data ALE 11 [Address latch enable. This sig- store instruction, under control nal occurs once during each of ALE, RD, and WR. cycle and is useful as a clock TO 1 input pin testable using the output. conditional transfer instruc- The negative edge of ALE ‘tions JTO and JNTO. TO can be ‘strobes address into external designated as a clock output data and program memory. using ENTO CLK instuction. PSEN Program store enable. This J [eetrearecuasre ———— 373

(CJ PIN DESCRIPTION(Continued) [Symbol [PinNo.[ Function] [Symbol [Fino [Function] PSEN @ fetch to external program memory. Useful for emulation (Con’t) memory.(Actibe low) and debug, and essential. for Single step input can be used ‘testing and program verifica- in conjunction with ALE to tion.(Active high) “single step” the processor XTAL1 One side of crystal input for in- through = each_sinstruction. ternal oscillator. Also input for (Active low) external source. 7 |External access input which (Non TTL Via) forces all program memory XTAL2 Other side of crystal input. fetches to reference external (IDLE MODE DESCRIPTION The 80C48/80C35/80C49/80C39, when placed in idle mode, keeps the oscillator, the internal timer and the ‘external interrupt and counter pins functioning, and maintains the internal register and RAM status. To place the 80C48/80C35/80C49/80C39 in idle mode, a command instruction(op code 01H) is executed. To terminate idle mode, a reset must be performed or interrupts must be enabled and an interrupt signal generated. There are two interrupt sources that can restore normal operation. One is an external signal applied to the interrupt pin. The other is form the overflow of the timer/counter. When either interrupt is invoked, the CPU is taken out of Idle mode and vectors to the interrupt’s service routine address. Along with the idle mode, the standard MCS-48 power-down mode is still maintained. During normal oper- ation, Vec serves as the 5V supply pin for the bulk of the circuitry while the Vo pin supplies only the RAM array. In normal operation both Vcc and Von are at 5V. However, for power-down operation, Vec is at ground and Von is reduced to its standby value. To be certain that RAM is not inadvertently accessed and altered during power down, reset should be ap- plied to the processor until Vcc is at ground level. 374

(1) POWER DOWN MODE DESCRIPTION Extra circuitry has been added to the 80C48/80C49 ROM version to allow power to be removed from all but the data RAM array for low power standby operation. In the power down mode the contents of data RAM can be maintained while drawing typically 10% to 15% of normal operating power requirements. Vec serves as the 5V supply pin for the bulk of circuitry while the Voo pin supplies only the RAM array. In normal operation both pins are a 5V while in standby, Vic is at ground and Vpo is maintained at its ‘standby value. Applying Reset to the processor through the RESET pin inhibits any access to the RAM by the processor and guarantees that RAM cannot be inadvertently altered as power is removed from Voc. A typical power down sequence occurs as follows : 1) Imminent power supply failure is detected by user defined POWER circuitry. SUPPLY processor |, Signal must be early enough to allow 80C48 to save all INTERRUPTED! Pow! rod rower TE i} NORMAL Necessary data before Vc falls below normal operating FAILSIGNAL [i "|" ~~ sequence. limits. H ine +e 2) Power fail signal is used to interrupt processor and vector DATA'SAVE ACCESS TO ROUTINE — DATARAM it to a power fail service routine, EXECUTED INHIBITED 3) Power fail routine saves all important data and machine status in the internal data RAM array. Rou- tine may also initiate transfer of backup supply to the Voo pin and indicate to external circuitry that power fail routine is complete. 4) Reset is applied to guarantee data will not be altered as the power supply falls out of limits. Reset must be held how until Vcc is at ground level. SS EU EE 375

‘Accumulator Mnemonic Description Bytes Cycle Memenie Decrgtion byte Cydee ons out, Or immediateto BUS 2 ADD A, R ‘Acid register 20 A ' ' MOVD A, P Input expender-port to 1 2 ADD A,@R ‘Add data memory toA 1 1 A ADO A. fide, Addl inemedionn to A 2 2 MovoP, A Output A to expander 1 2 ADDCA,R ‘Add register with carry 1 1 port ADDCA,@R ‘Add data memory ' ' ANLDP, A ‘And A to expander 1 2 with carry port ADOCA, ffdata Add iewmadows wih 2 2 ORLDP, A Or Ato expander port 1 2 carry ANLA,R ‘And register to A 1 1 ANLA,@R And data memory to A 1 1 Roisters ANL A, # dota And immediate to A 2 2 ORLA,R Or register to A 1 1 Mnemonic Description Bytes Cycle ORLA, @R Or datamemorytoA 1 1 Incr Increment register 1 ' ORL A, # date Or immediateto A 2 2 INC @R Increment data 1 1 XRLA,R Exclusive or register 1 1 memory toA DECR Decrement register 1 1 XRLA,@R Exclusive or date 1 1 memory to A XRL. A, # data Exclusive or 2 2 Branch Immediate to A INCA increment A 1 1 Mnemonic Description Byte Cycle CECA Decrernent A 1 1 IMP addr Jump unconditional 2 2 CLRA Clear A 1 1 MPP @A, Jump indirect 1 2 CPLA Complement A 1 1 DINZR, addr Decrement register 2 2 DAA Decimal adjust A 1 1 nd skip SWAP A ‘Swap nibbles of A 1 1 sCoddr dump on carry = + 2 2 RLA Rotate A left 1 1 ING addr dump on carry = 0 2 2 RLCA Rotate A left 1 1 SZ edd dump on A zero 2 2 through carry JNZ addr Jumpon Anot zero 2 2 RRA Rotate A right 1 1 STO addr Jump on TO = 1 2 2 RRCA Rotate A right 1 1 INTO addr Jump on TO =0 2 2 through carry STI addr Jump on Tt =1 2 2 INT! eddr Jump on Ti =0 2 2 FO addr Jump on FO = 1 2 2 Input/Output JP addr Jump on FI = 1 2 2 STF eddr Jump on timer flag 2 2 Mnemonic Description Bytes Cycles JN1 addr Jump on INT =0 2 2 INA,P Input port to A 1 2 Bb addr Jumpon accumulator 2 2 OUTLP,A Output A to port 1 2 bit ANLP, # date And immediate to port 2 2 ORLP,# data — Orimmediateto port 2 2 INS A, BUS Input BUS to A 1 2 Subroutine OUTLBUS,A Output Ato BUS 1 2 ANL BUS, And immediate to 2 2 Mramenie Descrietion Bytes Cycle # data gus CALL addr Jump to subroutine 2 2 rE 376

© INSTRUCTION SET (Continued) Subroutine (Con‘t) Timer/Counter Mnemonic Description Bytes Cycles Moemonic Description. = Byten_ Cycles RET Return 1 2 MoV A,T Read timer/eounter) 1 1 RETR Return and restore 1 2 MOV T. A Losdtimer/counter 1 status STRTT Start timer 1 1 STRTCNT Start timer 1 1 STOPTCNT Stop timer/counter 1 1 Flags EN TONTI Enable timericounter 1 1 interrupt weenie ones ove ovat DIS TENT! Disable timer/counter 1 1 carry cre Complement carry 1 1 inverrup CLR FO Cheer flag 0 1 1 CPL FO Complement flag 0 1 1 Control CLR Ft Clear flag 1 1 1 PLFA Complement fiag 1 1 1 Mnemonic Description Bytes Cycles ENI Enable external 1 1 Interrupt Data Moves ois! Disable external 1 1 interrupt Mnemonic Desoription Byes Coles SEL RBO Select register benkO 1 1 MOV A, R Move register to A i ' SEL ABI Select repister benk 11 ' MOV A, @R ‘Move deta memory ’ 1 SEL MBO Select memory bankO 1 1 oA SEL MBI Select memory bank 1 1 1 MOV A, # data Move immediate toA = 22 ENTOCLK Enable clock output 1 1 MOV R, A Move A to regittar 1 1 on T0 MOV@R,A Move A to data 1 1 memory MOV R, # deta Move immediate to 2 2 Mnemonic Description Bytes Cycles register ‘NOP No operation 1 1 MOV @R, # data Move immediate to 2 2 toe Select Idle Operation 1 P date memory MOVA,PSW Move PSWto A 1 1 MOV PSW,A Move A to PSW 1 1 XCHA,R Exchange A and 14 register XCH A, @R Exchange Asnddeta 1 1 memory XCHD A, @R Exchange nibble of A 1 1 and register MOVX A,@R Move extarnal data 1 2 memory to A MOVX@R, A Move A to external 1 2 dats memory MOVPA,@A Mowe to A from 12 current page MOVP3.A,@ —— MovetoAfrom pepe 31 2 i 377

(7 ELECTRICAL CHARACTERISTICS(D.C) (Tx=0~T0°C, Vec=Voo=8V + 10%, IVer— Vogl S1V, Vss=0V fens] remem] Vi [Input Low Voltage -05 v Memon [|| | Wiarton vag x, REF) =| fae Vin [Input High Voltage Ve | V Nm re Hon Vox, RESET) Lone] | Wav Vou Output Low Voltage v lo. =1.8MA Mommy | | Vox [Output Low Voltage Vln =1.6mA [wowamer |_| | [a loupe Hg Votapst@05) ——_—_fureve| | [Wino ua Vou [Output High Voltage Vo | lov=—20nA Vow | Output High Voltage 0.78Vcc Vo lov=—40nA [Nooo ||| ln Input Leakage Current BA \\VssSViwSVec ho | Output Leakage Current (BUS, TO) || +5 i [eset (High Impedance State) __ le __|Input Leakage Current (RESET) fet VsSVnsVi lito [Power Down Standby Current 2 HA |Vp=2V RESET ro it sw} lec Active Current(mA) [Ve | 48V “55V] [Ve | 48V av | (BBV | p__ Mec S5V | i a i [ae [ea Absolute Maximum Unloaded Current a a ee 378

(7 ELECTRICAL CHARACTERISTICS(A.C) (T,=0~70C, Vec=Voo=5V + 10%, IVec—VoulS1V, Vss=0V) a f(t) | TIMHz | | Conditions ii Perometer | et) et Om [en [=| Gack Bariog | ‘tal frea[ 908 [~1000"| ne] (ot 3) tu | ALE Pulse Width [sem [ow [tet ta __| Addr Setup to ALE 2-110 | 70 || ns | (Note 2) | tus [Ade Hold from ALE 0 re | [tax | Control Pulse Width(RO, WA) | 780-200 | 40 [ns | toa | Control Pulse Width(PSEN) | et-200_ | 350 | [os || tow__| DAta Setup before WR | 65e-200 | 390_| [rs | | tw __| Data Hold after WR | eso [40 | ns [| tox __| Data Hol(RD, PSEN) __tse-0 [0 [0 [ins | | two, ___| RD to Data in [6-170 [| | rs | | ton _| Addr Setup to WR | _st-160 | 300 || ns | [tan | Add Setup to DatalAB) «dt —tose-220 [| 8D ne | tare [Addr Float to PSEN sta | 10 | _ns_| (Note 2) | tiarei_| ALE to Control(RO, WR) | aes | 20 | ns | tice | ALE to Control(PSEN) tse [60 [ns teu___| Control to ALE(RD, WR, PROG) j 40 | 0 | ns | | teu __| Control to ALE(PSEN) | ado | 320 | ns [| ter__| Port Control Setup to PROG | sao [0 | [ns | | [xc Poe Contra Hold to PROG [#200 | 00 | [rs | tmx | BROG toP2rgut Vata Pete ter Input Data Hold from PROG 15t IH | [tor [Ouro Data Setp ead | 50 oe | [tr | Output Data Hold | 15t-90 | 40 | ns | [i | PROG Pie Wt [tosi-250 [70 [ne | [tm [Port 21/0 Setup to ALE | aez00 [160 |e Port 21/0 Hold to ALE Z 15t-120 15 a trv Port Output from ALE | 45t+100 [rn || torm _ | TO Rep Rate 3t en a to [Oye Time ds Note : 1. Control output C, =80pF, Bus outputs C; = 150pF 2. Bus high impedance Load 20pf 3. f(t) assumes 50% duty cycle on X1, X2 Max. clock period is for a 1MHz crystal input. 379

© Waveforms Eaceiti Seucstuarca— fre} — cs a a ee ee trea] toca] _ fe tear Fb tec toa FE . = f ‘arcr+| ‘oR —fau oY stort FLoaring! be DRESS INSTRUCTION ADDRESS ‘Rot tady 02 taot Instruction Fetch From Program Memory Freed From External Date Memory —attarer -— ALE bf tccrttoatk— 2av 5 " es a oo PL) Aponess _ [OW bo wo AC. testing inputs are driven at 24V for e logic “1” and FLOATING susrLoarina XY __ DATA KF Inde at 2V for lol “1"and OV for one "0" FLOATING taw — Write To External Deta Memory Input And Output For A.C. Tests © Suggested ROM verification algorithm for CMOS devices only INITIAL ROM DUMP CLCLE ‘SUBSEQUENT ROM UMP CYCLES ave SUT }(ourPuT) H i +12v T + eA. }aNPUT) ' oe] DATA, INPUT) (OUTPUT) | (INPUT) (ouTPuT): i i i i i i | NPUTY H cae | C49 Veo" Yoo = *8¥ ATO [ADDR Veg" OV atl o | 0 ——— 380

C TIMING DIAGRAM (Continued) © 1/0 Port timing st CYCLE 2’ND CYCLE ‘am few aus fe PSEN a bn Xr ton a re P2-27 o | P1017 PORT 24-27, PORT 10-17 DATA X NEW PORT DATA t I OSCILLATOR MODE DRIVING FROM EXTERNAL SOURCE ° 2 2 T Fa] xTALI XTALI | Miz es ES H 74 HEXX By GI] XTAL2 SERIES GATE XTAL2 23KQ Ct = 20pF + 2pF - STRAY <opF C2= CRYSTAL - STRAY <8pF (C3 = 20pF + 2pF - STRAY <5pF Crystal series resistance should be les than 3022 at XTALI must be high 35-65% of the period.

11 MHz; lees than 762 at 6 MHz; less then 18022 at

3.6 MHz, ise and fall times must not be slower then 20 nS,

CD TIMING DIAGRAM(Continued) © Port 1/Port 2 timing vst vee pe Greve ae ) a | ee ee I | | ! ] a feu | { | | ore comer [X__1 re X__ronrsmmoara KX _enrna ara) = 1 1 OUTPUT i | ‘ | | — fetcat LP ue tp, EXPANDER tu —+— La pn YY \\ i tor PORT over [|X ren___—_—_—‘XfonranasoariXrontconrnotXjaureu oaral | | [1 ey oe | | [| fF" 4 wr Pe )XforraszspardXfponr cowrnou)X ERI) ] | btcrt-wre-| Vy | pr PROG N / ne 382