DM9081_01 DAVICOM | Alldatasheet
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Version: DM9081-DS-F02 February 02, 2001 General Description The 10BASE-T Hub Controller (DM9081) provides a system level solution for designing IEEE-compliant 802.3 repeaters that incorporate 10BASE-T transceivers. This device integrates the repeater functions specified by section 9 of the IEEE 802.3 standard. The Twisted Pair transceiver is compliant with 10BASE-T standards. The DM9081 provides eight integral Twisted Pair Media Attachment Units (MAUs) and two Attachment Unit Interface (AUI) p o r t s i n a 1 0 0 - p i n Q F P p a c k a g e . The total number of ports per repeater unit can be increased by connecting multiple DM9081 chips via their expansion ports. The DM9081 supports LED drivers to monitor port status. It displays Link, Carrier Sense, Collision, Partition, and Bit Rate Error Status. In minimum mode, Link, Carrier Sense, and Collision Status can be displayed without external TTL devices. Block Diagram TX MUX PREAMBLE JAM SIGNAL FIFO MANCHESTER DECODER RX MUX AUI PORT1 AUI PORT2 TP PORT0 TP PORT7 PLL MANCHESTER ENCODER DATA IN DATA OUTMUX STATE MACHINE TIMER LED PORT2LED PORT1 EXPANSION PORT NRZ DATA EXPIN# EXPOUT# DAT RXP1 RXN1 CDP1 CDN1 TXP1 TXN1 RXP2 RXN2 CDP2 CDN2 TXP2 TXN2 RXD0+ RXD0- TPO0+ DTPO0+ DTPO0- TPO0- RXD7+ RXD7- TPO7+ DTPO7+ DTPO7- TPO7- AUI1_CRS_LED AUI2_CRS_LED COL_LED AUI_LED TP_BIT_LED TP_POL_LED TP_JAB_LED TRAFFIC_LED TP_PAR_LED TP_LINK_LED TCK LED_LATCH RX_CLK
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Version: DM9081-DS-F02 February 02, 2001 Table of Contents Timing Waveforms Layout Recommendation
Version: DM9081-DS-F02 February 02, 2001
Features
Repeater functions comply with IEEE 802.3 Repeater Unit specification Eight Integral 10BASE-T transceivers utilize the required pre-distortion transmission technique Two Attachment Unit Interface (AUI) ports allow connection with 10BASE5 (Ethernet) and 10BASE2 (Cheapernet) networks Design a Dumb Hub in minimum mode by using minimum external logic that can respond to Link, Carrier Sense and Collision Status from LED Supports one LED output per port for additional status indicators such as Link, Partition, Carrier Sense, etc. Built-in Jabber LED reports global Jabber information of the DM9081 Hub Built-in Traffic LED indicates Hub global 10MHz bandwidth utilization status Expandable to accommodate two DM9081 connections, with no external logic required On board PLL, Manchester encoder/decoder and FIFO Expandable to accommodate increased number of repeater ports. Recommended IC cascade number: under 3 and inclusive Preamble loss effects eliminated by deep FIFO Each port can be isolated (partitioned) and reconnected separately Twisted Pair Link Test capability Full amplitude and timing regeneration for retransmitted signals Low power CMOS process with single 5V supply 100-pin QFP package Pin Configuration DTPO3- TPO3- DVDD DVDD LI/RX7 LI/RX6 LI/RX5 LI/RX4 DVDD LI/RX3 LI/RX1 LI/RX0 LI/RX2 AUI2_CRS_LED COL_LED RESET# TESTPIN1 TESTPIN0 DGND EXPIN# DAT EXPOUT# TCK NC NC DVDD CDP2 CDN2 RXP2 RXN2 TXP2 TXN2 CDP1 CDN1 RXP1 AGND RXD0- RXD1+ RXD2- RXD3+ RXD3- RXD4+ RXD4- RXD5+ RXD5- RXD6+ RXD6- RXD7+ RXD7- DVDD TPO7+ DTPO7+ DTPO7- TPO7- DGND TPO6+ DTPO6+ DTPO6- TPO6- DVDD TPO5+ DTPO5+ DTPO5- TPO5- DGND TPO4+ DTPO4+ DTPO4- TPO4- 100 TPO3+ DTPO3+ DTPO1+ DTPO1- TPO1- AVDD AGND DM9081F DGND DVDD TPO0+ DTPO0- TPO0- DGND TPO1+ DVDD TPO2+ DTPO2+ DTPO2- TPO2- DGND AUI1_CRS_LED RXD2+ RXD1- RXD0+ AVDD TXN1 TXP1 RXN1 DTPO0+ LED_LATCH AUI_LED TP_BIT_LED TP_POL_LED TP_JAB_LED TRAFFIC_LED TP_PAR_LED TP_LINK_LED
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Version: DM9081-DS-F02 February 02, 2001 Pin Description Pin No. Pin Name I/O Description Transceiver 100, 1 99, 2 34, 31 33, 32 39, 36 38, 37 44, 41 43, 42 49, 46 48, 47 84, 87 85, 86 89, 92 90, 91 94, 97 95, 96 DTPO3+/- TPO3+/- TPO4+/- DTPO4+/- TPO5+/- DTPO5+/- TPO6+/- DTPO6+/- TPO7+/- DTPO7+/- TPO0+/- DTPO0+/- TPO1+/- DTPO1+/- TPO2+/- DTPO2+/- O TP Driver Outputs. The TPO+/- output generate 10Mbits/s Manchester-encoded data. The DTPO+/- outputs are one-half bit time delayed and inverted with respect to TPO+/-. These four outputs provide the TP drivers with pre-distortion capability 52, 51 54, 53 56, 55 58, 57 60, 59 62, 61 64, 63 66, 65 RXD7+/- RXD6+/- RXD5+/- RXD4+/- RXD3+/- RXD2+/- RXD1+/- RXD0+/- I 10BASE-T Port Different Data Receivers 70, 69 76, 75 TXP1, TXN1 TXP2, TXN2 O AUI Port Different Data Drivers. The outputs are source followers that require a 270Ω pull-down resistor 72, 71 78, 77 RXP1, RXN1 RXP2, RXN2 I AUI Port Differential Receive Input Pair 74, 73 80, 79 CDP1, CDN1 CDP2, CDN2 I AUI Port Different Collision Input Pair Expansion Port
24 EXPOUT# O The assertion of this signal indicates that DM9081 is transmitting
data on DAT pins. It is active low
22 EXPIN# I The assertion of this signal indicates that DM9081 is receiving data
on DAT pins. The receiving data will be broadcast to the other ports. It is active low and is internally pulled high with a 100KΩ resistor 23 DAT I/O,Z The DAT pins of all DM9081 chips are inter-connected. The active DM9081 drives DAT with repeated data or jam signals in NRZ format. The inactive DM9081 receives the repeated data or jam signals from the DAT pin
Version: DM9081-DS-F02 February 02, 2001 Pin Description Pin No. Pin Name I/O Description Miscellaneous 3, 4, 9, 30, 40, 50, 83, 93 DVDD P Digital Power 14, 21, 35, 45, 88, 98 DGND P Digital Ground 18 RESET# I Active low to reset the internal logic of DM9081. It should be synchronized to X2 if multiple DM9081s are used 20, 19 TESTPIN0 TESTPIN1 I These two pins are used to select LED display mode. Normal mode is selected if both pins are connected to VDD. Minimum mode is selected if both pins are connected to GND. Other settings are prohibited 26, 29 NC - These pins should be left open
27 X2 I A 20MHz oscillator or crysta l should be attached to this pin
28 X1 O This pin is used in crystal connection only. It is left open when using an oscillator 67, 81 AV DD P Analog Power 68, 82 AGND P Analog Ground LED Display Pins
5 LED_LATCH
(LI/RX7) O This pin is used to latch the serial LED information from pins 6 to 13 In minimum mode, this pin sends out TP7 Link and Carrier Sense status
6 AUI_LED
(LI/RX6) O This pin transmits AUI port status synchronous to TCK In minimum mode, this pin sends out TP6 Link and Carrier Sense status
7 TP_BIT_LED
(LI/RX5) O This pin sends out global bit rate error status of the DM9081 Hub In minimum mode, this pin sends out TP5 Link and Carrier Sense status
8 TP_POL_LED
(LI/RX4) O In minimum mode, this pin sends out TP4 Link and Carrier Sense status
10 TP_JAB_LED
(LI/RX3) O This pin transmits global jabber status of the DM9081 Hub In minimum mode, this pin sends out TP3 Link and Carrier Sense status
11 TRAFFIC_LED
(LI/RX2) O This pin sends out utilization of 10MHz bandwidth synchronous to TCK In minimum mode, this pin sends out TP2 Link and Carrier Sense status
12 TP_PAR_LED
(LI/RX1) O This pin sends out the partition status synchronous to TCK for the eight TP ports In minimum mode, this pin sends out TP1 Link and Carrier Sense status
13 TP_LINK_LED
(LI/RX0) O This pin sends out the link and carrier sense status synchronous to TCK for the eight TP ports In minimum mode, this pin sends out TP0 Link and Carrier Sense status
15 AUI1_CRS_LED O Active low for 52ms when AUI Port 1 detects carrier
16 AUI2_CRS_LED O Active low for 52ms when AUI Port 2 detects carrier
17 COL_LED O Active low for 26 ms when collision is detected
25 TCK O A 10MHz clock synchronous to X2
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Version: DM9081-DS-F02 February 02, 2001 Functional Description The DM9081 Integrated Multiport Controller is a single chip implementation of an IEEE 802.3 Ethernet repeater (Hub). The DM9081 chip provides eight integral 10BASE-T ports plus two AUI ports, comprising the basic repeater. The DM9081 is also expandable, enabling the implementation of high port count repeaters based on more than one DM9081 chip. The DM9081 chip complies with the full set of repeater basic functions, as defined in Section 9 of ISO 8802.3 (ANSI/IEEE 802.3C). These functions are summarized below. Repeater Function When any single network port senses the start of a packet on its receive lines, the DM9081 chip will broadcast the received data to all other network ports. The repeated data will also be presented on the expansion port to provide multiple DM9081 chip repeater applications. Signal Regeneration When re-transmitting a packet, the DM9081 chip makes sure that the outgoing packet complies with the 802.3 specification in terms of preamble instructions, voltage amplitude and timing characteristics. Data packets repeated by the DM9081 chip will contain a minimum of 62 preamble bits before the start of Frame Delimiter. Finally, signal symmetry is restored to data packets repeated by the DM9081 chip, removing jitter and distortion caused by network cabling. Collision Function The DM9081 will detect and respond to collision conditions as specified in IEEE 802.3. A multiple DM9081 repeater (Hub) implementation also complies with the 802.3 specification. Specifically, a repeater based on one or more DM9081 chips will handle the transmit collision and one-port-left collision conditions correctly. Auto Partition/Reconnection The DM9081 monitors any TP ports or AUI ports and partitions them once certain criteria are met. TP ports and AUI ports will be partitioned under extended duration or when frequent collisions occur. Each TP port and the AUI port are partitioned separately, and are independent of other network ports. The DM9081 chip will cause the port to partition under either of following conditions. 1. A collision condition exists continuously for 1024-bit times (for example, when the AUI port SQE signal is active and the TP port is transmitting simultaneously and receiving). 2. Whenever each of 32 consecutive attempts to transmit to that port results in a collision. Any partitioned port can be reconnected if a packet longer than 512-bit times is transmitted or received from that port without collision. Fragment Extension If the total packet length received by the DM9081 is less than 96 bits, including preamble, the DM9081 chip will extend the repeated packet length to 96 bits by appending a Jam sequence to the original fragment. Link Integrity Test The integral TP ports implement the Link Test function, as specified in the 802.3 10BASE-T standard. The DM9081 will transmit Link Test pulses to any TP port after that port transmitter has been inactive for more than 8ms but less than 17 ms. Conversely, if a TP port does not receive any data packets or Link Test pulses for more than 65ms but less than 132ms, that port will enter link fail state. A port in link fail state will be disabled by the DM9081 chip (repeater transmit functions are disabled) until it receives either four consecutive Link Test pulses or a data packet. Note, however, that the DM9081 chip will always transmit Link Test pulses to all TP ports regardless of whether the port is enabled, partitioned, or in link fail state.
DM9081 chip following reset. Table 1. Initial State of DM9081 signal (EXPIN#), and an output signal (EXPOUT#). chips and asserts the EXPIN# line to each DM9081.
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Figure 1. Multiple DM9081 Devices
it responds to the next packet. until it responds to the next packet. low at least 52ms until it responds to the next packet. An example is shown in Figure 2. Figure 2. Minimum Mode Implementation
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devices to display the status from the LED pins. strobe in the state of the following LED pins. Figure 3. Serial LED Signal Timing Figure 4. Normal Mode Implementation
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pulse transformers into one package. Figure 5. Typical Single TP Port Using External Components Figure 6. Typical Single AUI Port Using Components
Version: DM9081-DS-F02 February 02, 2001 Absolute Maximum Ratings Absolute Maximum Ratings* ( 25°C ) Symbol Parameter Min. Max. Unit Conditions DVCC,AVCC Supply Voltage -0.5 7.0 V VIN DC Input Voltage (VIN) -0.5 5.5 V VOUT DC Output Voltage(VOUT) -0.5 5.5 V Tc Case Temperature Range 0 85 °C Tstg Storage Temperature Rang (Tstg) -65 150 °C LT Lead Temp. (TL, Soldering, 10 sec.) --- 220 °C ESD ESD Rating (Rzap=1.5K, Czap=100pF) --- 2000 V Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter Min. Typ. Max. Unit Conditions VIL Input Low Voltage -0.5 0.8 V DGND=0.0V, Except DAT VIH Input High Voltage 3.0 DV DD+0.5 V Except DAT VOL Output Low Voltage - 0.4 V I OL=4mA VOH Output High Voltage 3.5 - V I OH=-4mA IIL Input Leakage Current (also DAT as Input) - 10 uA DGND<V IN<DVDD VILX X2 Crystal Input Low Voltage -0.5 1.0 V DGND=0.0V VIHX X2 Crystal Input High Voltage 3.8 DV DD+0.5 V DGND=0.0V IILX Crystal Input Low Current - 10 uA V IN=DGND IIHX Crystal Input High Current - 10 uA V IN=DVDD AUI Port VOD Differential Output Voltage (TXP, TXN) 550 1200 mV 78Ω termination, and 270Ω from each to GND VOB Differential Output Voltage Imbalance (TXP, TXN) - 40 mV 78Ω termination, and 270Ω from each to GND VU Undershoot Voltage (TXP, TXN) - 100 mV 78Ω termination, and 270Ω from each to GND VDS Differential Squelch Threshold (RXP/RXN and CDP/CDN) 175 300 mV Negative pulse VCM Differential Input Common Mode Voltage (RXP/RXN and CDP/CDN) V DD/2 V Twisted Pair Port VTIDF TP Input Voltage 350 2000 mV
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Version: DM9081-DS-F02 February 02, 2001 VOL VOH TPO+/TPO-/DTPO+/DTPO-: Low High 4.9 0.1 V V DC Output Series Impedance: RTP0 TP Drives - 10 Ω RTPI RXD+/RXD- Input Resistance 16 24 KΩ Power Supply Current IDD Power Supply Current (idle) - 130 - mA Power Supply Current (Transmitting with TP Port load) - 240 - mA Symbol Parameter Min. Typ. Max. Unit Conditions AUI Port TCB Collision Turn-on Time 0 900 ns TCE Collision Turn-off Time 0 900 ns tCIDL CDP High To Idle Time 250 350 ns tCPH Collision High-Pulse Width 40 50 60 ns tCP Collision Period 80 100 120 ns tRIDL RXP High To Idle Time 250 350 ns Twisted Pair Port tTPDY DTPO- To TPO+ & DTPO+ To TPO- Delay 47 53 ns tRD Receive Delay From RXD To RXP/RXN 0 500 ns tROFF RXD+ High To Idle Time 200 ns tLP Transmitted Link Integrity Pulse Period 8 16 24 ms tLPWT Link Integrity Pulse Width For TPO+ 80 100 120 ns tLPWD Link Integrity Pulse Width For DTPO 40 50 60 ns Jabber Timing tJMT Maximum Transmit Time for TPO 45 50 55 ms tJCB Time from Jabber to Enable CI Output 0 900 ms tJU Unjab Time 250 450 750 ms
Version: DM9081-DS-F02 February 02, 2001 Timing Waveforms Expansion Port Input Timing Symbol Parameter Min. Typ. Max. Unit Conditions tDJSET DAT Setup Time - 20 ns tDJHOLD DAT Hold Time 60 - ns TCK EXPOUT EXPIN DAT tDJSET IN tDJHOLD Expansion Port Output Timing Symbol Parameter Min. Typ. Max. Unit Conditions tHRL TCK Rising Edge to EXPOUT# Driven Low - 20 ns CL=100pF tHRH TCK Rising Edge to EXPOUT# Driven High - 20 ns CL=100pF tHDR TCK Rising Edge to DAT Driven - 20 ns CL=100pF tHDZ TCK Rising Edge to DAT Not Driven - 20 ns CL=100pF TCK EXPOUT EXPIN DAT tHRL tHDR tHRH tHDZ OUT
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Version: DM9081-DS-F02 February 02, 2001 Expansion Port Collision Timing Symbol Parameter Min. Typ. Max. Unit Conditions tDOFF DAT Data Off - 20 ns CL=100pF TCK EXPIN DAT OUT tDOFF EXPOUT AUI Transmit Timing Symbol Parameter Min. Typ. Max. Unit Conditions tTXTD X2 Rising Edge To TXP/TXN Toggle - 30 ns tTXTR TXP, TXN Rise Time (10% to 90%) 2.5 5.0 ns tTXTF TXP, TXN Fall Time (90% to 10%) 2.5 5.0 ns tTXRM TXP, TXN Rise & Fall Time Mismatch - 1.0 ns TXP TXN tTXTD tTXTR tTXTF 11 1 1 00 1 0
Version: DM9081-DS-F02 February 02, 2001 AUI Receive Timing Symbol Parameter Min. Typ. Max. Unit Conditions tPWORX RXP/RXN Pulse Width Accept/Reject Threshold 15 45 ns |V IN|>|VASQ| tPWKRX RXP/RXN Pulse Width Maintain/Turn-Off Threshold 136 200 ns |V IN|>|VASQ| RXP/RXN VASQ tPWKRX tPWORX tPWKRX AUI Collision Timing Symbol Parameter Min. Typ. Max. Unit Conditions tPWOCD CDP/CDN Pulse Width Accept/Reject Threshold 10 26 ns |V IN|>|VASQ| tPWKCD CDP/CDN Pulse Width Maintain/Turn-off Threshold 90 160 ns |V IN|>|VASQ| CDP/CDN VASQ tPWOCD tPWKCD Transmit Timing Symbol Parameter Min. Typ. Max. Unit Conditions tPREDY DTPO- to TPO+ and DTPO+ To TPO- Delay 47 53 ns tIDL TPO+ High To Idle Time 250 350 ns TPO+ DTPR+ TPO- DTPR- tPREDY tIDL
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Version: DM9081-DS-F02 February 02, 2001 Receive Timing Symbol Parameter Min. Typ. Max. Unit Conditions tROFF RXD+ High To Idle Time 200 ns RXD+ RXD- tROFF Link Integrity Timing Symbol Parameter Min. Typ. Max. Unit Conditions tLP Transmitted Link Integrity Pulse Period 8 16 24 ms tLPWT Link Integrity Pulse Width For TPO+ 80 100 120 ns tLPWD Link Integrity Pulse Width For DTPO+/- 40 50 60 ns TPO+ DTPO+ TPO- DTPO- tLPWT tLPWD tLPWD tLP
decoupling values for the DM9081 chip. Figure 7. DM9081 Device Power Supply Decouping Recommendations
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cross-talk within the filters. Figure 8. DM9081 Device Power Plane Recommendations
Version: DM9081-DS-F02 February 02, 2001
Package Information
QFP 100L Outline Dimensions Unit: Inches/mm A1 A2 A Seating Plane b31 50 81100 HD D F E HE e GE GD See Detail F D y L GD ~~~ L1 Detail F c Symbol Dimensions In Inches Dimensions In mm A 0.130 Max. 3.30 Max. A1 0.004 Min. 0.10 Min. A2 0.112±0.005 2.85 ±0.13 b 0.012 +0.004 0.31 +0.10 -0.002 -0.05 c 0.006 +0.004 0.15 +0.10 -0.002 -0.05 D 0.551±0.005 14.00 ±0.13 E 0.787±0.005 20.00 ±0.13 e 0.026 ±0.006 0.65 ±0.15 F 0.742 NOM. 18.85 NOM. GD 0.693 NOM. 17.60 NOM. GE 0.929 NOM. 23.60 NOM. HD 0.740±0.012 18.80 ±0.31 HE 0.976±0.012 24.79 ±0.31 L 0.047±0.008 1.19 ±0.20 L1 0.095 ±0.008 2.41 ±0.20 y 0.006 Max. 0.15 Max. Note: 1. Dimensions D&E do not include resin fins. 2. Dimensions GD & GE are for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system.
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Version: DM9081-DS-F02 February 02, 2001
Ordering Information
Part Number Pin Count Package DM9081F 100 QFP DM9081FP 100 QFP (Pb-Free) Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM deserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. DAVICOM’s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer’s orders shall be based on these terms. Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that re the industry’s best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Industrial Park, Hsin-chu City, Taiwan, R.O.C. TEL: +886-3-5798797 FAX: +886-3-5646929 MAIL: sales@davicom.com.tw HTTP: http://www.davicom.com.tw WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.