DM81LS95AN

DM81LS95A FAIRCHILD | Alldatasheet

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■ Typical power dissipation DM81LS95A, DM81LS97A 80 mW DM81LS96A 65 mW ■ Typical propagation delay DM81LS95A, DM81LS97A 15 ns DM81LS96A 10 ns ■ Low power-Schottky, 3-STATE technology Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions DM81LS95A and DM92LS96A Note 1: Both G1 and G2 must be LOW for outputs to be enabled. DM81LS97A Order Number Package Number Package Description DM81LS95AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM81LS95AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM81LS96AWM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM81LS96AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM81LS97AN N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Descriptions A1–A8 Inputs Y1–Y8 Outputs G 1–G 2 Active LOW Output Enables (Note 1) Pin Names Descriptions A1–A8 Inputs Y1–Y8 Outputs G 1 Active LOW Output Enable (Y1–Y4) G 2 Active LOW Output Enable (Y5–Y8)

www.fairchildsemi.com 2 DM81LS95A • DM81LS96A • DM81LS97A Logic Symbols DM81LS95A DM81LS96A DM81LS97A Truth Tables DM81LS95A DM81LS96A DM81LS97A Inputs Output G 1G 2A Y H X X Hi-Z X H X Hi-Z LLHH LLL L Inputs Output G 1G 2A Y H X X Hi-Z X H X Hi-Z LLH L LLL H Inputs Output G 1 A1–A4 Y1–Y4 H X Hi-Z LHH LLL G 2 A5–A6 Y5–Y8 H X Hi-Z LHH LLL

3 www.fairchildsemi.com DM81LS95A • DM81LS96A • DM81LS97A Absolute Maximum Ratings(Note 2) Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Recommended Operating Conditions Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −5.2 mA IOL LOW Level Output Current 24 mA TA Free Air Operating Temperature 0 70 °C

www.fairchildsemi.com 4 DM81LS95A • DM81LS96A • DM81LS97A over recommended operating free air temperature range (unless otherwise noted) Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Both G inputs are at 2V. Note 5: Both G inputs are at 0.4V. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. VCC = 5V, TA = 25°C Note 7: C L = 5 pF. Symbol Parameter Conditions Min Typ Max Units (Note 3) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level Output Voltage V CC = Min, IOH = Max 2.7 V VIL = Max, VIH = Min VOL LOW Level Output Voltage V CC = Min, IOL = Max 0.5 VIOL = Max, VIH = Min IOL = 12 mA, VCC = Min 0.4 II Input Current @ Max V CC = Max, VI = 7V 0.1 mA Input Voltage IIH HIGH Level Input Current V CC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current V CC = Max V I = 0.5V A (Note 4) −20 µAVI = 0.4V A (Note 5) −50 G −50 IOZH Off-State Output Current V CC = Max, VO = 2.4V 20 µAwith HIGH Level Output V IH = Min, VIL = Max Voltage Applied IOZL Off-State Output Current V CC = Max, VO = 0.4V −20 µAwith LOW Level Output V IH = Min, VIL = Max Voltage Applied IOS Short Circuit V CC = Max −20 −100 mA Output Current (Note 6) ICC Supply Current V CC = Max (Note 4) 16 26 mA Symbol Parameter R L = 667 Ω UnitsC L = 50 pF C L = 150 pF Min Max Min Max tPLH Propagation Delay Time 16 25 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time 28 40 ns HIGH-to-LOW Level Output tPZH Output Enable Time 25 30 ns to HIGH Level Output tPZL Output Enable Time 30 42 ns to LOW Level Output tPHZ Output Disable Time 20 ns from HIGH Level Output (Note 7) tPLZ Output Disable Time 27 ns from LOW Level Output (Note 7)

5 www.fairchildsemi.com DM81LS95A • DM81LS96A • DM81LS97A over recommended operating free air temperature range (unless otherwise noted) Note 8: All typicals are at VCC = 5V, TA = 25°C. Note 9: Both G inputs are at 2V. Note 10: Both G inputs are at 0.4V. Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second. VCC = 5V, TA = 25°C Note 12: C L = 5 pF. Symbol Parameter Conditions Min Typ Max Units (Note 8) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level Output Voltage V CC = Min, IOH = Max 2.7 V VIL = Max, VIH = Min VOL LOW Level Output Voltage V CC = Min, IOL = Max 0.5 VIOL = Max, VIH = Min IOL = 12 mA, VCC = Min 0.4 II Input Current @ Max V CC = Max, VI = 7V 0.1 mA Input Voltage IIH HIGH Level Input Current V CC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current V CC = Max V I = 0.5V A (Note 9) −20 µAVI = 0.4V A (Note 10) −50 G −50 IOZH Off-State Output Current V CC = Max, VO = 2.4V 20 µAwith HIGH Level Output V IH = Min, VIL = Max Voltage Applied IOZL Off-State Output Current V CC = Max, VO = 0.4V −20 µAwith LOW Level Output V IH = Min, VIL = Max Voltage Applied IOS Short Circuit V CC = Max −20 −100 mA Output Current (Note 11) ICC Supply Current V CC = Max (Note 10) 13 21 mA Symbol Parameter R L = 667 Ω UnitsC L = 50 pF C L = 150 pF Min Max Min Max tPLH Propagation Delay Time 10 16 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time 17 30 ns HIGH-to-LOW Level Output tPZH Output Enable Time 15 30 ns to HIGH Level Output tPZL Output Enable Time 35 45 ns to LOW Level Output tPHZ Output Disable Time 20 ns from HIGH Level Output (Note 12) tPLZ Output Disable Time 27 ns from LOW Level Output (Note 12)

www.fairchildsemi.com 6 DM81LS95A • DM81LS96A • DM81LS97A Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 7 www.fairchildsemi.com DM81LS95A • DM81LS96A • DM81LS97A 3-STATE Octal Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com