DM8131 NSC | Alldatasheet

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z= Semiconductor > Corporation z DM7131/DM8131 6-Bit Unified Bus Comparator General Description Features The DM7131/DM8131 compares two binary words of two- ™ Low bus input current 15 A typ to-six bits in fength and indicates matching (bit-for-bit) of the ™ High bus input noise immunity 1.4V typ two words. Inputs for one word are 54/74 series-compatible ™ Bus inputs comply with IEEE 488-1975 TTL inputs, whereas those of the second word are high-im- TTL-compatible output pedance receivers driven by a terminated data bus. These g Output latch provision bus inputs include 0.65V typical hysteresis, which provides 1.4V noise immunity. The DM7131/0M8131 has active pull- up outputs and goes to the low state upon equality. The device has an output latch which is strobe controlled. The transfer of information to the output occurs when the STROBE input goes from a logic “1” to a logic “0” state. Inputs may be changed while the STROBE is at the logic “1” level, without affecting the state of the output. These devices are useful as address comparators in computer sys- tems utilizing unified data bus organization. Connection Diagram Dual-in-Line Package Veo 86 TS 85 1S 84 T4 OUTPUT te [is [ra fro [oz [sr [ro fo cn a a BI Ti 82 12 83 TS STROBE GND (BUS INPUT) (TTL INPUT) Tuves76-1 Order Number DM7131J or DM8131N ‘See NS Package Number J16A or N16A Function Table condition | STROBE |_outeut_| DM71/8131 T=B,T¥*B H Qn -1* T=8 L L T#B L H “Latched in a previous stat H = High Logle Level L = Low Logic Level. 4-224

[=] Absolute Maximum Ratings (note) 5 Specifications for Military/Aerospace products are not Note: The “Absolute Maximum Ratings” are those values o contained in this datasheet. Refer to the associated beyond which the safety of the device cannot be guaran | reliability electrical test specifications document. teed, The device should not be operated at these limits. The i=] Supply Voltage wv parametric values defined in the “Electrical Characteristics” | = Input Volta 58v table are not guaranteed at the absolute maximum ratings. | & ge : The “Recommended Operating Conditions” table will define | © Operating Free Air Temperature Range the conditions for actual device operation. DM71 —55°C to + 125°C DM8t OC to +70°C ‘Storage Temperature Range —65°C to +150°C Recommended Operating Conditions srt | teem ee Vor Sappy vonage i Vre Positive-Going Input Threshold Voltage for Bus Inputs 1.75 1.45 1.75 v (Note 1) Vie Negative-Going Input Threshold Voltage for Bus inputs: 1 13 v (Note 1) Vin High Level Input Voltage for v Strobe and TTL Inputs: Vit Low Level Input Voltage for v Strobe and TTL Inputs lon High Level Output Current [oe 0 Tima lou Low Level Output Current po ie ts ma Ts Free Air Operating Temperature | -s5 [ | 1s [ o | [7 | Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ vi Input lamp Vottage | Voc = Min, = —12 mA a es eo Vou High Level Output Voc = Min, oy = Max Vv Voltage Vit = Max, Vin = Min Vou Low Level Output Voc = Min, lo, = Max v Voltage Vin = Min, Vi_ = Max wtvotege | w= 88 [ewes | im High Level Input Veo=max [im of fT wo In Low Level input Veo=max [om [TT re Ty iw Bus Input wea | VocsMax [Ts To los Short Circuit Vec= Max [om | =e | | -55 |, Quip | tes) [wes te | ss 4 | loc Supply Current Voc = Max (Note 4) a ee Note t Voc = 5V Note 2: Al typical aro at Voc ~ 5V, Ta ~ 25° Note 3: Not more than one output shouldbe shorted at a time Note 4: Ics moasure with al Irputs grounded and al outputs open. 4-225

b tet, | Switching Characteristics at voc = 5v and Ts = 25°C (See Section 1 for Test Waveforms and Output Load) a >= From (Input) Ry = 4000, Cy = 15 pF a) ome [meme | Se pene iS = tPLH Propagation Delay Time TILto a Low to High Level Output Output ns tpHL Propagation Delay Time TILto High to Low Level Output Output ns tpLH Propagation Delay Time Bus to Low to High Level Output Output ns tpHL Propagation Delay Time Bus to High to Low Level Output Output ns tPLH Propagation Delay Time Strobe to Low to High Level Output Output ns tPHL Propagation Delay Time Strobe to High to Low Level Output Output ns Logic Diagram DM71/8131 " (2) 81 a 2 4) 62 (3) vs (6) wt {9) OUTPUT ™ 10) we a5 22) ps (12 re (tt) pe (19) ‘STROBE Tuvesren2 FR = High impedance aus Receiver 4-226