DM7497

DM7497 NSC | Alldatasheet

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5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier June 1989 5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier General Description The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency. The out- put pulse rate, relative to the clock frequency, is determined by signals applied to the Select (S0–S5) inputs. Both true and complement outputs are available, along with an enable input for each. A Count Enable input and a Terminal Count output are provided for cascading two or more packages. An asynchronous Master Reset input prevents counting and resets the counter. Connection Diagram Dual-In-Line Package TL/F/9780–1 Order Number 5497DMQB, 5497FMQB or DM7497N See NS Package Number J16A, N16E or W16A Logic Symbol TL/F/9780–2 VCC e Pin 16 GND e Pin 8 Pin Names Description S0–S5 Rate Select Inputs EZ OZ Enable Input (Active LOW) EY OY Enable Input CE Count Enable Input (Active LOW) CP Clock Pulse Input (Active Rising Edge) MR Asynchronous Master Reset Input (Active HIGH) OZ Gated Clock Output (Active LOW) Oy Complement Output (Active HIGH) TC Terminal Count Output (Active LOW) C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b55§Ct o a125§C DM74 0 §Ct o a70§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for acutual device operation. Recommended Operating Conditions Symbol Parameter 5497 DM7497 Units Min Nom Max Min Nom Max VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V VIH High Level Input Voltage 2 2 V VIL Low Level Input Voltage 0.8 0.8 V IOH High Level Output Current b0.4 b0.4 mA IOL Low Level Output Current 16 16 mA TA Free Air Operating Temperature b55 125 0 70 §C ts(L) Setup Time LOW, CE to CP Rising 25 25 ns th(H) Hold Time HIGH, CE to CP Rising 0 0 ns th(L) Hold Time LOW, CE to CP Falling 0 0 ns tw(H) CP Pulse Width HIGH 20 20 ns tw(L) CP Pulse Width LOW 20 ns tw(H) MR Pulse Width HIGH 15 15 ns Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage V CC e Min, I I eb 12 mA b1.5 V VOH High Level Output V CC e Min, I OH e Max, 2.4 3.4 VVoltage V IL e Max VOL Low Level Output V CC e Min, I OL e Max, 0.2 0.4 VVoltage V IH e Min II Input Current @ Max V CC e Max, V I e 5.5V 1m AInput Voltage IIH High Level Input Current V CC e Max, V I e 2.4V DM74 40 mAClock Inputs 54 80 IIL Low Level Input Current V CC e Max, V I e 0.4V DM74 b1.6 mAClock Inputs 54 b3.2 IOS Short Circuit V CC e Max 54 b20 b55 mAOutput Current (Note 2) DM74 b18 b55 ICC Supply Current With V CC e Max 120 mAOutputs High

VCC ea 5.0V, T A ea 25§C (See Section 1 for waveforms and load configurations)

5497 DM7497

Symbol Parameter CL e 15 pF C L e 15 pF UnitsRL e 400X RL e 400X Min Max Min Max fmax Maximum Clock Frequency 25 25 MHz tPLH Propagation Delay 18 18 nstPHL EZ to O Z 23 23 tPLH Propagation Delay 30 30 nstPHL EZ to O Y 33 33 tPLH Propagation Delay 14 14 nstPHL EY to O Y 10 10 tPLH Propagation Delay 23 23 nstPHL Sn to O Y 23 23 tPLH Propagation Delay 14 14 nstPHL Sn to O Z 14 14 tPLH Propagation Delay 39 39 nstPHL CP to O Y 30 30 tPLH Propagation Delay 18 18 nstPHL CP to O Z 26 26 tPLH Propagation Delay 35 30 nstPHL CP to TC 33 33 tPLH Propagation Delay 25 20 nstPHL CE to TC 21 21 tPLH Propagation Delay 43 36 nsMR to O Y tPHL Propagation Delay 34 23 nsMR to O Z Timing Diagrams TL/F/9780–5 TL/F/9780–6

The ’97 contains six JK flip-flops connected as a synchro- nous modulo-64 binary counter. A LOW signal on the Count Enable (CE ) input permits counting, with all state changes initiated simultaneously by the rising edge of the clock. When the count reaches maximum (63), with all Qs HIGH, the Terminal Count (TC ) output will be LOW if CE is LOW. A HIGH signal on Master Reset (MR) resets the flip-flops and prevents counting, although output pulses can still occur if the clock is running, E Z is LOW and S5 is HIGH. The flip-flop outputs are decoded by a 6-wide AND-OR-IN- VERT gate. Each AND gate also contains the buffered and inverted CP and Z-enable (E Z) functions, as well as one of the Select (S0–S5) inputs. The Z output, O Z is normally HIGH and goes LOW when CP and E Z are LOW and any of the AND gates has its other inputs HIGH. The AND gates are enabled by the counter at different times and different rates relative to the clock. For example, the gate to which S5 is connected is enabled during every other clock period, assuming S5 is HIGH. Thus, during one complete cycle of the counter (64 clocks) the S5 gate is enabled 32 times and can therefore gate 32 clocks per cycle to the output. The S4 gate is enabled 16 times per cycle, the S3 gate 8 times per cycle, etc. The output pulse rate thus depends on the clock rate and which of the S0–S5 inputs is HIGH. f out e m 64 # fin Where: m e S5 # 25 a S4 # 24 a S3 # 23 a S2 # 22 a S1 # 21 a S0 # 20 Thus by appropriate choice of signals applied to the S0–S5 inputs, the output pulse rate can range from (/64 to $*/64 of the clock rate, as suggested in Rate Select Table. There is no output pulse when the counter is in the ‘‘all ones’’ condi- tion. When m is 1, 2, 4, 8, 16 or 32, the output pulses are evenly spaced, assuming that the clock frequency is con- stant. For any other value of m the output pulses are not evenly spaced, since the pulse train is formed by interleav- ing pulses passed by two or more of the AND gates. The Pulse Pattern Table indicates the output pattern for several values of m. In each row, a one means that the O Z output will be HIGH during that entire clock period, while a zero means that O Z will be LOW when the clock is LOW in that period. The first column in the output field coincides with the ‘‘all zeroes’’ condition of the counter, while the last column represents the ‘‘all ones’’ condition. The pulse pattern for any particular value of m can be deduced by factoring it into the sum of appropriate powers of two (e.g. 19 e 16 a 2 a 1) and combining the pulses (i.e., the zeroes) shown for each for the relevant powers of two (e.g. for m e 16, 2 and 1). The Y output O Y is the complement of O Z and is thus nor- mally LOW. A LOW signal on the Y-enable input, E Y, dis- ables O y. To expand the multiplier to 12-bit rate select, two packages can be cascaded as shown in Figure A . Both cir- cuits operate from the basic clock, with the TC output of the first acting to enable both counting and the output pulses of the second package. Thus the second counter advances at only (/64 the rate of the first and a full cycle of the two coun- ters combined requires 4096 clocks. Each rate select input of the first package has 64 times the weight of its counter- part in the second package. f out e m1 a m2 64 # 64 # fin Where: m 1 e S5 # 211 a S4 # 210 a S3 # 29 a S2 # 28 a S1 # 27 a S0 # 26 (first package) m2 e S5 # 25 a S4 # 24 a S3 # 23 a S2 # 22 a S1 # 21 a S0 # 20 (second package) Combined output pulses are obtained in Figure A by letting the Z output of the first circuit act as the Y-enable function for the second, with the interleaved pulses obtained from the Y output of the second package being opposite in phase to the clock. TL/F/9780–3 FIGURE A. Cascading for 12-Bit Rate Select

Functional Description (Continued) Mode and Rate Select Table (Note 1) Inputs Clock Outputs Notes MR CE EZ S5 S4 S3 S 2 S1 S0 Pulses EY OY OZ TC HXH X X XXX X X HLHH 2 L LL L L LLL L 6 4 H LH1 3 L LL L L LLL H 6 4 H 111 3 L LLLLL LHL 6 4 H2 2 1 3 L LLLLLHLL 6 4 H441 3 LL L L L H L L L 6 4 H 8 8 1 3 L L L L H L L L L 64 H 16 16 1 3 L L L H L L L L L 64 H 32 32 1 3 L L L H H H H H H 64 H 63 62 1 3 L L LH H HHH H 6 4 LH 6 3 1 4 L L L H L L L L L 64 H 40 40 1 5 H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Note 1: Numerals indicate number of pulses per cycle. Note 2: This is a simplified illustration of the clear function. CP and E Z also affect the logic level of O Y and O Z. A LOW signal on E Y will cause O Y to remain HIGH. Note 3: Each rate illustrated assumes S0–S5 are constant throughout the cycle; however, these illustrations in no way prohibit variable- rate operation. Note 4: EY is used to inhibit output Y. Note 5: fout e m # fin e (32 a 8) f in e 40 f in e 0.625 f in Pulse Pattern Table m Output Pulse Pattern at O Z 1 1111111111111111111111111111111011111111111111111111111111111111 2 1111111111111110111111111111111111111111111111101111111111111111 3 1111111111111110111111111111111011111111111111101111111111111111 4 1111111011111111111111101111111111111110111111111111111011111111 5 1111111011111111111111101111111011111110111111111111111011111111 6 1111111011111110111111101111111111111110111111101111111011111111 8 1110111111101111111011111110111111101111111011111110111111101111 10 1110111111101111111011111110111111101111111011101110111111101111 1 2 1110111011101111111011101110111111101110111011111110111011101111 1 4 1110111011101110111011101110111111101110111011101110111011101111 1 6 1011101110111011101110111011101110111011101110111011101110111011 2 0 1011101010111011101110101011101110111010101110111011101110111011 2 4 1010101110101011101010111010101110101011111010111010101110101011 2 8 1010101010101011101010101010101110101010101010111010101010101011

TL/F/9780–4

Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 5497DMQB 16-Lead Molded Dual-In-Line Package (N) Order Number DM7497N

5497/DM7497 Synchronous Modulo-64 Bit Rate Multiplier Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 5497FMQB LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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