DM54LS96 ETC1 | Alldatasheet

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$4 MS\\ DM54/DM7496,LS96 5-Bit Shift Registers General Description _ These shift registers consist of fore RS master-slave Transfer of information to the outputs occurs on the flip-flops connected to perform paratiefto-serial or serial- Positive-going edge of the clock pulse. The proper in- to-parallel conversion of binary data. Since both inputs formation must be set up at the R-S inputs of each and outputs for all flip-flops are accessible, parallel-in/ flip-flop prior to the rising edge of the clock input parallel-out or serial-in/seriat-out operation may also be waveform. The serial input provides this information performed. as to the first flip-flop, while the outputs of the subsequent flip-flops provide information for the remaining R-S A ub fobs are simultaneously Set to @ tow output inputs. The clear input must be high and the preset or level by applying a low-level voltage to the clear input preset enable inputs must be low when clocking occurs. while the preset is low. Clearing is independent of the level of the clock input. The register may be parallel loaded by using the clear Features input in conjunction with the preset inputs. After clearing all stages to low output levels, data to be loaded © N-bit serial-to-parallel converter is applied to the individual preset inputs (A, B, C, D, and E} and a high-level load pulse is applied to the | N-bit parallel-to-serial converter preset enable input. Presetting is also independent of the level of the clock input. = Nebit storage register Connection Diagram oureurs ourours — eS semat cus Gy cua a wots fe fo fo fs fo Co a enone ENABLE vase mest Truth Table preser [preset Toc GQ, Gm Gm OC. enaste[aA 8 oc pe | _ * * n cu [xx x x xf x x fo oc © co L x feceueeif x x feooe ce cok 4 wo ofa now wow] x x |e oH ow How BoP HM fe bok bo eyo *X | Qa Qe Aco = Apne. H H HoL KH LOH L x Ho Qe Hog 4 bop xk KX KR KR KP OL X [Ono Aso Ao Aon Oo. H bo} k xX KX Kx Kf ot Ho} H Qan Gen Gen Gon, H t xX XK xX xX KX t L L Dan Aan Gen Dow H = high level (standy state), = low lave (steady state X= don't care (any input, including transitions! 41» transition from low to high level Ojo, go. ee. = the level of Qa, Qg, etc, respectively before the indicated steady stte input conditions were established. Qan, Ogn, etc. = the level of Qa, Og, etc., respectively before the most recent t transition of the clock. Tentative Dave For L596 239 (S06 To Be Announced In 1976

$3 Ms\\ DM54/DM7496,LS96 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) OMEALS/74US [wen recy wax [ mn TvPIn) MAX Vn [Misr tesinowvome Te Viz | Cow Leves input Voltage fowss[ ow | FY [owe] os [| “ WET (ema ee a Yon | Hig Level Out Curent ° [so fat fa Vou | Mish Level Output Voltage Vee = Mi0. Win = 20 fomsa 24 38 [as 35 Tou | tow Level Output Current Jowss[ te fa [owal te [a Vou | Low Levet Output Votrage Veo = Min [owsa| oz os | ozs oa | Toa | High bevel input Curent | Any input Except [vezey a PO Preset Enable ee Pres nable - ve ees ZL NE Ta | Low Level input Gvsent | An toput Except Preset Enable | Voc = Max V, » 04V mA [ae Veo = Maxi2h mA i ae ice | Supniy Gurcent Voom A) 8 a" a Notes (1) Ail typical values are at Voc ® 5V. Ta = 25°C. . (2) Not more than one output shouldbe shorted a atime, and for DMS4LS/74LS duration of short circuit should not exceed one second. (3) icc is measured with the claor input rounded and all other inputs and outputs open, Switching Characteristics Vcc = 5V, Ta = 25°C DMGALS/74LS PARAMETER ee [| conoirions [min Typ max | conorrions [win _TvP_wax | ‘wun [Proneention Delay Tie Lowe ih Lave Output From Clock Ps Tene [Propeontion Only Time, High |Low Level Output From Clock ” wu [Propagation Delay Time, Low-to: Cy = 15 pF, Ry = 4002 igh Lave! Output From Preset os or Preset Enable Tot [Propegion Delay Tine, Higa |Low Level Output From Clear 8s s wcroeni|watnofCeckimpurruie a c a ee ee tserur a ee 0 ‘wo. [Sevat input Hota Tie ° 0 - 2-40

A DM54/DM7496,LS96 Logic Diagram neser ratser eset rneser reser ts ae] vy iy f racser in i Seo >o-p-d ys a s a s 0 s e s a ctean 22.650 Timing Diagram TYPICAL CLEAR, SHIFT, PRESET, AND SHIFT SEQUENCES ee FLO ee oan cuean senuat nese | A 1 ‘ r , i ‘ t . a7 77 | ft ns rs Aes i | ourrurs {a | dl oo _ --4 . i) it a nr — catan vest 241