DM7490A

5490 NSC | Alldatasheet

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: A National < ry $ Semiconductor 5490/DM5490A/DM7490A, DM5493A/DM7493A Decade, and Binary Counters Genera! Description Each of these monolithic counters contains four master- connecting the Qp output to the A input and applying the slave flip-flops and additional gating to provide a divide-by- _input count to the B input which gives a divide-by-ten square two counter and a three-stage binary counter for which the = wave at output Qa. count cycle length is divide-by-five for the 890A and divide- by-eight for the 93A. Features All of these counters have a gated zero reset and the 90A ~—sm_Typical power dissipation also has gated set-to-nine inputs for use in BCD nine’s com- —90A 145 mW plement applications. —93A 130 mW To use their maximum count length (decade or four-bit bina- | ™ Count frequency 42 MHz ty}, the B input is connected to the Qa output. The input ™ Alternate Military/Aerospace device (5490) is available. count pulses are applied to input A and the outputs are as Contact a National Semiconductor Sales Office/Distrib- described in the appropriate truth table. A symmetrical di- utor for specifications. vide-by-ten count can be obtained from the 90A counters by Connection Diagrams Dual-in-Line Package iweuT A NC GK QD GND Og Og CC Le AC KL GO OC ; O_O im >A ag o> Rota) i Rot) Rava) = | + fz) fs fs ys fe [7 INT Porn Foray NC Voc Rat) Roca) TLF/6533-1 Order Number 5490DMQB, 5490FMQB, DM5490AJ, DM5490AW or DM7490AN See NS Package Number J14A, N14A or W14B Dual-In-Line Package wut A NCQ, QD GND OB Oc 1a |is_|i2_ [ar fro fo |s i &% AD Og Qe bs | i Rois) Roya) INQ T Row Roma NC Voc MC MC TUF /6533-2 Order Number DM5493AJ, DM5493AW or DM7493AN See NS Package Number J14A, N14A or W14B. 4-94

o o Absolute Maximum Ratings (note) > If Military/Aerospace specified devices are required, Note: The “Absolute Maximum Ratings” are those values o Please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran- = Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The Supply Voltage Vv parametric values defined in the “Electrical Characteristics” Input Voltage 55V table are not guaranteed at the absolute maximum ratings. pi se The “Recommended Operating Conditions” table will define Operating Free Air Temperature Range the conditions for actual device operation. DMS54 and 54 —55°C to + 125°C DM74 OC to +70°C Storage Temperature Range —65°C to + 150°C Recommended Operating Conditions DM7490A srt | Pemba poe ae te Pe | Voo__| SvppiyVohage [ass [55 [7 | 5 | ses] v Vin High Level input Voltage Pet of pet yy Vi Low Level Input Voltage a lon High Level Output Current a ee lou Low Level Output Current a ee were) a ww | alse wath fas is wore) peo ao co os [Reset Ts Ps trey ___| Reset Release Time (Note 5) [as [as Ta Free Air Operating Temperature [=s5[ [ws [oo TT 7% [sc ’90A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ vi Input Clamp Voltage | Voc = Min, | = —12mA rs ee ee Vou High Level Output Voc = Min, lon = Max 24 34 v Voltage Vit = Max, Viy = Min : i Vou Low Level Output Voc = Min, Io. = Max Vv Voltage Vin = Min, Vi, = Max (Note 4) \\ Input Current @ Max | Vcc = Max, Vj = 5.5V 1 mA Input Voltage pet 20 In Low Level Input Voc = Max pa ft 3277 a ee los Short Circuit Yoo = Max | omss [| -20 | | -s7 | ng loc ‘Supply Current Voc = Max (Note 3) ee ee Note 1: All typicals are at Voc = 5V, Ta = 25°C. Note 2: Not more than one output should be shorted af a time. ‘Note 3: Icc is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and al other inputs grounded. Note 4: Q, outputs are tested at lo, = Max plus the limit value of |, for the B input. This permits driving the B input while maintaining full fan-out capability, Note 5: Ta = 25°C and Voc = SV. 4-95

©) ’90A Switching Characteristics & |_8tVoc = 5V and Ty = 25°C (See Section 1 for Test Waveforms and Output Load)

8 Ry = 4000

ones | me ne , ae 7 [| - _ fax Maximum Clock | Ate ee Frequency [| Boge | te TT teLH Propagation Delay Time Low to High Level Output AtoQa ns tPHL Propagation Delay Time High to Low Level Output AtoQa ns tPLH Propagation Delay Time Low to High Level Output AtoQp ns tPHL Propagation Delay Time High to Low Level Output AtoQp ns tPLH Propagation Delay Time Low to High Level Output BtoQp ns tPHL Propagation Delay Time High to Low Level Output BtoQg ns tPLH Propagation Delay Time Low to High Level Output Btodc ns tPHL Propagation Delay Time High to Low Level Output BtoQc ns tPLH Propagation Delay Time Low to High Level Output BtoQp ns tPHL Propagation Delay Time High to Low Level Output BtoQp ns teLH Propagation Delay Time SET-9 to Low to High Level Output Qa, Qn ns tpHL Propagation Delay Time SET-9 to High to Low Level Output Qe, Qc ns tpHL Propagation Delay Time SET-O High to Low Level Output AnyQ ns 4-96

o o Recommended Operating Conditions > o symbot | _omsaosa[owras2A Tne | 8 ™ Prem ee pe > Voo__| Supply Voltage [as | 5 [oss [ars | s | sas |v Vir High Level Input Voltage pet ot fey Ty Vu | LowLevetinputvotage TTL os || S| oe |v lon High Level Output Gurrent a ee) lo Low Level Output Current Pe tema tex | Clock Frequency fa fo TT a fo |) CUdL leh motes) peo te Fo te | w Pulse Width pac as as wotes) pe 0 Po os [Rest Tw TT Ps | ‘ret | Reset Release Time (Note 5) ee ’93A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Typ Vou High Level Output Voc = Min, loy = Max v Voltage Vit = Max, Viq = Min Vo. Low Level Output Voc = Min, Io. = Max v Voltage Vin = Min, Vii = Max (Note 4) \\ Input Current @ Max Voc = Max, V; = 5.5V mA Input Voltage Ii High Level Input Voc = Max [ rest | | Two | los Short Circuit Voc = Max | omsa | -20 [| sr Tig Note 1: All typicals are at Voo = 5V, Ta = 25°C. Note 2: Not more than one output should be shorted at a time. Note 3: loc is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded. Note 4: Q, outputs are tested at io, = Max pius the limit value of i, for the B input. This permits driving the B input while maintaining full fan-out capability. Note 5: Ta = 25°C and Voc = SV. 4-97

bcd 5 A tat, ° ’93A Switching Characteristics at Voc = 5V and Ta = 25°C (See Section 1 for Test Waveforms and Output Load) R, = 4000 fax Maximum Clock [| Ato, Tez Frequency | Bteds | te teLH Propagation Delay Time Ato ns Low to High Level Output Qa {PHL Propagation Delay Time Ato ns High to Low Level Output Qa tely Propagation Delay Time Ato 70 ns Low to High Level Output Qp tPHL Propagation Delay Time Ato 70 ns High to Low Level Output Qp tPLH Propagation Delay Time Bto 16 ns Low to High Level Output Qg TPHL Propagation Delay Time Bto 24 ns High to Low Level Output Qs, tPLH Propagation Delay Time Bto ns Low to High Level Output Qc tHE Propagation Delay Time Bto ns High to Low Level Output Qc tPLH Propagation Delay Time Bto ns Low to High Level Output Qp tee Propagation Delay Time Bto ns High to Low Level Output Qp tPHL Propagation Delay Time SET-O High to Low Level Output to 40 ns Any Q 4-98

Function Tables (note p) > o 90A 90A 93A $ BCD Count Sequence BCD Bi-Quinary (5-2) Count Sequence (See Note A) (See Note B) (See Note C) | come Qo Qc Qe Qa | oom Gm @ Ge | oom Qn Qc Gp Qa ° a 0 bok bk 0 bok oboe

1 Lob ob oH 1 LoL oL oH 1 |

2 Lob HoL 2 LoL HOLL 2 Lok HOL

3 Lok oH oH 3 | 3 LoL oH oH

4 bc oH LoL 4 Lo oH LoL 4 Lo oH Lot

5 L oH oL oH 5 HOLL Lot 5 L oH LH

6 L H H L 6 H L L H 6 L H H L

7 lL oH oH oH 7 Ho ob HL 7 LH oH oH

8 HL LoL 8 H tL oH oH 8 HOLL LoL

9 H L L H 9 H H L L 9 H L t H

10 HOLL HOL

12 H H L L

13 H oH L oH

14 H H H Lt

15 H H H H

Reset/Count Function Table Reset/Count Function Table RO(1) RO(2) RA(1) RAZ) | Ap Ac Qe Qa RO(1) R0(2) Qp Qc Qp Qa H H L x feo vc coe H H L L L L H H x hs i L x COUNT x x H H H L L H x L COUNT eb x COUNT Note a: Ou q comet orp 8 or C0 ou L x x L COUNT Note B: Output Qp is connected to input A for bi-quinary count. x L L x COUNT Note C: Output Qa Is connected to input B. Note D: H = High Level, L = Low Level, X = Don't Care. 4-99

° Logic Diagrams s @ 90A 93A (6) R91) (13) Rai2) [OD io) 78 on (7) Q INPUT A Op CLOCK rary (12) on « (14) INPUT A OP CLOCK o 0 ®) Os (8) (9) . 3 INPUT B iw] Op (9) (10) (8) (8) Qc af (13 J a d ep OP CLOCK () « pT ron 2 J noia) ——L_? a |__-4 TUF 16888-4 11] of pts Kk @ RO 2 |) LE ) o. a ROK2) I) ‘TL/F/6533-3 The J and K inputs shown without connection are for reference only and are functionally at a high level. 4-100