DM7476N

DM7476_01 FAIRCHILD | Alldatasheet

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© 2001 Fairchild Semiconductor Corporation DS006528 www.fairchildsemi.com September 1986 Revised July 2001 DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs General Description This device contains two independent positive pulse trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic state of J and K inputs must not be allowed to change while the clock is HIGH. The data is transferred to the outputs on the falling edge of the clock pulse. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Connection Diagram Function Table H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level /c12 = Positive pulse data. The J and K inputs must be held constant while the clock is HIGH. Data is transferred to the outputs on the falling edge of the clock pulse. Q 0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each complete active HIGH level clock pulse. Note 1: This configuration is nonstable; that is, it will not persist when the preset and/or clear inputs return to their inactive (HIGH) level. Order Number Package Number Package Description DM7476N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Inputs Outputs PR CLR CLK J K Q Q LHXXX H L HLXXX L H LLXXX H (Note 1) H (Note 1) HH /c12 LLQ 0 Q 0 HH /c12 HL H L HH /c12 LH L H HH /c12 H H Toggle

www.fairchildsemi.com 2 DM7476 Absolute Maximum Ratings(Note 2) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Note 3: TA = 25°C and VCC = 5V. Note 4: The symbol (↑, ↓) indicates the edge of the clock pulse is used for reference (↑) for rising edge, (↓) for falling edge.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Note 5: All typicals are at VCC = 5V, TA = 25°C. Note 6: Clear is measured with preset HIGH and preset is measured with clear HIGH. Note 7: Not more than one output should be shorted at a time. Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock input is grounded. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range 0 °C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units VCC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 16 mA fCLK Clock Frequency (Note 3) 0 15 MHz tW Pulse Width Clock HIGH 20 (Note 3) Clock LOW 47 nsPreset LOW 25 Clear LOW 25 t SU Input Setup Time (Note 3)(Note 4) 0 ↑ ns tH Input Hold Time (Note 3)(Note 4) 0 ↓ ns TA Free Air Operating Temperature 0 70 °C Symbol Parameter Conditions Min Typ Max Units (Note 5) VI Input Clamp Voltage V CC = Min, II = −12 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max 2.4 3.4 V Output Voltage V IL = Max, VIH = Min VOL LOW Level V CC = Min, IOL = Max 0.2 0.4 V Output Voltage V IH = Min, VIL = Max II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA IIH HIGH Level V CC = Max J, K 40 Input Current V I = 2.4V Clock 80 µA Clear 80 Preset 80 IIL LOW Level V CC = Max J, K −1.6 Input Current V I = 0.4V Clock −3.2 mA (Note 6) Clear −3.2 Preset −3.2 IOS Short Circuit Output Current V CC = Max (Note 7) −18 −55 mA ICC Supply Current V CC = Max (Note 8) 18 34 mA

3 www.fairchildsemi.com DM7476 Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter From (Input) R L = 400Ω , CL = 15 pF Units To (Output) Min Max fMAX Maximum Clock Frequency 15 MHz tPHL Propagation Delay Time Preset to Q 40 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Preset to Q 25 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clear to Q 40 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Clear to Q 25 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to Q or Q 40 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Clock to Q or Q 25 ns LOW-to-HIGH Level Output

www.fairchildsemi.com 4 DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com