DM74161

DM54161_11 TI1 | Alldatasheet

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DM54161,DM74161,DM74163 DM54161 DM74161 DM74163 Synchronous 4-Bit Counters Literature Number: SNOS240A

DM54161/DM74161/DM74163 Synchronous 4-Bit Counters October 1992 DM54161/DM74161/DM74163 Synchronous 4-Bit Counters General Description These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs. The 161 and 163 are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus pre- venting spikes during the normal counting mode of opera- tion. Synchronous operation is provided by having all flip- flops clocked simultaneously so that the outputs change co- incident with each other when so instructed by the count- enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the 161 is asynchronous; and a low level at the clear input sets all four of the flip-flop out- puts low, regardless of the levels of clock, load, or enable inputs. The clear function for the 163 is synchronous; and a low level at the clear input sets all four of the flip-flop out- puts low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maxi- mum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low out- puts. Low-to-high transitions at the clear input of the 163 are also permissible, regardless of the logic levels on the clock, enable, or load inputs. The carry look-ahead circuitry provides for cascading coun- ters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count- enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple car- ry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the Q A output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High- to-low-level transitions at the enable P or T inputs of the 161 through 163 may occur, regardless of the logic level on the clock.

Features

Y Synchronously programmable Y Internal look-ahead for fast counting Y Carry output for n-bit cascading Y Synchronous counting Y Load control line Y Diode-clamped inputs Connection Diagram Dual-In-Line Package TL/F/6551–1 Order Number DM54161J, DM54161W, DM74161N or DM74163N See NS Package Number J16A, N16E or W16A C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A. Obsolete

Absolute Maximum Ratings (Note) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range DM54 b55§Ct o a125§C DM74 0§Ct o a70§C Storage Temperature Range b65§Ct o a150§C Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaran- teed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Recommended Operating Conditions Symbol Parameter DM54161 DM74161 and 163 Units Min Nom Max Min Nom Max VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V VIH High Level Input Voltage 2 2 V VIL Low Level Input Voltage 0.8 0.8 V IOH High Level Output Current b0.8 b0.8 mA IOL Low Level Output Current 16 16 mA fCLK Clock Frequency (Note 6) 0 25 0 25 MHz tW Pulse Width Clock 25 25 ns(Note 6) Clear 20 20 tSU Setup Time Data 20 20 (Note 6) Enable P 34 34 ns Load 25 25 Clear (Note 5) 20 20 tH Hold Time (Note 6) 0 0 ns TA Free Air Operating Temperature b55 125 0 70 §C

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units(Note 1) VI Input Clamp Voltage V CC e Min, I I eb 12 mA b1.5 V VOH High Level Output V CC e Min, I OH e Max 2.4 3.4 VVoltage VIL e Max, V IH e Min VOL Low Level Output V CC e Min, I OL e Max 0.2 0.4 VVoltage VIH e Min, V IL e Max II Input Current @ Max V CC e Max, V I e 5.5V 1m AInput Voltage IIH High Level Input V CC e Max Enable T 80 Current VI e 2.4V Clock 80 mA Others 40 IIL Low Level Input V CC e Max Enable T b3.2 Current VI e 0.4V Clock b3.2 mA Others b1.6 Obsolete

Over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol Parameter Conditions Min Typ Max Units(Note 1) IOS Short Circuit VCC e Max DM54 b20 b57 mAOutput Current (Note 2) DM74 b20 b57 ICCH Supply Current V CC e Max DM54 85 mAwith Outputs High (Note 3) DM74 59 94 ICCL Supply Current V CC e Max DM54 91 mAwith Outputs Low (Note 4) DM74 63 101 Note 1: All typicals are at V CC e 5V, T A e 25§C. Note 2: Not more than one output should be shorted at a time. Note 3: ICCH is measured with the LOAD high, then again with the LOAD low, with all inputs high and all outputs open. Note 4: ICCL is measured with the CLOCK high, then again with the CLOCK input low, with all inputs low and all outputs open. Note 5: Applies to 163 which has synchronous clear inputs. Note 6: TA e 25§C and V CC e 5V. Switching Characteristics at V CC e 5V and T A e 25§C (See Section 1 for Test Waveforms and Output Load) Symbol Parameter From (Input) RL e 400X,C L e 15 pF Units To (Output) Min Max fMAX Maximum Clock 25 MHzFrequency tPLH Propagation Delay Time Clock to 35 nsLow to High Level Output Ripple Carry tPHL Propagation Delay Time Clock to 35 nsHigh to Low Level Output Ripple Carry tPLH Propagation Delay Time Clock 20 nsLow to High Level Output (Load High) to Q tPHL Propagation Delay Time Clock 23 nsHigh to Low Level Output (Load High) to Q tPLH Propagation Delay Time Clock 25 nsLow to High Level Output (Load Low) to Q tPHL Propagation Delay Time Clock 29 nsHigh to Low Level Output (Load Low) to Q tPLH Propagation Delay Time Enable T to 16 nsLow to High Level Output Ripple Carry tPHL Propagation Delay Time Enable T to 16 nsHigh to Low Level Output Ripple Carry tPHL Propagation Delay Time Clear (Note 7) 38 nsHigh to Low Level Output to Q Note 7: Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163. Obsolete

TL/F/6551–3 Obsolete

Logic Diagrams (Continued) 163 TL/F/6551–8 Obsolete

Logic Diagrams (Continued) 161, 163 Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences TL/F/6551–5 (1) Clear outputs to zero (2) Reset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit Obsolete

Parameter Measurement Information Switching Time Waveforms TL/F/6551–6 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, Z OUT & 50X. For 161 and 163, tr s 10 ns, t f s 10 ns. Vary PRR to measure f MAX. Note B: Outputs Q D and carry are tested at t na16 for 161, 163 where t n is the bit time when all outputs are low. Note C: For 161 and 163, V REF e 1.5V. Obsolete

Parameter Measurement Information (Continued) Switching Time Waveforms TL/F/6551–7 Note A: The input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, Z OUT & 50X. For 161 and 163, tr s 10 ns, t f s 10 ns. Vary PRR to measure f MAX. Note B: Enable P and enable T setup times are measured at t na0. Note C: For 161 and 163, V REF e 1.5V. Obsolete

Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54161J or DM54163AJ 16-Lead Molded Dual-In-Line Package (N) Order Number DM74161N or DM74163N Obsolete

DM54161/DM74161/DM74163 Synchronous 4-Bit Counters Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number DM54161W or DM54163AW LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete

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