DM7300

DM7300 POWER-ONE | Alldatasheet

Document overview

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• PDF pages: 36

Technical content

Features

• RoHS compliant for all six substances
• Compatible with both lead-free and standard reflow processes
• Programs, controls, and manages up to 32 independent dPOL converters via an industry standard I2C interface (both 100kHz and 400kHz)
• JTAG IEEE 1149.1 compliant programming interface
• Controls and monitors industry standard power supplies and other peripheral devices (fans, etc)
• Programs output voltage, protections, optimal voltage positioning, turn-on and turn-off delays and slew rates, switching frequency, interleave (phase shift), and feedback loop compensation of the dPwer TM POL converters
• User friendly GUI interface for programming, monitoring, and performance simulation
• Four independent OK lines for flexible fault management and fast fault propagation
• Four interrupt inputs with programmable hot swap support capabilities
• Intermediate bus voltage monitoring and protection
• AC Fail input
• Non-volatile system configuration data memory
• 1K Byte of user accessible non-volatile memory
• Control of industry standard DC-DC front ends
• Crowbar output to trigger the optional crowbar protection
• Run-time counter
• Small footprint semiconductor industry standard QFN64 package: 9x9mm
• Wide industrial operating temperature range

Description

Power-One’s point-of-load converters are recommended for use with regulated bus converters in an Intermediate Bus Architecture (IBA). T he DM7300 is a fully programmable digital power manager that utilizes the industry-standard I 2C communication bus interface to control, manage, program and monitor up to 32 dP-series POL converters and 4 independent power devices. The DM7300 completely eliminates the need for external components for power management and programming and monitoring of the dPwer TM POL converters and other industry standard power and peripheral devices. Parameters of the DM7300 are programmable via the I 2C bus and can be changed by a user at any time during product development and deployment.

1 Selection Chart

2 Ordering Information

1 Packaging option is used only for ordering and not included in the part number printed on the DPM label.

2 The evaluation board is available in only one configuration: DM7300-KIT-HKS

is labeled DM7316G-12345. Refer to Figure 1 for label marking information. Figure 1. Label Drawing (5 digits Plus Rev Letter) Line 3 : Firmware Rev.

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3 Standard 5-Digit Identifiers

DPM Type DPM preloaded with default configuration file DPM configured for JTAG programming Packaging Options DM7304G 65511 65515 B1, B2, R100 DM7308G 65512 65516 B1, B2, R100 DM7316G 65513 65517 B1, B2, R100 DM7332G 65514 65518 B1, B2, R100

4 Reference Documents

• DP7XXX / DP8XXX Point of Load Regulator Data Sheets
• DM7300 Digital Power Manager. Programming Manual, Revision A09 or later
• Graphical User Interface, Revision 6.3.5 or later
• Programming DM7300 DPMs via JTAG Interface. Application Note
• ZM00056-KIT USB to I 2C Adapter Kit. User Manual

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5 Absolute Maximum Ratings

Stresses beyond those listed may cause permanent damage to the DPM. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the DPM at absolute maximum ratings or conditions beyond those indicated in the operational sections of this specification is not implied. Parameter Conditions/Description Min Max Units Ambient Temperature Range -40 85 °C Storage Temperature (Ts) -55 150 °C Junction Temperature (T J) 125 °C Input Voltage VDD pin -0.3 3.6 VDC Input Voltage Any pin other than VDD -0.5 VDD+0.5 VDC Pin Current DC 40 mA

6 Mechanical Specifications

Parameter Conditions/Description Min Nom Max Units Peak Reflow Temperature 40 sec maximum duration 260 °C Lead Plating 100% matte tin Moisture Sensitivity Level JEDEC J-STD-020C 3

7 Reliability Specifications

Parameter Conditions/Description Min Nom Max Units Failure Rate Demonstrated at 55 °C, 60% Confidence Level 2.26 FIT Non-Volatile Memory Endurance -40° C to 85° C ambient 10,000 Read- Write cycles

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8 Electrical Specifications

Specifications apply at VDD from 3V to 3.6V, ambient temperature from -40°C to 85°C, and utilizing proper decoupling as shown in Figure 3 unless otherwise noted.

8.1 Power Specifications

Parameter Conditions/Description Min Nom Max Units Input Supply Voltage VDD pin 3.0 3.6 VDC Undervoltage Lockout Hardware reset is triggered below this threshold 2.3 2.5 2.7 VDC Input Supply Current VDD pin=3.3V 12 20 mA VREF voltage AREF pin 2.3 2.56 2.7 VDC IBVS input voltage range GND VREF VDC IBVS input resistance 100 MΩ

8.2 Feature Specifications

Parameter Conditions/Description Min Nom Max Units Intermediate Voltage Bus Protections Overvoltage Protection Threshold With external 5.7:1 ratio divider IBV 14.6 V Undervoltage Protection Threshold With external 5.7:1 ratio divider 0 IBV V Threshold Hysteresis With external 5.7; 1ratio divider. Symmetrical relative to average threshold value ±114 mV Accuracy of Protection Thresholds Internal voltage reference, 1% resistive divider -10 10 %V TH Internal ADC Conversion Error With external 5.7:1 ratio divider -43 43 mV Front End Enable (FE_EN) VFE_EN Front End logic level enabled High VFE_EN Front End logic level disabled Low Isrc Source Current, V FE_EN =V DD -0.5V 5 mA Isink Sink Current, V FE_EN =0.5V 5 mA Crowbar (CB) VCB Crowbar Enable High VCB Crowbar Disable Low Isrc Source Current, V CB =V DD -0.5V 5 mA Isink Sink Current, V CB =0.5V 5 mA TCB Duration of Enabling Pulse 1 ms

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8.3 Signal Specifications

Parameter Conditions/Description Min Nom Max Units SYNC/DATA Line SDpu SD pull up resistor 5 kΩ SDthrL SD input low voltage threshold 0.31·VDD 0.52·VDD V SDthrH SD input high voltage threshold 0.45·VDD 0.81·VDD V SDhys SD input hysteresis 0.37 1.1 V SDsink SD sink capability (V SD =0.5V) 30 mA Freq_sd Clock frequency 450 550 kHz Tsynq Sync pulse duration 22 28 % of clock cycle T0 Data=0 pulse duration 72 78 % of clock cycle Interrupt Inputs (INT_N[3:0]) Rpu3 Pull up resistor 30 kΩ VthrL3 Input low voltage threshold 0.31·VDD 0.52·VDD V VthrH3 Input high voltage threshold 0.45·VDD 0.81·VDD V Vhys3 Input hysteresis 0.37 1.1 V ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs Rpu1 Pull up resistor 20 50 kΩ VthrL1 Input low voltage -0.5 0.2·VDD V VthrH1 Input high voltage 0.7·VDD VDD+0.5 V HRES_N Input Rpu2 HRES_N pull up resistor (with series diode, see note 1) 30 60 kΩ VthrL2 HRES_N input low voltage -0.5 0.2·VDD V VthrH2 HRES_N input high voltage 0.9·VDD VDD+0.5 V Inputs/Outputs (OK_A, OK_B, OK_C, OK_D) OKpu OK pull up resistor 5 kΩ OKthrL OK input low voltage threshold 0.31·VDD 0.52·VDD V OKthrH OK input high voltage threshold 0.45·VDD 0.81·VDD V OKhys OK input hysteresis 0.37 1.1 V OKsink OK sink capability (V OK =0.5V) 30 mA Enable Outputs (EN[3:0]) VEN EN logic level enabled High VEN EN logic level disabled Low VEN H EN output high voltage IOH = -10 mA VDD-0.6 V VEN L EN output low voltage IOL = 5 mA 0.5 V 1 HRES_N Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external diode between the HRES_N and VDD pins as shown in Figure 3.

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8.4 I2C Interface

Parameter Conditions/Description Min Nom Max Units ViL Input low voltage -0.5 0.3·VDD V ViH Input high voltage 0.7·VDD VDD+0.5 V Vhys Input hysteresis 0.05·VDD V VoL Output low voltage, I SINK =3mA 0 0.4 V tr Rise time for SDA and SCL 20+0.1C b 1 300 ns tof Output fall time from ViHmin to ViLmax 20+0.1C b 1 250 ns Ii Input current each I/O pin, 0.1VDD <V i<0.9V DD -10 10 µA Ci Capacitance for each I/O pin 10 pF fSCL SCL clock frequency 0 400 kHz Standard-Mode I 2C (f SCL ≤ 100kHz) RPU External pull-up resistor 1 1000/C b 1 kΩ tHDSTA Hold time (repeated) START condition 4.0 µs tLOW Low period of the SCL clock 4.7 µs tHIGH High period of the SCL clock 4.0 µs tSUSTA Setup time for a repeated START condition 4.7 µs tHDDAT Data hold time 0 3.45 µs tSUDAT Data setup time 250 ns tSUSTD Setup time for STOP condition 4.0 µs tSUF Bus free time between a STOP and START condition 4.7 µs Fast-Mode I2C (100kHz < fSCL ≤ 400kHz) RPU External pull-up resistor 1 300/C b 1 kΩ tHDSTA Hold time (repeated) START condition 0.6 µs tLOW Low period of the SCL clock 1.3 µs tHIGH High period of the SCL clock 0.6 µs tSUSTA Setup time for a repeated START condition 0.6 µs tHDDAT Data hold time 0 0.9 µs tSUDAT Data setup time 100 ns tSUSTD Setup time for STOP condition 0.6 µs tSUF Bus free time between a STOP and START condition 1.3 µs

1 C b – bus capacitance in pF, typically from 10pF to 400pF

Figure 2. I 2C Timing Parameters

9 Typical Application

Figure 3. Typical Application Schematic of Multiple Output System with Digital Power Manager and I 2C Interface and define margining functions, monitoring, startup behavior, and reporting conventions. the I2C bus with the host system and/or the Graphical User Interface.

ZD-00896 Rev. 5.2, 9-Apr-13 www.power-one.com Page 9 of 36 In this application, besides POL converters, the DPM also controls and monitors two auxiliary devices – a Voltage Regulation Module (VRM) and a Low Dropout Regulator (LDO). While these devices are not dPwer compliant and may not even be manufactured by Power-One, they are integrated into the system by communicating with the DPM via their Enable pins connected to ENX outputs of the DPM. In addition, the DPM monitors status of the auxiliary devices via its PGX inputs connected to Power Good and Error Flag outputs of the auxiliary devices. The DPM can control and monitor four or more independent auxiliary devices. The DPM can also trigger an optional crowbar circuit and provide undervoltage and overvoltage protections of the intermediate bus voltage. In addition, the DPM can be controlled by a host system via the interrupt inputs, RES_N and the ACFAIL_N inputs.

10 Description

The DM7300 series DPMs perform translation between the I2C interface connected to a host system or the Graphical User Interface and the SD communication bus connected to dPOL converters. In addition, DPMs carry out programming, monitoring, data storage, POL group management, hot-swap control, protection, and control and monitoring of auxiliary devices. The DPMs can be controlled via the GUI or directly via the I2C bus by using specific commands described in the “DPM Programming Manual”.

10.1 DPM Memory

The DPM memory consists of RAM and non-volatile memory (Flash). The RAM is used for programming operations and manipulation of the various blocks of configuration, setup, status, and monitoring registers. Non-volatile memory is used to store programming and configuration data. Flash memory holds DPM set-up registers, POL set-up registers, monitoring data, and user memory data. Setup registers for the DPM and the POL converters are protected by CRCs that are checked during programming of POL converters and at the power-up of the DPM. The LCK_N pin and the write protection register WP limit the write access to the memory blocks in the DPM and POL converters. The WP register content is defaulted to write protect upon powering up the DPM.

10.1.1 Write Protection

There are hardware-based and software-based memory write protections. The hardware protection takes precedence over the software protection.

10.1.1.1 Hardware Protection

The LCK_N pin enables the hardware memory write protection. If the pin is pulled low, the hardware lock is active and the memory blocks are then read-only. I2C write commands to the DPM return an error code (0x00). The write commands to the POL converters bypassing the DPM are also disabled. If the pin is left floating, the hardware lock is disabled and the software write protection is active.

10.1.1.2 Software Protection

Software write protection allows users to protect the various memory blocks from being overwritten through the I2C bus. At the power-up the WP register is defaulted to write protect. Software write protection can be disabled by checking appropriate boxes in the Write Protection subsection of the DPM/Program/Advanced dialog shown in Figure 4 or via the I2C bus by writing directly into the register. Write protections are automatically restored when the DPM’s input power is recycled.

Figure 4. GUI DPM Advanced Programming Dialog

10.1.2 DPM Registers

Table 1. DPM Setup Registers

1 Writing into memory locations beyond address offset 0x96 must be avoided

volatile register that defaults to write protect at power-up.

10.1.3 POL Setup Registers

POLs which are still supported. Differences are in bold for the DP series devices.

Table 2. POL Setup Registers

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10.1.4 Monitoring Data

The DPMs can retrieve current, temperature, output voltage, and status information from each of the POL converters and status information only from Auxiliary Devices. Monitoring data is stored in RAM and can be accessed via the I2C bus. Monitoring registers are read only. The monitoring data consists of 5 Bytes for each POL converter and Auxiliary Device as shown in Table 3. When the status monitoring is enabled, the ST registers get continuously updated. When the parametric monitoring is enabled, the VOH, VOL, IO, and TMP registers get continuously updated. Scaling data from the registers is specific to each DP and ZY series POL. Refer to the DM7300 Programming manual for calculation information. Table 3: Monitoring Data Registers POL Converter Auxiliary Device Register Content Register Content ST Status Register ST Status Register VOH Output Voltage High Byte reserved VOL Output Voltage Low Byte reserved IO Output Current reserved TMP Temperature reserved

10.1.5 User Memory

This non-volatile memory block is reserved for users’ notes and not related to other functions in the DPM. It can be used to save user-specific information such as manufacturing data and location, serial number, application code, configuration file version, warranty or repair information, etc. A total of 1024 Bytes organized in 4 pages is provided. The user memory can be accessed via the GUI System Configuration window shown in Figure 8 or directly via the I2C bus using specific commands. Content of the user memory is saved into the configuration file when the file is saved. Note that this does not change the current DPM contents until the DPM is programmed with the file currently in memory.

Figure 5. User Memory Window

10.2 Auxiliary Devices

via the Graphical User Interface. group turn-on and off commands and are fully synchronized with turn-on/off timing of POL converters. uncommitted address and then the AUX device desired. In this example two AUX devices are already present.

10.3 DPM Functions

10.3.1 POL Programming

memory via the SD bus to the POL converters. System Configuration window shown in Figure 8, or when the specific command is sent directly via the I2C bus. Figure 8. System Configuration Window be programmed, and continues programming the next POL converter. tab. Otherwise, the user will need to send the turn-on command via the I2C bus.

Figure 9. POL Configuration Window

10.3.2 Programming Time

TINIT - DPM initialization interval after the DPM supply voltage exceeds the UVLO threshold. TINIT =11.5ms. TPOL - Time required for programming and verifying of one POL converter. T POL =26.5ms. TAD - Time required for programming and verifying of one Auxiliary Device. T AD =7.5ms. nPOL - Number of POL converters in the system. nAD - Number of Auxiliary Devices in the system.

ZD-00896 Rev. 5.2, 9-Apr-13 www.power-one.com Page 18 of 36 The programming data (DPM and POL setup registers and the user memory) can be preloaded into DPMs by Power- One or the DPMs can be programmed by the user via the GUI, I2C bus, or JTAG programming interface. The DPMs can be programmed either before or after installation on a host board. To modify POL converter settings, the user can directly access the registers of a POL converter via the I2C bus, bypassing DPM’s POL setup registers. The I2C commands are translated by the DPM and converted into appropriate SD commands to read / write from / into the registers of a POL converter. Writing into these registers is limited by the hardware (LCK_N) and/or software write protections. Since POL converters do not have non-volatile memory, data written directly into POL converter registers will be lost when the input voltage is removed.

10.4 Monitoring

10.4.1 POL Monitoring

dPwer TM and Z-one™ POL converters continuously monitor their own performance parameters such as output voltage, output current, and temperature. The monitored parameters are stored locally in the POL converters and updated every 1ms. If monitoring feature is enabled, the DPM will be continuously copying status and parametric data from POL converters into DPM’s monitoring data registers. The monitoring is enabled by checking the appropriate Retrieve Monitoring bits in the GUI Group Configuration window shown in Figure 9 or directly via the I2C bus by specific commands. If the status monitoring is enabled, the status of each protection (overcurrent, overvoltage, etc.) is being reported. If the parametric monitoring is enabled, then real-time values of voltage, current, and temperature are being reported. Status and parametric monitoring data of a single POL converter and groups of POL converters can be examined in the GUI IBS Monitoring Window shown in Figure 10 or directly via the I2C bus using specific commands. Status data for each group of POL converters is presented in the Group Status block in the left top corner of the window. Parametric data for individual POL converters is shown in Voltage [V], Current [A], and Temp [T] screens. DPMs also monitor and report programming status of each POL converter and results of CRC operations.

10.4.2 Monitoring of Auxiliary Devices

The DPM can read status information of the Auxiliary Devices via the PG0…PG3 inputs. The PG0…PG3 are digital 3.3V compliant inputs with internal pull-up resistors. Logic high input on a PGX pin should correspond to normal operation of an Auxiliary Device. Status monitoring data of Auxiliary Devices is stored in the DPM and displayed in the IBS Monitoring Window shown in Figure 10.

Figure 10. IBS Monitoring Window

10.4.3 Run Time Counter

GUI IBS Monitoring Window shown in Figure 10 or directly via the I2C bus using specific commands.

10.4.4 IBV Monitoring

programmed in the GUI Intermediate Bus Configuration Window shown in Figure 11.

configuration window shown in Figure 9. Otherwise, the user will need to send the turn-on command via the I2C bus. pull the CB pin high for 1ms to trigger an optional crowbar protection. converters, if the Auto Turn-On is enabled in the POL Group configuration window shown in Figure 9. pulling down OK lines and triggering the turn-off process is approximately 1ms.

10.4.4.1 Voltage Reference

Voltages dialog as shown previously in Figure 11 . GUI automatically changes values of the IBL and IBH thresholds when the reference selection is changed. Figure 13. External Voltage Reference Connections U1 and R1 are additional components. U1 is an industry standard 2.5V voltage reference such as TL431 or similar. reference part numbers and values of associated components are shown in Table 4.

Table 4. Component Values For External Reference

10.5 POL Group Management

10.5.1 Fault and Error Propagation

fault/error propagations is less than 10µs. and vice versa) should be avoided.

Figure 14. Fault and Error Propagation Window.

Figure 15. Auxiliary Device Fault Management Window

Table 5. Fault and Error Propagation Scenarios

ZD-00896 Rev. 5.2, 9-Apr-13 www.power-one.com Page 26 of 36 When propagation is enabled, the faulty POL converter pulls its OK pin low. A low OK line initiates turn-off of other POL converters in the group and signals the DPM to pull other OK lines low to initiate turn-off of other POL converters as programmed. The regular turn-off of a POL converter means that the output voltage is ramping down according to its turn-off delay and falling slew rate settings. If a POL converter triggers an undervoltage or overtemperature fault, it will initiate the regular turn-off. In the case of an overcurrent or tracking fault, the POL converter initiates the fast turn-off by opening both high and low side switches instantaneously. If either output overvoltage or phase voltage errors are triggered, the faulty POL converter initiates the fast turn-off and turns on its low side switch. In addition, when an error is propagated, the DPM can generate commands to turn off a front end (a DC-DC converter generating the intermediate bus voltage) and trigger an optional crowbar protection to accelerate removal of the intermediate bus voltage (IBV). Once the fault has recovered in the faulty POL converter, the other POL converters will turn on in a controlled manner according to their turn-on delay and rising slew rate settings.

10.5.2 Margining

Margining can be executed separately for each group by clicking an appropriate radio button in the GUI IBS monitoring window shown in Figure 10 or directly via the I2C bus by the margining command. All POL converters in a group are margined in the same direction (up or down) by the percentage programmed individually for each POL converter.

10.5.3 Turn-ON and Turn-Off

Automatic turn–on upon application of the input voltage is enabled by checking the Auto Turn-On bit in the GUI Group Configuration window shown in Figure 9. Turn-on and turn-off of various groups during the operation is controlled from the GUI IBS Monitoring window or directly via the I2C bus by specific commands.

10.5.4 Interrupt Configurations

The DPM has four interrupt inputs that can be programmed to:

• Inhibit the operation of one or several Groups of POL converters when pulled low or
• Act as a Group Reprogramming Trigger. The two functions are mutually exclusive – an interrupt can be either programmed as an Inhibit or as a Group Reprogramming Trigger. The interrupts are programmed in the GUI Interrupt Configuration window shown in Figure 16 or directly via the I2C bus by specific commands. In Figure 16 the Interrupt 0 is programmed as the inhibit for group A and the Interrupt 2 is programmed as the group C reprogramming trigger.

10.5.4.1 Group Inhibit

An interrupt input can be programmed to act as an inhibit on a single or multiple groups of POL converters. When the interrupt input is pulled low, the DPM will pull the appropriate OK lines low. The affected POL converters will execute regular turn-off ramping their output voltages down according to the turn-off delay and falling slew rate settings. Once the interrupt is released, the POL converters will automatically turn-on according to their turn-on delay and rising slew rates settings. The inhibit function can be used for a variety of applications, such as

• Hardware-based control of groups of POL converters and Auxiliary Devices

• Delayed turn-on at power-up (Automatic Turn-On is enabled but the interrupts are held low during power-up. Note that POL converters can be programmed even when an interrupt is held low.) The interrupt inputs should be controlled with open collector devices. The propagation delay between the external device pulling the interrupt input low and the DPM pulling down OK lines and triggering the turn-off process is approximately 10µs. This option is set as part of DPM/Configure/Faults dialogs.

Figure 16. Interrupt Configuration Dialog

10.5.4.2 Group Reprogramming Trigger

An interrupt that is programmed as a group reprogramming trigger always acts only on one group of POL converters. DPM will clear all bits in the POL Programming Status registers. DPM installed on them as shown in Figure 17.

ZD-00896 Rev. 5.2, 9-Apr-13 www.power-one.com Page 28 of 36 Figure 17: INT0 Configured as Group A Reprogramming Trigger In this configuration the Interrupt 0 (INT0_N) is configured as the group A reprogramming trigger. The DPM is installed on a mother board or a backplane. A daughter card with a group of POL converters is being inserted in the system during normal operation. At first, the long pins carrying power and the OK_A line signal make contact. Then the short pins carrying the SD and interrupt signals make contact. Once the interrupt senses low input voltage, it will command the DPM to program all POL converters in the group A. Upon completion of the programming, the DPM will turn-on the POL converters, if the Auto Turn-On is enabled. When the daughter card is being removed, the interrupt input is released as soon as the short pins break the contact. The DPM will immediately pull the OK_A line low turning off all POL converters in the group A according to the turn-off delay and falling slew rate settings.

10.6 Controls

10.6.1 ACFAIL_N and RES_N

The ACFAIL_N and RES_N are active low digital inputs. When one of the inputs is pulled low, the DPM will pull all OK lines low turning off all the POL converters and the Auxiliary Devices in all groups. The POL converters will execute regular turn-off ramping their output voltages down according to the turn-off delay and falling slew rate settings. In addition, the DPM will clear all bits in the POL Programming Status Registers and save the contents of the Run Time Counter into the non-volatile memory. The AC_FAIL in or RES_N in bit in the IBS Monitoring Window will change to red. When the input is released, the DPM will first program all POL converters and then turn them on, if the Auto Turn-On is enabled. Otherwise, the user will need to send the turn-on command via the I2C bus. The ACFAIL_N is typically connected to an AC-DC front end. Whenever the AC voltage disappears, the ACFAIL_N signal will be set low. If there is no battery backup, it usually means the DC output will disappear after 20ms. If the turn-off delays and falling slew rates of each POL converter are set to the values such that all POL converters will have fully turned off within the hold time of the AC-DC front end, then output voltage tracking during turn-off is guaranteed. The RES_N input has the same functionality as the ACFAIL_N input and can be connected to a simple turn on/off switch or to a sensor that shuts the entire system down when it is activated. IBV GND SD INT 0_ N OK _ A POL POL POL Vox Group A Daugther Card Mother Board or Back Plane DM 7300 SD

10.6.2 Front End Enable

can control the DC-DC Front End. the GUI IBS Monitoring Window or directly via the I2C bus using specific commands. addition, the Enable pin can be pulled up internally to a voltage potentially damaging to the DPM FE_EN output. configuration provides interface for negative logic front ends. Figure 18. Interface Between DPM and DC-DC Front End

10.6.3 Crowbar

5mA to turn on a crowbar circuit.

10.6.4 HRES_N

turn them on, if the Auto Turn-On is enabled. connected to VDD. Therefore, it is necessary to add the diode externally as shown in Figure 3.

CPLD (or similar device) and controlled via the system supervisory circuitry.

10.7 Communication Interfaces

10.7.1 I2C Interface

• standard (100kbs) and fast (400kbs) data transfer rates
• 7-bit addressing: 4 MSBs fixed, 3 LSBs programmable by ADDR[2:0]. The address prefix of the DM7300 is 0x50. This allows encoding DPM addresses 0x50, 0x52, …, 0x5E (Bit0 is the read/write bit) The DPM always acts as the I2C slave while the host processor always acts as the I2C master. Refer to the “DPM Programming Manual” for the detailed description of the I2C communications. Note: It is recommended to use Power-One’s ZM00056-KIT USB to I 2C Adapter kit for the communication between a DPM and a computer with the Power-One I2CGraphical User Interface

10.7.1.1 Watchdog Timer

10.7.2 JTAG Interface

configuration settings. JTAG boundary-scan capabilities are not currently supported. JTAG-programmable DPMs have unique 5-digit identifiers listed in Table 6. Table 6. JTAG Programmable DPM Part Numbers Only the DPM part numbers listed in the table can be programmed via the JTAG interface.

10.7.2.1 SVF File

appropriate Serial Vector Format file. The resulting file is used to program the DPMs through the JTAG interface. Refer to “Programming DM7300 DPMs via JTAG Interface” Application Note for more details. Figure 19. SVF File Generator Window

10.7.2.2 JTAG Instructions

DM7300 series DPMs support only BYPASS and IDCODE instructions defined by IEEE 1149.1. instructions is shown in Table 7. Table 7. JTAG Instructions

10.7.2.3 Identification Register

Format and contents of the JTAG Identification Register are shown in Table 8.

Table 8. JTAG ID Register

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11 Pinout Table

Pin Name Pin No. Pin Type Buffer Type Pin Descripti on Notes VDD 6, 25, 42, 57, 60 Supply --- Positive Supply VSS 8, 9, 26 38, 43, 58 Supply --- Ground SD 56 I/O ST/OCPU Sync-Data Line OKA OKB OKC OKD I/O ST/OCPU OK Lines FE_EN 17 O CMOS Front-End Enable CB 23 O CMOS Crowbar Trigger SDA 30 I/O ST/OC I 2C Interface SCL 27 I/O ST/OC I 2C Interface ADDR0 ADDR1 ADDR2 I STPU I 2C Interface Address IN0_N IN1_N IN2_N IN3_N I STPU Interrupts TCK TMS TDO TDI JTAG Interface Leave open, if JTAG interface is not utilized EN0 EN1 EN2 EN3 O CMOS Auxiliary Device Enables PG0 PG1 PG2 PG3 I STPU Auxiliary Device Power Good RES_N 18 I STPU System Soft Reset ACFAIL_N 16 I STPU AC-Fail Trigger LCK_N 61 I STPU Write Protect Lock HRES_N 4 I STPU Cold Reset See important usage instructions in paragraph 10.6.4 IBVS 48 I A Intermediate Bus Voltage Sense AREF 44 - A Analog Reference IR 63 Internal Reset Connect to VSS via 10k nc 1, 2, 3, 10, 12, 14, 15, 19, 21, 22, 24, 28, 29, 35, 39, 59, 62, 64 - - No Connect Leave floating Legend: I=input, O=output, I/O=input/output, P=powe r, ST=Schmitt-trigger, OCPU=open collector with pull-up, OC=open collector, CMOS=CMOS output stage, STPU=Schmitt-trigger with pull-up, A=analog

ZD-00896 Rev. 5.2, 9-Apr-13 www.power-one.com Page 34 of 36

12 Pins Description

ACFAIL_N, AC Fail Input (Pin 16): Schmitt-Trigger input with internal pull-up resistor (active low). Pulling low the input indicates to the DPM that an AC-DC front-end has lost the mains and that a system shut down should immediately be initiated. ADDR[0:2], I 2C Address Inputs (Pins 47, 46, 45): Inputs with internal pull-up resistor. The 3 bit encoded address determines the DPM communication address for the I 2C interface. AREF, Analog Reference (Pin 44): An analog reference which is used internally. A 10nF capacitor should be connected as close as possible to the package between CB, Crowbar Output (Pin 23): A CMOS output which is used to trigger a crowbar (SCR) in case of overvoltage on the Intermediate Voltage Bus. EN[0:3], Enable Outputs for Auxiliary Devices (Pins 5, 7, 55, 50): CMOS outputs to control Auxiliary Devices like linear regulators, analog POLs, fans or other devices. .FE_EN, Front-End Enable (Pin 17): A CMOS output which is used to turn-on/off the DC/DC converter generating the IBV. HRES_N, Hardware Reset (Pin 4): Input with internal pull-up resistor. When pulled low a cold start of the Digital Power Manager is initiated. Refer to paragraph 10.6.4 for important information regarding connections of this pin. IBVS, Intermediate Voltage Bus Sense (Pin 48): Analog input to an internal ADC circuit to measure the Intermediate Bus Voltage. The full scale range of the input is 2.56V and the IBV should be scaled down by a factor of 5.7 for proper reporting of the IBV with the dPwer™ GUI. INT[0:3], Interrupts (Pins 41, 40, 37, 36): Four active low inputs with internal pull-ups. Each of the inputs can be configured for two functions: first, the interrupt input acts on the OK line(s) to stop momentarily the operation of group of POLs and Auxiliary Devices, second the interrupt can be used as a hot swap trigger. In this function the interrupt input triggers the programming of a group. When released, POLs are assumed to be disconnected from the DPM. IR, Internal Reset (Pin 63): Connect to VSS via a 10kOhm resistor. LCK_N, Memory Lock (Pin 61): Active low input with internal pull-up. When LCK_N is pulled low, all memory within the DPM is write-protected. The write protection cannot be disabled by software. OKA, OKB, OKC, OKD, Group OK Signals (Pins 11, 13, 20, 53): An open drain input/output with internal pull- up resistor. Pulling low the OK input will indicate to the DPM a fault in a Group, the DPM can also pull an OK line low to disable a Group. PG[0:3], Power Good (Pins 54, 52, 51, 49): Input with internal pull-up resistor. The pin is used to read the status of an Auxiliary Device. RES_N, Active Low Reset In/Out (Pin 18): Input with internal pull-up resistor. When pulled low a soft reset of the system (sequenced turned off of all POLs and Auxiliary Devices) is initiated. When released the whole system is reprogrammed and started if necessary. SD, Sync Data Line (Pin 56): An open drain input / output with internal pull-up resistor. Communication line to distribute a master clock to all converters and at the same time to communicate with all POLs. JTAG Interface (Pins 34, 33, 32, 31): Connect to a JTAG IEEE-1149.1-compliant programmer supporting SVF files or leave open, if not used. VDD, Positive Supply (Pins 6, 25, 42, 57, 60): Supply voltage. At least 4x100nF decoupling capacitors should be connected between VDD and VSS pins. All VDD pins must be connected. VSS, Ground (Pins 8, 9, 26, 38, 43, 58): Ground. Decoupling capacitors need to be connected as close as possible to the pins. All VSS pins must be connected. nc, No Connect (Pin 1, 2, 3, 10, 12, 14, 15, 19, 21, 22, 24, 28, 29, 35, 39, 59, 62, 64): All nc pins must remain floating.

13 Mechanical Drawings

Figure 20. DM7300 Mechanical Drawing Figure 21. DM7300 Terminals

1. Compliant to JEDEC standard MO-220 variation VMMD-3

Figure 22. DM7300 Mechanical Drawing – Top View

1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One pro ducts are not designed, intended for use in, or aut horized for use as critical

consent of the respective divisional president of Power-One, Inc.

1. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on

the date manufactured. Specifications are subject to change without notice. 2C is a trademark of Philips Corporation.