DM6446ANB6C2127VC

TMS320DM6446_17 TI1 | Alldatasheet

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Technical content

www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 TMS320DM6446 DigitalMediaSystem-on-Chip Check forSamples: TMS320DM6446

1 DigitalMedia System-on-Chip (DMSoC)

1.1 Features

• High-PerformanceDigitalMedia SoC • C64x+ L1/L2Memory Architecture – 513-,594-,810-MHz C64x+ ™ Clock Rates – 32K-Byte L1P Program RAM/Cache (Direct Mapped)– 256.5-,297-,405-MHz ARM926EJ-S ™ Clock Rates – 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)– Eight32-BitC64x+ Instructions/Cycle – 64K-Byte L2 UnifiedMapped RAM/Cache– 4104,4752,6480 C64x+ MIPS (FlexibleRAM/Cache Allocation)– FullySoftware-CompatibleWith C64x /
• ARM926EJ-S CoreARM9 ™ – Support for32-Bitand 16-Bit(Thumb ®– Extended Temperature Devices Available Mode) InstructionSets• Advanced Very-Long-Instruction-Word(VLIW) – DSP InstructionExtensionsand SingleCycleTMS320C64x+ ™ DSP Core MAC– EightHighlyIndependentFunctionalUnits – ARM ® Jazelle® Technology• SixALUs (32-/40-Bit),Each Supports – EmbeddedICE-RT ™ Logic forReal-TimeSingle32-Bit,Dual 16-Bit,or Quad 8-Bit DebugArithmeticper Clock Cycle
• ARM9 Memory Architecture• Two MultipliersSupport Four 16 x 16-Bit Multiplies(32-BitResults)per Clock – 16K-Byte InstructionCache Cycle or Eight8 x 8-BitMultiplies(16-Bit – 8K-Byte Data Cache Results)per Clock Cycle – 16K-Byte RAM – Load-StoreArchitectureWith Non-Aligned – 8K-Byte ROMSupport • Embedded Trace Buffer™ (ETB11™ )With 4KB– 64 32-BitGeneral-PurposeRegisters Memory forARM9 Debug – InstructionPacking Reduces Code Size • Endianness:LittleEndian forARM and DSP – AllInstructionsConditional • Video Imaging Co-Processor (VICP) – AdditionalC64x+ ™ Enhancements • Video ProcessingSubsystem
• ProtectedMode Operation – FrontEnd Provides:
• ExceptionsSupport forErrorDetection • CCD and CMOS Imager Interfaceand Program Redirection • BT.601/BT.656DigitalYCbCr 4:2:2• Hardware Support forModulo Loop (8-/16-Bit)InterfaceOperation • Preview Engine forReal-TimeImage• C64x+ InstructionSet Features Processing – Byte-Addressable(8-/16-/32-/64-BitData) • GluelessInterfacetoCommon Video – 8-BitOverflowProtection Decoders – Bit-FieldExtract,Set,Clear • Histogram Module – Normalization,Saturation,Bit-Counting • Auto-Exposure,Auto-WhiteBalance and – Compact 16-BitInstructions Auto-Focus Module – AdditionalInstructionstoSupport Complex • ResizeEngine Multiplies – ResizeImages From 1/4xto4x – SeparateHorizontal/VerticalControl Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas of publicationdate. Copyright© 2005–2010,Texas InstrumentsIncorporatedProducts conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

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• Video ProcessingSubsystem (Continued) • One SerialPeripheralInterface(SPI)With Two Chip-Selects– Back End Provides:
• Master/SlaveInter-IntegratedCircuit(I2C Bus ™ )• Hardware On-Screen Display(OSD)
• Audio SerialPort(ASP)• Four 54-MHz DACs fora Combination of – I2S– Composite NTSC/PAL Video – AC97 Audio Codec Interface– Luma/Chroma Separate Video (S-video) – Standard Voice Codec Interface(AIC12) – Component (YPbPr or RGB) Video • 10/100Mb/s EthernetMAC (EMAC) (Progressive) – IEEE 802.3Compliant
• DigitalOutput – Media IndependentInterface(MII) – 8-/16-bitYUV or up to24-BitRGB • VLYNQ ™ Interface(FPGA Interface) – HD Resolution • Host PortInterface(HPI)with16-Bit – Up to2 Video Windows MultiplexedAddress/Data
• ExternalMemory Interfaces(EMIFs) • USB PortWith Integrated2.0PHY – 32-BitDDR2 SDRAM Memory ControllerWith – USB 2.0High-/Full-Speed(480-Mbps)Client 256M-Byte Address Space (1.8-VI/O) – USB 2.0High-/Full-/Low-SpeedHost
• Up to167-MHz Controller(A-513,-594) (Mini-Host,SupportingOne External Device)• Up to189-MHz Controller(-810)
• Three Pulse Width Modulator(PWM) Outputs– Asynchronous16-Bit-WideEMIF (EMIFA) With 128M-Byte Address Reach • On-Chip ARM ROM Bootloader(RBL) toBoot From NAND Flashor UART• FlashMemory Interfaces
• ATA/ATAPI I/F(ATA/ATAPI-6 Specification)– NOR (8-/16-Bit-WideData)
• IndividualPower-Saving Modes forARM/DSP– NAND (8-/16-Bit-WideData)
• FlexiblePLL Clock Generators• FlashCard Interfaces
• IEEE-1149.1(JTAG) Boundary-– MultimediaCard (MMC)/Secure Digital(SD) Scan-CompatiblewithSecure Data I/O(SDIO)
• Up to71 General-PurposeI/O(GPIO)Pins– Compact FlashControllerWith True IDE (MultiplexedWith Other Device Functions)Mode
• 361-PinPb-FreeBGA Package– SmartMedia (ZWT Suffix),0.8-mm BallPitch• Enhanced Direct-Memory-Access(EDMA3)
• 0.09-mm/6-LevelCu MetalProcess (CMOS)Controller(64IndependentChannels)
• 3.3-Vand 1.8-VI/O,1.2-VInternal(513,594)• Two 64-BitGeneral-PurposeTimers (Each Configurableas Two 32-BitTimers) • 3.3-Vand 1.8-VI/O,1.2-VDAC and USB, 1.3-V Internal(810only)• One 64-BitWatch Dog Timer
• Applications:• Three UARTs (One withRTS and CTS Flow Control) – DigitalMedia – Networked Media Encode/Decode – Video Imaging

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1.2 Description

The TMS320DM6446 (alsoreferencedas DM6446) leveragesTI’s DaVinci™ technologyto meet the networkedmedia encode and decode applicationprocessingneeds ofnext-generationembedded devices. The DM6446 enablesOEMs and ODMs to quicklybringto market devicesfeaturingrobustoperating systems support,richuser interfaces,high processingperformance,and long batterylifethroughthe maximum flexibilityofa fullyintegratedmixed processorsolution. The dual-corearchitectureof the DM6446 providesbenefitsof both DSP and Reduced InstructionSet Computer (RISC) technologies,incorporatinga high-performanceTMS320C64x+ ™ DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bitRISC processorcore thatperforms32-bitor 16-bitinstructionsand processes32-bit,16-bit,or 8-bitdata.The core uses pipeliningso thatallpartsof the processorand memory systemcan operatecontinuously. The ARM coreincorporates:

• A coprocessor15 (CP15)and protectionmodule
• Data and programMemory Management Units(MMUs) withtablelook-asidebuffers.
• Separate16K-byteinstructionand 8K-bytedatacaches.Botharefour-wayassociativewithvirtual indexvirtualtag(VIVT). The TMS320C64x+ ™ DSPs are the highest-performancefixed-pointDSP generation in the TMS320C6000 ™ DSP platform.It is based on an enhanced versionof the second-generation high-performance,advanced very-long-instruction-word(VLIW) architecturedeveloped by Texas Instruments(TI),making theseDSP coresan excellentchoicefordigitalmedia applications.The C64x isa code-compatiblemember oftheC6000 ™ DSP platform.The TMS320C64x+ DSP isan enhancement of theC64x+™ DSP withadded functionalityand an expanded instructionset. Any referencetotheC64x™ DSP or C64x™ CPU alsoapplies,unlessotherwisenoted,totheC64x+™ DSP and C64x+™ CPU, respectively. With performanceofup to6480 millioninstructionsper second (MIPS) ata clockrateof810 MHz, the C64x+ coreofferssolutionstohigh-performanceDSP programmingchallenges.The DSP corepossesses theoperationalflexibilityofhigh-speedcontrollersand thenumericalcapabilityofarrayprocessors.The C64x+ DSP core processorhas 64 general-purposeregistersof 32-bitword lengthand eighthighly independentfunctionalunits— two multipliersfora 32-bitresultand sixarithmeticlogicunits(ALUs).The eightfunctionalunitsincludeinstructionstoacceleratetheperformanceinvideoand imagingapplications. The DSP corecan producefour16-bitmultiply-accumulates(MACs) per cyclefora totalof3240 million MACs persecond (MMACS), oreight8-bitMACs percyclefora totalof6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and InstructionSet Reference Guide (literaturenumber SPRU732 ). The DM6446 also has application-specifichardware logic,on-chipmemory, and additionalon-chip peripheralssimilarto the otherC6000 DSP platformdevices.The DM6446 core uses a two-level cache-basedarchitecture.The Level1 program cache (L1P)isa 256K-bitdirectmapped cache and the Level1 data cache (L1D) isa 640K-bit2-way set-associativecache.The Level2 memory/cache (L2) consistsofan 512K-bitmemory space thatissharedbetween program and dataspace.L2 memory can be configuredas mapped memory, cache,orcombinationsofthetwo. The peripheralset includes:2 configurablevideoports;a 10/100 Mb/s EthernetMAC (EMAC) witha Management Data Input/Output(MDIO) module;an inter-integratedcircuit(I2C)Bus interface;one audio serialport(ASP); 2 64-bitgeneral-purposetimerseach configurableas 2 independent32-bittimers; 1 64-bitwatchdog timer;up to 71-pinsof general-purposeinput/output(GPIO) with programmable interrupt/eventgenerationmodes, multiplexedwith other peripherals;3 UARTs with hardware handshakingsupporton 1 UART; 3 pulsewidthmodulator(PWM) peripherals;and 2 externalmemory interfaces:an asynchronousexternalmemory interface(EMIFA) forslowermemories/peripherals,and a higherspeed synchronousmemory interfaceforDDR2. Copyright© 2005–2010,Texas InstrumentsIncorporated DigitalMedia System-on-Chip(DMSoC) 3 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com The DM6446 deviceincludesa VideoProcessingSubsystem (VPSS) withtwo configurablevideo/imaging peripherals:1 Video ProcessingFront-End(VPFE) inputused forvideocapture,1 Video Processing Back-End (VPBE) outputwithimagingco-processor(VICP)used fordisplay. The Video ProcessingFront-End(VPFE) iscomprisedof a CCD Controller(CCDC), a PreviewEngine (Previewer),HistogramModule, Auto-Exposure/WhiteBalance/FocusModule (H3A),and Resizer.The CCDC iscapableofinterfacingtocommon videodecoders,CMOS sensors,and Charge Coupled Devices (CCDs).The Previewerisa real-timeimage processingenginethattakesraw imagerdatafroma CMOS sensororCCD and convertsfroman RGB Bayer PatterntoYUV4:2:2.The Histogramand H3A modules providestatisticalinformationon theraw colordataforuse by theDM6446. The Resizeracceptsimage data forseparatehorizontaland verticalresizingfrom 1/4x to 4x in incrementsof 256/N,where N is between 64 and 1024. The Video ProcessingBack-End (VPBE) iscomprisedof an On-Screen DisplayEngine (OSD) and a VideoEncoder(VENC).The OSD engineiscapableofhandling2 separatevideowindows and 2 separate OSD windows.Other configurationsinclude2 videowindows,1 OSD window, and 1 attributewindow allowingup to 8 levelsof alphablending.The VENC providesfouranalogDACs thatrun at 54 MHz, providinga means forcompositeNTSC/PAL video,S-Video,and/orComponent videooutput.The VENC alsoprovidesup to24 bitsofdigitaloutputtointerfacetoRGB888 devices.The digitaloutputiscapableof 8/16-bitBT.656 outputand/orCCIR.601 withseparatehorizontaland verticalsyncs. The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween theDM644x and the network.The DM6446 EMAC supportboth 10Base-T and 100Base-TX, or 10 Mbits/second(Mbps) and 100 Mbps ineitherhalf-orfull-duplexmode, withhardwareflowcontroland qualityofservice(QOS) support. The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerate allPHY devicesinthe system.Once a PHY candidatehas been selectedby the ARM, the MDIO module transparentlymonitorsitslinkstateby readingthePHY statusregister.Linkchange events are storedintheMDIO module and can optionallyinterrupttheARM, allowingtheARM topollthelink statusofthedevicewithoutcontinuouslyperformingcostlyMDIO accesses. The HPI,I2C,SPI,USB2.0, and VLYNQ portsallowDM6446 toeasilycontrolperipheraldevicesand/or communicate withhostprocessors.The DM6446 alsoprovidesmultimediacardsupport,MMC/SD, with SDIO support. The DM6446 alsoincludesa Video/ImagingCo-processor(VICP) to offloadmany videoand imaging processingtasksfrom theDSP core,making more DSP MIPS availableforcommon videoand imaging algorithms.For more informationon the VICP enhanced codecs,such as H.264 and MPEG4, please contactyournearestTIsalesrepresentative. The richperipheralsetprovidesthe abilityto controlexternalperipheraldevicesand communicate with externalprocessors.For detailson each oftheperipherals,see therelatedsectionslaterinthisdocument and the associatedperipheralreferenceguideslistedinSection2.8.3.1, RelatedDocumentationFrom Texas Instruments. The DM6446 has a completeset of developmenttoolsforboth the ARM and DSP. These includeC compilers,a DSP assembly optimizerto simplifyprogramming and scheduling,and a Windows ™ debuggerinterfaceforvisibilityintosourcecode execution.

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Clock(s) Power/Sleep Controller Pin Multiplexing ARM Subsystem ARM926EJ-S CPU 16 KB I-Cache

16 KB RAM

8 KB ROM

C64x+™ DSP CPU 32 KB L1 Pgm

64 KB L2 RAM

Coprocessor (VICP) BT.656, Y/C, Raw (Bayer) Video Processing Subsystem (VPSS) CCD Controller Video Interface Front End Resizer Histogram/ Preview 10b DAC On-Screen Display (OSD) Video Encoder (VENC) 10b DAC 10b DAC 10b DAC Back End 8b BT.656, Y/C, 24b RGB NTSC/ PAL, S-Video, RGB, YPbPr Switched Central Resource (SCR) Peripherals EDMA3 Audio Serial Port I C2 SPI UART Serial Interfaces DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA/ Compact Flash MMC/ SD/ SDIO Program/DataStorage Watchdog Timer PWM System General- Purpose Timer USB 2.0 PHY VLYNQ EMAC With MDIO Connectivity HPI TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010

1.3 FunctionalBlock Diagram

Figure1-1shows thefunctionalblockdiagramofthedevice. Figure1-1.TMS320DM6446 FunctionalBlock Diagram Copyright© 2005–2010,Texas InstrumentsIncorporated DigitalMedia System-on-Chip(DMSoC) 5 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Thisdatamanual revisionhistoryhighlightsthetechnicalchanges made totheSPRS283G device-specific datamanual tomake itan SPRS283H revision. Scope: Added information/dataon siliconrevision2.3. ApplicableupdatestotheDM644x devicefamily,specificallyrelatingtotheTMS320DM6446 device,have been incorporated. TMS320DM6446 RevisionHistory SEE ADDITIONS/MODIFICATIONS/DELETIONS Global • Added information/dataon siliconrevision2.3 Section2.1 Table2-1,CharacteristicsoftheProcessor: DeviceCharacteristics• Updated/changed"C64x+ Megamodule Revision"forsiliconrevision2.3

• Updated/changed"JTAG BSDL_ID" forsiliconrevision2.3 Section2.8.3.1 • Updated/changedlistofreferencedocuments RelatedDocumentation From Texas Instruments Section3.3.1.1 • Updated/changedtheaddressoftheBOOTCFG registerfrom"0x01C4 000A" to"0x01C4 0014" BOOTCFG Register [Updatemade inRevisionG]

Description

Section3.5.1 Figure3-6,MSTPRI1 Register: SwitchedCentral • Updated/changedthedefaultvalueofbits22:20from"R-100"to"R/W-100" Resource(SCR) Bus Priorities Section3.5.4 Figure3-7,PINMUX0 Register: PINMUX0 Register • Updated/changedthedefaultvalueofbits4:0from"R/W-LLLL"to"R/W-LLLLL" Section6.3.1.3 Figure6-6,PLL1 and PLL2 ClockDomain BlockDiagram: DM6446 Power and • PLL Controller2:Updated/changed"PLLDIV1 (/1)"to"PLLDIV1 (/10)" ClockDomains Section6.6.3 Table6-19,SwitchingCharacteristicsOver Recommended OperatingConditionsforCLK_OUT1: ClockPLL Electrical • Parameter1 [tc]:Added "ns"intheUNIT column Data/Timing(Inputand OutputClocks) Section6.10.1.2 Table6-35,SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Data/Timing • Parameter24 [tw(EMWEL) ]:Added "ns"intheUNIT column Section6.12.1 Table6-43,MMC/SD/SDIO RegisterDescriptions: MMC/SD/SDIO • Updated/changed0x01E1 0064 from"SDIO"to"SDIOCTL (SDIO ControlRegister)" Peripheral • Updated/changed0x01E1 0068 from"SDIO"to"SDIOST0 (SDIO StatusRegister0)"Description(s)

• Updated/changed0x01E1 006C from"SDIO"to"SDIOIEN (SDIO InterruptEnableRegister)"
• Updated/changed0x01E1 0070 from"Reserved"to"SDIOIST (SDIO InterruptStatusRegister)" Copyright© 2005–2010,Texas InstrumentsIncorporated Contents 7 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com TMS320DM6446 RevisionHistory(continued) SEE ADDITIONS/MODIFICATIONS/DELETIONS Section6.15.3 Table6-72,SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB2.0: USB2.0 Electrical • Parameter8,[tw(EOPR) ]:Added footnoteaboutbeingacceptedas validEOP Data/Timing JTAG Peripheral Figure6-79,JTAG ID RegisterDescription-DM6446 RegisterValue-0xXB70 002F: RegisterDescription(s)• Updated/changedfootnote– JTAG ID Register Table6-114,JTAG ID RegisterSelectionBitDescriptions:

• Updated/changedDESCRIPTION ofBits31:28(VARIANT)

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2 Device Overview

2.1 Device Characteristics

Table2-1 providesan overviewoftheTMS320DM6446 SoC. The tableshows significantfeaturesofthe device,includingthecapacityofon-chipRAM, peripherals,internalperipheralbus frequencyrelativetothe C64x+ DSP, and thepackage typewithpincount. Table2-1.CharacteristicsoftheProcessor HARDWARE FEATURES DM6446 DDR2 Memory Controller DDR2 (16/32-bitbus width) Asynchronous(8/16-bitbus width)RAM, FlashAsynchronousEMIF (EMIFA) (NOR, NAND) Compact Flash FlashCards MMC/SD withsecuredatainput/output(SDIO) SmartMedia/xD 64 independentchannelsEDMA3 8 QDMA channels 2 64-BitGeneralPurpose(eachconfigurableas 2 Timers separate32-bittimers) 1 64-BitWatchdog UART 3 (onewithRTS and CTS flowcontrol) Peripherals SPI 1 (supports2 slavedevices) Not allperipheralspinsare I2C 1 (Master/Slave)availableatthesame time. AudioSerialPort[ASP] 1(Formore details,see Section3,Device 10/100EthernetMAC withManagement Data 1Configurations). Input/Output VLYNQ 1 HPI 1 (16-bitmultiplexedaddress/data) General-PurposeInput/OutputPort Up to71 PWM 3 outputs ATA/CF 1 (ATA/ATAPI-6)

1 Input(VPFE)ConfigurableVideoPorts 1 Output(VPBE)

HighSpeed DeviceUSB 2.0 HighSpeed Host VICP 1 Size(Bytes) 160KB RAM, 8KB ROM DSP

• 32KB L1 Program (L1P)/Cache(upto32KB)
• 80KB L1 Data (L1D)/Cache(upto32KB)
• 64KB UnifiedMapped RAM/Cache (L2) On-ChipMemory Organization ARM
• 16KB I-cache
• 8KB D-cache
• 16KB RAM
• 8KB ROM CPU ID + CPU Rev ID ControlStatusRegister(CSR.[31:16]) 0x1000 C64x+ Megamodule RevisionID Register(MM_REVID[15:0]) 0x0000 (SiliconRevisions1.3and earlier) Revision (addresslocation:0x0181 2000) 0x0003 (SiliconRevisions2.1and later) JTAGID Register 0x0B70 002F (SiliconRevisions1.3and earlier)JTAG BSDL_ID (addresslocation:0x01C4 0028) 0x1B70 002F (SiliconRevisions2.1and later) Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-1.CharacteristicsoftheProcessor (continued) HARDWARE FEATURES DM6446 DSP 810 MHz DM6446 -810 ARM 405 MHz DSP 594 MHz CPU Frequency MHz DM6446 -594 ARM 297 MHz DSP 513 MHz DM6446A -513 ARM 256.5MHz DSP 1.23ns DM6446 -810 ARM 2.47ns DSP 1.68ns CycleTime ns DM6446 -594 ARM 3.37ns DSP 1.95ns DM6446A -513 ARM 3.90ns 1.2V (-594,A-513) Core (V) Voltage 1.3V (-810) x1 (Bypass),x30 (-810)CLKIN frequencymultiplierPLL Options (27MHz reference) x1 (Bypass),x22 (-594,A-513) 16 x 16 mmBGA Package 361-PinBGA (ZWT)ballfinishSnAgCu ProcessTechnology mm 0.09mm ProductPreview(PP), ProductStatus(1) Advance Information(AI), PD orProductionData (PD) (1) PRODUCTION DATA informationiscurrentas ofpublicationdate.ProductsconformtospecificationsperthetermsofTexas Instrumentsstandardwarranty.Productionprocessingdoes notnecessarilyincludetestingofallparameters.

2.2 Device Compatibility

The ARM926EJ-S RISC CPU iscompatiblewithotherARM9 CPUs fromARM Holdingsplc. The C64x+ DSP core iscode-compatiblewiththe C6000 ™ DSP platformand supportsfeaturesof the C64x DSP family.

2.3 ARM Subsystem

The ARM Subsystem isdesignedto givethe ARM926EJ-S (ARM9) master controlof the device.In general,theARM isresponsibleforconfigurationand controlofthedevice;includingtheDSP Subsystem, theVPSS Subsystem,and a majorityoftheperipheralsand externalmemories. The ARM Subsystem includesthefollowingfeatures:

• ARM926EJ-S RISC processor
• ARMv5TEJ (32/16-bit)instructionset
• Littleendian
• Co-Processor15 (CP15)
• MMU
• 16KB Instructioncache
• 8KB Data cache
• WriteBuffer
• 16KB InternalRAM (32-bit-wideaccess)
• 8KB InternalROM (ARM bootloaderfornon-EMIFA bootoptions)
• Embedded TraceModule and Embedded TraceBuffer(ETM/ETB)

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• ARM Interruptcontroller
• PLL Controller
• Power and SleepController(PSC)
• System Module

2.3.1 ARM926EJ-S RISC CPU

The ARM Subsystem integratestheARM926EJ-S processor.The ARM926EJ-S processorisa member of ARM9 familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplications where fullmemory management, highperformance,low diesize,and low power are allimportant.The ARM926EJ-S processorsupportsthe32-bitARM and 16 bitTHUMB instructionsets,enablingtheuserto tradeoffbetween high performanceand high code density.Specifically,the ARM926EJ-S processor supportstheARMv5TEJ instructionset,whichincludesfeaturesforefficientexecutionofJava bytecodes, providingJava performancesimilarto JustinTime (JIT)Java interpreter,but withoutassociatedcode overhead. The ARM926EJ-S processorsupportsthe ARM debug architectureand includeslogicto assistinboth hardware and softwaredebug. The ARM926EJ-S processorhas a Harvardarchitectureand providesa completehighperformancesubsystem,including:

• ARM926EJ -S integercore
• CP15 systemcontrolcoprocessor
• Memory Management Unit(MMU)
• Separateinstructionand dataCaches
• Writebuffer
• Separateinstructionand dataTightly-CoupledMemories (TCMs) [internalRAM] interfaces
• Separateinstructionand dataAHB bus interfaces
• Embedded TraceModule and Embedded TraceBuffer(ETM/ETB) For more completedetailson theARM9, refertotheARM926EJ-S TechnicalReferenceManual,available athttp://www.arm.com.

2.3.2 CP15

The ARM926EJ-S system controlcoprocessor(CP15) isused to configureand controlinstructionand data caches,Tightly-CoupledMemories (TCMs), Memory Management Unit(MMU), and otherARM subsystem functions.The CP15 registersare programmed usingthe MRC and MCR ARM instructions, when theARM ina privilegedmode such as supervisororsystemmode.

2.3.3 MMU

The ARM926EJ-S MMU providesvirtualmemory featuresrequiredby operatingsystemssuch as Linux® , Windows ® CE, Ultron® ,ThreadX® ,etc.A singlesetoftwo levelpage tablesstoredinmain memory is used tocontroltheaddresstranslation,permissionchecksand memory regionattributesforbothdataand instructionaccesses.The MMU uses a singleunifiedTranslationLookasideBuffer(TLB) to cache the informationheldinthepage tables.The MMU featuresare:

• StandardARM architecturev4 and v5 MMU mapping sizes,domains and accessprotectionscheme.
• Mapping sizesare: – 1MB (sections) – 64KB (largepages) – 4KB (smallpages) – 1KB (tinypages)
• Access permissionsforlargepages and smallpages can be specifiedseparatelyforeach quarterof thepage (subpagepermissions)
• Hardware page tablewalks Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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• InvalidateentireTLB, usingCP15 register8
• InvalidateTLB entry,selectedby MVA, usingCP15 register8
• Lockdown ofTLB entries,usingCP15 register10

2.3.4 Caches and WriteBuffer

The sizeoftheInstructionCache is16KB, Data cache is8KB. Additionally,theCaches have thefollowing features:

• Virtualindex,virtualtag,and addressedusingtheModifiedVirtualAddress(MVA)
• Four-waysetassociative,witha cache linelengthofeightwords perline(32-bytesperline)and with two dirtybitsintheDcache
• Dcache supportswrite-throughand write-back(orcopy back)cache operation,selectedby memory regionusingtheC and B bitsintheMMU translationtables.
• Critical-wordfirstcache refilling
• Cache lockdownregistersenablecontroloverwhich cache ways are used forallocationon a linefill, providinga mechanism forbothlockdown,and controllingcache corruption
• Dcache storesthePhysicalAddress TAG (PA TAG) correspondingtoeach Dcache entryintheTAG RAM foruse duringthe cache linewrite-backs,inadditionto the VirtualAddress TAG storedinthe TAG RAM. Thismeans thattheMMU isnotinvolvedinDcache write-backoperations,removingthe possibilityofTLB missesrelatedtothewrite-backaddress.
• Cache maintenanceoperationsprovideefficientinvalidationof,theentireDcache orIcache,regionsof theDcache orIcache,and regionsofvirtualmemory. The writebufferisused forallwritestoa noncachablebufferableregion,write-throughregionand write misses toa write-backregion.A separatebufferisincorporatedintheDcache forholdingwrite-backfor cache lineevictionsorcleaningofdirtycache lines.The main writebufferhas 16-worddatabufferand a four-addressbuffer.The Dcache write-backhas eightdataword entriesand a singleaddressentry.

2.3.5 TightlyCoupled Memory (TCM)

ARM internalRAM isprovidedforstoringreal-timeand performance-criticalcode/dataand theInterrupt Vectortable.ARM internalROM enablesnon-EMIFA bootoptions,such as NAND and UART. The RAM and ROM memories interfacedtotheARM926EJ-S viathetightlycoupledmemory interfacethatprovides forseparateinstructionand databus connections.SincetheARM TCM does notallowinstructionson the D-TCM bus or data on the I-TCM bus,an arbiterisincludedso thatboth data and instructionscan be storedin the internalRAM/ROM. The arbiteralsoallowsaccesses to the RAM/ROM from extra-ARM sources(e.g.,EDMA3 orothermasters).The ARM926EJ-S has built-inDMA supportfordirectaccesses totheARM internalmemory froma non-ARM master.Because ofthetime-criticalnatureoftheTCM link totheARM internalmemory, allaccessesfromnon-ARM devicesaretreatedas DMA transfers. Instructionand Data accesses are differentiatedviaaccessingdifferentmemory map regions,withthe instructionregionfrom 0x0000 through0x7FFF and data from 0x8000 through0xFFFF. The instruction regionat 0x0000 and data regionat 0x8000 map to the same physical16KB TCM RAM. Placingthe instructionregionat0x0000 isnecessarytoallowtheARM InterruptVectortabletobe placedat0x0000, as requiredby the ARM architecture.The internal16-KB RAM issplitintotwo physicalbanks of 8KB each,which allowssimultaneousinstructionand dataaccessestobe accomplishedifthecode and data areinseparatebanks.

2.3.6 Advanced High-PerformanceBus (AHB)

The ARM Subsystem uses theAHB portoftheARM926EJ-S toconnecttheARM totheConfigbus and theexternalmemories.Arbitersareemployed toarbitrateaccesstotheseparateD-AHB and I-AHB by the ConfigBus and theexternalmemories bus.

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2.3.7 Embedded Trace Macrocell(ETM) and Embedded Trace Buffer(ETB)

To supportreal-timetrace,theARM926EJ-S processorprovidesan interfacetoenableconnectionofan Embedded Trace Macrocell(ETM). The ARM926ES-J Subsystem in the DM6446 also includesthe Embedded TraceBuffer(ETB).The ETM consistsoftwo parts:

• TracePortprovidesreal-timetracecapabilityfortheARM9.
• Triggeringfacilitiesprovidetriggerresources,which includeaddressand data comparators,counter, and sequencers. The DM6446 traceportisnotpinnedoutand isinsteadonlyconnectedtotheEmbedded Trace Buffer. The ETB has a 4KB buffermemory. ETB enableddebug toolsarerequiredtoread/interpretthecaptured tracedata.

2.3.8 ARM Memory Mapping

The ARM memory map isshown inSection2.5,Memory Map Summary ,ofthisdocument.The ARM has accesstomemories shown inthefollowingsections.

2.3.8.1 ARM InternalMemories

The ARM has accesstothefollowingARM internalmemories:

• 16KB ARM InternalRAM on TCM interface,logicallyseparatedintotwo 8KB pages to allow simultaneousaccesson any givencycleifthereareseparateaccessesforcode (I-TCMbus)and data (D-TCM) tothedifferentmemory regions.
• 8KB ARM InternalROM

2.3.8.2 ExternalMemories

The ARM has accesstothefollowingexternalmemories:

• DDR2 SynchronousDRAM
• AsynchronousEMIF /NOR Flash/NAND Flash
• ATA/CF
• Flashcarddevices: – MMC/SD withSDIO – xD – SmartMedia

2.3.8.3 DSP Memories

The ARM has accesstothefollowingDSP memories:

• L2 RAM
• L1P RAM
• L1D RAM

2.3.8.4 ARM-DSP Integration

DM6446 ARM and DSP integrationfeaturesareas follows:

• DSP visibilityfromARM ’s memory map, see Section2.5,Memory Map Summary ,fordetails
• BootModes forDSP -see Section3 (DeviceConfigurations)and Section3.3.3(DSP Boot)fordetails
• ARM controlofDSP boot/reset-see Section3 (DeviceConfigurations)and Section3.3.2(ARM Boot) fordetails
• ARM controlofDSP isolationand powerdown /powerup - see Section3,DeviceConfigurations,for details
• ARM and DSP Interrupts-see Section6.7.1,ARM CPU Interrupts,and Section6.7.2,DSP Interrupts, fordetails Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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2.3.9 Peripherals

The ARM9 has accesstoalloftheperipheralson theDM6446 devicewiththeexceptionoftheVICP.

2.3.10 PLL Controller(PLLC)

The ARM Subsystem includesthe PLL Controller.The PLL Controllercontainsa set of registersfor configuringDM6446 ’s two internalPLLs (PLL1 and PLL2).The PLL Controllerprovidesthe following configurationand control:

• PLL Bypass Mode
• SetPLL multiplierparameters
• SetPLL dividerparameters
• PLL power down
• Oscillatorpower down The PLLs arebrieflydescribedinthisdocument inSection6.6,ClockPLLs.For more detailedinformation on thePLLs and PLL Controllerregisterdescriptions,see theTMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ).

2.3.11 Power and Sleep Controller(PSC)

The ARM Subsystem includesthe Power and Sleep Controller(PSC). Through registersettings accessibleby theARM9, thePSC providestwo levelsofpower savings:peripheral/moduleclockgating and power domain shut-off.Briefdetailson thePSC aregiveninSection6.3,Power Supplies.For more detailedinformationand completeregisterdescriptionsforthe PSC, see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ).

2.3.12 ARM InterruptController(AINTC)

The ARM InterruptController(AINTC)acceptsdeviceinterruptsand maps them toeithertheARM ’s IRQ (interruptrequest)or FIQ (fastinterruptrequest).The ARM InterruptControllerisbrieflydescribedin Section6.7,Interrupts,ofthisdocument.For detailedinformationon theARM InterruptController,see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ).

2.3.13 System Module

The ARM Subsystem includestheSystem module.The System module consistsofa setofregistersfor configuringand controllinga varietyof system functions.For detailsand registerdescriptionsforthe System module, see Section3, Device Configurations, and see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ).

2.3.14 Power Management

DM6446 has severalmeans of managing power consumption.There isextensiveuse of clockgating, which reduces the power used by globaldevice clocks and individualperipheralclocks.Clock management can be utilizedto reduce clockfrequenciesinorderto reduce switchingpower.For more detailson power management techniques,see Section3 (DeviceConfigurations),Section6 (Peripheral and ElectricalSpecifications),and see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ). DM6446 givestheprogrammer fullflexibilitytouse any and allofthepreviouslymentionedcapabilitiesto customizean optimalpower management strategy.Severaltypicalpower management scenariosare describedinthefollowingsections.

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2.4 DSP Subsystem

The DSP Subsystem includesthefollowingfeatures:

• C64x+ DSP CPU
• 32KB L1 Program (L1P)/Cache(upto32KB)
• 80KB L1 Data (L1D)/Cache(upto32KB)
• 64KB UnifiedMapped RAM/Cache (L2)
• Littleendian

2.4.1 C64x+ DSP CPU Description

The C64x+ CentralProcessingUnit(CPU) consistsof eightfunctionalunits,two registerfiles,and two data paths as shown in Figure2-1. The two general-purposeregisterfiles(A and B) each contain 32 32-bitregistersfora totalof64 registers.The general-purposeregisterscan be used fordataorcan be data addresspointers.The data typessupportedincludepacked 8-bitdata,packed 16-bitdata,32-bit data,40-bitdata,and 64-bitdata.Valueslargerthan32 bits,such as 40-bit-longor64-bit-longvaluesare storedin registerpairs,withthe 32 LSBs of data placedin an even registerand the remaining8 or 32 MSBs inthenextupperregister(whichisalwaysan odd-numberedregister). performa generalsetofarithmetic,logical,and branchfunctions.The .D unitsprimarilyloaddata from memory totheregisterfileand storeresultsfromtheregisterfileintomemory. The C64x+ CPU extendstheperformanceoftheC64x corethroughenhancements and new features. Each C64x+ .M unitcan performone ofthefollowingeach clockcycle:one 32 x 32 bitmultiply,one 16 x 32 bitmultiply,two 16 x 16 bitmultiplies,two 16 x 32 bitmultiplies,two 16 x 16 bitmultiplieswith add/subtractcapabilities,four8 x 8 bitmultiplies,four8 x 8 bitmultiplieswithadd operations,and four 16 x 16 multiplieswithadd/subtractcapabilities(includinga complex multiply).There isalsosupportfor Galoisfieldmultiplicationfor8-bitand 32-bitdata.Many communicationsalgorithmssuch as FFTs and modems requirecomplex multiplication.The complex multiply(CMPY) instructiontakesfor16-bitinputs and producesa 32-bitrealand a 32-bitimaginaryoutput.There arealsocomplex multiplieswithrounding capabilitythatproducesone 32-bitpacked outputthatcontain16-bitrealand 16-bitimaginaryvalues.The 32 x 32 bitmultiplyinstructionsprovidethe extended precisionnecessary for audio and other high-precisionalgorithmson a varietyofsignedand unsigned32-bitdatatypes. The .Lor (ArithmeticLogicUnit)now incorporatestheabilitytodo paralleladd/subtractoperationson a pairofcommon inputs.Versionsofthisinstructionexisttowork on 32-bitdataor on pairsof16-bitdata performingdual16-bitadd and subtractsinparallel.Therearealsosaturatedformsoftheseinstructions. The C64x+ core enhances the .S unitinseveralways. In the C64x core,dual16-bitMIN2 and MAX2 comparisonswere onlyavailableon the.Lunits.On theC64x+ coretheyarealsoavailableon the.S unit which increasesthe performanceof algorithmsthatdo searchingand sorting.Finally,to increasedata packingand unpackingthroughput,the.S unitallowssustainedhighperformanceforthequad 8-bit/16-bit and dual16-bitinstructions.Unpack instructionsprepare8-bitdata forparallel16-bitoperations.Pack instructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Othernew featuresinclude:

• SPLOOP -A smallinstructionbufferintheCPU thataidsincreationofsoftwarepipeliningloopswhere multipleiterationsofa loopareexecutedinparallel.The SPLOOP bufferreducesthecode size associatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOP bufferarefullyinterruptible.
• Compact Instructions-The nativeinstructionsizefortheC6000 devicesis32 bits.Many common instructionssuch as MPY, AND, OR, ADD, and SUB can be expressedas 16 bitsiftheC64x+ compilercan restrictthecode touse certainregistersintheregisterfile.Thiscompressionis performedby thecode generationtools.
• InstructionSet Enhancement -As notedabove,therearenew instructionssuch as 32-bit multiplications,complexmultiplications,packing,sorting,bitmanipulation,and 32-bitGaloisfield multiplication.
• ExceptionsHandling-Intendedtoaidtheprogrammer inisolatingbugs.The C64x+ CPU isableto detectand respondtoexceptions,bothfrominternallydetectedsources(suchas illegalop-codes)and fromsystemevents(suchas a watchdogtimeexpiration).
• Privilege-Definesuserand supervisormodes ofoperation,allowingtheoperatingsystemtogivea basiclevelofprotectiontosensitiveresources.Localmemory isdividedintomultiplepages,each with read,write,and executepermissions.
• Time-Stamp Counter -PrimarilytargetedforReal-TimeOperatingSystem (RTOS) robustness,a free-runningtime-stampcounterisimplementedintheCPU whichisnot sensitivetosystemstalls. For more detailson theC64x+ CPU and itsenhancements overtheC64x architecture,see thefollowing documents:
• TMS320C64x/C64x+ DSP CPU and InstructionSetReferenceGuide (literaturenumber SPRU732 )
• TMS320C64x TechnicalOverview(literaturenumber SPRU395 )

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Á Á Á Á Á Á Á .D1 .M1 Á Á Á Á Á Á Á Á Á Á Á Á Á .S1 Á Á Á Á Á Á Á Á Á Á .L1 long src odd dst src2 src1 Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á Á Á src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Á Á Á Odd register file B (B1, B3, B5...B31) Á Á Á .D2 Á Á Á Á src1 dst src2DA2 LD2a LD2b src2 .M2 src1 Á Á Á dst1 Á Á Á .S2 src1 Á Á Á Á even dst long src odd dst ST2a ST2b long src .L2 Á Á Á Á even dst odd dst Á Á Á src1 Data path B Control Register

32 MSB

32 LSB

dst2 (A) (B) (B) (A) (C) (C) Even register file A (A0, A2, A4...A30) Even register file B (B0, B2, B4...B30) (D) (D) (D) (D) A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure2-1.TMS320C64x+ ™ CPU (DSP Core)Data Paths Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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2.4.2 DSP Memory Mapping

The DSP memory map isshown in Section2.5, Memory Map Summary . Configurationof the control registersforDDR2, EMIFA, and ARM InternalRAM issupportedby the ARM. The DSP has access to memories shown inthefollowingsections.

2.4.2.1 ARM InternalMemories

The DSP has accesstothe16KB ARM InternalRAM on theARM D-TCM interface(i.e.,dataonly).

2.4.2.2 ExternalMemories

The DSP has accesstothefollowingExternalmemories:

• DDR2 SynchronousDRAM
• AsynchronousEMIF /NOR Flash

2.4.2.3 DSP InternalMemories

The DSP has accesstothefollowingDSP memories:

• L2 RAM
• L1P RAM
• L1D RAM

2.4.2.4 C64x+ CPU

The C64x+ coreuses a two-levelcache-basedarchitecture.The Level1 Program cache (L1P)is32 KB directmapped cache and theLevel1 Data cache (L1D)is80 KB 2-way setassociatedcache.The Level2 memory/cache (L2)consistsofa 64 KB memory space thatissharedbetween program and dataspace. L2 memory can be configuredas mapped memory, cache,ora combinationofboth. Table2-2shows a memory map oftheC64x+ CPU cache registersforthedevice. Table2-2.C64x+ Cache Registers HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 0000 L2CFG L2 Cache configurationregister 0x0184 0020 L1PCFG L1P SizeCache configurationregister 0x0184 0024 L1PCC L1P FreezeMode Cache configurationregister 0x0184 0040 L1DCFG L1D SizeCache configurationregister 0x0184 0044 L1DCC L1D FreezeMode Cache configurationregister 0x0184 0048 -0x0184 0FFC - Reserved 0x0184 1000 EDMAWEIGHT L2 EDMA3 accesscontrolregister 0x0184 1004 -0x0184 1FFC - Reserved 0x0184 2000 L2ALLOC0 L2 allocationregister0 0x0184 2004 L2ALLOC1 L2 allocationregister1 0x0184 2008 L2ALLOC2 L2 allocationregister2 0x0184 200C L2ALLOC3 L2 allocationregister3 0x0184 2010 -0x0184 3FFF - Reserved 0x0184 4000 L2WBAR L2 writebackbase addressregister 0x0184 4004 L2WWC L2 writebackword countregister 0x0184 4010 L2WIBAR L2 writebackinvalidatebase addressregister 0x0184 4014 L2WIWC L2 writebackinvalidateword countregister 0x0184 4018 L2IBAR L2 invalidatebase addressregister 0x0184 401C L2IWC L2 invalidateword countregister 0x0184 4020 L1PIBAR L1P invalidatebase addressregister 0x0184 4024 L1PIWC L1P invalidateword countregister

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-2.C64x+ Cache Registers(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 4030 L1DWIBAR L1D writebackinvalidatebase addressregister 0x0184 4034 L1DWIWC L1D writebackinvalidateword countregister 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D BlockWriteback 0x0184 4044 L1DWWC L1D BlockWriteback 0x0184 4048 L1DIBAR L1D invalidatebase addressregister 0x0184 404C L1DIWC L1D invalidateword countregister 0x0184 4050 -0x0184 4FFF - Reserved 0x0184 5000 L2WB L2 writebackallregister 0x0184 5004 L2WBINV L2 writebackinvalidateallregister 0x0184 5008 L2INV L2 GlobalInvalidatewithoutwriteback 0x0184 500C -0x0184 5027 - Reserved 0x0184 5028 L1PINV L1P GlobalInvalidate 0x0184 502C -0x0184 5039 - Reserved 0x0184 5040 L1DWB L1D GlobalWriteback 0x0184 5044 L1DWBINV L1D GlobalWritebackwithInvalidate 0x0184 5048 L1DINV L1D GlobalInvalidatewithoutwriteback 0x0184 8000 -0x0184 8004 MAR0 -MAR1 Reserved0x0000 0000 -0x01FF FFFF 0x0184 8008 -0x0184 8024 MAR2 -MAR9 Memory AttributeRegistersforEMIFA 0x0200 0000 -0x09FF FFFF 0x0184 8028 -0x0184 802C MAR10 -MAR11 Reserved0x0A00 0000 -0x0BFF FFFF 0x0184 8030 -0x0184 803C MAR12 -MAR15 Memory AttributeRegistersforVLYNQ 0x0C00 0000 -0x0FFF FFFF 0x0184 8040 -0x0184 8104 MAR16 -MAR65 Reserved0x1000 0000 -0x41FF FFFF Memory AttributeRegistersforEMIFA/VLYNQ Shadow 0x4200 0000 -0x0184 8108 -0x0184 813C MAR66 -MAR79 0x4FFF FFFF 0x0184 8140-0x0184 81FC MAR80 -MAR127 Reserved0x5000 0000 -0x7FFF FFFF 0x0184 8200 -0x0184 823C MAR128 -MAR143 Memory AttributeRegistersforDDR2 0x8000 0000 -0x8FFF FFFF 0x0184 8240 -0x0184 83FC MAR144 -MAR255 Reserved0x9000 0000 -0xFFFF FFFF

2.4.3 Peripherals

The DSP has controllabilityforthefollowingperipherals:

• VICP
• EDMA3
• ASP
• 2 Timers(Timer0 and Timer1)thatcan each be configuredas 1 64-bitor2 32-bittimers

2.4.4 DSP InterruptController

The DSP InterruptControlleraccepts device interruptsand appropriatelymaps them to the DSP ’s availableinterrupts.The DSP InterruptControllerisbrieflydescribedin Section6.7, Interrupts, of this document.For more detailedon theDSP InterruptController,see theTMS320C64x/C64x+ DSP CPU and InstructionSetReferenceGuide (literaturenumber SPRU732 ).

2.5 Memory Map Summary

Table2-3shows thememory map addressrangesofthedevice.Table2-4depictstheexpanded map of theConfigurationSpace (0x01800000 through0x0FFF FFFF).The devicehas multipleon-chipmemories associatedwithitstwo processorsand varioussubsystems.To help simplifysoftwaredevelopmenta unifiedmemory map isused where possibletomaintaina consistentviewofdeviceresourcesacrossall bus masters. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-3.Memory Map Summary START END SIZE EDMA3/ARM C64x+ HPI VPSSADDRESS ADDRESS (Bytes) PERIPHERAL 0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction) 0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction) Reserved Reserved 0x0000 4000 0x0000 5FFF 8K ARM ROM (Instruction) 0x0000 6000 0x0000 7FFF 8K Reserved 0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) Reserved ARM RAM0 ARM RAM0 0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) ARM RAM1 ARM RAM1 0x0000 C000 0x0000 DFFF 8K ARM ROM (Data) ARM ROM ARM ROM 0x0000 E000 0x0000 FFFF 8K 0x0001 0000 0x000F FFFF 960K 0x0010 0000 0x001F FFFF 1M VICP 0x0020 0000 0x007F FFFF 6M Reserved 0x0080 0000 0x0080 FFFF 64K L2 RAM/Cache 0x0081 0000 0x00E0 7FFF 6112K Reserved Reserved 0x00E0 8000 0x00E0 FFFF 32K L1P Cache 0x00E1 0000 0x00F0 3FFF 976K Reserved Reserved Reserved 0x00F0 4000 0x00F0 FFFF 48K L1D RAM 0x00F1 0000 0x00F1 7FFF 32K L1D Cache 0x00F1 8000 0x017F FFFF 9120K Reserved 0x0180 0000 0x01BB FFFF 3840K 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers CFG Space 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BF FFFF 255744 Reserved Reserved0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals(1) 0x0200 0000 0x09FF FFFF 128M EMIFA (Code and Data) EMIFA (Data) EMIFA (Data) 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved VLYNQ (Remote) 0x1000 0000 0x1000 7FFF 32K Reserved 0x1000 8000 0x1000 9FFF 8K ARM RAM0 ARM RAM0 0x1000 A000 0x1000 BFFF 8K ARM RAM1 ARM RAM1 0x1000 C000 0x1000 DFFF 8K ARM ROM ARM ROM Reserved 0x1000 E000 0x1000 FFFF 8K 0x1001 0000 0x110F FFFF 17344K Reserved Reserved Reserved0x1110 0000 0x111F FFFF 1M 0x1120 0000 0x117F FFFF 6M 0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache 0x1181 0000 0x11E0 7FFF 6112K Reserved Reserved Reserved 0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache 0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved 0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM 0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache 0x11F1 8000 0x1FFF FFFF 241M- Reserved Reserved Reserved 32K 0x2000 0000 0x2000 7FFF 32K DDR2 ControlRegisters DDR2 ControlRegisters DDR2 ControlRegisters DDR2 ControlRegisters 0x2000 8000 0x41FF FFFF 544M-32k Reserved Reserved Reserved 0x4200 0000(2) 0x4FFF FFFF 224M Reserved EMIFA/VLYNQ Shadow EMIFA/VLYNQ Shadow Reserved 0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved 0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2 DDR2 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved Reserved (1) HPI's accesstotheconfigurationbus peripheralsislimitedtothepower and sleepcontrollerregisters,PLL1 and PLL2 registers,and HPI configurationregisters. (2) EMIFA shadow memory starteda 0x4200 0000 isphysicallythesame memory as location0x0200 0000.Memory range0x200 0000 through0x09FF FFFF shouldonlybe used by C64x+ fordataaccesses.Memory range0x4200 0000 through0x4FFF FFFF can be used by C64x+ forbothcode executionand dataaccesses.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-4.ConfigurationMemory Map Summary START END SIZE ARM/EDMA3 C64x+ADDRESS ADDRESS (Bytes) 0x0180 0000 0x0180 FFFF 64K C64x+ InterruptController 0x0181 0000 0x0181 0FFF 4K C64x+ Powerdown Controller 0x0181 1000 0x0181 1FFF 4K C64x+ SecurityID 0x0181 2000 0x0181 2FFF 4K C64x+ RevisionID 0x0182 0000 0x0182 FFFF 64K Reserved C64x+ EMC 0x0183 0000 0x0183 FFFF 64K Reserved 0x0184 0000 0x0184 FFFF 64K C64x+ Memory System 0x0185 0000 0x0187 FFFF 192K Reserved 0x0188 0000 0x01BB FFFF 3328K Reserved 0x01BC 0000 0x01BC 00FF 256 Reserved 0x01BC 0100 0x01BC 01FF 256 ARM ETB Memory PinManager and Trace 0x01BC 0200 0x01BC 0FFF 3.5K 0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher 0x01BC 1900 0x01BF FFFF 255744 Reserved 0x01C0 0000 0x01C0 FFFF 64K EDMA3 CC EDMA3 CC 0x01C1 0000 0x01C1 03FF 1K EDMA3 TC0 EDMA3 TC0 0x01C1 0400 0x01C1 07FF 1K EDMA3 TC1 EDMA3 TC1 0x01C1 8800 0x01C1 9FFF 6K Reserved 0x01C1 A000 0x01C1 FFFF 24K 0x01C2 0000 0x01C2 03FF 1K UART0 0x01C2 0400 0x01C2 07FF 1K UART1 Reserved 0x01C2 0800 0x01C2 0BFF 1K UART2 0x01C2 0C00 0x01C2 0FFF 1K Reserved 0x01C2 1000 0x01C2 13FF 1K I2C 0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0 0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1 0x01C2 1C00 0x01C2 1FFF 1K Timer2(Watchdog) 0x01C2 2000 0x01C2 23FF 1K PWM0 0x01C2 2400 0x01C2 27FF 1K PWM1 Reserved 0x01C2 2800 0x01C2 2BFF 1K PWM2 0x01C2 2C00 0x01C3 FFFF 117K Reserved 0x01C4 0000 0x01C4 07FF 2K System Module System Module 0x01C4 0800 0x01C4 0BFF 1K PLL Controller1 Reserved 0x01C4 0C00 0x01C4 0FFF 1K PLL Controller2 0x01C4 1000 0x01C4 1FFF 4K Power and SleepController Power and SleepController 0x01C4 2000 0x01C4 202F 48 Reserved Reserved 0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP Reg 0x01C4 2034 0x01C4 23FF 1K -52 Reserved 0x01C4 2400 0x01C4 7FFF 23K 0x01C4 8000 0x01C4 83FF 1K ARM InterruptController 0x01C4 8400 0x01C5 FFFF 95K Reserved 0x01C6 0000 0x01C6 3FFF 16K Reserved 0x01C6 4000 0x01C6 5FFF 8K USB2.0 Registers/RAM 0x01C6 6000 0x01C6 67FF 2K ATA/CF 0x01C6 6800 0x01C6 6FFF 2K SPI 0x01C6 7000 0x01C6 77FF 2K GPIO Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-4.ConfigurationMemory Map Summary (continued) START END SIZE ARM/EDMA3 C64x+ADDRESS ADDRESS (Bytes) 0x01C6 7800 0x01C6 7FFF 2K HPI HPI 0x01C6 8000 0x01C6 FFFF 32K Reserved 0x01C7 0000 0x01C7 3FFF 16K VPSS Registers 0x01C7 4000 0x01C7 FFFF 48K Reserved 0x01C8 0000 0x01C8 0FFF 4K EMAC ControlRegisters 0x01C8 1000 0x01C8 1FFF 4K EMAC ControlModule Registers Reserved 0x01C8 2000 0x01C8 3FFF 8K EMAC ControlModule RAM 0x01C8 4000 0x01C8 47FF 2K MDIO ControlRegisters 0x01C8 4800 0x01C8 4FFF 2K Reserved 0x01C8 5000 0x01CB FFFF 236K 0x01CC 0000 0x01CD FFFF 128K VICP VICP 0x01CE 0000 0x01CF FFFF 128K Reserved 0x01D0 0000 0x01DF FFFF 1M Reserved 0x01E0 0000 0x01E0 0FFF 4K EMIFA Control 0x01E0 1000 0x01E0 1FFF 4K VLYNQ ControlRegisters 0x01E0 2000 0x01E0 3FFF 8K ASP ASP 0x01E0 4000 0x01E0 FFFF 48K Reserved 0x01E1 0000 0x01E1 FFFF 64K MMC/SD/SDIO Reserved 0x01E2 0000 0x01E3 FFFF 128K Reserved 0x01E4 0000 0x01FF FFFF 1792K 0x0200 0000 0x03FF FFFF 32M EMIFA Data/Code(CS2) EMIFA Data (CS2) 0x0400 0000 0x05FF FFFF 32M EMIFA Data/Code(CS3) EMIFA Data (CS3) 0x0600 0000 0x07FF FFFF 32M EMIFA Data/Code(CS4) EMIFA Data (CS4) 0x0800 0000 0x09FF FFFF 32M EMIFA Data/Code(CS5) EMIFA Data (CS5) 0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved 0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote)

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W V U T R P N M L K 10987654321 10987654321 DDR_D[1] DV DDR2 EM_A[4]/ GPIO27 CLK_OUT0/ GPIO48 MXI/CLKIN EM_A[5]/ GPIO26 MXV SS PLLV DD18 RSV24 EM_A[6]/ GPIO25 EM_A[8]/ GPIO23 EM_A[7]/ GPIO24 EM_A[13]/ GPIO18 EM_A[10]/ GPIO21 EM_A[15]/ GPIO16/ VLYNQ_TXD3 EM_A[11]/ GPIO20 EM_A[17]/ GPIO14/ VLYNQ_TXD2 EM_A[19]/ GPIO12/ VLYNQ_TXD1 EM_A[20]/ GPIO11/ VLYNQ_RXD0 EM_CS4 / GPIO9/ VLYNQ_ SCRUN DDR_ DQM[0] DDR_D[0] EM_A[21]/ GPIO10/ VLYNQ_TXD0 EM_A[14]/ GPIO17/ VLYNQ_RXD3 EM_A[9]/ GPIO22 MXV DDRESET VSS RSV3 VSS CV DD DV DDR2 DV DDR2 VSS VSS DDR_A[11]DDR_A[12]DDR_CLK0DDR_CLK0DDR_D[14] DV DDR2 VSS VSS DDR_D[5] DDR_D[6] DDR_D[9] DV DD18 EM_A[16]/ GPIO15/ VLYNQ_RXD2 DV DDR2 DDR_BS[2] CV DD DDR_D[11] DDR_D[15] DDR_CKE DDR_A[8] VSS DV DDR2 VSS VSS DV DDR2 DDR_ DQM[1] DDR_CAS DDR_WE DDR_VDDDLL CV DDDSP CV DD DDR_DQS[1] DDR_RAS DDR_A[10] CV DD CV DD DDR_D[2] DDR_D[3] DDR_D[8] DDR_D[13] DDR_BS[1] DDR_D[4] DDR_D[12] VSS EM_A[3]/ GPIO28 DV DD18 CV DD DV DD18 RSV7 MXO VSS DV DD18 VSS EM_A[18]/ GPIO13/ VLYNQ_RXD1 VSS EM_A[12]/ GPIO19 VSS DDR_CS CV DDDSP DDR_DQS[0] DDR_D[10] DDR_BS[0] EM_CS5 / GPIO8/ VLYNQ_ CLOCK RSV6 DDR_D[7] W V U T R P N M L K TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010

2.6 Pin Assignments

Extensiveuse ofpinmultiplexingisused toaccommodate thelargestnumber ofperipheralfunctionsin the smallestpossiblepackage. Pin multiplexingis controlledusing a combinationof hardware configurationat deviceresetand softwareprogrammable registersettings.For more informationon pin muxing,see Section3.5.2,MultiplexedPinConfigurations,ofthisdocument.

2.6.1 Pin Map (Bottom View)

Figure2-2throughFigure2-5show thebottomviewofthepackage pinassignmentsinfourquadrants(A, B,C, and D). Figure2-2.Pin Map [QuadrantA] Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

W V U T R P N M L K 191817161514131211 191817161514131211 DDR_A[9] VSS VSSCV DD CV DD VSS CV DD VSSDV DDR2 DV DDR2 DV DDR2VSS DV DDR2 DV DDR2VSS DDR_ VSSDLL DDR_ZPDDR_ZN VSS VSS VSSDV DD18 DV DD18 HD PCLK VDDA _1P8V CI6/CCD14/ UART_TXD2 CI7/CCD15/ UART_RXD2 DAC_IOUT_B RSV4DDR_D[29]DDR_D[27]DDR_D[21]DDR_D[18] DAC_IOUT_A YI4/CCD4 DAC_RBIAS DDR_A[3] DDR_A[4] DDR_A[0] VSS VSS DDR_DQM[2] DDR_D[26] YI7/CCD7 DDR_D[17] DDR_D[22] DDR_D[24] DDR_D[30] YI0/CCD0 VSSA _1P8V CI5/CCD13/ UART_CTS2 CI1/CCD9 CI4/CCD12/ UART_RTS2 DDR_VREF DDR_DQM[3] DDR_D[23] DAC_IOUT_D YI1/CCD1 YI3/CCD3 DDR_D[20] DDR_DQS[3] DDR_D[31] YI6/CCD6 VD DDR_A[7] DDR_A[2] DDR_D[19] DDR_D[28] DDR_A[6] DDR_D[16] DAC_IOUT_C CV DDDSP VSS CI2/CCD10 YI5/CCD5 DAC_V REF DV DD18 CI0/CCD8 CI3/CCD11 DV DDR2 VDDA _1P1V DV DDR2 VSSA _1P1V YI2/CCD2 DDR_A[1] DDR_DQS[2] DDR_D[25] VSS DDR_A[5] W V U T R P N M L K TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure2-3.Pin Map [QuadrantB]

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H G F E D C B A 191817161514131211 191817161514131211 CV DDDSP YOUT4/R4/ AEAW4 GPIOV33_1/ TXCLK GPIOV33_2/ COL GPIOV33_9/ RXD2 GPIOV33_8/ RXD1 GPIOV33_6/ TXD3 GPIOV33_4/ TXD1 GPIOV33_12/ RXDV GPIO2/G0 GPIOV33_7/ RXD0 GPIOV33_10/ RXD3 DV DD33 DV DD33DV DD33 VSS VSSVSS GPIO1/ C_WE GPIO0/ LCD_OE GPIO4/R0/ C_FIELD GPIOV33_0/ TXEN GPIO6/B1 VSYNC VPBECLK M24XI YOUT3/R3/ AEAW3 VCLK YOUT7/R7 CLK_OUT1/ TIM_IN/ GPIO49 PWM1/R2/ GPIO46 M24V DD CV DDDSP GPIO38/R1 DV DD18 VSS USB_R1 COUT5/G2 COUT0/B3/ BTSEL0 YOUT6/R6 YOUT2/G7/ AEAW2 COUT7/G4 YOUT1/G6/ AEAW1 DV DD18 USB_ VSSREF USB_ VSSA1P2LD0 USB_DP COUT2/B5/ EM_WIDTH RSV2 VSS USB_V SS1P8 USB_DM COUT3/B6/ DSP_BT COUT6/G3 M24XO GPIOV33_5/ TXD2 PWM2/ B2/GPIO47 HSYNC COUT1/B4/ BTSEL1 M24V SS GPIO3/B0/ LCD_FIELD PWM0/ GPIO45 YOUT0/G5/ AEAW0 GPIO5/G1 YOUT5/R5 CV DD USB_ VDDA1P2LD0 COUT4/B7 VSS DV DD18 USB_V DD1P8 GPIOV33_3/ TXD0 H G F E D C B A J CV DDDSP VSS USB_ VSSA3P3 DV DD18 USB_ID USB_ VDDA3P3 CV DDDSP VSS USB_VBUS J TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure2-4.Pin Map [QuadrantC] Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

J H G F E D C B A 10987654321 10987654321 EM_BA[1]/ DA1/ GPIO52 TMS SPI_EN0/ GPIO37RSV1 EM_CS3 SPI_CLK/ GPIO39 SPI_EN1/ HDDIR/ GPIO42 EM_CS2 / HCS GPIO7 EM_D12/ DD12/ HD12 EM_D1/ DD1/ HD1 EM_D5/ DD5/ HD5 RSV5 EM_D15/ DD15/ HD15 EM_D3/ DD3/ HD3 EM_D9/ DD9/ HD9 EM_D13/ DD13/ HD13 EM_D6/ DD6/ HD6 EM_D8/ DD8/ HD8 EM_WE /(WE)/ (IOWR )/DIOW/ HDS2 EM_D11/ DD11/ HD11 GPIO51/ ATA_CS1 EM_R/W / INTRQ/ HR/W EM_D4/ DD4/ HD4 SCL/ GPIO43 TDOSDA/GPIO44 TDI SD_DATA3 GPIOV33_14/ CRS VSS SD_DATA2 GPIOV33_13/ RXER SD_DATA1 GPIOV33_15/ MDIO RTCK VSS DMACK/ UART_TXD1 EM_BA[0]/ DA0/ HINT UART_RXD0/ GPIO35 EM_D2/ DD2/ HD2 EM_D10/ DD10/ HD10 VSS SD_CMD GPIO50/ ATA_CS0 DV DD18 VSS CV DDDSP DR/ GPIO34 VSS SD_DATA0 FSR/ GPIO32 TRST VSS DV DD18 VSS VSS CLKR/ GPIO30 GPIOV33_11/ RXCLK DV DD18 VSS CV DDDSP CLKX/ GPIO29 GPIOV33_16/ MDCLK EM_A[2]/ (CLE)/ HCNTL0 EM_A[1]/ (ALE)/ HHWIL EM_A[0]/ DA2/ HCNTL1/ GPIO53 VSS CV DDDSP DV DD33 SPI_DO/ GPIO41 TCK FSX/ GPIO31 DX/ GPIO33 DV DD18 EM_D7/ DD7/ HD7 UART_TXD0/ GPIO36 EMU1 EMU0 EM_D0/ DD0/ HD0 DV DD18 EM_WAIT/ (RDY/BSY )/ IORDY / HRDY DV DD18 DV DD18 SD_CLK EM_OE /(RE)/ (IORD)/DIOR/ HDS1 EM_D14/ DD14/ HD14 CV DDDSP DMARQ/ UART_RXD1 SPI_DI/ GPIO40 J H G F E D C B A TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure2-5.Pin Map [QuadrantD]

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010

2.7 TerminalFunctions

The terminalfunctionstables(Table 2-5 throughTable 2-30) identifythe externalsignalnames, the associatedpin(ball)numbers alongwiththemechanicalpackage designator,thepintype,whetherthepin has any internalpullupor pulldown resistors,and a functionalpin description.For more detailed informationon deviceconfiguration,peripheralselection,multiplexed/sharedpins,see Section3,Device Configurations,ofthisdatamanual. Table2-5.BOOT TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. BOOT These pinsaremultiplexedbetween ARM bootmode and theVPBE. Atreset,thebootmode inputsBTSEL0 and BTSEL1 aresampled todeterminetheARM bootCOUT0/ IPD configuration.See belowforthebootmodes setby theseB3/ A16 I/O/Z DV DD18 inputs.See Section3.3,Bootmode,formore details.BTSEL0 Afterreset,thesearevideoencoderoutputsCOUT0 and COUT1, orRGB666/888 Blueoutputdatabits3 and 4 B3/B4. BTSEL1 BTSEL0 ARM Boot Mode ARM ROM Boot(NAND, SPI)0 0COUT1/ [default]IPDB4/ B16 I/O/Z DV DD18 0 1 ARM EMIFA Boot(NOR)BTSEL1 1 0 ARM ROM Boot(HPI) 1 1 ARM ROM Boot(UART0) Thispinismultiplexedbetween EMIFA and theVPBE. At reset,theinputstateissampled tosettheEMIFA data COUT2/ bus width(EM_WIDTH). Foran 8-bit-wideEMIFA dataIPDB5/ A17 I/O/Z bus,EM_WIDTH = 0.Fora 16-bit-wideEMIFA databus,DV DD18EM_WIDTH EM_WIDTH = 1. Afterreset,itisvideoencoderoutputCOUT2 or RGB666/888 Blueoutputdatabit5 B5. Thispinismultiplexedbetween DSP bootand theVPBE. Atreset,theinputstateissampled tosettheDSP boot COUT3/ sourceDSP_BT. The DSP isbootedby theARM whenIPDB6/ B17 I/O/Z DSP_BT=0. The DSP bootsfromEMIFA whenDV DD18DSP_BT DSP_BT=1. Afterreset,itisvideoencoderoutputCOUT3 or RGB666/888 Bluedatabit6 outputB6. YOUT0/ IPDG5/ D15 I/O/Z DV DD18AEAW0 These pinsaremultiplexedbetween EMIFA and the YOUT1/ VPBE. Atreset,theinputstatesofAEAW[4:0] areIPDG6/ D16 I/O/Z sampled tosettheEMIFA addressbus width.SeeDV DD18AEAW1 Section3.4.2,PeripheralSelectionatDeviceReset,for details. YOUT2/ Afterreset,thesearevideoencoderoutputsYOUT[0:4]IPDG7/ D17 I/O/Z orRGB666/888 Red and Green databitoutputsG5, G6,DV DD18AEAW2 G7, R3, and R4. YOUT3/ IPDR3/ D18 I/O/Z DV DD18AEAW3 YOUT4/ IPDR4/ E15 I/O/Z DV DD18AEAW4 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-6.Oscillator/PLLTerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. OSCILLATOR, PLL CrystalinputMXI forMX oscillator(systemoscillator,typically27 MHz). Ifa crystal MXI/CLKIN L1 I DV DD18 inputisnot used,butinsteada physicalclock-insourceissupplied,thisisthe externaloscillatorclockinput. CrystaloutputforMX oscillator.Ifa crystalinputisnot used,butinsteada physicalMXO M1 O DV DD18 clock-insourceissupplied,MXO shouldbe leftas a No Connect. 1.8-Vpower supplyforMX oscillator.Ifa crystalinputisnot used,butinsteada MXV DD L5 S (3) physicalclock-insourceissupplied,MXV DD shouldstillbe connectedtothe1.8-V power supply. Ground forMX oscillator.Ifa crystalinputisnot used,butinsteada physicalMXV SS L2 GND (3) clock-insourceissupplied,MXV SS shouldstillbe connectedtoground. CrystalinputforM24 oscillator(24MHz forUSB). Ifa crystalinputisnot used,but M24XI F18 I DV DD18 insteada physicalclock-insourceissupplied,thisistheexternaloscillatorclock input.When theUSB peripheralisnot used,M24XI shouldbe leftas a No Connect. CrystaloutputforM24 oscillator.Ifa crystalinputisnot used,butinsteada physical M24XO F19 O DV DD18 clock-insourceissupplied,M24XO shouldbe leftas a No Connect.When theUSB peripheralisnot used,M24XO shouldbe leftas a No Connect. 1.8-Vpower supplyforM24 oscillator.Ifa crystalinputisnot used,butinsteada physicalclock-insourceissupplied,M24V DD shouldstillbe connectedtothe1.8-VM24V DD F16 S (3) power supply.When theUSB peripheralisnot used,M24V DD shouldbe connected tothe1.8-Vpower supply. Ground forM24 oscillator.Ifa crystalinputisnot used,butinsteada physical M24V SS F17 GND (3) clock-insourceissupplied,M24V SS shouldstillbe connectedtoground.When the USB peripheralisnot used,M24V SS shouldbe connectedtoground. PLLV DD18 M2 S (3) 1.8-Vpower supplyforPLLs (system). (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal (3) Formore information,see Section5.2,Recommended OperatingConditions. Table2-7.Clock GeneratorTerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. CLOCK GENERATOR Thispinismultiplexedbetween thePLL1 clockgeneratorand GPIO.CLK_OUT0/ K1 I/O/Z DV DD18 ForthePLL1 clockgenerator,itisclockoutputCLK_OUT0. ThisisconfigurableforGPIO48 13.5MHz or27 MHz clockoutputs. CLK_OUT1/ Thispinismultiplexedbetween theUSB clockgenerator,timer,and GPIO. TIM_IN/ E19 I/O/Z DV DD18 FortheUSB clockgenerator,itisclockoutputCLK_OUT1. Thisisconfigurablefor GPIO49 12 MHz or24 MHz clockoutputs. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-8.RESET and JTAG TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. RESET IPURESET L4 I Thisistheactivelowglobalresetinput.DV DD18 JTAG IPUTMS E6 I JTAG test-portmode selectinputDV DD18 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-8.RESET and JTAG TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. –TDO B5 O/Z JTAG test-portdataoutputDV DD18 IPUTDI A5 I JTAG test-portdatainputDV DD18 IPUTCK A6 I JTAG test-portclockinputDV DD18 –RTCK B6 O/Z JTAG test-portreturnclockoutputDV DD18 IPUEMU1 C6 I/O/Z Emulationpin1DV DD18 IPUEMU0 D6 I/O/Z Emulationpin0DV DD18 Table2-9.EMIFA TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EMIFA BOOT CONFIGURATION Thispinismultiplexedbetween EMIFA and theVPBE. Atreset,theinputstateis COUT2/ sampled tosettheEMIFA databus width(EM_WIDTH). Foran 8-bit-wideEMIFAIPDB5/ A17 I/O/Z databus,EM_WIDTH = 0.Fora 16-bit-wideEMIFA databus,EM_WIDTH = 1.DV DD18EM_WIDTH Afterreset,itisvideoencoderoutputCOUT2 orRGB666/888 Blueoutputdatabit5 B5. Thispinismultiplexedbetween DSP bootand theVPBE. Atreset,theinputstateis COUT3/ sampled tosettheDSP bootsourceDSP_BT. The DSP isbootedby theARM whenIPDB6/ B17 I/O/Z DSP_BT=0. The DSP bootsfromEMIFA when DSP_BT=1.DV DD18DSP_BT Afterreset,itisvideoencoderoutputCOUT3 orRGB666/888 Bluedatabit6 output B6. YOUT0/ IPDG5/ D15 I/O/Z DV DD18AEAW0 YOUT1/ IPDG6/ D16 I/O/Z DV DD18AEAW1 These pinsaremultiplexedbetween EMIFA and theVPBE. Atreset,theinputstates YOUT2/ ofAEAW[4:0] aresampled tosettheEMIFA addressbus width.See Section3.4.2,IPDG7/ D17 I/O/Z PeripheralSelectionatDeviceReset,fordetails.DV DD18AEAW2 Afterreset,thesearevideoencoderoutputsYOUT[0:4]orRGB666/888 Red and Green databitoutputsG5, G6, G7, R3, and R4.YOUT3/ IPDR3/ D18 I/O/Z DV DD18AEAW3 YOUT4/ IPDR4/ E15 I/O/Z DV DD18AEAW4 EMIFA FUNCTIONAL PINS: ASYNC /NOR Thispinismultiplexedbetween EMIFA and HPI. EM_CS2/ ForEMIFA, thispinisChipSelect2 outputEM_CS2 foruse withasynchronousC2 I/O/Z DV DD18HCS memories (i.e.,NOR flash)orNAND flash.Thisisthechipselectforthedefaultboot and ROM bootmodes. ForEMIFA, thispinisChipSelect3 outputEM_CS3 foruse withasynchronousEM_CS3 B1 I/O/Z DV DD18 memories (i.e.,NOR flash)orNAND flash. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-9.EMIFA TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EM_CS4/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ. GPIO9/ T2 I/O/Z DV DD18 ForEMIFA, itisChipSelect4 outputEM_CS4 foruse withasynchronousmemories VLYNQ_SCRUN (i.e.,NOR flash)orNAND flash. EM_CS5/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ. GPIO8/ T1 I/O/Z DV DD18 ForEMIFA, itisChipSelect5 outputEM_CS5 foruse withasynchronousmemories VLYNQ_CLOCK (i.e.,NOR flash)orNAND flash. EM_R/ W/ Thispinismultiplexedbetween EMIFA, ATA/CF, and HPI.INTRQ/ G3 I/O/Z DV DD18 ForEMIFA, itisread/writeoutputEM_R/ W.HR/W EM_WAIT/ (RDY/BSY)/ IPU Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.F1 I/O/ZIORDY/ DV DD18 ForEMIFA, itiswaitstateextensioninputEM_WAIT. HRDY EM_OE/ (RE)/ Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.(IORD)/ H4 I/O/Z DV DD18 ForEMIFA, itisoutputenableoutputEM_OE.DIOR/ HDS1 EM_WE (WE) Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.(IOWR)/ G2 I/O/Z DV DD18 ForNAND/SmartMedia/xD orEMIFA, itiswriteenableoutputEM_WE.DIOW/ HDS2 Thispinismultiplexedbetween EMIFA, ATA/CF, and HPI. ForEMIFA, thisistheBank Address0 output(EM_BA[0]).EM_BA[0]/ IPD When connectedtoan 8-bitasynchronousmemory, thispinisthelowestorderbitofDA0/ J3 I/O/Z DV DD18 thebyteaddress.HINT When connectedtoa 16-bitasynchronousmemory, thispinhas thesame function as EMIF addresspin22 (EM_A[22]). Thispinismultiplexedbetween EMIFA, ATA/CF, and GPIO. ForEMIFA, thisistheBank Address1 outputEM_BA[1].EM_BA[1]/ When connectedtoa 16 bitasynchronousmemory thispinisthelowestorderbitofDA1/ H2 I/O/Z DV DD18 the16-bitword address.GPIO52 When connectedtoan 8-bitasynchronousmemory, thispinisthe2nd bitofthe address. EM_A[21]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO10/ T3 I/O/Z DV DD18 ForEMIFA, itisaddressbit21 outputEM_A[21].VLYNQ_TXD0 EM_A[20]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO11/ R3 I/O/Z DV DD18 ForEMIFA, itisaddressbit20 outputEM_A[20].VLYNQ_RXD0 EM_A[19]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO12/ R4 I/O/Z DV DD18 ForEMIFA, itisaddressbit19 outputEM_A[19].VLYNQ_TXD1 EM_A[18]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO13/ P5 I/O/Z DV DD18 ForEMIFA, itisaddressbit18 outputEM_A[18].VLYNQ_RXD1 EM_A[17]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO14/ R2 I/O/Z DV DD18 ForEMIFA, itisaddressbit17 outputEM_A[17].VLYNQ_TXD2 EM_A[16]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO15/ R5 I/O/Z DV DD18 ForEMIFA, itisaddressbit16 outputEM_A[16].VLYNQ_RXD2 EM_A[15]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO16/ P3 I/O/Z DV DD18 ForEMIFA, itisaddressbit15 outputEM_A[15].VLYNQ_TXD3 EM_A[14]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO17/ P4 I/O/Z DV DD18 ForEMIFA, itisaddressbit14 outputEM_A[14].VLYNQ_RXD3

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-9.EMIFA TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EM_A[13]/ Thispinismultiplexedbetween EMIFA and GPIO.N4 I/O/Z DV DD18GPIO18 ForEMIFA, itisaddressbit13 outputEM_A[13]. EM_A[12]/ Thispinismultiplexedbetween EMIFA and GPIO.R1 I/O/Z DV DD18GPIO19 ForEMIFA, itisaddressbit12 outputEM_A[12]. EM_A[11]/ Thispinismultiplexedbetween EMIFA and GPIO.P2 I/O/Z DV DD18GPIO20 ForEMIFA, itisaddressbit11 outputEM_A[11]. EM_A[10]/ Thispinismultiplexedbetween EMIFA and GPIO.P1 I/O/Z DV DD18GPIO21 ForEMIFA, itisaddressbit10 outputEM_A[10]. EM_A[9]/ Thispinismultiplexedbetween EMIFA and GPIO.M4 I/O/Z DV DD18GPIO22 ForEMIFA, itisaddressbit9 outputEM_A[9]. EM_A[8]/ Thispinismultiplexedbetween EMIFA and GPIO.N3 I/O/Z DV DD18GPIO23 ForEMIFA, itisaddressbit8 outputEM_A[8]. EM_A[7]/ Thispinismultiplexedbetween EMIFA and GPIO.N2 I/O/Z DV DD18GPIO24 ForEMIFA, itisaddressbit7 outputEM_A[7]. EM_A[6]/ Thispinismultiplexedbetween EMIFA and GPIO.N1 I/O/Z DV DD18GPIO25 ForEMIFA, itisaddressbit6 outputEM_A[6]. EM_A[5]/ Thispinismultiplexedbetween EMIFA and GPIO.K3 I/O/Z DV DD18GPIO26 ForEMIFA, itisaddressbit5 outputEM_A[5]. EM_A[4]/ Thispinismultiplexedbetween EMIFA and GPIO.K4 I/O/Z DV DD18GPIO27 ForEMIFA, itisaddressbit4 outputEM_A[4]. EM_A[3]/ Thispinismultiplexedbetween EMIFA and GPIO.K2 I/O/Z DV DD18GPIO28 ForEMIFA, itisaddressbit3 outputEM_A[3]. EM_A[2]/ Thispinismultiplexedbetween EMIFA and HPI.(CLE)/ J1 I/O/Z DV DD18 ForEMIFA, thispinistheEM_A[2] addressline.HCNTL0 EM_A[1]/ (ALE)/ J2 I/O/Z DV DD18 Thispinismultiplexedbetween EMIFA (NAND/SmartMedia.xD)and HPI. HHWIL Thispinismultiplexedbetween EMIFA, ATA/CF, HPI,and GPIO. EM_A[0]/ ForEMIFA, thisisAddressoutputEM_A[0],whichistheleastsignificantbiton a DA2/ 32-bitword address.J4 I/O/Z DV DD18HCNTL1/ When connectedtoa 16-bitasynchronousmemory, thispinisthe2nd bitofthe GPIO53 address. Foran 8-bitasynchronousmemory, thispinisthe3rdbitoftheaddress. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-9.EMIFA TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EM_D0/ DD0/ E5 I/O/Z DV DD18 HD0 EM_D1/ DD1/ D3 I/O/Z DV DD18 HD1 EM_D2/ DD2/ F5 I/O/Z DV DD18 HD2 EM_D3/ DD3/ E3 I/O/Z DV DD18 HD3 EM_D4/ DD4/ E4 I/O/Z DV DD18 HD4 EM_D5/ DD5/ D2 I/O/Z DV DD18 HD5 EM_D6/ DD6/ F4 I/O/Z DV DD18 HD6 EM_D7/ DD7/ C1 I/O/Z DV DD18 These pinsaremultiplexedbetween EMIFA (NAND), ATA/CF, and HPI.InallcasesHD7 theyareused as a 16 bitbi-directionaldatabus. EM_D8/ ForEMIFA (NAND), theseareEM_D[15:0]. DD8/ F3 I/O/Z DV DD18 HD8 EM_D9/ DD9/ E2 I/O/Z DV DD18 HD9 EM_D10/ DD10/ G5 I/O/Z DV DD18 HD10 EM_D11/ DD11/ G4 I/O/Z DV DD18 HD11 EM_D12/ DD12/ D1 I/O/Z DV DD18 HD12 EM_D13/ DD13/ F2 I/O/Z DV DD18 HD13 EM_D14/ DD14/ H5 I/O/Z DV DD18 HD14 EM_D15/ DD15/ E1 I/O/Z DV DD18 HD15

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-9.EMIFA TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EMIFA FUNCTIONAL PINS: NAND /SMARTMEDIA /xD EM_A[1]/ Thispinismultiplexedbetween EMIFA and HPI.(ALE)/ J2 I/O/Z DV DD18 ForNAND/SmartMedia/xD,itisAddressLatchEnableoutput(ALE).HHWIL EM_A[2]/ Thispinismultiplexedbetween EMIFA and HPI.(CLE)/ J1 I/O/Z DV DD18 ForNAND/SmartMedia/xD,thispinistheCommand LatchEnableoutput(CLE).HCNTL0 EM_WAIT/ (RDY/BSY)/ IPU Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.F1 I/O/ZIORDY/ DV DD18 ForNAND/SmartMedia/xD,itisready/busyinput(RDY/BSY). HRDY EM_OE/ (RE )/ Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.(IORD )/ H4 I/O/Z DV DD18 ForNAND/SmartMedia/xD,itisreadenableoutput(RE).DIOR/ HDS1 EM_WE (WE) Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.(IOWR)/ G2 I/O/Z DV DD18 ForNAND/SmartMedia/xD,itiswriteenableoutput(WE).DIOW/ HDS2 Thispinismultiplexedbetween EMIFA and HPI. EM_CS2/ ForEMIFA, thispinisChipSelect2 outputEM_CS2 foruse withasynchronousC2 I/O/Z DV DD18HCS memories (i.e.NOR flash)orNAND flash.Thisisthechipselectforthedefaultboot and ROM bootmodes. ForEMIFA, thispinisChipSelect3 outputEM_CS3 foruse withasynchronousEM_CS3 B1 I/O/Z DV DD18 memories (i.e.NOR flash)orNAND flash. EM_CS4/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ. ForEMIFA, itisChip GPIO9/ T2 I/O/Z DV DD18 Select4 outputEM_CS4 foruse withasynchronousmemories (i.e.,NOR flash)or VLYNQ_SCRUN NAND flash. EM_CS5/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ. ForEMIFA, itisChip GPIO8/ T1 I/O/Z DV DD18 Select5 outputEM_CS5 foruse withasynchronousmemories (i.e.,NOR flash)or VLYNQ_CLOCK NAND flash. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-9.EMIFA TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EM_D0/ DD0/ E5 I/O/Z DV DD18 HD0 EM_D1/ DD1/ D3 I/O/Z DV DD18 HD1 EM_D2/ DD2/ F5 I/O/Z DV DD18 HD2 EM_D3/ DD3/ E3 I/O/Z DV DD18 HD3 EM_D4/ DD4/ E4 I/O/Z DV DD18 HD4 EM_D5/ DD5/ D2 I/O/Z DV DD18 HD5 EM_D6/ DD6/ F4 I/O/Z DV DD18 HD6 EM_D7/ DD7/ C1 I/O/Z DV DD18 These pinsaremultiplexedbetween EMIFA (NAND), ATA/CF, and HPI.InallcasesHD7 theyareused as a 16 bitbi-directionaldatabus. EM_D8/ ForEMIFA (NAND), theseareEM_D[15:0]. DD8/ F3 I/O/Z DV DD18 HD8 EM_D9/ DD9/ E2 I/O/Z DV DD18 HD9 EM_D10/ DD10/ G5 I/O/Z DV DD18 HD10 EM_D11/ DD11/ G4 I/O/Z DV DD18 HD11 EM_D12/ DD12/ D1 I/O/Z DV DD18 HD12 EM_D13/ DD13/ F2 I/O/Z DV DD18 HD13 EM_D14/ DD14/ H5 I/O/Z DV DD18 HD14 EM_D15/ DD15/ E1 I/O/Z DV DD18 HD15

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-10.DDR2 Memory ControllerTerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. DDR2 Memory Controller DDR_CLK0 W7 I/O/Z DV DDR2 DDR2 Clock DDR_CLK0 W8 I/O/Z DV DDR2 DDR2 Differentialclock DDR_CKE V8 I/O/Z DV DDR2 DDR2 ClockEnable DDR_CS T9 I/O/Z DV DDR2 DDR2 Activelowchipselect DDR_WE T8 I/O/Z DV DDR2 DDR2 ActivelowWriteenable DDR_DQM[3] T16 I/O/Z DV DDR2 DDR2 Data mask outputs DQM3: Forupperbytedatabus DDR_D[31:24]DDR_DQM[2] T14 I/O/Z DV DDR2 DQM2: ForDDR_D[23:16] DDR_DQM[1] T6 I/O/Z DV DDR2 DQM1: ForDDR_D[15:8] DQM0: ForlowerbyteDDR_D[7:0]DDR_DQM[0] T4 I/O/Z DV DDR2 DDR_RAS U7 I/O/Z DV DDR2 DDR2 Row Access Signaloutput DDR_CAS T7 I/O/Z DV DDR2 DDR2 Column Access Signaloutput DDR_DQS[0] U4 I/O/Z DV DDR2 Data strobeinput/outputsforeach byteofthe32-bitdatabus.They areoutputsto theDDR2 memory when writingand inputswhen reading.They areused toDDR_DQS[1] U6 I/O/Z DV DDR2 synchronizethedatatransfers. DDR_DQS[2] U14 I/O/Z DV DDR2 DQS3 :ForupperbyteDDR_D[31:24] DQS2: ForDDR_D[23:16] DQS1: ForDDR_D[15:8]DDR_DQS[3] U16 I/O/Z DV DDR2 DQS0: ForbottombyteDDR_D[7:0] DDR_BS[0] U8 DDR_BS[1] V9 I/O/Z DV DDR2 Bank selectoutputs(BS[2:0]).Two arerequiredtosupport1Gb DDR2 memories. DDR_BS[2] U9 DDR_A[12] W9 DDR_A[11] W10 DDR_A[10] U10 DDR_A[9] U11 DDR_A[8] V10 DDR_A[7] V11 DDR_A[6] W11 I/O/Z DV DDR2 DDR2 addressbus DDR_A[5] W12 DDR_A[4] V12 DDR_A[3] U12 DDR_A[2] V13 DDR_A[1] U13 DDR_A[0] W13 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal (3) Formore information,see Section5.2,Recommended OperatingConditions. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-10.DDR2 Memory ControllerTerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. DDR_D[31] U19 DDR_D[30] V19 DDR_D[29] W18 DDR_D[28] V18 DDR_D[27] W17 DDR_D[26] U18 DDR_D[25] U17 DDR_D[24] V17 DDR_D[23] T17 DDR_D[22] V16 DDR_D[21] W16 DDR_D[20] U15 DDR_D[19] V15 DDR_D[18] W15 DDR_D[17] V14 DDR_D[16] W14 I/O/Z DV DDR2 DDR2 databus can be configuredas 32 bitswideor16 bitswide. DDR_D[15] V7 DDR_D[14] W6 DDR_D[13] V6 DDR_D[12] W5 DDR_D[11] V5 DDR_D[10] U5 DDR_D[9] W4 DDR_D[8] V4 DDR_D[7] W3 DDR_D[6] V3 DDR_D[5] U3 DDR_D[4] W2 DDR_D[3] V2 DDR_D[2] V1 DDR_D[1] U2 DDR_D[0] U1 DDR_VREF T15 I (4) ReferencevoltageinputfortheSSTL_18 IO buffers. DDR_VSSDLL T11 GND (4) Ground fortheDDR2 DigitalLocked Loop. DDR_VDDDLL T10 S (4) Power (1.8Volts)fortheDDR2 DigitalLocked Loop. Impedance controlforDDR2 outputs.Thismust be connectedviaa 200 Ω resistorDDR_ZN T12 O/Z (4) toDV DDR2 . Impedance controlforDDR2 outputs.Thismust be connectedviaa 200 Ω resistorDDR_ZP T13 O/Z (4) toVSS . (4) Formore information,see Section5.2,Recommended OperatingConditions.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-11.I2C TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. I2C SCL/ Thispinismultiplexedbetween I2C and GPIO.C4 I/O/Z DV DD18GPIO43 ForI2C,itisclockoutputSCL. SDA/ Thispinismultiplexedbetween I2C and GPIO.B4 I/O/Z DV DD18GPIO44 ForI2C,itisbi-directionaldatasignalSDA. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-12.Audio SerialPort(ASP) TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. Audio SerialPort(ASP) CLKX/ Thispinismultiplexedbetween ASP and GPIO.B8 I/O/Z DV DD18GPIO29 ForASP, itisTransmitclockIO CLKX. CLKR/ Thispinismultiplexedbetween ASP and GPIO.A8 I/O/Z DV DD18GPIO30 ForASP, itisReceiveclockIO CLKR. FSX/ Thispinismultiplexedbetween ASP and GPIO.C8 I/O/Z DV DD18GPIO31 ForASP, itisTransmitframesynchronizationIO FSX. FSR/ Thispinismultiplexedbetween ASP and GPIO.C7 I/O/Z DV DD18GPIO32 ForASP, itisReceiveframesynchronizationIO FSR. DX/ Thispinismultiplexedbetween ASP and GPIO.B7 I/O/Z DV DD18GPIO33 ForASP, itisData TransmitoutputDX. DR/ Thispinismultiplexedbetween ASP and GPIO.A7 I/O/Z DV DD18GPIO34 ForASP, itisData ReceiveinputDR. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-13.SPI TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. SerialPeripheralInterface(SPI) SPI_EN0/ Thispinismultiplexedbetween SPI and GPIO.A4 I/O/Z DV DD18GPIO37 When used by SPI,itisSPI slavedevice0 enableoutputSPI_EN0. SPI_EN1/ Thispinismultiplexedbetween SPI,ATA, and GPIO.HDDIR/ B2 I/O/Z DV DD18 When used by SPI,itisSPI slavedevice1 enableoutputSPI_EN1.GPIO42 SPI_CLK/ Thispinismultiplexedbetween SPI and GPIO.A3 I/O/Z DV DD18GPIO39 ForSPI,itisclockoutputSPI_CLK. SPI_DI/ Thispinismultiplexedbetween SPI and GPIO.B3 I/O/Z DV DD18GPIO40 ForSPI,itisdatainputSPI_DI. SPI_DO/ Thispinismultiplexedbetween SPI and GPIO.A2 I/O/Z DV DD18GPIO41 ForSPI itisdataoutputSPI_DO. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-14.EMAC and MDIO TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. EMAC GPIOV33_0/ Thispinismultiplexedbetween GPIO and EthernetMAC.B13 I/O/Z DV DD33TXEN InEthernetMAC mode, itisTransmitEnableoutputTXEN. GPIOV33_1/ Thispinismultiplexedbetween GPIO and EthernetMAC.A13 I/O/Z DV DD33TXCLK InEthernetMAC mode, itisTransmitClockinputTXCLK. GPIOV33_2/ Thispinismultiplexedbetween GPIO and EthernetMAC.A12 I/O/Z DV DD33COL InEthernetMAC mode, itisCollisionDetectinputCOL. GPIOV33_6/ Thispinismultiplexedbetween GPIO and EthernetMAC.C12 I/O/Z DV DD33TXD3 InEthernetMAC mode, itisTransmitData 3 outputTXD3. GPIOV33_5/ Thispinismultiplexedbetween GPIO and EthernetMAC.A11 I/O/Z DV DD33TXD2 InEthernetMAC mode, itisTransmitData 2 outputTXD2. GPIOV33_4/ Thispinismultiplexedbetween GPIO and EthernetMAC.D12 I/O/Z DV DD33TXD1 InEthernetMAC mode, itisTransmitData 1 outputTXD1. GPIOV33_3/ Thispinismultiplexedbetween GPIO and EthernetMAC.B12 I/O/Z DV DD33TXD0 InEthernetMAC mode, itisTransmitData 0 outputTXD0. GPIOV33_11/ Thispinismultiplexedbetween GPIO and EthernetMAC.A10 I/O/Z DV DD33RXCLK InEthernetMAC mode, itisReceiveClockinputRXCLK. GPIOV33_12/ Thispinismultiplexedbetween GPIO and EthernetMAC.D11 I/O/Z DV DD33RXDV InEthernetMAC mode, itisReceiveData ValidinputRXDV. GPIOV33_13/ Thispinismultiplexedbetween GPIO and EthernetMAC.D10 I/O/Z DV DD33RXER InEthernetMAC mode, itisReceiveErrorinputRXER. GPIOV33_14/ Thispinismultiplexedbetween GPIO and EthernetMAC.C10 I/O/Z DV DD33CRS InEthernetMAC mode, itisCarrierSense inputCRS. GPIOV33_10/ Thispinismultiplexedbetween GPIO and EthernetMAC.E11 I/O/Z DV DD33RXD3 InEthernetMAC mode, itisReceiveData 3 inputRXD3. GPIOV33_9/ Thispinismultiplexedbetween GPIO and EthernetMAC.B11 I/O/Z DV DD33RXD2 InEthernetMAC mode, itisReceiveData 2 inputRXD2. GPIOV33_8/ Thispinismultiplexedbetween GPIO and EthernetMAC.C11 I/O/Z DV DD33RXD1 InEthernetMAC mode, itisReceivedata1 inputRXD1. GPIOV33_7/ Thispinismultiplexedbetween GPIO and EthernetMAC.E12 I/O/Z DV DD33RXD0 InEthernetMAC mode, itisReceiveData 0 inputRXD0. MDIO GPIOV33_16/ Thispinismultiplexedbetween GPIO and EthernetMAC.B10 I/O/Z DV DD33MDCLK InEthernetMAC mode, itisManagement Data ClockoutputMDCLK. GPIOV33_15/ Thispinismultiplexedbetween GPIO and EthernetMAC.E10 I/O/Z DV DD33MDIO InEthernetMAC mode, itisManagement Data IO MDIO. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-15.GPIOV33 TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. GPIOV33 GPIOV33_16/ Thispinismultiplexedbetween GPIO and EthernetMAC.B10 I/O/Z DV DD33MDCLK InGPIO mode, itis3.3VGPIO GPIOV33_16. GPIOV33_15/ Thispinismultiplexedbetween GPIO and EthernetMAC.E10 I/O/Z DV DD33MDIO InGPIO mode, itis3.3VGPIO GPIOV33_15. GPIOV33_14/ Thispinismultiplexedbetween GPIO and EthernetMAC.C10 I/O/Z DV DD33CRS InGPIO mode, itis3.3VGPIO GPIOV33_14. GPIOV33_13/ Thispinismultiplexedbetween GPIO and EthernetMAC.D10 I/O/Z DV DD33RXER InGPIO mode, itis3.3VGPIO GPIOV33_13. GPIOV33_12/ Thispinismultiplexedbetween GPIO and EthernetMAC.D11 I/O/Z DV DD33RXDV InGPIO mode, itis3.3VGPIO GPIOV33_12. GPIOV33_11/ Thispinismultiplexedbetween GPIO and EthernetMAC.A10 I/O/Z DV DD33RXCLK InGPIO mode, itis3.3VGPIO GPIOV33_11. GPIOV33_10/ Thispinismultiplexedbetween GPIO and EthernetMAC.E11 I/O/Z DV DD33RXD3 InGPIO mode, itis3.3VGPIO GPIOV33_10. GPIOV33_9/ Thispinismultiplexedbetween GPIO and EthernetMAC.B11 I/O/Z DV DD33RXD2 InGPIO mode, itis3.3VGPIO GPIOV33_9. GPIOV33_8/ Thispinismultiplexedbetween GPIO and EthernetMAC.C11 I/O/Z DV DD33RXD1 InGPIO mode, itis3.3VGPIO GPIOV33_8. GPIOV33_7/ Thispinismultiplexedbetween GPIO and EthernetMAC.E12 I/O/Z DV DD33RXD0 InGPIO mode, itis3.3VGPIO GPIOV33_7. GPIOV33_6/ Thispinismultiplexedbetween GPIO and EthernetMAC.C12 I/O/Z DV DD33TXD3 InGPIO mode, itis3.3VGPIO GPIOV33_6. GPIOV33_5/ Thispinismultiplexedbetween GPIO and EthernetMAC.A11 I/O/Z DV DD33TXD2 InGPIO mode, itis3.3VGPIO GPIOV33_5. GPIOV33_4/ Thispinismultiplexedbetween GPIO and EthernetMAC.D12 I/O/Z DV DD33TXD1 InGPIO mode, itis3.3VGPIO GPIOV33_4. GPIOV33_3/ Thispinismultiplexedbetween GPIO and EthernetMAC.B12 I/O/Z DV DD33TXD0 InGPIO mode, itis3.3VGPIO GPIOV33_3. GPIOV33_2/ Thispinismultiplexedbetween GPIO and EthernetMAC.A12 I/O/Z DV DD33COL InGPIO mode, itis3.3VGPIO GPIOV33_2. GPIOV33_1/ Thispinismultiplexedbetween GPIO and EthernetMAC.A13 I/O/Z DV DD33TXCLK InGPIO mode, itis3.3VGPIO GPIOV33_1. GPIOV33_0/ Thispinismultiplexedbetween GPIO and EthernetMAC.B13 I/O/Z DV DD33TXEN InGPIO mode, thispinis3.3VGPIO pinGPIOV33_0. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-16.StandaloneGPIOV18 TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. StandaloneGPIOV18 GPIO7 C3 I/O/Z DV DD18 Thispinisstandaloneand functionsas GPIO7. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 39 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-17.USB TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. USB 2.0 CrystalinputforM24 oscillator(24MHz forUSB). Ifa crystalinputisnot used,butinsteada physicalclock-insourceissupplied,thisM24XI F18 I DV DD18 istheexternaloscillatorclockinput. When theUSB peripheralisnot used,M24XI shouldbe leftas a No Connect. CrystaloutputforM24 oscillator. Ifa crystalinputis not used, but insteada physicalclock-insource issupplied,M24XO F19 O DV DD18 M24XO shouldbe leftas a No Connect. When theUSB peripheralisnot used,M24XO shouldbe leftas a No Connect. 1.8-Vpower supplyforM24 oscillator. Ifa crystalinputis not used, but insteada physicalclock-insource issupplied, M24V DD F16 S (3) M24V DD shouldstillbe connectedtothe1.8-Vpower supply. When theUSB peripheralisnot used,M24V DD shouldbe connectedtothe1.8-V power supply. Ground forM24 oscillator. Ifa crystalinputis not used, but insteada physicalclock-insource issupplied,M24V SS F17 GND (3) M24V SS shouldstillbe connectedtoground. When theUSB peripheralisnot used,M24V SS shouldbe connectedtoground. 5-V inputthatsignifiesthatVBUS isconnected. USB_VBUS J17 A I/O (3) When the USB peripheralis not used, the USB_VBUS signalshouldbe either pulleddown orpulledup viaa 10-kΩ resistor. USB operatingmode identificationpin.ForHostmode operation,pulldown thispin toground(VSS )viaan external1.5-kΩ resistor.ForDevicemode operation,pullup thispintoDV DD33 railviaan external1.5-kΩ resistor.USB_ID J16 A I/O When theUSB peripheralisnot used,theUSB_ID signalshouldbe eitherpulled down orpulledup viaa 10-kΩ resistor. USB_DP G19 A I/O USB bi-directionalData Differentialsignalpair[positive/negative]. When the USB peripheralis not used,the USB_DP signalshouldbe pulledhighUSB_DM H19 A I/O and theUSB_DM signalshouldbe pulleddown viaa 10-kΩ resistor. Referencecurrentoutput.Thismust be connectedviaa 10-kΩ ±1% resistorto USB_V SSREF . USB_R1 H18 A I/O (3) When theUSB peripheralisnot used,theUSB_R1 signalshouldbe connectedvia a 10-kΩ resistortoUSB_V SSREF . Ground forreferencecurrent.Thismust be connectedviaa 10-kΩ ±1% resistorto USB_R1. USB_V SSREF G16 GND (3) When theUSB peripheralisnot used,theUSB_V SSREF signalshouldbe connected toVSS . Analog3.3V power supplyforUSB phy. USB_V DDA3P3 J19 S (3) When the USB peripheralis not used, the USB_V DDA3P3 signalshould be connectedtoDV DD33 . AnaloggroundforUSB phy.When theUSB peripheralisnot used,theUSB_V SSA3P3 J18 GND (3) USB_V SSA3P3 signalshouldbe connectedtoVSS . 1.8-VI/Opower supplyforUSB phy. USB_V DD1P8 H17 S (3) When theUSB peripheralisnot used,theUSB_V DD1P8 signalshouldbe connected toDV DD18 . I/OGround forUSB phy. USB_V SS1P8 H16 GND (3) When theUSB peripheralisnot used,theUSB_V SS1P8 signalshouldbe connected toVSS . (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal (3) Formore information,see Section5.2,Recommended OperatingConditions.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-17.USB TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. Core Power supplyLDO outputforUSB phy.Thismust be connectedviaa 1-mF capacitortoVSS . USB_V DDA1P2LDO G18 S (3) When theUSB peripheralisnot used,theUSB_V DDA1P2LDO signalshouldstillbe connectedviaa 1-mF capacitortoVSS . Core Ground forUSB phy.ThisisthegroundfortheLDO and must be connectedto VSS . USB_V SSA1P2LDO G17 GND (3) When the USB peripheralis not used,the USB_V SSA1P2LDO signalshouldstillbe connectedtoVSS . Table2-18.VLYNQ TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. VLYNQ EM_CS5/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO8/ T1 I/O/Z DV DD18 ForVLYNQ, itistheclock(VLYNQ_CLOCK).VLYNQ_CLOCK EM_CS4/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO9/ T2 I/O/Z DV DD18 ForVLYNQ, itistheSerialClockrunrequest(VLYNQ_SCRUN).VLYNQ_SCRUN EM_A[15]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO16/ P3 I/O/Z DV DD18 ForVLYNQ, itistransmitbus bit3 outputVLYNQ_TXD3.VLYNQ_TXD3 EM_A[17]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO14/ R2 I/O/Z DV DD18 ForVLYNQ, itistransmitbus bit2 outputVLYNQ_TXD2.VLYNQ_TXD2 EM_A[19]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO12/ R4 I/O/Z DV DD18 ForVLYNQ, itistransmitbus bit1 outputVLYNQ_TXD1.VLYNQ_TXD1 EM_A[21]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO10/ T3 I/O/Z DV DD18 ForVLYNQ, itisbit0 ofthetransmitbus (VLYNQ_TXD0).VLYNQ_TXD0 EM_A[14]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO17/ P4 I/O/Z DV DD18 ForVLYNQ, itisreceivebus bit3 inputVLYNQ_RXD3.VLYNQ_RXD3 EM_A[16]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO15/ R5 I/O/Z DV DD18 ForVLYNQ, itisreceivebus bit2 inputVLYNQ_RXD2.VLYNQ_RXD2 EM_A[18]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO13/ P5 I/O/Z DV DD18 ForVLYNQ, itisreceivebus bit1 inputVLYNQ_RXD1.VLYNQ_RXD1 EM_A[20]/ Thispinismultiplexedbetween EMIFA, GPIO, and VLYNQ.GPIO11/ R3 I/O/Z DV DD18 ForVLYNQ, itisreceivebus bit0 inputVLYNQ_RXD0.VLYNQ_RXD0 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 41 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-19.VPFE TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. VIDEO/IMAGE IN (VPFE) – Pixelclockinputused toloadimage dataintotheCCD Controller(CCDC) on pinsPCLK M19 I DV DD18 CI[7:0]and YI[7:0]. – Verticalsynchronizationsignalthatcan be eitheran input(slavemode) oran outputVD L19 I/O/Z DV DD18 (mastermode),whichsignalsthestartofa new frametotheCCDC. – Horizontalsynchronizationsignalthatcan be eitheran input(slavemode) oranHD M18 I/O/Z DV DD18 output(mastermode),whichsignalsthestartofa new linetotheCCDC. Thispinismultiplexedbetween theCCDC and UART2. When used by theCCDC as inputCI7,itsupportsseveralmodes.CI7/ IPD In16-bitCCD Analog-Front-End(AFE)mode, itisinputCCD15.CCD15/ N19 I/O/Z DV DD18 In16-bitYCbCr mode, itistimemultiplexedbetween CB7 and CR7 inputs.UART_RXD2 In8-bitYCbCr mode, itistimemultiplexedbetween Y7,CB7, and CR7 oftheupper 8-bitchannel. Thispinismultiplexedbetween theCCDC and UART2. When used by theCCDC as inputCI6,itsupportsseveralmodes. In16-bitCCDCI6/ IPD AFE mode, itisinputCCD14.CCD14/ N18 I/O/Z DV DD18 In16-bitYCbCr mode, itistimemultiplexedbetween CB6 and CR6 inputs.UART_TXD2 In8-bitYCbCr mode, itistimemultiplexedbetween Y6,CB6, and CR6 oftheupper 8-bitchannel. Thispinismultiplexedbetween theCCDC and UART2. When used by theCCDC as inputCI5,itsupportsseveralmodes.CI5/ IPD In16-bitCCD AFE mode, itisinputCCD13.CCD13/ N17 I/O/Z DV DD18 In16-bitYCbCr mode, itistimemultiplexedbetween CB5 and CR5 inputs.UART_CTS2 In8-bitYCbCr mode, itistimemultiplexedbetween Y5,CB5, and CR5 oftheupper 8-bitchannel. Thispinismultiplexedbetween theCCDC and UART2. When used by theCCDC as inputCI4,itsupportsseveralmodes.CI4/ IPD In16-bitCCD AFE mode, itisinputCCD12.CCD12/ N16 I/O/Z DV DD18 In16-bitYCbCr mode, itistimemultiplexedbetween CB4 and CR4 inputs.UART_RTS2 In8-bitYCbCr mode, itistimemultiplexedbetween Y4,CB4, and CR4 oftheupper 8-bitchannel. ThispinisCCDC inputCI3 and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD11.CI3/ IPDN15 I In16-bitYCbCr mode, itistimemultiplexedbetween CB3 and CR3 inputs.CCD11 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y3,CB3, and CR3 oftheupper 8-bitchannel. ThispinisCCDC inputCI2 and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD10.CI2/ IPDM17 I In16-bitYCbCr mode, itistimemultiplexedbetween CB2 and CR2 inputs.CCD10 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y2,CB2, and CR2 oftheupper 8-bitchannel. ThispinisCCDC inputCI1 and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD9.CI1/ IPDM16 I In16-bitYCbCr mode, itistimemultiplexedbetween CB1 and CR1 inputs.CCD9 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y1,CB1, and CR1 oftheupper 8-bitchannel. ThispinisCCDC inputCI0 and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD8.CI0/ IPDM15 I In16-bitYCbCr mode, itistimemultiplexedbetween CB0 and CR0 inputs.CCD8 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y0,CB0, and CR0 oftheupper 8-bitchannel. ThispinisCCDC inputYI7and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD7.YI7/ IPDL18 I In16-bitYCbCr mode, itisinputY7.CCD7 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y7,CB7, and CR7 ofthelower 8-bitchannel. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-19.VPFE TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. ThispinisCCDC inputYI6and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD6.YI6/ IPDL17 I In16-bitYCbCr mode, itisinputY6.CCD6 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y6,CB6, and CR6 ofthelower 8-bitchannel. ThispinisCCDC inputYI5and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD5.YI5/ IPDL16 I In16-bitYCbCr mode, itisinputY5.CCD5 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y5,CB5, and CR5 ofthelower 8-bitchannel. ThispinisCCDC inputYI4and itsupportsseveralmodes. In16-bitCCD Analog-Front-End(AFE)mode, itisinputCCD4.YI4/ IPDL15 I In16-bitYCbCr mode, itisinputY4.CCD4 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y4,CB4, and CR4 ofthelower 8-bitchannel. ThispinisCCDC inputYI3and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD3.YI3/ IPDK19 I In16-bitYCbCr mode, itisinputY3.CCD3 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y3,CB3, and CR3 ofthelower 8-bitchannel. ThispinisCCDC inputYI2and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD2.YI2/ IPDK18 I In16-bitYCbCr mode, itisinputY2.CCD2 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y2,CB2, and CR2 ofthelower 8-bitchannel. ThispinisCCDC inputYI1and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD1.YI1/ IPDK17 I In16-bitYCbCr mode, itisinputY1.CCD1 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y1,CB1, and CR1 ofthelower 8-bitchannel. ThispinisCCDC inputYI0and itsupportsseveralmodes. In16-bitCCD AFE mode, itisinputCCD0.YI0/ IPDK16 I In16-bitYCbCr mode, itisinputY0.CCD0 DV DD18 In8-bitYCbCr mode, itistimemultiplexedbetween Y0,CB0, and CR0 ofthelower 8-bitchannel. GPIO1/ Thispinismultiplexedbetween GPIO and theVPFE.E13 I/O/Z DV DD18C_WE InVPFE mode, itistheCCD ControllerwriteenableinputC_WE. GPIO4/ Thispinismultiplexedbetween GPIO, theVPFE, and theVPBE.R0/ B14 I/O/Z DV DD18 InVPFE mode, itisCCDC fieldidentificationbidirectionalsignalC_FIELD.C_FIELD Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 43 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-20.VPBE TerminalFunctions SIGNAL OTHER (2) TYPE (1) DESCRIPTION(3) NAME NO. VIDEO OUT (VPBE) IPDHSYNC C17 I/O/Z VPBE HorizontalSync signalthatcan be eitheran inputoran output.DV DD18 IPDVSYNC C18 I/O/Z VPBE VerticalSync signalthatcan be eitheran inputoran output.DV DD18 VCLK D19 I/O/Z DV DD18 VPBE ClockOutput IPDVPBECLK C19 I/O/Z VPBE ClockInputDV DD18 COUT0/ Thispinismultiplexedbetween ARM bootmode and theVPBE.IPDB3/ A16 I/O/Z Afterreset,thispiniseithervideoencoderoutputsCOUT0, orDV DD18BTSEL0 RGB666/888 Blueoutputdatabits3,B3. COUT1/ Thispinismultiplexedbetween ARM bootmode and theVPBE.IPDB4/ B16 I/O/Z Afterreset,thispiniseithervideoencoderoutputsCOUT1, orDV DD18BTSEL1 RGB666/888 Blueoutputdatabits4,B4. COUT2/ Thispinismultiplexedbetween EMIFA and theVPBE.IPDB5/ A17 I/O/Z Afterreset,itisvideoencoderoutputCOUT2 orRGB666/888 BlueoutputDV DD18EM_WIDTH databit5 B5. COUT3/ Thispinismultiplexedbetween DSP bootand theVPBE.IPDB6/ B17 I/O/Z Afterreset,itisvideoencoderoutputCOUT3 orRGB666/888 BluedatabitDV DD18DSP_BT 6 outputB6. COUT4/ A18 O DV DD18 VideoencoderoutputCOUT4 orRGB666/888 Bluedatabit7 outputB7.B7 COUT5/ B18 O DV DD18 VideoencoderoutputCOUT5 orRGB666/888 Green databit2 outputG2.G2 COUT6/ B19 O DV DD18 VideoencoderoutputCOUT6 orRGB666/888 Green databit3 outputG3.G3 COUT7/ C16 O DV DD18 VideoencoderoutputCOUT7 orRGB666/888 Green databit4 outputG4.G4 YOUT0/ IPDG5/ D15 I/O/Z DV DD18AEAW0 YOUT1/ IPDG6/ D16 I/O/Z DV DD18AEAW1 YOUT2/ These pinsaremultiplexedbetween EMIFA and theVPBE.IPDG7/ D17 I/O/Z Afterreset,thesearevideoencoderoutputsYOUT[0:4]orRGB666/888DV DD18AEAW2 Red and Green databitoutputsG5, G6, G7, R3, and R4. YOUT3/ IPDR3/ D18 I/O/Z DV DD18AEAW3 YOUT4/ IPDR4/ E15 I/O/Z DV DD18AEAW4 YOUT5/ E16 O DV DD18 VideoencoderoutputYOUT5 orRGB666/888 Red databit5 outputR5.R5 YOUT6/ E17 O DV DD18 VideoencoderoutputYOUT6 orRGB666/888 Red databit6 outputR6.R6 YOUT7/ E18 O DV DD18 VideoencoderoutputYOUT7 orRGB666/888 Red databit7 outputR7.R7 GPIO0/ Thispinismultiplexedbetween GPIO and theVPBE.C13 I/O/Z DV DD18LCD_OE InVPBE mode, itistheLCD outputenableLCD_OE. GPIO2/ Thispinismultiplexedbetween GPIO and theVPBE.D13 I/O/Z DV DD18G0 InVPBE mode, itisRGB888 Green databit0 outputG0. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-20.VPBE TerminalFunctions(continued) SIGNAL OTHER (2) TYPE (1) DESCRIPTION(3) NAME NO. GPIO3/ Thispinismultiplexedbetween GPIO, and theVPBE. B0/ C14 I/O/Z DV DD18 InVPBE mode, itisRGB888 Bluedatabit0 outputB0 orLCD interlaced LCD_FIELD bidirectionalLCD_FIELD. GPIO4/ Thispinismultiplexedbetween GPIO, theVPFE, and theVPBE.R0/ B14 I/O/Z DV DD18 InVPBE mode, itisRGB888 Red databit0 outputR0.C_FIELD GPIO5/ Thispinismultiplexedbetween GPIO and theVPBE.E14 I/O/Z DV DD18G1 InVPBE mode, itisRGB888 Green databit1 outputG1. GPIO6/ Thispinismultiplexedbetween GPIO and theVPBE.A14 I/O/Z DV DD18B1 InVPBE mode, itisRGB888 Bluedatabit1 outputB1. GPIO38/ Thispinismultiplexedbetween VPBE and GPIO.D14 I/O/Z DV DD18R1 InVPBE mode, itisRGB888 Red outputdatabit1. PWM1/ Thispinismultiplexedbetween PWM1, VPBE, and GPIO.R2/ B15 I/O/Z DV DD18 InVPBE mode, itisRGB888 Red outputbit2 (R2).GPIO46 PWM2/ Thispinismultiplexedbetween PWM2, VPBE, and GPIO.B2/ A15 I/O/Z DV DD18 InVPBE mode, itisRGB888 Blueoutputbit2 (B2).GPIO47 Table2-21.DAC [PartofVPBE] TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. DAC[A:D] Referencevoltageinput(0.5V).When theDAC isnotused,theDAC_VREF signalDAC_VREF R17 A I (3) shouldbe connectedtoVSS . OutputofDAC A.When theDAC isnotused,theDAC_IOUT_A signalshouldbeDAC_IOUT_A P19 A O leftas a No Connect. OutputofDAC B.When theDAC isnotused,theDAC_IOUT_B signalshouldbeDAC_IOUT_B P18 A O leftas a No Connect. OutputofDAC C. When theDAC isnotused,theDAC_IOUT_C signalshouldbeDAC_IOUT_C R19 A O leftas a No Connect. OutputofDAC D. When theDAC isnotused,theDAC_IOUT_D signalshouldbeDAC_IOUT_D T19 A O leftas a No Connect. 1.8-VanalogI/Opower.When theDAC isnotused,theVDDA_1P8V signalshouldbeVDDA_1P8V R18 S (3) connectedtoVSS . AnalogI/Oground.When theDAC isnotused,theVSSA_1P8V signalshouldbeVSSA_1P8V P17 GND (3) connectedtoVSS . 1.20-Vanalogcoresupplyvoltage(A-513,-594,-810devices).When theDAC isVDDA_1P1V P16 S (3) notused,theVDDA_1P1V signalshouldbe connectedtoVSS . Analogcoreground.When theDAC isnotused,theVSSA_1P1V signalshouldbeVSSA_1P1V T18 GND (3) connectedtoVSS . Externalresistorconnectionforcurrentbiasconfiguration.Thispinmust be DAC_RBIAS R16 A I (3) connectedviaa 4-kΩ resistortoVSSA_1P8V .When theDAC isnotused,the DAC_RBIAS signalshouldbe connectedtoVSS . (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal (3) Formore information,see Section5.2,Recommended OperatingConditions. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 45 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-22.UART0, UART1, UART2 TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. UART2 CI7/ IPD Thispinismultiplexedbetween theCCDC and UART2.CCD15/ N19 I/O/Z DV DD18 When used by UART2 itisthereceivedatainputUART_RXD2.UART_RXD2 CI6/ IPD Thispinismultiplexedbetween theCCDC and UART2.CCD14/ N18 I/O/Z DV DD18 InUART2 mode, itisthetransmitdataoutputUART_TXD2.UART_TXD2 CI5/ IPD Thispinismultiplexedbetween theCCDC and UART2.CCD13/ N17 I/O/Z DV DD18 InUART2 mode, itisthecleartosend inputUART_CTS2.UART_CTS2 CI4/ IPD Thispinismultiplexedbetween theCCDC and UART2.CCD12/ N16 I/O/Z DV DD18 InUART2 mode, itisthereadytosend outputUART_RTS2.UART_RTS2 UART1 DMACK/ Thispinismultiplexedbetween ATA/CF and UART1.H3 I/O/Z DV DD18UART_TXD1 ForUART1, itistransmitdataoutputUART_TXD1. DMARQ/ IPD Thispinismultiplexedbetween ATA/CF and UART1.G1 I/O/ZUART_RXD1 DV DD18 ForUART1, itisreceivedatainputUART_RXD1. UART0 UART_RXD0/ Thispinismultiplexedbetween UART0 and GPIO.D5 I/O/Z DV DD18GPIO35 ForUART0, itisreceivedatainputUART_RXD0. UART_TXD0/ Thispinismultiplexedbetween UART0 and GPIO. .C5 I/O/Z DV DD18GPIO36 ForUART0, itistransmitdataoutputUART_TXD0. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-23.PWM0, PWM1, PWM2 TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. PWM2 PWM2/ Thispinismultiplexedbetween PWM2, VPBE, and GPIO.B2/ A15 I/O/Z DV DD18 ForPWM2, itisoutputPWM2.GPIO47 PWM1 PWM1/ Thispinismultiplexedbetween PWM1, VPBE, and GPIO.R2/ B15 I/O/Z DV DD18 ForPWM1, itisoutputPWM1.GPIO46 PWM0 PWM0/ Thispinismultiplexedbetween PWM0 and GPIO.C15 I/O/Z DV DD18GPIO45 ForPWM0, itisoutputPWM0. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-24.ATA/CF TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. ATA/CF SPI_EN1/ Thispinismultiplexedbetween SPI,ATA, and GPIO.HDDIR/ B2 I/O/Z DV DD18 ForATA, itisbufferdirectioncontroloutputHDDIR.GPIO42 GPIO50/ Thispinismultiplexedbetween GPIO and ATA/CF.J5 O DV DD18ATA_CS0 InATA mode, itisATA/CF chipselectoutputATA_CS0. GPIO51/ Thispinismultiplexedbetween GPIO and ATA/CF.H1 O DV DD18ATA_CS1 InATA mode, itisATA/CF chipselectoutputATA_CS1. EM_R/ W/ Thispinismultiplexedbetween EMIFA, ATA/CF, and HPI.INTRQ/ G3 I DV DD18 ForATA/CF, itisinterruptrequestinputINTRQ.H/W EM_WAIT/ (RDY/BSY)/ IPU Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.F1 IIORDY/ DV DD18 ForATA/CF, itisIO Ready inputIORDY. HRDY EM_OE/ (RE )/ Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI. (IORD )/ H4 O DV DD18 ForCF, itisreadstrobeoutput(IORD). DIOR/ ForATA, itisreadstrobeoutputDIOR. HDS1 EM_WE (WE) Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI. (IOWR)/ G2 O DV DD18 ForCF, itiswritestrobeoutput(IOWR). DIOW/ ForATA, itiswritestrobeoutputDIOW. HDS2 DMACK/ Thispinismultiplexedbetween ATA/CF and UART1.H3 O DV DD18UART_TXD1 ForATA/CF, itisDMA acknowledgeoutputDMACK. DMARQ/ IPD Thispinismultiplexedbetween ATA/CF and UART1.G1 OUART_RXD1 DV DD18 ForATA/CF, itisDMA requestDMARQ input. (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 47 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-24.ATA/CF TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EM_D15/ DD15/ E1 HD15 EM_D14/ DD14/ H5 HD14 EM_D13/ DD13/ F2 HD13 EM_D12/ DD12/ D1 HD12 EM_D11/ DD11/ G4 HD11 EM_D10/ DD10/ G5 HD10 EM_D9/ DD9/ E2 HD9 EM_D8/ DD8/ F3 These pinsaremultiplexedbetween EMIFA (NAND), ATA/CF, and HPI.InallcasesHD8 I/O/Z DV DD18 theyareused as a 16 bitbi-directionaldatabus. EM_D7/ ForATA/CF, theseareDD[15:0]. DD7/ C1 HD7 EM_D6/ DD6/ F4 HD6 EM_D5/ DD5/ D2 HD5 EM_D4/ DD4/ E4 HD4 EM_D3/ DD3/ E3 HD3 EM_D2/ DD2/ F5 HD2 EM_D1/ DD1/ D3 HD1 EM_D0/ DD0/ E5 HD0 EM_A[0]/ DA2/ Thispinismultiplexedbetween EMIFA, ATA/CF, HPI,and GPIO.J4 I/O/Z DV DD18HCNTL1/ ForATA/CF, itisDeviceaddressbit2 outputDA2. GPIO53 EM_BA[1]/ Thispinismultiplexedbetween EMIFA, ATA/CF, and GPIO.DA1/ H2 I/O/Z DV DD18 ForATA/CF, itisDeviceaddressbit1 outputDA1.GPIO52 EM_BA[0]/ Thispinismultiplexedbetween EMIFA, ATA/CF, HPI.DA0/ J3 I/O/Z DV DD18 ForATA/CF, itisDeviceaddressbit0 outputDA0.HINT

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-25.MMC/SD/SDIO TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. MMC/SD/SDIO SD_CLK A9 O DV DD33 Data clockoutputSD_CLK SD_CMD B9 I/O/Z DV DD33 Bi-directionalcommand IO SD_CMD SD_DATA3 C9 I/O/Z SD_DATA2 D9 I/O/Z DV DD33 These pinsarethenibble-widebi-directionaldatabus SD_DATA[3:0]. SD_DATA1 E9 I/O/Z SD_DATA0 D8 I/O/Z (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-26.HPI TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. Host-PortInterface(HPI) ForEMIFA, thispinisChipSelect3 output.EM_CS3 B1 I/O/Z DV DD18 InHPI mode thispinmust be pulledhighviaan external10-kΩ resistor. EM_BA[0]/ Thispinismultiplexedbetween EMIFA, ATA/CF, and HPI.DA0/ J3 I/O/Z DV DD18 InHPI mode, itisthehostinterruptoutputHINT.HINT EM_A[0]/ Thispinismultiplexedbetween EMIFA, ATA/CF, HPI,and GPIO. DA2/ ForHPI,itiscontrolinputHCNTL1. The stateofHCNTL1 and HCNTL0 determineJ4 I/O/Z DV DD18HCNTL1/ ifaddress,data,orcontrolinformationisbeingtransmittedbetween an external GPIO53 hostand DM644X. Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),and HPI.EM_A[2]/ InHPI mode, itiscontrolinputHCNTL0. The stateofHCNTL1 and HCNTL0(CLE)/ J1 I/O/Z DV DD18 determineifaddress,data,orcontrolinformationisbeingtransmittedbetween anHCNTL0 externalhostand DM644X. EM_A[1]/ Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),and HPI.(ALE)/ J2 I/O/Z DV DD18 InHPI mode, itisHalf-wordidentificationinputHHWIL.HHWIL EM_R/ W/ Thispinismultiplexedbetween EMIFA, ATA/CF, and HPI. INTRQ/ G3 I/O/Z DV DD18 ForHPI,itistheHostRead WriteinputHR/W. Thissignalisactivehighforreads HR/W and lowforwrites. EM_CS2/ Thispinismultiplexedbetween EMIFA and HPI.C2 I/O/Z DV DD18HCS InHPI mode, thispinisHPI ActiveLow ChipSelectinputHCS. EM_WE (WE) Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.(IOWR)/ G2 I/O/Z DV DD18 ForHPI,itisdatastrobe2 inputHDS2.DIOW/ HDS2 EM_OE/ (RE)/ Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.(IORD)/ H4 I/O/Z DV DD18 ForHPI,itisdatastrobe1 inputHDS1.DIOR/ HDS1 EM_WAIT/ (RDY/BSY)/ IPU Thispinismultiplexedbetween EMIFA (NAND/SmartMedia/xD),ATA/CF, and HPI.F1 I/O/ZIORDY/ DV DD18 ForHPI,itisreadyoutputHRDY. HRDY (1) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (2) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 49 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-26.HPI TerminalFunctions(continued) SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. EM_D15/ DD15/ E1 HD15 EM_D14/ DD14/ H5 HD14 EM_D13/ DD13/ F2 HD13 EM_D12/ DD12/ D1 HD12 EM_D11/ DD11/ G4 HD11 EM_D10/ DD10/ G5 HD10 EM_D9/ DD9/ E2 HD9 EM_D8/ DD8/ F3 These pinsaremultiplexedbetween EMIFA (NAND), ATA/CF, and HPI.HD8 I/O/Z DV DD18 InHPI mode, theseareHD[15:0]and aremultiplexedinternallywiththeHPI EM_D7/ addresslines. DD7/ C1 HD7 EM_D6/ DD6/ F4 HD6 EM_D5/ DD5/ D2 HD5 EM_D4/ DD4/ E4 HD4 EM_D3/ DD3/ E3 HD3 EM_D2/ DD2/ F5 HD2 EM_D1/ DD1/ D3 HD1 EM_D0/ DD0/ E5 HD0

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-27.Timer 0,Timer 1,and Timer 2 TerminalFunctions SIGNAL TYPE (1) OTHER (2) DESCRIPTION NAME NO. Timer 2 and Timer 1 No externalpins.The Timer2 and Timer1 peripheralpinsarenotpinnedoutas externalpins. Timer 0 CLK_OUT1/ Thispinismultiplexedbetween theUSB clockgenerator,timer,and GPIO.TIM_IN/ E19 I/O/Z DV DD18 ForTimer0,itisthetimereventcaptureinputTIM_IN.GPIO49 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal Table2-28.Reserved TerminalFunctions SIGNAL TYPE (1) OTHER (2)(3) DESCRIPTION NAME NO. RESERVED RSV1 A1 Reserved.(Leaveunconnected,do not connecttopower orground) RSV2 A19 Reserved.(Leaveunconnected,do not connecttopower orground) RSV3 W1 Reserved.(Leaveunconnected,do not connecttopower orground) RSV4 W19 Reserved.(Leaveunconnected,do not connecttopower orground) IPDRSV5 D4 I Reserved.Thispinmust be tieddirectlytoVSS fornormaldeviceoperation.VSS RSV6 L3 A O Reserved.(Leaveunconnected,do not connecttopower orground) RSV7 R8 A Reserved.(Leaveunconnected,do not connecttopower orground) RSV24 M3 S Reserved.(Leaveunconnected,do not connecttopower orground) (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal (2) IPD = Internalpulldown,IPU = Internalpullup.(Topullup a signaltotheoppositesupplyrail,a 1-kΩ resistorshouldbe used.) (3) SpecifiestheoperatingI/Osupplyvoltageforeach signal Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 51 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-29.Supply TerminalFunctions SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. SUPPLY VOLTAGE PINS F10 F11 3.3V I/OsupplyvoltageDV DD33 S (seeSection6.3.1.2,Power-SupplyDecoupling,ofthisdatamanual)F12 F13 G15 F14 J15 H14 K14 M14 L13 G9 1.8V I/OsupplyvoltageDV DD18 S (seeSection6.3.1.2,Power-SupplyDecoupling,ofthisdatamanual)F8 P10 1.8V DDR2 I/OsupplyvoltageDV DDR2 S (seeSection6.3.1.2,Power-SupplyDecoupling,ofthisdatamanual)N11 R11 P12 N13 R13 P14 R15 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-29.Supply TerminalFunctions(continued) SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. F15 K12 M12 L11 1.3V coresupplyvoltage(-810devices)M10 CV DD S 1.20V coresupplyvoltage(A-513,-594,-810devices) L10 (seeSection6.3.1.2,Power-SupplyDecoupling,ofthisdatamanual) K10 J13 H12 H11 J11 K11 1.3V coresupplyvoltage(-810devices) CV DDDSP J10 S 1.20V DSPSS supplyvoltage(A-513,-594,-810devices) (seeSection6.3.1.2,Power-SupplyDecoupling,ofthisdatamanual)H10 Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 53 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table2-30.Ground TerminalFunctions SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. GROUND PINS VSS M9 GND Ground pins G10 N10 R10 G11 M11 P11 G12 J12 N12 L12 R12 G13 H13 K13 M13 P13 G14 J14 (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table2-30.Ground TerminalFunctions(continued) SIGNAL TYPE (1) OTHER DESCRIPTION NAME NO. L14 N14 R14 VSS GND Ground pins H15 K15 P15 Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 55 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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2.8 Device Support

2.8.1 Development Support

TI offersan extensivelineofdevelopmenttoolsfortheTMS320DM644x SoC platform,includingtoolsto evaluatetheperformanceoftheprocessors,generatecode,developalgorithmimplementations,and fully integrateand debug softwareand hardwaremodules.The tool'ssupportdocumentationiselectronically availablewithintheCode Composer Studio™ IntegratedDevelopmentEnvironment(IDE). The followingproductssupportdevelopmentofTMS320DM644x SoC-based applications: SoftwareDevelopment Tools: Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCode Generation,and Debug plusadditionaldevelopmenttools Scalable,Real-TimeFoundationSoftware(DSP/BIOS™ ),which providesthe basicrun-timetarget softwareneeded tosupportany SoC application. Hardware Development Tools: ExtendedDevelopmentSystem (XDS ™ )Emulator For a completelistingof development-supporttoolsforthe TMS320DM644x SoC platform,visitthe Texas Instrumentsweb siteon the Worldwide Web at http://www.ti.comuniformresourcelocator (URL).For informationon pricingand availability,contactthenearestTIfieldsalesofficeorauthorized distributor.

2.8.2 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall DSP devicesand supporttools.Each DSP commercialfamilymember has one ofthreeprefixes:TMX, TMP, or TMS (e.g.,TMX320DM6446ZWT ).Texas Instrumentsrecommends two ofthreepossibleprefix designatorsforitssupporttools:TMDX and TMDS. These prefixesrepresentevolutionarystages of product development from engineeringprototypes(TMX/TMDX) through fullyqualifiedproduction devices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies.

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DM644x DMSoC: DM6443 DM6446 PREFIX DEVICE SPEED RANGE TMS 320 DM6446 ZWT ( ) TMX = Experimental device TMS = Qualified device DEVICE FAMILY 320 = TMS320 ™ DSP family PACKAGE TYPE(A) ZWT = 361-pin plastic BGA, with Pb-free soldered balls DEVICE(B) TEMPERATURE RANGE (DEFAULT: 0 C TO 85 C)° ° ( ) Blank = 0 C to 85 C, commercial temperature° ° A = -40 C to 105 C, extended temperature° ° Blank = 594-MHz DSP, 297-MHZ ARM9, commercial temperature Blank = 513-MHz DSP, 256.5-MHZ ARM9, extended temperature A. BGA = Ball Grid Array B. For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com). ( ) SILICON REVISION Blank = Silicon 1.3 A = Silicon 2.1 8 = 810-MHz DSP, 405-MHZ ARM9, commercial temperature B = Silicon 2.3 TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Predictionsshow thatprototypedevices(TMX or TMP) have a greaterfailureratethan the standard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production systembecause theirexpectedend-usefailureratestillisundefined.Onlyqualifiedproductiondevicesare tobe used. TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type (forexample, ZWT), the temperaturerange (forexample, "Blank"is the commercial temperaturerange),and the devicespeed range in megahertz (forexample, "Blank"is the default [594-MHz DSP, 297-MHz ARM9]). Figure2-6providesa legendforreadingthecompletedevicename forany TMS320DM644x SoC platform member. Figure2-6.Device Nomenclature Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 57 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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2.8.3 Documentation Support

2.8.3.1 RelatedDocumentation From Texas Instruments

The followingdocuments describetheTMS320DM644x DigitalMedia System-on-Chip(DMSoC). Copies of thesedocuments are availableon the Internetat www.ti.com.Tip:Enterthe literaturenumber inthe searchbox providedatwww.ti.com. The currentdocumentationthatdescribestheDM644x DMSoC, relatedperipherals,and othertechnical collateral,isavailableintheC6000 DSP productfolderat:www.ti.com/c6000. SPRU395 TMS320C64x Technical Overview. Providesan introductionto the TMS320C64x digital signalprocessors(DSPs) oftheTMS320C6000 DSP family. SPRU732 TMS320C64x/C64x+ DSP CPU and InstructionSet Reference Guide.DescribestheCPU architecture,pipeline,instructionset,and interruptsfortheTMS320C64x and TMS320C64x+ digitalsignalprocessors(DSPs) of the TMS320C6000 DSP family.The C64x/C64x+ DSP generationcomprisesfixed-pointdevicesintheC6000 DSP platform.The C64x+ DSP isan enhancement oftheC64x DSP withadded functionalityand an expanded instructionset. SPRU871 TMS320C64x+ DSP Megamodule Reference Guide. Describesthe TMS320C64x+ digital signalprocessor(DSP) megamodule. Includedisa discussionon theinternaldirectmemory access (IDMA) controller,the interruptcontroller,the power-down controller,memory protection,bandwidthmanagement, and thememory and cache. SPRUE14 TMS320DM644x DMSoC ARM Subsystem Reference Guide. Describes the ARM subsystem in the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The ARM subsystem isdesignedto givethe ARM926EJ-S (ARM9) master controlof the device.In general,the ARM isresponsibleforconfigurationand controlof the device;includingthe DSP subsystem,the videoprocessingsubsystem,and a majorityof the peripheralsand externalmemories. SPRUE15 TMS320DM644x DMSoC DSP Subsystem Reference Guide. Describesthe digitalsignal processor(DSP) subsystemintheTMS320DM644x DigitalMedia System-on-Chip(DMSoC). SPRUE19 TMS320DM644x DMSoC PeripheralsOverview Reference Guide. Providesan overview and brieflydescribesthe peripheralsavailableon the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). SPRUE20 TMS320DM644x DMSoC Asynchronous ExternalMemory Interface(EMIF) Reference Guide. Describes the asynchronous external memory interface(EMIF) in the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The EMIF supportsa glueless interfacetoa varietyofexternaldevices. SPRUE21 TMS320DM644x DMSoC ATA ControllerUser's Guide. Describesthe ATA controllerin theTMS320DM644x DigitalMedia System-on-Chip(DMSoC). The ATA controllerprovidesa gluelessinterfacetostoragemedia tobe used by videoand audioapplicationsforvideoand audiodatastorage. SPRUE22 TMS320DM644x DMSoC DDR2 Memory ControllerUser's Guide. Describesthe DDR2 memory controllerin the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The DDR2 memory controllerisused to interfacewithJESD79D-2A standardcompliantDDR2 SDRAM devices. SPRUE23 TMS320DM644x DMSoC Enhanced DirectMemory Access (EDMA3) ControllerUser's Guide. Describestheoperationoftheenhanced directmemory access (EDMA3) controller in the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The EDMA3 controller’s primarypurposeistoserviceuser-programmeddatatransfersbetween two memory-mapped slaveendpointson theDMSoC.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 SPRUE24 TMS320DM644x DMSoC EthernetMedia Access Controller(EMAC)/Management Data Input/Output(MDIO) Module User's Guide. Discusses the ethernetmedia access controller(EMAC) and physicallayer(PHY) devicemanagement data input/output(MDIO) module intheTMS320DM644x DigitalMedia System-on-Chip(DMSoC). The EMAC controls the flowof packetdata from the DMSoC to the PHY. The MDIO module controlsPHY configurationand statusmonitoring. SPRUE25 TMS320DM644x DMSoC General-PurposeInput/Output(GPIO) User'sGuide.Describes the general-purposeinput/output(GPIO) peripheralin the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The GPIO peripheralprovidesdedicatedgeneral-purposepins thatcan be configuredas eitherinputsor outputs.When configuredas an input,you can detectthestateoftheinputby readingthestateofan internalregister.When configuredas an output,you can writetoan internalregistertocontrolthestatedrivenon theoutputpin. SPRUE26 TMS320DM644x DMSoC 64-BitTimer User's Guide. Describesthe operationof the software-programmable64-bittimerinthe TMS320DM644x DigitalMedia System-on-Chip (DMSoC). Timer 0 and Timer 1 are used as general-purpose(GP) timersand can be programmed in 64-bitmode, dual 32-bitunchainedmode, or dual 32-bitchainedmode; Timer 2 isused onlyas a watchdog timer.The GP timermodes can be used togenerate periodicinterruptsor enhanced directmemory access (EDMA) synchronizationevents.The watchdog timermode isused toprovidea recoverymechanism forthedeviceintheeventof a faultcondition,such as a non-exitingcode loop. SPRUE29 TMS320DM644x DMSoC Audio SerialPort (ASP) User'sGuide. Describestheoperation of the audio serialport (ASP) audio interfacein the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The primaryaudiomodes thataresupportedby theASP arethe AC97 and IISmodes. In additionto the primaryaudiomodes, the ASP supportsgeneral serialportreceiveand transmitoperation,but isnot intendedto be used as a high-speed interface. SPRUE35 TMS320DM644x DMSoC UniversalSerialBus (USB) ControllerUser'sGuide.Describes the universalserialbus (USB) controllerin the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). The USB controllersupportsdata throughputratesup to 480 Mbps. Itprovidesa mechanism fordata transferbetween USB devicesand alsosupports hostnegotiation. SPRUE37 TMS320DM644x DMSoC Video Processing Back End (VPBE) User'sGuide. Describes thevideoprocessingback end (VPBE) intheTMS320DM644x DigitalMedia System-on-Chip (DMSoC) video processingsubsystem. Includedin the VPBE is the video encoder, on-screendisplay,and digitalLCD controller. SPRUE97 TMS320DM644x DMSoC Host Port Interface(HPI)User'sGuide. Describesthefeatures and operationof the host port interface(HPI) in the TMS320DM644x DigitalMedia System-on-Chip(DMSoC). SPRA839 Using IBIS Models forTiming Analysis.Describeshow to properlyuse IBISmodels to attainaccuratetiminganalysisfora givensystem. SPRAA84 TMS320C64x to TMS320C64x+ CPU MigrationGuide.DescribesmigratingfromtheTexas InstrumentsTMS320C64x digitalsignalprocessor(DSP) to the TMS320C64x+ DSP. The objectiveofthisdocument istoindicatedifferencesbetween thetwo cores.Functionalityin thedevicesthatisidenticalisnotincluded. SPRAAA6 EDMA v3.0(EDMA3) MigrationGuide forTMS320DM644x DMSoC. Describesmigrating from the Texas InstrumentsTMS320C64x digitalsignalprocessor(DSP) enhanced direct memory access (EDMA2) to the TMS320DM644x DigitalMedia System-on-Chip(DMSoC) EDMA3. This document summarizes the key differencesbetween the EDMA3 and the EDMA2 and providesguidanceformigratingfromEDMA2 toEDMA3. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOverview 59 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com SPRAAC5 Implementing DDR2 PCB Layout on the TMS320DM644x DSP. Containsimplementation instructionsfor the DDR2 interfacecontainedon the TMS320DM644x digitalsignal processor(DSP) device. SPRAAD6 TMS320DM6446/3 Power Consumption Summary. This document discussesthe power consumptionoftheTexas InstrumentsTMS320DM6446 and TMS320DM6443 digitalmedia System-on-Chip(DMSoC).

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3 Device Configurations

3.1 System Module Registers

The system module includesstatusand controlregistersrequiredforconfigurationof the device.Brief descriptionsofthevariousregistersareshown inTable3-1.System Module registersrequiredfordevice configurationsarediscussedinthefollowingsections. Table3-1.System Module RegisterMemory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C4 0000 PINMUX0 Pinmultiplexingcontrol0.Fordetails,see Section3.5.4,PINMUX0 Register Description. 0x01C4 0004 PINMUX1 Pinmultiplexingcontrol1.Fordetails,see Section3.5.5,PINMUX1 Register Description. 0x01C4 0008 DSPBOOTADDR BootaddressofDSP. Fordetails,see Section3.3.1.2,DSPBOOTADDR RegisterDescription. 0x01C4 000C SUSPSRC EmulatorSuspend Source.Fordetails,see Section3.6,EmulationControl. 0x01C4 0010 INTGEN ARM/DSP InterruptStatusand Control.Fordetails,see Section6.7.3, ARM/DSP CommunicationsInterrupts. 0x01C4 0014 BOOTCFG Devicebootconfiguration.Fordetails,see Section3.3.1.1,BOOTCFG RegisterDescription. 0x01C4 0018 -0x01C4 0027 – Reserved. 0x01C4 0028 JTAGID JTAGID/DeviceID number.Fordetails,see Section6.25.1,JTAG Peripheral RegisterDescription(s)– JTAG ID Register. 0x01C4 002C – Reserved. 0x01C4 0030 HPI_CTL HPI control.Fordetails,see Section3.5.6.10,HPI and EMIFA/ATA Pin Multiplexing. 0x01C4 0034 USBPHY_CTL USB PHY control.Fordetails,see Section6.15.1,USBPHY_CTL Register Description. 0x01C4 0038 CHP_SHRTSW Chipshortingswitchcontrol.Fordetails,see Section3.2.1,Power ConfigurationsatReset. 0x01C4 003C MSTPRI0 Bus masterprioritycontrol0.Fordetails,see Section3.5.1,SwitchedCentral Resource(SCR) Bus Priorities. 0x01C4 0040 MSTPRI1 Bus masterprioritycontrol1.Fordetails,see Section3.5.1,SwitchedCentral Resource(SCR) Bus Priorities. 0x01C4 0044 VPSS_CLKCTL VPSS clockcontrol. 0x01C4 0048 VDD3P3V_PWDN VDD 3.3VI/Opowerdown control.Fordetails,see Section3.2.2,Power ConfigurationsafterReset. 0x01C4 004C DRRVTPER EnablesaccesstotheDDR2 VTP Register. 0x01C4 0050 -0x01C4 006F – Reserved. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 61 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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3.2 Power Considerations

Globaldevicepower domains are controlledby thePower and Sleep Controller,exceptas shown inthe followingsections.

3.2.1 Power ConfigurationsatReset

As describedin Section6.3.1.3, DM6446 Power and Clock Domains, the DM6446 has two power domains:Always On and DSP. There isa shortingswitchbetween thetwo power domains thatmust be opened when theDSP domain ispowered offand closedwhen theDSP domain ispowered on. The CHP_SHRTSW register,shown in Figure3-1, controlsthe shortingswitchbetween the device always-onand DSP power domains.Thisswitchshouldbe enabledafterpowering-uptheDSP domain. SettingtheDSPPWRON bitto'1’closes(enables)theswitchand enablestheDSP power domain.The defaultswitchvalue is determinedby the DSP_BT configurationinput.IfDSP selfboot is selected (DSP_BT=1), theDSP willbe powered-upand DSPPWRON willbe settoa valueof'1'.For ARM boot operation(DSP_BT=0), DSPPWRON willbe settothedisablevalueof'0'and must be setby theARM beforetheDSP domain power isturnedon. Note: Once the DSP power domain isenabled (powered up),itcannot be disabled(powered down). Dynamic power down oftheDSP isnot supportedon thisdevice. Figure3-1.CHP_SHRTSW Register 31 1 0 RESERVED DSPPWRON R-0000 0000 0000 0000 0000 0000 0000 000 R/W-L LEGEND: R = Read, W = Write,n = valueatreset,L = pinstatelatchedatresetrising Table3-2.CHP_SHRTSW RegisterDescription NAME DESCRIPTION DSPPWRON DSP power domain enable. 0 = Shortingswitchopen 1 = Shortingswitchclosed

3.2.2 Power ConfigurationsafterReset

The VDD3P3V_PWDN registercontrolspower tothe3.3V I/ObuffersforMMC/SD/SDIO and GPIOV33. The 3.3V I/Os are separatedintotwo groups forindependentcontrolas shown in Figure3-2 and describedinTable3-3.By default,thesepinsarealldisabledatreset. Figure3-2.VDD3P3V_PWDN Register 31 2 1 0 RESERVED IOPWDN1 IOPWDN0 R-0000 0000 0000 0000 0000 0000 0000 00 R/W-1 R/W-1 LEGEND: R = Read, W = Write,n = valueatreset Table3-3.VDD3P3V_PWDN RegisterDescription NAME DESCRIPTION IOPWDN0 GIOV33 I/OPowerdown controlsGIOV33[16:0]pins. 0 = I/Obufferspowered up 1 = I/Obufferspowered down IOPWDN1 MMC/SD/SDIO I/OPowerdown controlsSD_CLK, SD_CMD, SD_DATA[3:0] pins. 0 = I/Obufferspowered up 1 = I/Obufferspowered down

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3.3 Bootmode

The deviceisbooted throughmultiplemeans: pinstatescapturedat reset,primarybootloaderswithin internalROM or EMIFA, and secondaryuser bootloadersfrom peripheralsor externalmemories.Boot modes, pinconfigurations,and registerconfigurationsrequiredforbootingthedevice,aredescribedinthe followingsections.

3.3.1 Bootmode Registers

The BOOTCFG and DSPBOOTADDR registersaredescribedinthefollowingsections.Atreset,thestatus ofvariouspinsrequiredforproperbootarestoredwithintheseregisters.

3.3.1.1 BOOTCFG RegisterDescription

The BOOTCFG register(locatedat address0x01C4 0014) containsthe statusvaluesof the BTSEL1, BTSEL0, DSP_BT, EM_WIDTH, and AEAW[4:0] pinscapturedattherisingedge ofRESET. The register formatisshown inFigure3-3 and bitfielddescriptionsare shown inTable 3-4. The capturedbitsare softwarereadableafterreset. Figure3-3.BOOTCFG Register 31 9 8 7 6 5 4 0 RESERVED DSP_BT BTSEL EM_WIDTH DAEAW R-0000 0000 0000 0000 0000 000 R-L R-LL R-L R-LLLLL LEGEND: R = Read; W = Write;L = pinstatelatchedatresetrising;-n = valueafterreset Table3-4.BOOTCFG RegisterDescription NAME DESCRIPTION BTSEL ARM Bootmode selectionpinstates(BTSEL1, BTSEL0) capturedattherisingedge ofRESET. ‘00’indicatesARM bootsfromROM (NAND Flash/SPIFlash). ‘01’indicatesthatARM bootsfromEMIFA (NOR Flash). ‘10’indicatesthatARM bootsfromROM (HPI). ‘11’indicatesthatARM bootsfromROM (UART0). DSP_BT DSP Bootmode selectionpinstatecapturedattherisingedge ofRESET. ‘0’setsARM bootofC64x+. ‘1’setsC64x+ selfboot. EM_WIDTH EMIFA databus widthselectionpinstatecapturedattherisingedge ofRESET. ‘0’setsEMIFA to8 bitdatabus width ‘1’setsEMIFA to16 bitdatabus width. DAEAW EMIFA addressbus widthselectionpinstates(AEAW[4:0])capturedattherisingedge ofRESET. Thisconfigures EMIFA addresspinsmultiplexedwithGPIO. See theGPIO and EMIFA Multiplexingtables(Table3-9,Table3-10, and Table3-11). Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 63 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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3.3.1.2 DSPBOOTADDR RegisterDescription

The DSPBOOTADDR registercontainsthe upper 22 bitsof the C64x+ DSP resetvector.The register formatisshown in Figure3-4 and bitfielddescriptionsare shown in Table 3-5. DSPBOOTADDR is readableand writableby softwareafterreset. Figure3-4.DSPBOOTADDR Register 31 10 9 0 BOOTADDR[21:0] RESERVED R- 0100 0010 0010 0000 0000 00 R-00 0000 0000 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset Table3-5.DSPBOOTADDR RegisterDescription NAME DESCRIPTION BOOTADDR[21:0] Upper 22 bitsoftheC64x+ DSP bootaddress.

3.3.2 ARM Boot

The DM6446 ARM can bootfrom EMIFA, internalROM (NAND, SPI),UART0, or HPI,as determinedby thesettingoftheBTSEL[1:0]pins.The BTSEL[1:0]pinsarereadby theARM ROM Boot Loader(RBL) to furtherdefinetheROM bootmode. The ARM bootmodes aresummarized inTable3-6. Table3-6.ARM Boot Modes BTSEL1 BTSEL0 BOOT MODE ARM RESET BRIEF DESCRIPTION VECTOR 0 0 ARM NAND, SPI RBL 0x0000 4000 Up to14 K-bytessecondarybootloaderthroughNAND withup to2 K-bytespage sizes. 0 1 ARM EMIFA ExternalBoot 0x0200 0000 EMIFA EM_CS2 externalmemory space. 1 0 ARM HPI RBL 0x0000 4000 Up to14 K-btyessecondarybootloaderthroughan external host. 1 1 ARM UART RBL 0x0000 4000 Up to14 K-bytessecondarybootloaderthroughUART0. When theBTSEL[1:0]pinsaresettotheARM EMIFA ExternalBoot ("01"),theARM immediatelybegins executingcode from the EMIFA EM_CS2 memory space (0x0200 0000).When the BTSEL[1:0]pins indicatea conditionotherthantheARM EMIFA ExternalBoot(!01),theRBL beginsexecution. ARM NAND/SPI Bootmode has thefollowingfeatures:

• Loads a secondaryUser Boot Loader (UBL) from NAND/SPI flashto ARM InternalRAM (AIM)and transferscontroltotheusersoftware.
• SupportforNAND withpage sizesup to8192 bytes.
• Supportforerrorcorrectionwhen loadingUBL
• Supportforup to14KB UBL
• Optional,userselectable,supportforuse ofDMA, I-cache,and PLL enablewhileloadingUBL ARM UART Bootmode has thefollowingfeatures:
• Loads a secondaryUBL viaUART0 toAIM and transferscontroltotheusersoftware.
• Supportforup to14KB UBL ARM HPI BootMode has thefollowingfeatures:
• No supportfora fullfirmwareboot.Instead,waitsforexternalhosttoloada secondaryUBL viaHPI to AIM and transferscontroltotheusersoftware.
• Supportforup to14KB UBL. For furtherdetailson theROM Bootloader,see theTMS320DM644x DMSoC ARM Subsystem Reference Guide (literaturenumber SPRUE14 ).

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3.3.3 DSP Boot

For C64x+ booting,thestateoftheDSP_BT pinissampled atreset.IfDSP_BT islow,theARM willbe themasterofC64x+ and controlbooting(HostBoot mode). IfDSP_BT ishigh,theC64x+ willbootitself coming outofdevicereset(Self-Bootmode).Table3-7shows a summary oftheDSP bootmodes. Table3-7.DSP Boot Modes DSP_BT DSP ARM DSPBOOTADDR BRIEF DESCRIPTION BOOT MODE BOOT MODE REGISTER VALUE

0 HostBoot InternalBoot Programmable ARM setsan internalDSP memory locationinDSPBOOTADDR

registerwhere validDSP code residesand loadscode tothis internalDSP memory throughDMA priortoreleasingDSP reset.

0 HostBoot ExternalBoot Programmable ARM setsan externalDSP memory locationinDSPBOOTADDR

register(EMIFA orDDR2) where validDSP code residespriorto releasingDSP reset.

1 SelfBoot Any,exceptHPI 0x4220 0000 DefaultEMIFA Base Address

1 HostBoot HPI Programmable ARM setsa DSP memory locationintheDSPBOOTADDR

register.HPI loadscode intotheDM6446 memory map withthe entrypointsettothememory locationspecifiedinthe DSPBOOTADDR register.Once theHPI completesloadingthe code,theARM shouldreleasetheDSP fromreset.

3.3.3.1 Host-BootMode

Inhostbootmode, theARM isthemasterand controlstheresetand bootoftheC64x+. The C64x+ DSP remainspowered-offafterdevicereset.The ARM isresponsibleforenablingpower to the C64x+ and releasingitfromreset(PSC MMR bits:MDCTL[39].LRST and MRSTOUT1.MRSTz[39]). Priortoreleasing theC64x+ reset,theARM must program theaddressfrom which theC64x+ willbeginexecutioninthe DSPBOOTADDR register.

3.3.3.2 Self-BootMode

In self-bootmode, the C64x+ power domain isturnedon and the C64x+ DSP isreleasedfrom reset withoutARM intervention.The C64x+ beginsexecutionfrom the defaultEMIFA address(0x4220 0000) containedwithintheDSPBOOTADDR register.The C64x+ beginsexecutionwithinstruction(L1P)cache enabled. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 65 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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3.4 ConfigurationsatReset

The followingsectionsgiveinformationon configurationsettingsforthedeviceatreset.

3.4.1 Device ConfigurationatDevice Reset

Table 3-8 shows a summary of deviceinputsrequiredforbootingthe ARM and DSP, and configuring EMIFA dataand addressbus widthsforproperoperationofthedeviceattherisingedge oftheRESET input. Table3-8.Device Configurations(InputPins Sampled atReset) DEVICE SIGNALS DEVICE SIGNAL NAMESAMPLED DESCRIPTIONAFTER RESETAT RESET BTSEL[1:0] COUT[1:0] ARM Bootmode selectionpins. ‘00’indicatesARM bootsfromROM (NAND/SPI Flash). ‘01’indicatesthatARM bootsfromEMIFA (NOR Flash). ‘10’indicatesthattheARM bootsfromtheHPI (ROM) ‘11’indicatesthatARM bootsfromROM (UART0). DSP_BT COUT3 DSP Bootmode selectionpin. ‘0’setsARM bootofC64x+. ‘1’setsC64x+ selfboot. EM_WIDTH COUT2 EMIFA databus widthselectionpin. ‘0’setsEMIFA to8-bitdatabus width ‘1’setsEMIFA to16-bitdatabus width. AEAW[4:0] YOUT[4:0] EMIFA addressbus widthselectionpinsforEMIFA addresspinsmultiplexedwithGPIO. See theGPIO and EMIFA Multiplexingtables(Table3-9,Table3-10,and Table3-11)for details.

3.4.2 PeripheralSelectionatDevice Reset

As brieflymentioned in Table 3-8, the stateof the AEAW[4:0] pinscapturedat resetconfiguresthe number ofEMIFA addresspinsrequiredfordeviceboot.These valuesarestoredintheAEAW fieldofthe PINMUX0 register.At reset,thisprovidesproperaddressingforexternalboot.Unused addresspinsare availableforuse as GPIO. The registersettingsare softwareprogrammable afterreset.Table 3-9, Table 3-10, and Table 3-11 show the AEAW[4:0] bitsettingsand the correspondingmultiplexingfor EMIFA addressand GPIO pins. The number ofEMIFA addressbitsenabledisconfigurablefrom0 to23.EM_BA[1] and EM_A[21:0]pins thatare notassignedtoanotherperipheraland notenabledas addresssignalsbecome GPIO pins.The enabledaddresspinsarealwayscontiguousfromEM_BA[1] upwards and addressbitscannotbe skipped. The exceptiontothisare theEM_A[2:1]pins.EM_A[2:1]are usableas theALE and CLE signalsforthe NAND Flashmode ofEMIFA and arealwaysenabledas EMIFA pins.Ifan addresswidthof0 isselected, thisstillallowsa NAND Flashtobe accessed.Also,selectingan addresswidthof2,3,or4 (AEAW[4:0]= 00010, 00011, or 00100) always resultsin4 addressoutputs.For theseand otheraddressbitenable settings,see theGPIO and EMIFA Multiplexingtables(Table3-9,Table3-10,and Table3-11).

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table3-9.GPIO and EMIFA Multiplexing(Part1) Pin Mux RegisterAEAW[4:0] BitSettings 00000 00001 00010 00011 00100 00101 00110 00111 (default) GPIO[52] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] GPIO[53] GPIO[53] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[28] GPIO[28] GPIO[28] GPIO[28] GPIO[28] EM_A[3] EM_A[3] EM_A[3] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] GPIO[27] EM_A[4] EM_A[4] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] GPIO[26] EM_A[5] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[25] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[24] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[23] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[22] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[21] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 67 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table3-10.GPIO and EMIFA Multiplexing(Part2) Pin Mux RegisterAEAW[4:0] BitSettings 01000 01001 01010 01011 01100 01101 01110 01111 EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] GPIO[24] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] GPIO[23] GPIO[23] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] GPIO[22] GPIO[22] GPIO[22] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] GPIO[21] GPIO[21] GPIO[21] GPIO[21] EM_A[10] EM_A[10] EM_A[10] EM_A[10] GPIO[20] GPIO[20] GPIO[20] GPIO[20] GPIO[20] EM_A[11] EM_A[11] EM_A[11] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] GPIO[19] EM_A[12] EM_A[12] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] GPIO[18] EM_A[13] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[17] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[16] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10]

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table3-11.GPIO and EMIFA Multiplexing(Part3) Pin Mux RegisterAEAW[4:0] BitSettings 10000 10001 10010 10011 10100 10101 10110 Others EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] GPIO[16] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] EM_A[15] GPIO[15] GPIO[15] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] GPIO[14] GPIO[14] GPIO[14] EM_A[17] EM_A[17] EM_A[17] EM_A[17] EM_A[17] GPIO[13] GPIO[13] GPIO[13] GPIO[13] EM_A[18] EM_A[18] EM_A[18] EM_A[18] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] EM_A[19] EM_A[19] EM_A[19] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] EM_A[20] EM_A[20] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] EM_A[21] Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 69 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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3.5 ConfigurationsAfterReset

The followingsectionsgivethedetailson configuringthedeviceafterreset.

3.5.1 Switched CentralResource (SCR) Bus Priorities

Prioritizationwithintheswitchedcentralresource(SCR) isprogrammableforeach master.The registerbit fieldsand defaultprioritylevelsforDM6446 bus mastersare shown inTable 3-12. The prioritylevels shouldbe tunedtoobtainthebestsystem performancefora particularapplication.Lower valuesindicate higherpriority.For most masters,theirpriorityvaluesareprogrammed atthesystem levelby configuring theMSTPRI0 and MSTPRI1 registers.Detailson theMSTPRI0/1 registersare shown inFigure3-5 and Figure3-6.The C64x+, VPSS, and EDMA3 masterscontainregistersthatcontroltheirown priorityvalues. Table3-12.DM6446 DefaultBus Master Priorities BUS PRIORITY BIT FIELD MASTER DEFAULT PRIORITY LEVEL VPSSP VPSS 0 (VPSS PCR Register,DMA_PRI bitfield) [Formore detailedinformationon theDMA_PRI bitfield,see the TMS320DM644x DMSoC VideoProcessingBack End (VPBE) User'sGuide (literaturenumber SPRUE37 ).] EDMATC0P EDMATC0 0 (EDMA3CC QUEPRI Register) [Formore detailedinformationon theQUEPRI register,see the TMS320DM644x DMSoC Enhanced DirectMemory Access (EDMA3) ControllerUser'sGuide (literaturenumber SPRUE23 ).] EDMATC1P EDMATC1 0 (EDMA3CC QUEPRI Register) [Formore detailedinformationon theQUEPRI register,see the TMS320DM644x DMSoC Enhanced DirectMemory Access (EDMA3) ControllerUser'sGuide (literaturenumber SPRUE23 ).] ARM_DMAP ARM (DMA) 1 (MSTPRI0 Register) ARM_CFGP ARM (CFG) 1 (MSTPRI0 Register) C64X+_DMAP C64X+ 7 (C64x+ MDMAARBE.PRI Registerbitfield) (DMA) [Formore detailedinformationon thePRI bitfield,see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ).] C64X+_CFGP C64X+ 1 (MSTPRI0 Register) (CFG) EMACP EMAC 4 (MSTPRI1 Register) USBP USB 4 (MSTPRI1 Register) ATAP ATA/CF 4 (MSTPRI1 Register) VLYNQP VLYNQ 4 (MSTPRI1 Register) HPIP HPI 4 (MSTPRI1 Register) VICPP VICP 5 (MSTPRI0 Register) Figure3-5.MSTPRI0 Register 31 19 18 16 RESERVED VICPP (1) R-0000 0000 0000 0 R/W-101 15 11 10 8 7 6 4 3 2 0 RESERVED C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001 LEGEND: R = Read; W = Write;-n = valueafterreset (1) The VICPP bitfieldisconfiguredby thethird-partysoftware.When modifyingtheMSTPRI0 registera read/modify/writemust be performedtopreservetheconfigurationsetby thethird-partysoftware.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure3-6.MSTPRI1 Register 31 23 22 20 19 18 16 RESERVED HPIP RSV VLYNQP R-0000 0000 0 R/W-100 R-0 R/W-100 15 14 12 11 10 8 7 6 4 3 2 0 RSV ATAP RSV USBP RSV RESERVED RSV EMACP R-0 R/W-100 R-0 R/W-100 R-0 R-100 R-0 R/W-100 LEGEND: R = Read; W = Write;-n = valueafterreset

3.5.2 MultiplexedPin Configurations

There are numerous multiplexedpinsthatare sharedby more thanone peripheral.Some ofthesepins areconfiguredby externalpullup/pulldownresistorsonlyatreset,and othersareconfiguredby software. As describedin detailin Section3.4.1(Device Configurationat Device Reset) and Section3.4.2 (PeripheralSelectionat Device Reset),hardware configurablemultiplexedpins are programmed by externalpullup/pulldownresistorsat resetto set the initialfunctionalityof pins foruse by a single peripheral.Afterreset,softwareconfigurablemultiplexedpinsareprogrammablethroughMemory Mapped Registers(MMR) toallowtheswitchingofpinfunctionalitiesduringrun-time.See Section3.5.3,Peripheral SelectionAfterDeviceReset,formore detailson theregistersettings. A summary ofthepinmultiplexingisshown inTable3-13.The EMAC peripheralsharespinswiththe3.3V GPIO pins.The VLYNQ pinsoverlapupper EMIFA addresspinsresultingina reducedEMIFA address range as theVLYNQ widthisincreased.The ATA peripheralsharesdatalinesand some controlsignals withEMIFA. The ATA DMA pins are multiplexedwithUART1. The ASP, UART0/1/2, SPI, I2C, and PWM0/1/2 alldefaulttoGPIO pinswhen notenabled.The VPBE functionoftheVPSS requiresadditional pinstoimplementtheRGB888 mode, thesearemultiplexedwithGPIOs. Table3-13.DM6446 MultiplexedPeripheralPins and MultiplexingControls PRIMARY SECONDARY TERTIARYMULTIPLEXED SECONDARY (1) TERTIARY (2) (DEFAULT) REGISTER/PIN (3) REGISTER/PIN (3) PERIPHERALS FUNCTION FUNCTIONFUNCTION CONTROL CONTROL EMIFA (NAND), HPI EMIFA (NAND): HPI: PinMux0:HPIEN, EM_A[1] (ALE), HHWIL, HCNTL0, Pins:BTSEL[1:0]= 10 EM_A[2] (CLE), HCS EM_CS2, EM_CS3 EMIFA, HPI,ATA EMIFA: ATA (CF): HPI: PinMux0:ATAEN PinMux0:HPIEN, (CF) EM_D[0:15], DD[0:15],DA0 HD[0:15],HINT Pins:BTSEL[1:0]= 10 EM_BA[0] EMIFA (NAND), EMIFA (NAND): ATA (CF): HPI: PinMux0:ATAEN PinMux0:HPIEN, HPI,ATA (CF) R/W, EM_WAIT INTRQ, IORDY, HR/W, HRDY, HDS1, Pins:BTSEL[1:0]= 10 (RDY/BSY), DIOR(IORD) , HDS2 EM_OE (RE), DIOW (IOWR) EM_WE (WE) VPBE LCD, GPIO GPIO:GPIO[0] VPBE: LCD_OE PinMux0:LOEEN VPFE CCD, GPIO GPIO:GPIO[1] VPFE: C_WE PinMux0:CWE VPBE RGB888, GPIO:GPIO[2] VPBE: PinMux0:RGB888 GPIO RGB888 G0 VPBE GPIO:GPIO[3] VPBE: VPBE: PinMux0:RGB888 PinMux0:LFLDEN LCD/RGB888, GPIO RGB888 B0 LCD_FIELD VPFE CCD, VPBE GPIO:GPIO[4] VPBE: VPFE: PinMux0:RGB888 PinMux0:CFLDEN RGB888, GPIO RGB888 R0 CCD_FIELD (1) When theSecondaryfunctionisenabled,toavoidpotentialcontention,ensurethatthePrimary(ifnotGPIO) and Tertiaryfunctionsare disabled. (2) When theTertiaryfunctionisenabled,toavoidpotentialcontention,ensurethatthePrimary(ifnotGPIO),Secondary,and otherTertiary functionsaredisabled. (3) Pinstatesaresampled atpower on resetand writtenintotheregisterfields. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 71 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table3-13.DM6446 MultiplexedPeripheralPins and MultiplexingControls(continued) PRIMARY SECONDARY TERTIARYMULTIPLEXED SECONDARY (1) TERTIARY (2) (DEFAULT) REGISTER/PIN (3) REGISTER/PIN (3) PERIPHERALS FUNCTION FUNCTIONFUNCTION CONTROL CONTROL VPBE RGB888, GPIO: VPBE: PinMux0:RGB888 GPIO GPIO[5:6,38] RGB888 G1, B1, EMIFA, VLYNQ, GPIO:GPIO[8] EMIFA: VLYNQ: PinMux0:AECS5 PinMux0:VLYNQEN GPIO EM_CS5 VLYNQ_CLOCK EMIFA, VLYNQ, GPIO:GPIO[9] EMIFA: VLYNQ: PinMux0:AECS4 PinMux0:VLSCREN GPIO EM_CS4 VLYNQ_SCRUN EMIFA, VLYNQ, GPIO: EMIFA: VLYNQ: PinMux0:AEAW, PinMux0:VLYNQEN, GPIO GPIO[10:17] EM_A[21:14] VLYNQ_TXD[0:3], Pins:DAEAW[4:0] PinMux0:VLYNQWD[1:0] VLYNQ_RXD[0:3] EMIFA, GPIO GPIO: EMIFA: PinMux0:AEAW, GPIO[18:28] EM_A[13:3] Pins:DAEAW[4:0] ASP, GPIO GPIO: ASP: PinMux1:ASP GPIO[29:34] (allpins)(4) UART0, GPIO GPIO: UART0: PinMux1:UART0 GPIO[35:36] RXD, TXD SPI,GPIO GPIO: SPI: PinMux1:SPI GPIO[37,39:41] SPI_EN0, SPI_CLK, SPI_DI,SPI_DO SPI,ATA, GPIO GPIO:GPIO[42] SPI:SPI_EN1 ATA: HDDIR PinMux1:SPI PinMux0:HDIREN I2C,GPIO GPIO: I2C:SCL, SDA PinMux1:I2C GPIO[43:44] PWM0, GPIO GPIO:GPIO[45] PWM0 PinMux1:PWM0 PWM1, VPBE GPIO:GPIO[46] VPBE: PWM1: PinMux0:RGB666/ PinMux1:PWM1 (RGB666/RGB888), RGB666/RGB888 PWM1 PinMux0:RGB888 GPIO R2 PWM2, VPBE GPIO:GPIO[47] VPBE: PWM2: PinMux0:RGB666/ PinMux1:PWM2 (RGB666/RGB888), RGB666/RGB888 PWM2 PinMux0:RGB888 GPIO B2 ClockOut0,GPIO GPIO:GPIO[48] CLK_OUT0 PinMux1:CLK0 ClockOut1,TIMER0, GPIO:GPIO[49] CLK_OUT1 TIMER0: PinMux1:CLK1 PinMux1:TIM_IN GPIO TIM_IN ATA, GPIO GPIO: ATA: PinMux0:ATAEN GPIO[50:51] ATA_CS0, ATA_CS1 EMIFA, GPIO, ATA GPIO:GPIO[52] EMIFA: ATA (CF): PinMux0:AEAW[4:0], PinMux0:ATAEN (CF) EM_BA[1] DA1 Pins:DAEAW[4:0] EMIFA, HPI,ATA GPIO:GPIO[53] EMIFA: ATA (CF):DA2/ PinMux0:AEAW[4:0], PinMux0:ATAEN, (CF),GPIO EM_A[0] HPI:HCNTL1 Pins:DAEAW[4:0] PinMux0:HPIEN, Pins:BTSEL[1:0]= 10 EMAC, GPIO3V GPIO: EMAC: PinMux0:EMACEN GPIO3V[0:13] (allpins,except CRS) (5) EMAC, MDIO, GPIO: EMAC: PinMux0:EMACEN GPIO3V GPIO3V[14:16] CRS, MDIO: MDIO, MDCLK UART1, ATA (CF) N/A ATA (CF): UART1: TXD, RXD PinMux0:ATAEN PinMux1:UART1 DMACK, DMARQ UART2, VPFE VPFE: UART2: PinMux1:UART2 CI[7:6]/ UART_RXD2, CCD_DATA[15:14] UART_TXD2 (4) See Section2.7,TerminalFunctions,forpindetails. (5) See Section2.7,TerminalFunctions,forpindetails.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table3-13.DM6446 MultiplexedPeripheralPins and MultiplexingControls(continued) PRIMARY SECONDARY TERTIARYMULTIPLEXED SECONDARY (1) TERTIARY (2) (DEFAULT) REGISTER/PIN (3) REGISTER/PIN (3) PERIPHERALS FUNCTION FUNCTIONFUNCTION CONTROL CONTROL UART2, VPFE VPFE: UART2: PinMux1:UART2, CI[5:4]/ UART_CTS2, PinMux1:U2FLO CCD_DATA[13:12] UART_RTS2

3.5.3 PeripheralSelectionAfterDevice Reset

Afterdevicereset,thePINMUX0 and PINMUX1 registersaresoftwareprogrammabletoallowmultiplexing of shared devicepinsbetween peripherals,as giveninSection2.7, TerminalFunctions. Section3.5.4 (PINMUX0 RegisterDescription),Section3.5.5(PINMUX1 RegisterDescription),and Section3.5.6(Pin MultiplexingRegisterFieldDetails)identifytheregistersettingsnecessarytoconfigurespecificmultiplexed functionsand show theprimary(default)functionafterreset.

3.5.4 PINMUX0 RegisterDescription

The PINMUX0 pin multiplexingregistercontrolswhich peripheralisgivenownershipover shared pins among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals.The registerformatisshown inFigure3-7 and bitfielddescriptionsare giveninTable3-14.More detailson thePINMUX0 pinmuxing fieldsaregiveninSection3.5.6,PinMultiplexingRegisterFieldDetails.A value of'1'enablesthesecondaryortertiarypinfunction. Figure3-7.PINMUX0 Register(1) 31 30 29 28 27 26 25 24 23 22 21 18 17 16 EMACEN Rsvd HPIEN Rsvd CFLDEN CWE LFLDEN LOEEN RGB888 RGB666 Reserved ATAEN HDIREN R/W-0 R/W-0 R/W-D R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 15 14 13 12 11 10 9 5 4 0 VLYNQEN VLSCREN VLYNQWD AECS5 AECS4 Reserved AEAW R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R-00000 R/W-LLLLL LEGEND: R = Read; W = Write;L = pinstatelatchedatresetrisingedge;D = derivedfrompinstates;-n = valueafterreset (1) ForproperDM6446 deviceoperation,always writea valueof'0'toRSV bit30. Table3-14.PINMUX0 RegisterDescription Name Description EMACEN EnableEMAC and MDIO functionon defaultGPIO3V[0:16]pins. HPIEN EnableHPI module pins.DefaultvalueisderivedfromBTSEL[1:0]configurationinputs. HPIEN is1 when theBTSEL[1:0]= 10 and HPIEN is0 (thedefaultstate)when BTSEL[1:0]is00,01,or11. CFLDEN EnableCCD C_FIELD functionon defaultGPIO[4]pin CWE EnableCCD C_WE functionon defaultGPIO[1]pin LFLDEN EnableLCD_FIELD functionon defaultGPIO[3]pin LOEEN EnableLCD_OE functionon defaultGPIO[0]pin RGB888 EnableVPBE RGB888 functionon defaultGPIO[2:6,46:47]pins RGB666 EnableVPBE RGB666 functionon defaultGPIO[46:47]pins ATAEN EnableATA functionon defaultEMIFA and GPIO[52:53]pinsand sharedUART1 pins HDIREN EnableHDDIR functionon defaultGPIO[42]pin VLYNQEN EnableVLYNQ functionon defaultGPIO[9,10:17]pins VLSCREN EnableVLYNQ SCRUN functionon defaultGPIO[9]pin VLYNQWD VLYNQ datawidthselection.Thisexpands theVLYNQ TXD[0:3]and RXD[0:3] functionson defaultGPIO[10:17]pins. AECS5 EnableEMIFA EM_CS5 functionon GPIO[8] Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 73 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table3-14.PINMUX0 RegisterDescription(continued) Name Description AECS4 EnableEMIFA EM_CS4 functionon GPIO[9] AEAW EMIFA addresswidthselection.DefaultvalueislatchedatresetfromAEAW[4:0] configurationinputpins.ThisenablesEMIF addressfunctionon defaultGPIO[10:28] pins.

3.5.5 PINMUX1 RegisterDescription

The PINMUX1 pin multiplexingregistercontrolswhich peripheralisgivenownershipover shared pins among Timer,PLL, ASP, SPI, I2C, PWM, and UART peripherals.The registerformatis shown in Figure3-8 and bitfielddescriptionsare giveninTable 3-15. More detailson the PINMUX1 pinmuxing fieldsare given in Section3.5.6, Pin MultiplexingRegisterFieldDetails. A value of "1"enables the secondaryortertiarypinfunction. Figure3-8.PINMUX1 Register(1) 31 19 18 17 16 Reserved TIMIN CLK1 CLK0 R-0000 0000 0000 0 R/W-0 R/W-0 R/W-0 15 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ASP Rsvd SPI I2C PWM2 PWM1 PWM0 U2FLO UART2 UART1 UART0 R-0000 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write;R = Read only;-n = valueafterreset (1) ForproperDM6446 deviceoperation,always writea valueof'0'toRSV bit9. Table3-15.PINMUX1 RegisterDescription Name Description TIMIN EnableTIM_IN functionon defaultGPIO[49]pin CLK1 EnableCLK_OUT1 functionon defaultGPIO[49]pin CLK0 EnableCLK_OUT0 functionon defaultGPIO[48]pin ASP EnableASP functionon defaultGPIO[29:34]pins SPI EnableSPI functionon defaultGPIO[37,39:42]pins I2C EnableI2C functionon defaultGPIO[43:44]pins PWM2 EnablePWM2 functionon defaultGPIO[47]pin PWM1 EnablePWM1 functionon defaultGPIO[46]pin PWM0 EnablePWM0 functionon defaultGPIO[45]pin U2FLO EnableUART2 flowcontrolfunctionon defaultVPFE CI[5:4]/CCD_DATA[13:12]pins UART2 EnableUART2 functionon defaultVPFE CI[7:6]/CCD_DATA[15:14] pins UART1 EnableUART1 functionon sharedATA (CF)DMACK, DMARQ pins UART0 EnableUART0 functionon defaultGPIO[35:36]pins

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3.5.6 Pin MultiplexingRegisterFieldDetails

The bitfieldsforvariouspin multiplexingoptionswithinthe PINMUX0 and PINMUX1 registersare describedinthefollowingsections.

3.5.6.1 EMAC and GPIO3V Pin Multiplexing

The EMAC pinfunctionsareselectedas shown inTable3-16.The functionalityforeach oftheindividual pinsaffectedby thePINMUX0 fieldsettingsisgiveninTable3-17. Table3-16.EMAC and GPIO3V Pin MultiplexingControl EMACEN PIN FUNCTIONALITY SELECTED

0 GPIO3V

1 EMAC

Table3-17.EMAC and GPIO3V MultiplexedPins GPIO EMAC GPIO3V[0] TXEN GPIO3V[1] TXCLK GPIO3V[2] COL GPIO3V[3] TXD[0] GPIO3V[4] TXD[1] GPIO3V[5] TXD[2] GPIO3V[6] TXD[3] GPIO3V[7] RXD[0] GPIO3V[8] RXD[1] GPIO3V[9] RXD[2] GPIO3V[10] RXD[3] GPIO3V[11] RXCLK GPIO3V[12] RXDV GPIO3V[13] RXER GPIO3V[14] CRS GPIO3V[15] MDIO GPIO3V[16] MDCLK Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 75 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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3.5.6.2 VPFE (CCD),VPBE (LCD),and GPIO Pin Multiplexing

The CCD and LCD controllersin the VPSS requiremultiplexcontrolbitsettingsforcertainmodes of operation.BitswithinthePinMux0 register,whichselectbetween theCCD orLCD controlsignalfunction and GPIO, aresummarized inTable3-18. Table3-18.VPFE (CCD),VPBE (LCD),and GPIO Pin Multiplexing PINMUX0 REGISTER FIELDS MULTIPLEXED PINS C_FIELD/ LCD_FIELD/ C_WE/ LCD_OE/ CFLDEN LFLDEN CWE LOEEN R0/ B0/ GPIO[1] GPIO[0] GPIO[4] GPIO[3] - - - 1 - - - LCD_OE - - 1 - - - C_WE - - 1 - - - LCD_FIELD - - 1 - - - C_FIELD - - - (1) Depends on RGB888 bitsetting,see Table3-19.

3.5.6.3 VPBE (RGB666 and RGB888) and GPIO Pin Multiplexing

Use oftheRGB666 and RGB888 modes oftheVPBE requiresenablingRGB pinsas shown inTable3-19 and Table3-20.EnablingPWM2, PWM1, CCD, and LCD functionalityoverridestheRGB modes. RGB666 interfacepinfunctionalityrequiressettingthe RGB666 PINMUX0 Registerbitfieldto ‘1’and PINMUX1 RegisterbitfieldsPWM2 and PWM1 to‘0’.ProperRGB888 interfaceoperationrequiressettingPINMUX0 RegisterbitfieldRGB888 to‘1’and bitfieldsPWM2, PWM1, CFLDEN, and LFLDEN must be setto‘0’. Table3-19.VPBE (RGB666, RGB888, and LCD), VPFE (CCD),and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS PWM2/ PWM1/ C_FIELD/ LCD_FIELD/ RGB888 RGB666 PWM2 PWM1 CFLDEN LFLDEN B2/ R2/ R0/ B0/ GPIO[47] GPIO[46] GPIO[4] GPIO[3] 0 0 0 0 0 0 GPIO[47] GPIO[46] GPIO[4] GPIO[3] - - - - - 1 - - - LCD_FIELD 0 1 0 0 0 0 B2 R2 GPIO[4] GPIO[3] 1 - 0 0 0 0 B2 R2 R0 B0 Table3-20.VPBE (RGB666, RGB888, and LCD) and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS R1/ B1/ G1/ G0/RGB888 PWM2 PWM1 CFLDEN LFLDEN GPIO[38] GPIO[6] GPIO[5] GPIO[2] 0 0 0 0 0 GPIO[38] GPIO[6] GPIO[5] GPIO[2] 1 0 0 0 0 R1 B1 G1 G0

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3.5.6.4 ATA, EMIFA, UART1, SPI,and GPIO Pin Multiplexing

The ATA peripheralshares pins with the EMIFA and UART1 as seen in Table 3-21. IfATA pin functionalityisenabledby settingthe ATAEN bitfield,the ATA module willdrivethe EMIFA data and controlpins.EnablingUART1 disablesthe use of the ATA DMARQ and DMACK signalsand thusonly allowsthe ATA module to use PIO mode. The ATA HDDIR bufferdirectioncontrolbitfieldworks in conjunctionwiththeHDIREN enablebitfieldtoallowtheATA pinstostillbe used as a GPIO orSPI_EN1 ifthebufferisnotbeingused (i.e.forCompact Flash).Thismultiplexingisshown inTable3-22.When ATAEN=0 and HDIREN=1 itindicatesthattheATA interfacehas been disabledso thattheEMIFA can be used,buttheATA buffersare stillpresent.HDDIR isdrivenlow inthissituationtoensurethattheATA buffersdriveaway from DM644X and don’t cause bus contentionwiththe EMIFA. Note thatswitching between EMIFA and ATA (clearingor settingATAEN) must be carefullyperformed to preventbus contention.SincetheATA devicecan be a bus master,softwaremust ensurethatalloutstandingDMA requestshave completedbeforeclearingtheATAEN bit. Table3-21.ATA, EMIFA, and GPIO Pin MultiplexingControl(1) PINMUX0 REGISTER MULTIPLEXED PINS BIT FIELD EM_BA[1]/ EM_A[0]/ EM_D[15:0]/GPIO[50]/ GPIO[51]/ EM_R/ W EM_BA[0]/ EM_WAIT/ DIOR/ DIOW/ATAEN GPIO[52]/ GPIO[53]/ DD[15:0]ATA_CS0 ATA_CS1 INTRQ ATA0 IORDY EM_OE EM_WE ATA1 ATA2 GPIO[50] GPIO[51] EM_R/ W EM_BA[0] EM_WAIT EM_OE EM_WE EM_BA[1]/ EM_A[0]/ EM_D[15:0]0 GPIO52 GPIO53

1 ATA_CS0 ATA_CS1 INTRQ ATA0 IORDY DIOR DIOW ATA1 ATA2 DD[15:0]

(1) Thistableassumes thattheHPIEN bitinthePINMUX0 registeris"0". (2) ThispinsharesGPIO functionalitysetby AEAW[4:0] as shown inTable3-9. Table3-22.ATA, EMIFA, UART1, SPI,and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS SPI_EN1/UART_TXD1/ UART_RXD1/ATAEN UART1 HDIREN SPI HDDIR/DMACK DMARQ GPIO[42] 0 0 0 0 DMACK DMARQ GPIO[42] 0 0 0 1 DMACK DMARQ SPI_EN1 0 0 1 - DMACK DMARQ DrivenLow 0 1 0 0 UART_TXD1 UART_RXD1 GPIO[42] 0 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1 0 1 1 - UART_TXD1 UART_RXD1 DrivenLow 1 0 0 0 DMACK DMARQ GPIO[42]x 1 0 0 1 DMACK DMARQ SPI_EN1x 1 0 1 - DMACK DMARQ HDDIR 1 1 0 0 UART_TXD1 UART_RXD1 GPIO[42]x 1 1 0 1 UART_TXD1 UART_RXD1 SPI_EN1x 1 1 1 - UART_TXD1 UART_RXD1 HDDIR Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 77 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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3.5.6.5 VLYNQ, EMIFA, and GPIO Pin Multiplexing

Table 3-23 and Table 3-24 show the VLYNQ pin controland multiplexing.IfVLYNQ is disabled (VLYNQEN=0), theAECS5 and AECS4 bitsselectbetween theGPIO[8]/EMIFA EM_CS5 and GPIO[9]/ EMIFA EM_CS4 functions,and theAEAW fielddeterminesthepartitioningbetween GPIO and theupper EMIFA address pins.If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and VLYNQ_RXD0 are always selected.The VLYNQ_SCRUN functionisonlyenabledifVLYNQEN=1 and VLSCREN=1 (VLSCREN overridesAECS4). The remainingVLYNQ TX/RX pinsare selectedbased on the VLYNQWD value.UnselectedVLYNQ TX/RX pinswillfunctionas eitherGPIO or EMIFA address based on theAEAW value. Table3-23.VLYNQ Control,EMIFA, and GPIO Pin Multiplexing PINMUX0 REGISTER BIT FIELDS MULTIPLEXED PINS EM_CS5/ EM_CS4/ VLYNQEN VLSCREN AECS5 AECS4 GPIO[8]/ GPIO[9]/ VLYNQ_CLOCK VLYNQ_SCRUN 0 - 0 0 GPIO[8] GPIO[9] 0 - 0 1 GPIO[8] EM_CS4 0 - 1 0 EM_CS5 GPIO[9] 0 - 1 1 EM_CS5 EM_CS4 1 0 - 0 VLYNQ_CLOCK GPIO[9] 1 0 - 1 VLYNQ_CLOCK EM_CS4 1 1 - - VLYNQ_CLOCK VLYNQ_SCRUN Table3-24.VLYNQ Data,EMIFA, and GPIO Pin Multiplexing PINMUX0 REGISTER MULTIPLEXED PINS BIT FIELDS EM_A[21]/ EM_A[20]/ EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/ VLYNQEN VLYNQWD GPIO[10]/ GPIO[11]/ GPIO[12]/ GPIO[13]/ GPIO[14]/ GPIO[15]/ GPIO[16]/ GPIO[17]/ VL_TXD0 VL_RXD0 VL_TXD1 VL_RXD1 VL_TXD2 VL_RXD2 VL_TXD3 VL_RXD3 EM_A[21]/ EM_A[20]/ EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/0 - GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 VL_TXD0 VLRXD0 EM_A[19]/ EM_A[18]/ EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/1 00 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 EM_A[17]/ EM_A[16]/ EM_A[15]/ EM_A[14]/1 01 GPIO14 GPIO15 GPIO16 GPIO17 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 EM_A[15]/ EM_A[14]/1 10 GPIO16 GPIO17 1 11 VL_TXD0 VLRXD0 VL_TXD1 VLRXD1 VL_TXD2 VLRXD2 VL_TXD3 VLRXD3 (1) ThispinsharesGPIO functionalitysetby AEAW[4:0] as shown inTable3-9.

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3.5.6.6 Timer0 Input,CLK_OUT1, and GPIO Pin Multiplexing

The multiplexingoftheCLK_OUT1 and Timer0Input(Timer0 only)functionsisshown inTable3-25. Table3-25.Timer0 Input,CLK_OUT1, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS CLK_OUT1/ TIMIN CLK1 TIM_IN/ GPIO[49] 0 0 GPIO[49] 0 1 CLK_OUT1 1 - TIM_IN

3.5.6.7 ASP, SPI,I2C,ATA, and GPIO Pin Multiplexing

When theASP, SPI,or I2C serialportfunctionsare notselected,theirpinsmay be used as GPIOs as seen inTable3-26,Table3-27,and Table3-28.The SPI_EN1 pincan alsofunctionas theHDDIR buffer controlwhen ATAEN isselectedand theHDIREN bitisset. Table3-26.ASP and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELD MULTIPLEXED PINS CLKX/ CLKR/ FSX/ FSR/ DX/ DR/ASP GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34]

0 GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34]

1 CLKX CLKR FSX FSR DX DR

Table3-27.SPI and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS SP_EN1/ SPI_DO/ SPI_DI/ SPI_CLK/ SPI_EN0/ SPI ATAEN HDIREN HDDIR/ GPIO[41] GPIO[40] GPIO[39] GPIO[37] GPIO[42] 0 0 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 0 1 DrivenLow GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 0 GPIO[42] GPIO[41] GPIO[40] GPIO[39] GPIO[37] 0 1 1 HDDIR GPIO[41] GPIO[40] GPIO[39] GPIO[37] 1 0 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 0 1 DrivenLow SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 0 SP_EN1 SPI_DO SPI_DI SPI_CLK SPI_EN0 1 1 1 HDDIR SPI_DO SPI_DI SPI_CLK SPI_EN0 Table3-28.I2C and GPIO Pin Multiplexing PINMUX1 REGISTER MULTIPLEXED PINSBIT FIELD I2C_CLK/ I2C_DATA/I2C GPIO[43] GPIO[44]

0 GPIO[43] GPIO[44]

1 I2C_CLK I2C_DATA

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3.5.6.8 PWM, RGB888, and GPIO Pin Multiplexing

Table 3-29 shows the PWM0/1/2 pinmultiplexing.Each PWM outputisindependentlycontrolledby its own enablebit.The PWM functionhas priorityoverRGB888 muxing [seeSection3.5.6.3,VPBE (RGB666 and RGB888) and GPIO PinMultiplexing]. Table3-29.PWM0/1/2, RGB888, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS MULTIPLEXED PINS PWM2/ PWM1/ PWM0/ PWM2 PWM1 PWM0 RGB888 B2/ R2/ GPIO[45] GPIO[47] GPIO[46] 0 0 0 0 GPIO[47] GPIO[46] GPIO[45] 0 0 0 1 B2 R2 GPIO[45] - - 1 - - - PWM0 - 1 - - - PWM1 - 1 - - - PWM2 - -

3.5.6.9 UART, VPFE, ATA, and GPIO Pin Multiplexing

Each UART has independentpinmultiplexingcontrolbitsinthePINMUX1 register.The UART2 peripheral may be used withorwithouttheflowcontrolsignals.Table3-30shows how UART2 selectionreducesthe widthoftheVPFE interface. SettingtheUART1 bitenablesUART1 transmitand receivepinfunctionality.Sincethesearesharedwith the ATA DMA handshake signals,enablingUART1 effectivelydisablesthe ATA DMA mode. However, ATA PIO mode isstillsupportedwithUART1 enabled.Thisisshown inTable3-31.IftheATA module is notenabled,thepinsarealwaysconfiguredforuse by UART1. Table3-30.UART2, VPFE, and GPIO Pin Multiplexing PINMUX1 REGISTER MULTIPLEXED PINSBIT FIELDS CCD[15]/ CCD[14]/ CCD[13]/ CCD[12]/ UART2 U2FLO CI[7]/ CI[6]/ CI[5]/ CI[4]/ UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2 CCD[15]/ CCD[14]/ CCD[13]/ CCD[12]/0 - CI7 CI6 CI5 CI4 UART_RXD2 UART_TXD2 CCD[13]/ CCD[12]/1 0 CI5 CI4 1 1 UART_RXD2 UART_TXD2 UART_CTS2 UART_RTS2 (1) Functionalitysetby VPFE operatingmode. Table3-31.UART1 and ATA Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER MULTIPLEXED PINSBIT FIELDS UART_TXD1/ UART_RXD1/ATAEN UART1 DMACK DMARQ 0 - UART_TXD1 UART_RXD1 1 0 DMACK DMARQ 1 1 UART_TXD1 UART_RXD1

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 As Table 3-32 shows, the UART0 pinsare configurableforeitherUART0 transmitand receivedata functionsorforGPIO. Table3-32.UART0 and GPIO Pin Multiplexing PINMUX1 REGISTER BIT MULTIPLEXED PINSFIELD UART_TXD0/ UART_RXD0/UART0 GPIO[36] GPIO[35]

0 GPIO[36] GPIO[35]

1 UART_TXD0 UART_RXD0

3.5.6.10HPI and EMIFA/ATA Pin Multiplexing When theHPIEN bitisset,theHPI module isgivencontrolofmost oftheEMIFA/ATA controlpinsas well as theEMIFA/ATA databus.Table3-33shows whichpinstheHPI controls.HPIEN issetto1 when the stateoftheBTSEL[1:0]pins= 10 islatchedattherisingedge ofreset.Also,thisbitcan be manipulated afterresetby software.When theATAEN bitissetand HPIEN is0,theATA mode ofoperationforpins shared withthe HPI isavailable.EMIFA mode functionalityforthe shared HPI pinsisset when both HPIEN and ATAEN are'0'. Table3-33.HPI and EMIFA/ATA Pin Multiplexing PINMUX0 REGISTER MULTIPLEXED PINS BIT FIELDS HR/W/ HRDY/ HDS1/ HDS2/ HCNTLB/ HINT/ HD[15:0]/HPI ATA HCS/ HHWIL/ HCNTLA/INTRQ/ EM_WAIT/ DIOR/ DIOW/ ATA2/ ATA0/ DD[15:0]/EN EN EM_CS2 EM_A[1] EM_A[2]EM_R/ W IORDY EM_OE EM_WE EM_A[0] EM_BA[0] EM_D[15:0] 0 0 EM_CS2 EM_A1 EM_R/ W EM_WAIT EM_OE EM_WE EM_A2 EM_A0 EM_BA[0] EM_D[15:0] 0 1 EM_CS2 EM_A1 INTRQ IORDY DIOR DIOW EM_A2 EM_A0 ATA0 DD[15:0] 1 - HCS HHWIL HR/W HRDY HDS1 HDS2 HCNTLA HCNTLB HINT HD[15:0] (1) ThispinsharesGPIO functionalityand issetby AEAW[4:0] as shown inTable3-12,Table3-13,and Table3-14.

3.6 EmulationControl

The flexibilityoftheDM644x architectureallowseithertheARM orDSP tocontrolthevariousperipherals (setupregisters,serviceinterrupts,etc.).Whilethisassignmentispurelya matterofsoftwareconvention, duringan emulationhaltitisnecessaryforthedevicetoknow whichperipheralsareassociatedwiththe haltingprocessorso thatonly those modules receivethe suspend signal.This allowsperipherals associatedwiththe other(unhalted)processorto continuenormal operation.The SUSPSRC register indicatesthe emulationsuspend source forthose peripheralswhich supportemulationsuspend. The SUSPSRC registerformatisshown inFigure3-9.Briefdetailson theperipheralswhichcorrespondtothe registerbitsisgiveninTable3-34.When theassociatedSUSPSRC bitis‘0’,theperipheral’s emulation suspend signaliscontrolledby theARM emulatorand when setto‘1’itiscontrolledby theDSP emulator. Figure3-9.EmulationSuspend Source Register(SUSPSRC) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VICP VICP TIMR2 TIMR1 TIMR0 GPIO PWM2 PWM1 PWM0 SPI UART2 UART1 UART0 I2C ASP RsvdSRC EN SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC SRC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 15 13 12 11 10 9 8 6 5 4 0 HPI USB EMACRsvd Rsvd Rsvd ReservedSRC SRC SRC R-000 R/W-0 R-00 R/W-0 R-000 R/W-0 R-0 0000 LEGEND: R = Read, W = Write,n = valueatreset Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceConfigurations 81 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table3-34.SUSPSRC RegisterDescription Name Description VICPSRC VideoImagingCoprocessoremulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend VICPEN VideoImagingCoprocessoremulationsuspend enable 0 = Emulationsuspend ignoredby VICP 1 = VICP emulationsuspend enabled TIMR2SRC Timer2(WD Timer)emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend TIMR1SRC Timer1emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend TIMR0SRC Timer0emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend GPIOSRC GPIO emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend PWM2SRC PWM2 emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend PWM1SRC PWM1 emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend PWM0 SRC PWM0 emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend SPISRC SPI emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend UART2SRC UART2 emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend UART1SRC UART1 emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend UART0SRC UART0 emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend I2CSRC I2C emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend ASPSRC ASP emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend HPISRC HPI emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend USBSRC USB emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend EMACSRC EthernetMAC emulationsuspend source 0 = ARM emulationsuspend 1 = DSP emulationsuspend

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4 System Interconnect

On the DM6446 device,the C64x+ megamodule, the ARM subsystem,the EDMA3 transfercontrollers, and thesystem peripheralsareinterconnectedthrougha switchfabricarchitecture(shown inFigure4-1). The switchfabriciscomposed of multipleswitchedcentralresources(SCRs) and multiplebridges.The SCRs establishlow-latencyconnectivitybetween master peripheralsand slaveperipherals.Additionally, theSCRs providepriority-basedarbitrationand facilitateconcurrentdatamovement between masterand slaveperipherals.Through SCR, the ARM subsystem can send data to the DDR2 Memory Controller withoutaffectinga datatransferbetween theEMAC and L2 memory. Bridgesaremainlyused toperform bus-widthconversionas wellas bus operatingfrequencyconversion.For example,inFigure4-1,Bridge8 performsa frequencyconversionbetween a bus operatingat DSP/6 clockrateand a bus operatingat DSP/3 clockrate.Furthermore,Bridge3 performsa bus-widthconversionbetween a 64-bitbus and a 32-bitbus. The C64x+ megamodule, the ARM subsystem,the EDMA3 transfercontrollers,and the varioussystem peripheralscan be classifiedintotwo categories:master peripheralsand slave peripherals.Master peripheralsaretypicallycapableofinitiatingreadand writetransfersinthesystem and do notrelyon the EDMA3 or on a CPU toperformtransferstoand from them.The system masterperipheralsincludethe C64x+ megamodule, theARM subsystem,theEDMA3 transfercontrollers,CF/ATA, VLYNQ, EMAC, USB, and VPSS. Not allmaster peripheralsmay connectto allslaveperipherals.The supportedconnections aredesignatedby an X inTable4-1. Table4-1.System Connection Matrix SLAVE MASTER C64x+ ARM DDR2 MEMORY CONTROLLER SCR3 (1) C64x+ X X X ARM X X X VPSS X CF/ATA X X X X VLYNQ X X X X EMAC X X X X USB X X X X EDMA3TC0 X X X X EDMA3TC1 X X X X HPI X X X (2) (1) The C64x+ megamodule has accesstoonlythefollowingperipheralsconnectedtoSCR3: EDMA3, ASP, and Timers.Allother peripherals/modulesthatsupporta connectiontoSCR3 have accesstoallperipherals/modulesconnectedtoSCR3. (2) HPI's accesstoSCR3 islimitedtothepower and sleepcontrollerregisters,PLL1 and PLL2 registers,and HPI configurationregisters. Copyright© 2005–2010,Texas InstrumentsIncorporated System Interconnect 83 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

USB□2.0 SCR2 Bridge1 Bridge7 ARM C64x+ CFG MDMA L2□Cache VICP Bridge6 Bridge5 SCR3 VPSS EDMA3TC1 Bridge3 ARM TCM C64x+ L2/L1SDMA DDR2□Ctrl (Mem/Reg) SCR6 CF/ATA Reg USB□Reg EMAC□Reg EMAC□Ctrl□Mod□Reg EMAC□Ctrl□Mod□RAM MDIO VPSS□Reg SPI□0/1 GPIO AINTC System□Reg PSC PLLC□0 PLLC□1 Bridge9 Bridge8 SCR7 ASP VLYNQ MMC/SD EMIFA/NAND SCR8 UART0 UART1 UART2 I2C PWM0 PWM1 PWM2 Timer□0 Timer□1 Timer□2 SCR4 EDMA3CC EDMA3TC0 EDMA3TC1 32 64 Read Write Read Write 128 256 32 32 DSP/2□Clock□Rate DSP/3□Clock□Rate DSP/6□Clock□Rate EDMA3TC0 MXI/CLKIN□Rate HPI 32 HPI TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

4.1 System InterconnectBlock Diagram

Figure4-1 displaysthe DM6446 system interconnectblockdiagram.The followingisa listthathelps interpretthisdiagram:

• The directionofthearrowsindicateseitherbus masterorbus slave.
• The arroworiginatesata bus masterand terminatesata bus slave.
• The directionofthearrowsdoes notindicatethedirectionofdataflow.Data flowistypically bi-directionalforeach ofthedocumented bus paths.
• The patternofeach arrow'slineindicatestheclockrateatwhichitisoperating,eitherDSP/2,DSP/3, orDSP/6 clockrate.
• Some peripheralsmay have multipleinstancesshown inthediagram.A peripheralmay have multiple instancesshown fora varietyofreasons,some ofwhicharedescribedbelow: – The peripheral/modulehas masterport(s)fordatatransfers,as wellas slaveport(s)forregister access,dataaccess,and/ormemory access.Examples oftheseperipheralsareC64x+ megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI. – The peripheral/modulehas a masterportas wellas slavememories.Examples ofthesearethe C64x+ megamodule and theARM subsystem. Figure4-1.System InterconnectBlock Diagram

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5 Device OperatingConditions

5.1 AbsoluteMaximum RatingsOver OperatingCase Temperature Range

(UnlessOtherwiseNoted) (1) Core (CVDD ,VDDA1P1V ,USB_V DDA1P2LDO (2),CV DDDSP ) (3) -0.5V to1.5V I/O,3.3V(DVDD33 ,USB_V DDA3P3 ) (3) -0.5V to4.2VSupplyvoltageranges I/O,1.8V(DVDD18 ,DV DDR2 ,DDR_V DDDLL ,PLLV DD18 ,VDDA1P8V , -0.5V to2.5V USB_V DD1P8 ,MXV DD ,M24V DD ) (3) VII/O,3.3V -0.5V to4.2V Inputvoltageranges VII/O,1.8V -0.5V to2.5V VO I/O,3.3V -0.5V to4.2V Outputvoltageranges VO I/O,1.8V -0.5V to2.5V (default)[-594,-810devices] 0°C to85°C Operatingcase temperatureranges,TC (A version)[A-513device] -40°C to105°C Storagetemperaturerange,Tstg (default) -55°C to150°C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Thispinisan internalLDO outputand connectedvia1 µF capacitortoUSB_V SSA1P2LDO . (3) AllvoltagevaluesarewithrespecttoVSS. Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOperatingConditions 85 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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5.2 Recommended OperatingConditions

(-810devices) 1.235 1.3 1.365 V Supplyvoltage,Core (CVDD ,CV DDDSP ) (1) (A-513,-594 1.14 1.2 1.26 VCV DD devices) Supplyvoltage,Core (VDDA1P1V , (Alldevices) 1.14 1.2 1.26 VUSB_V DDA1P2LDO (2)) (1) Supplyvoltage,I/O,3.3V(DVDD33 ,USB_DV DDA3P3 ) 3.15 3.3 3.45 V DV DD Supplyvoltage,I/O,1.8V(DVDD18 ,DV DDR2 ,DDR_V DDDLL , 1.71 1.8 1.89 VPLLV DD18 ,VDDA1P8V ,USB_V DD1P8 ,MXV DD ,M24V DD ) Supplyground(VSS ,VSSA1P8V ,VSSA1P1V ,DDR_V SSDLL , VSS USB_V SSREF ,USB_V SS1P8 ,USB_V SSA3P3 ,USB_V SSA1P2LDO , 0 0 0 V MXV SS (3),M24V SS (3)) DDR_VREF DDR2 referencevoltage(4) 0.49DVDDR2 0.5DVDDR2 0.51DVDDR2 V DDR_ZP DDR2 impedance control,connectedvia200 Ω resistortoVSS VSS V DDR_ZN DDR2 impedance control,connectedvia200 Ω resistortoDV DDR2 DV DDR2 V DAC_VREF DAC referencevoltageinput 0.475 0.5 0.525 V DAC_RBIAS DAC biasing,connectedvia4 kΩ resistortoVSSA_1P8V VSSA_1P8V V USB_VBUS USB externalchargepump input 4.75 5 5.25 V High-levelinputvoltage,I/O,3.3V 2 V VIH High-levelinputvoltage,non-DDR I/O,1.8V 0.65DVDD V Low-levelinputvoltage,I/O,3.3V 0.8 V VIL Low-levelinputvoltage,non-DDR I/O,1.8V 0.35DVDD V Default(-594,-810) 0 85 °C TC Operatingcase temperature A version(A-513 -40 105 °Cdevice) Default(-594) 20 600 MHz Default(-810) 20 810 MHzFSYSCLK1 DSP OperatingFrequency(SYSCLK1) A version(A-513 20 513 MHzdevice) (1) FuturevariantsofTISOC devicesmay operateatvoltagesrangingfrom0.9V to1.4V toprovidea rangeofsystempower/performance resistorvaluesorinputpinconfigurationmodifications.Not incorporatinga flexiblesupplymay limitthesystem's abilitytoeasilyadaptto futureversionsofTISOC devices. (2) Thispinisan internalLDO outputand connectedvia1 mF capacitortoUSB_V SSA1P2LDO . (3) Oscillatorgroundmust be keptseparatefromothergroundsand connecteddirectlytothecrystalloadcapacitorground. (4) DDR_VREF isexpectedtoequal0.5DVDDR2 ofthetransmittingdeviceand totrackvariationsintheDV DDR2 .

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5.3 ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltageand

OperatingCase Temperature (UnlessOtherwiseNoted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT Low/fullspeed: 2.8 USB_V DDAP3 VUSB_DN and USB_DP Highspeed: 360 440 mVVOH USB_DN and USB_DP High-leveloutputvoltage(3.3VI/O) DV DD33 = MIN, IOH = MAX 2.4 V High-leveloutputvoltage(1.8VI/O) DV DD18 = MIN, IOH = MAX DV DD -0.45 V Low/fullspeed: 0.0 0.3 VUSB_DN and USB_DP Highspeed: -10 10 mVVOL USB_DN and USB_DP Low-leveloutputvoltage(3.3VI/O) DV DD33 = MIN, IOL = MAX 0.4 V Low-leveloutputvoltage(1.8VI/O) DV DD18 = MIN, IOL = MAX 0.45 V VI= VSS toDV DD withoutopposing ±10 mAinternalresistor VI = VSS toDV DD withopposinginternalII (2) Inputcurrent 50 100 250 mApullupresistor(3) VI = VSS toDV DD withopposinginternal -250 -100 -50 mApulldownresistor(3) IOH High-leveloutputcurrent Allperipherals -4 mA IOL Low-leveloutputcurrent Allperipherals 4 mA VO = DV DD orVSS ;internalpulldisabled ±20 mA IOZ (4) I/OOff-stateoutputcurrent VO = DV DD orVSS ;internalpullenabled ±100 mA Core (CVDD ,VDDA1P1V ,USB_V DDA1P2LDO (5),ICDD CV DD = 1.2V,DSP clock= 594 MHz 767 mACV DDDSP )supplycurrent(6) 3.3VI/O(DVDD33 ,USB_V DDA3P3 )IDDD DV DD = 3.3V,DSP clock= 594 MHz 6 mAsupplycurrent(6) 1.8VI/O(DVDD18 ,DV DDR2 ,DDR_V DDDLL , IDDD PLLV DD18 ,VDDA1P8V ,USB_V DD1P8 ,MXVDD, DV DD = 1.8V,DSP clock= 594 MHz 102 mA M24VDD) supplycurrent(6) C I Inputcapacitance 4 pF C o Outputcapacitance 4 pF (1) Fortestconditionsshown as MIN, MAX, orNOM, use theappropriatevaluespecifiedinSection5.2,Recommended Operating Conditions. (2) IIappliestoinput-onlypinsand bi-directionalpins.Forinput-onlypins,IIindicatestheinputleakagecurrent.Forbi-directionalpins,II indicatestheinputleakagecurrentand off-state(Hi-Z)outputleakagecurrent. (3) Appliesonlytopinswithan internalpullup(IPU)orpulldown(IPD)resistor. (4) IOZ appliestooutput-onlypins,indicatingoff-state(Hi-Z)outputleakagecurrent. (5) Thispinisan internalLDO outputand connectedvia1 mF capacitortoUSB_V SSA1P2LDO . (6) Measured underthefollowingconditions:60% DSP CPU utilization;ARM doingtypicalactivity(peripheralconfigurations,other housekeepingactivities);DDR2 Memory Controllerat50% utilization(135MHz), 50% writes,32 bits,50% bitswitching;2 MHz ASP at 100% utilization;Timer0at100% utilization.Atroom temperature(25°C) fortypicalprocessdevices.The actualcurrentdraw varies acrossmanufacturingprocessesand ishighlyapplication-dependent.Formore detailson coreand I/Ovoltages,activitiesand typical currentsfor-594,A-513,and -810devcies,as wellas informationrelevanttoboardpower supplydesign,see theTMS320DM6446/3 Power ConsumptionSummary applicationreport(literaturenumber SPRAAD6 ). Copyright© 2005–2010,Texas InstrumentsIncorporated DeviceOperatingConditions 87 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

4.0 pF 1.85 pF Z0 = 50 Ω (see note) Tester Pin Electronics Data Manual Timing Reference Point Output Under Test NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data manual timings. 42 Ω 3.5 nH Device Pin (see note) Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Vref Vref = VIL MAX (or VOL MAX) Vref = VIH MIN (or VOH MIN) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

6 Peripheraland ElectricalSpecifications

6.1 Parameter Information

6.1.1 Parameter InformationDevice-SpecificInformation

Figure6-1.TestLoad CircuitforAC Timing Measurements The loadcapacitancevaluestatedisonlyforcharacterizationand measurement ofAC timingsignals.This loadcapacitancevaluedoes notindicatethemaximum loadthedeviceiscapableofdriving.

6.1.1.1 SignalTransitionLevels

Allinputand outputtimingparametersarereferencedtoVrefforboth"0"and "1"logiclevels.For3.3V I/O, Figure6-2.Inputand Output VoltageReferenceLevelsforAC Timing Measurements Allriseand falltransitiontimingparametersare referencedto VIL MAX and VIH MIN forinputclocks, VOL MAX and VOH MIN foroutputclocks. Figure6-3.Rise and FallTransitionTime VoltageReferenceLevels

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6.1.1.2 Timing Parameters and Board Routing Analysis

The timingparametervaluesspecifiedinthisdatamanual do notincludedelaysby board routings.As a good board designpractice,such delaysmust always be taken intoaccount.Timing valuesmay be adjustedby increasing/decreasingsuch delays.TI recommends utilizingthe availableI/O buffer informationspecification(IBIS)models toanalyzethetimingcharacteristicscorrectly.To properlyuse IBIS models to attainaccuratetiminganalysisfora givensystem,see the Using IBIS Models forTiming Analysisapplicationreport(literaturenumber SPRA839 ).Ifneeded, externallogichardware such as buffersmay be used tocompensate any timingdifferences. For theDDR2 memory controllerinterface,itisnotnecessarytouse theIBISmodels toanalyzetiming characteristics.TI providesa PCB routingrulessolutionthatdescribesthe routingrulesto ensure the DDR2 memory controllerinterfacetimingsare met. See the ImplementingDDR2 PCB Layout on the TMS320DM644x DSP ApplicationReport(literaturenumber SPRAAC5 ).

6.2 Recommended Clock and ControlSignalTransitionBehavior

Allclocksand controlsignalsshould transitionbetween VIH and VIL (orbetween VIL and VIH) in a monotonicmanner.

6.3 Power Supplies

For more informationregardingTI'spower management productsand suggesteddevicesto power TI DSPs, visitwww.ti.com/dsppower.

6.3.1 Power-Supply Sequencing

The DM6446 includestwo coresupplies— CV DD and CV DDDSP ,as wellas threeI/Osupplies— DV DD18 , DV DDR2 ,and DV DD33 .To ensureproperdeviceoperation,a specificpower-upsequence must be followed. The coresupplypower-upsequence isdependenton theDSP bootmode selectedatreset.IftheDSP boot mode isconfiguredas Self-Bootmode, then both core suppliesmust be powered up at the same time. IftheDSP bootmode isconfiguredas Host-Boot,where theARM bootstheDSP, thetwo coresupplies may be ramped simultaneouslyor powered up separately.When powered up separately,the CV DDDSP supplymust notbe ramped priortotheCV DD supply.The CV DDDSP supplymust be powered up beforethe shortingswitchisclosed(enabled).Priortopoweringup theCV DDDSP supply,itshouldbe leftfloatingand notdriventoground.Table6-1 and Figure6-4 describethepower-onsequence timingrequirementsfor DSP Host-Bootmode. To minimizethevoltagedifferencebetween thesetwo coresupplies,a singleregulatorsourcemust be used topower theCV DD and CV DDDSP supplies. Formore information,see Section3.2.1,Power ConfigurationsatReset. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

(A) Note A:□DV denotes□all□I/O□supplies.DDXX TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-1.Core Supply Power-On Timing Requirements forDSP Host-BootMode (seeFigure6-4) A-513, -594, NO. UNIT-810 MIN MAX 1 td(CVDD-CVDDDSP) Delaytime,CV DD supplyreadytoCV DDDSP supplyramp start 0 (1) ns (1) InHost-Bootmode, theCV DDDSP supplymust be powered up priortoclosing(enabling)theshortingswitchbetween theALWAYS ON and DSP power domains. Figure6-4.DSP Host-BootMode Core Supply Timings Once the CV DD supplyhas been powered up, the I/O suppliesmay be powered up. Table 6-2 and Figure6-5 show the power-on sequence timingrequirementsforthe Core vs.I/Opower-up.DV DDXX is used todenoteallI/Osupplies.Note:theDV DDXX supplypower-upisspecifiedrelativetotheCV DD supply power-up,nottheCV DDDSP supply. Table6-2.I/OSupply Power-On Timing Requirements (seeFigure6-5) A-513, -594, NO. UNIT-810 MIN MAX 1 td(CVDD-DVDD) Delaytime,CV DD supplyreadytoDV DDXX supplyramp start 0 100 ms Figure6-5.I/OSupply Timings Thereisnot a specificpower-upsequence thatmust be followedwithrespecttotheorderofthepower-up oftheDV DD18 ,DV DDR2 ,and DV DD33 supplies.Once theCV DD supplyispowered up and thetd(CVDD-DVDDXX) specificationis met, the DV DD18 , DV DDR2 , and DV DD33 suppliesmay be powered up in any orderof preference.Allothersuppliesmay alsobe powered up inany orderofpreferenceonce thetd(CVDD-DVDDXX) specificationhas been met.

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6.3.1.1 Power-Supply Design Considerations

Core and I/Osupplyvoltageregulatorsshouldbe locatedclosetotheDSP (orDSP array)tominimize inductanceand resistanceinthepower deliverypath.Additionally,when designingforhigh-performance applicationsutilizingthe DM6446 device,the PC board shouldincludeseparatepower planesforcore, I/O,and ground,allbypassedwithhigh-qualitylow-ESL/ESR capacitors.

6.3.1.2 Power-Supply Decoupling

Inordertoproperlydecouplethesupplyplanesfrom system noise,placeas many capacitors(caps)as possibleclosetoDM6446. Assuming 0603 caps,theusershouldbe abletofita totalof60 caps,30 for thecoresuppliesand 30 fortheI/Osupplies.These caps need tobe closetotheDM6446 power pins,no more than1.25cm maximum distancetobe effective.Physicallysmallercaps,such as 0402,are better because oftheirlowerparasiticinductance.Propercapacitancevaluesare alsoimportant.Smallbypass caps (near560 pF) shouldbe closesttothepower pins.Medium bypass caps (220nF oras largeas can be obtainedin a smallpackage) should be next closest.TI recommends no lessthan 8 smalland 8 medium caps per supplybe placedimmediatelynexttotheBGA vias,usingthe"interior"BGA space and atleastthecornersofthe"exterior". Largercaps foreach supplycan be placedfurtheraway forbulkdecoupling.Largebulkcaps (ontheorder of100 mF) shouldbe furthestaway, butstillas closeas possible.Large caps foreach supplyshouldbe placedoutsideoftheBGA footprint. Any cap selectionneeds tobe evaluatedfroma yield/manufacturingpoint-of-view.As withtheselectionof any component, verificationof capacitoravailabilityover the product’s productionlifetimeshould be considered.

6.3.1.3 DM6446 Power and Clock Domains

DM6446 includestwo separatepower domains:"AlwaysOn" and "DSP".The "AlwaysOn" power domain isalwayson when thechipison.The "AlwaysOn" domain ispowered by theVDD pinsoftheDM6446. The majorityoftheDM6446's modules liewithinthe"AlwaysOn" power domain.A separatedomain called the"DSP" domain houses theC64x+ and VICP. The "DSP" domain isnotalwayson.The "DSP" power domain ispowered by theCV DDDSP pinsoftheDM6446. Table6-3providesa listingoftheDM6446 power and clockdomains. Two primaryreferenceclocksare requiredfortheDM6446 device.These can eitherbe crystalinputor drivenby externaloscillators.A 27-MHz crystalisrecommended forthesystem PLLs,whichgeneratethe internalclocksfortheARM, DSP, coprocessors,peripherals(includingimagingperipherals),and EDMA3. The recommended 27-MHz inputenablestheuse ofthevideoDACs todriveNTSC/PAL televisionsignals at the properfrequencies.A 24-MHz crystalisalsorequiredifthe USB peripheralisto be used.For furtherdescriptionoftheDM6446 clockdomains,see Table6-4(DM6446 ClockDomains) and Figure6-6 (PLL1 and PLL2 ClockDomain BlockDiagram). Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-3.DM6446 Power and Clock Domains POWER DOMAIN CLOCK DOMAIN PERIPHERAL/MODULE AlwaysOn CLKIN UART0 AlwaysOn CLKIN UART1 AlwaysOn CLKIN UART2 AlwaysOn CLKIN I2C AlwaysOn CLKIN Timer0 AlwaysOn CLKIN Timer1 AlwaysOn CLKIN Timer2 AlwaysOn CLKIN PWM0 AlwaysOn CLKIN PWM1 AlwaysOn CLKIN PWM2 AlwaysOn CLKDIV2 ARM Subsystem AlwaysOn CLKDIV3 DDR2 AlwaysOn CLKDIV3 VPSS AlwaysOn CLKDIV3 EDMA3 AlwaysOn CLKDIV3 SCR AlwaysOn CLKDIV6 GPSC AlwaysOn CLKDIV6 LPSCs AlwaysOn CLKDIV6 IcePick AlwaysOn CLKDIV6 EMIFA AlwaysOn CLKDIV6 USB AlwaysOn CLKDIV6 HPI AlwaysOn CLKDIV6 VLYNQ AlwaysOn CLKDIV6 EMAC AlwaysOn CLKDIV6 ATA/CF AlwaysOn CLKDIV6 MMC/SD/SDIO AlwaysOn CLKDIV6 SPI AlwaysOn CLKDIV6 ASP AlwaysOn CLKDIV6 GPIO DSP CLKDIV1 C64x+ CPU Table6-4.DM6446 Clock Domains (1) CLOCK MODES (FREQUENCY)FIXED SUBSYSTEM RATIO PLL ENABLED PLL ENABLED PLL ENABLEDPLL BYPASSvs.PLL1 (A-513) (-594) (-810) PLL1 – 27 MHz 513 MHz 594 MHz 810 MHz DSP 1:1 27 MHz 513 MHz 594 MHz 810 MHz ARM 1:2 13.5MHz 256.5MHz 297 MHz 405 MHz EDMA3/VPSS 1:3 9 MHz 171 MHz 198 MHz 270 MHz Peripherals 1:6 4.5MHz 85.5MHz 99 MHz 135 MHz (1) These tablevaluesassume a MXI/CLKIN of27 MHz and a PLL1 multiplierequalto22 forbothA-513 and -594devices.For-810 device,thesetablevaluesassume a MXI/CLKIN of27 MHz and a PLL1 multiplierequalto30.

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PLLDIV1 (/10) PLLDIV2 (/2) BPDIV PLL Controller 2 PLL Controller 1 PLLDIV3 (/3) PLLDIV5 (/6) PLLDIV2 (/2) PLLDIV1 (/1) SYSCLK3 Bypass Clock UARTs (x3) I2C Timers (x3) ATA/CF EMIF/NAND EMAC VLYNQ MMC/SD SPI GPIO ASP HPI USB 2.0 USB PHY

60 MHz

24 MHz

27 MHz

PLLDIV4 (/4) ARM INTC PWMs (x3) PLLDIV1 (/1) PLLDIV2 (/2) PLLDIV4 (/4) PLLDIV3 (/3) PLLDIV5 (/6) SYSCLK1 SYSCLK2 SYSCLK4 SYSCLK3 SYSCLK5 Post−DIV PLLM PLL BPDIV CLKMODE CLKIN OSCIN PLLEN AUXCLK SYSCLKBP TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-6.PLL1 and PLL2 Clock Domain Block Diagram For furtherdetailon PLL1 and PLL2, see the structureblockdiagrams Figure6-7 and Figure6-8, respectively. Figure6-7.PLL1 StructureBlock Diagram Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

Post−Div (/1) PLLM PLL BPDIV CLKMODE CLKIN OSCIN PLLEN PLL2_SYSCLK1 (VPSS−VPBE) PLL2_SYSCLK2 (DDR2 PHY) PLL2_SYSCLKBP (DDR2 VTP) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-8.PLL2 StructureBlock Diagram

6.3.1.4 Power and Sleep Controller(PSC) Module

The Power and Sleep Controller(PSC) controlsDM6446 devicepower by turningoffunused power domains orgatingoffclockstoindividualperipherals/modules.The PSC consistsofa GlobalPSC (GPSC) and a setofLocalPSCs (LPSCs).The GPSC containsmemory mapped registers,power domain control, PSC interruptcontrol,and a statemachine foreach peripheral/module.An LPSC isassociatedwitheach peripheral/moduleand providesclockand resetcontrol.The GPSC controlsallofDM6446 ’s LPSCs. The ARM subsystemdoes nothave an LPSC module.ARM sleepmode isaccomplishedthroughthewaitfor interruptinstruction.The LPSCs forDM6446 are shown inTable6-5.The PSC registermemory map is givenin Table 6-6. For more detailson the PSC, see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ). Table6-5.DM6446 LPSC Assignments LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE LPSC PERIPHERAL/MODULE NUMBER NUMBER NUMBER

0 VPSS DMA 14 EMIFA 28 TIMER1

1 VPSS MMR 15 MMC/SD/SDIO 29 Reserved

2 EDMA3CC 16 Reserved 30 Reserved

3 EDMA3TC0 17 ASP 31 Reserved

4 EDMA3TC1 18 I2C 32 Reserved

5 EMAC 19 UART0 33 Reserved

6 EMAC Memory Controller 20 UART1 34 Reserved

7 MDIO 21 UART2 35 Reserved

8 Reserved 22 SPI 36 Reserved

9 USB 23 PWM0 37 Reserved

10 ATA/CF 24 PWM1 38 Reserved

11 VLYNQ 25 PWM2 39 C64x+ CPU

12 HPI 26 GPIO 40 VICP

13 DDR2 Memory Controller 27 TIMER0

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-6.PSC RegisterMemory Map REGISTERHEX ADDRESS RANGE DESCRIPTIONACRONYM 0x01C4 1000 PID PeripheralRevisionand ClassInformationRegister 0x01C4 1004 -0x01C4 1014 - Reserved 0x01C4 1018 INTEVAL InterruptEvaluationRegister 0x01C4 101C -0x01C4 103F - Reserved 0x01C4 1040 MERRPR0 Module ErrorPending0 (mod 0 -31)Register 0x01C4 1044 MERRPR1 Module ErrorPending1 (mod 32-63)Register 0x01C4 1048 -0x01C4 104F - Reserved 0x01C4 1050 MERRCR0 Module ErrorClear0 (mod 0 -31)Register 0x01C4 1054 MERRCR1 Module ErrorClear1 (mod 32 -63)Register 0x01C4 1058 -0x01C4 105F - Reserved 0x01C4 1060 PERRPR Power ErrorPendingRegister 0x01C4 1064 -0x01C4 1067 - Reserved 0x01C4 1068 PERRCR Power ErrorClearRegister 0x01C4 106C -0x01C4 106F - Reserved 0x01C4 1070 EPCPR ExternalPower ErrorPendingRegister 0x01C4 1074 -0x01C4 1077 - Reserved 0x01C4 1078 EPCCR ExternalPower ControlClearRegister 0x01C4 107C -0x01C4 111F - Reserved 0x01C4 1120 PTCMD Power Domain TransitionCommand Register 0x01C4 1124 -0x01C4 1127 - Reserved 0x01C4 1128 PTSTAT Power Domain TransitionStatusRegister 0x01C4 112C -0x01C4 11FF - Reserved 0x01C4 1200 PDSTAT0 Power Domain Status0 Register(AlwaysOn) 0x01C4 1204 PDSTAT1 Power Domain Status1 Register(DSP) 0x01C4 1208 -0x01C4 12FF - Reserved 0x01C4 1300 PDCTL0 Power Domain Control0 Register(AlwaysOn) 0x01C4 1304 PDCTL1 Power Domain Control1 Register(DSP) 0x01C4 1308 -0x01C4 17FF - Reserved 0x01C4 1800 MDSTAT0 Module Status0 Register(VPSS DMA) 0x01C4 1804 MDSTAT1 Module Status1 Register(VPSS MMR) 0x01C4 1808 MDSTAT2 Module Status2 Register(EDMA3CC) 0x01C4 180C MDSTAT3 Module Status3 Register(EDMA3TC0) 0x01C4 1810 MDSTAT4 Module Status4 Register(EDMA3TC1) 0x01C4 1814 MDSTAT5 Module Status5 Register(EMAC) 0x01C4 1818 MDSTAT6 Module Status6 Register(EMAC Memory Controller) 0x01C4 181C MDSTAT7 Module Status7 Register(MDIO) 0x01C4 1820 Reserved 0x01C4 1824 MDSTAT9 Module Status9 Register(USB) 0x01C4 1828 MDSTAT10 Module Status10 Register(ATA/CF) 0x01C4 182C MDSTAT11 Module Status11 Register(VLYNQ) 0x01C4 1830 MDSTAT12 Module Status12 Register(HPI) 0x01C4 1834 MDSTAT13 Module Status13 Register(DDR2) 0x01C4 1838 MDSTAT14 Module Status14 Register(EMIFA) 0x01C4 183C MDSTAT15 Module Status15 Register(MMC/SD/SDIO) 0x01C4 1840 Reserved 0x01C4 1844 MDSTAT17 Module Status17 Register(ASP) 0x01C4 1848 MDSTAT18 Module Status18 Register(I2C) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-6.PSC RegisterMemory Map (continued) REGISTERHEX ADDRESS RANGE DESCRIPTIONACRONYM 0x01C4 184C MDSTAT19 Module Status19 Register(UART0) 0x01C4 1850 MDSTAT20 Module Status20 Register(UART1) 0x01C4 1854 MDSTAT21 Module Status21 Register(UART2) 0x01C4 1858 MDSTAT22 Module Status22 Register(SPI) 0x01C4 185C MDSTAT23 Module Status23 Register(PWM0) 0x01C4 1860 MDSTAT24 Module Status24 Register(PWM1) 0x01C4 1864 MDSTAT25 Module Status25 Register(PWM2) 0x01C4 1868 MDSTAT26 Module Status26 Register(GPIO) 0x01C4 186C MDSTAT27 Module Status27 Register(TIMER0) 0x01C4 1870 MDSTAT28 Module Status28 Register(TIMER1) 0x01C4 1874 -0x01C4 189B - Reserved 0x01C4 189C MDSTAT39 Module Status39 Register(C64x+ CPU) 0x01C4 18A0 MDSTAT40 Module Status40 Register(VICP) 0x01C4 18A4 -0x01C4 19FF - Reserved 0x01C4 1A00 MDCTL0 Module Control0 Register(VPSS DMA) 0x01C4 1A04 MDCTL1 Module Control1 Register(VPSS MMR) 0x01C4 1A08 MDCTL2 Module Control2 Register(EDMA3CC) 0x01C4 1A0C MDCTL3 Module Control3 Register(EDMA3TC0) 0x01C4 1A10 MDCTL4 Module Control4 Register(EDMA3TC1) 0x01C4 1A14 MDCTL5 Module Control5 Register(EMAC) 0x01C4 1A18 MDCTL6 Module Control6 Register(EMAC Memory Controller) 0x01C4 1A1C MDCTL7 Module Control7 Register(MDIO) 0x01C4 1A20 Reserved 0x01C4 1A24 MDCTL9 Module Control9 Register(USB) 0x01C4 1A28 MDCTL10 Module Control10 Register(ATA/CF) 0x01C4 1A2C MDCTL11 Module Control11 Register(VLYNQ) 0x01C4 1A30 MDCTL12 Module Control12 Register(HPI) 0x01C4 1A34 MDCTL13 Module Control13 Register(DDR2) 0x01C4 1A38 MDCTL14 Module Control14 Register(EMIFA) 0x01C4 1A3C MDCTL15 Module Control15 Register(MMC/SD/SDIO) 0x01C4 1A40 Reserved 0x01C4 1A44 MDCTL17 Module Control17 Register(ASP) 0x01C4 1A48 MDCTL18 Module Control18 Register(I2C) 0x01C4 1A4C MDCTL19 Module Control19 Register(UART0) 0x01C4 1A50 MDCTL20 Module Control20 Register(UART1) 0x01C4 1A54 MDCTL21 Module Control21 Register(UART2) 0x01C4 1A58 MDCTL22 Module Control22 Register(SPI) 0x01C4 1A5C MDCTL23 Module Control23 Register(PWM0) 0x01C4 1A60 MDCTL24 Module Control24 Register(PWM1) 0x01C4 1A64 MDCTL25 Module Control25 Register(PWM2) 0x01C4 1A68 MDCTL26 Module Control26 Register(GPIO) 0x01C4 1A6C MDCTL27 Module Control27 Register(TIMER0) 0x01C4 1A70 MDCTL28 Module Control28 Register(TIMER1) 0x01C4 1A74 -0x01C4 1A9B - Reserved 0x01C4 1A9C MDCTL39 Module Control39 Register(C64x+ CPU) 0x01C4 1AA0 MDCTL40 Module Control40 Register(VICP) 0x01C4 1AA4 -0x01C4 1FFF - Reserved

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-6.PSC RegisterMemory Map (continued) REGISTERHEX ADDRESS RANGE DESCRIPTIONACRONYM 0x01C4 1000 MPFAR Memory ProtectionFaultAddressRegister 0x01C4 1004 MPFSR Memory ProtectionFaultStatusRegister 0x01C4 1008 MPFCR Memory ProtectionFaultCommand Register 0x01C4 100C MPAA Memory ProtectionPage AttributeRegister 0x01C4 1010 -0x01C4 1FFF - Reserved

6.4 Reset

DM6446 supportsvarioustypesofresets.Power-on-reset(POR), warm reset,max reset,system reset, C64x+ localreset,and module resetaresummarized inTable6-7. Table6-7.DM6446 Resets Type Initiator Description Power-on-reset(POR) RESET pinactivelowwhileTRST islow. Globalchipreset(Coldreset).ActivatesthePOR signal on chip,whichisused toresettestand emulationlogic. Warm reset RESET pinactivelowwhileTRST ishigh. Resetseverythingexceptfortestand emulationlogic. ARM emulatorstaysaliveduringwarm reset,butthe C64x+ emulatordoes not. Maximum reset Emulator,WD Timer Same as Warm reset,exceptforinitiators. C64x+ Localreset Software(registerbit) MMR controlstheC64x+ resetinput.Thisisused for controlofC64x+ resetby theARM. The C64x+ Slave DMA portisstillalivewhen inlocalreset. Power-on-reset(POR) isthe globalchipresetand itaffectstest,emulation,and othercircuitry.Itis invokedby drivingtheRESET pinactivelow whileTRST isheldlow.A POR isrequiredtoplaceDM6446 intoa known good initialstate.POR can be assertedpriortorampingthecoreand I/Ovoltagesor after the core and I/Ovoltageshave reached theirproperoperatingconditions.As a bestpractice,RESET shouldbe asserted(heldlow)duringpower-up.Priorto deassertingRESET (low-to-hightransition),the coreand I/Ovoltagesshouldbe attheirproperoperatingconditionsand ifan external27 MHz oscillatoris used on theMXI/CLKIN pin,theexternalclockshouldalsobe runningatthecorrectfrequency. Warm resetisactivatedby drivingtheRESET pinactivelow,whileTRST isinactivehigh.Thisdoes not resettestor ARM emulationlogic.An ARM emulatorsessionwillstayaliveduringwarm reset,but a C64x+ emulatorsessionwillnot. Maximum resetisinitiatedby theemulatororthewatchdog timerand thereseteffectsarethesame as a warm reset.The emulatorinitiatesa maximum resetviatheICEPICK module.When thewatchdog timer counterreacheszero,thiswillinitiatea maximum resettorecoverfroma runaway condition.Both ofthe maximum resetinitiatorscan be masked by theARM emulator. System resetisinitiatedby the emulatorand isa softreset.Memory contentsare maintained.Test, emulation,clock,and power controllogicare unaffected.The emulatorinitiatesa system resetviathe C64x+ emulationlogic,orthroughICECRUSHER. Bothoftheseresetinitiatorsarenon-maskableresets. The C64x+ DSP has an internalresetinputthatallowsa hosttocontrolit.Thisresetisconfiguredthrough a MMR bit(MDCTL[39].LRSTz)inthePSC module.When inC64x+ localreset,theslaveDMA porton C64x+ willremainactiveand theinternalmemory willbe accessible,includingaccesstotheVICP memory throughtheL2 port(UMAP port). For detailson resetcontrol/statusregisters,see theTMS320DM644x DMSoC ARM Subsystem Reference Guide (literaturenumber SPRUE14 ). Forinformationon peripheralselectionattherisingedge ofRESET, see Section3,DeviceConfigurations, ofthisdatamanual. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 97 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.4.1 Reset ElectricalData/Timing

Table6-8.Timing Requirements forReset (seeFigure6-9) A-513, -594, NO. UNIT-810 MIN MAX 1 tw(RST) WidthoftheRESET pulse 444 ns 2 tsu(BOOT) Setuptime,bootconfigurationbitsvalidbeforeRESET high 444 ns 3 th(BOOT) Holdtime,bootconfigurationbitsvalidafterRESET high 444 ns Table6-9.SwitchingCharacteristicsOver Recommended OperatingConditionsDuring Reset(1) (seeFigure6-9) A-513, -594, NO. UNIT-810 MIN MAX 26 td(PLL_LOCK) Delaytime,PLL1 locktime 2000P ns 4 td(RSTL-DDRZZ) Delaytime,RESET lowtoDDR2 Z Group highimpedance 0 2P + 20 ns 5 td(RSTL-DDRLL) Delaytime,RESET lowtoDDR2 Low Group low 0 20 ns 6 td(RSTL-DDRHH) Delaytime,RESET lowtoDDR2 HighGroup high 0 20 ns 16 td(RSTL-DDRZHZ) Delaytime,RESET lowtoDDR2 Z/HighGroup highimpedance 0 5P + 20 ns 17 td(RSTL-DDRLHL) Delaytime,RESET lowtoDDR2 Low/HighGroup low 0 20 ns 7 td(RSTL-ZZ) Delaytime,RESET lowtoZ Group highimpedance 0 20 ns 8 td(RSTL-LOWL) Delaytime,RESET lowtoLow Group low 0 20 ns 9 td(RSTL-HIGHH) Delaytime,RESET lowtoHighGroup high 0 20 ns 18 td(RSTL-HIGHLOWH) Delaytime,RESET lowtoHigh/LowGroup high 0 20 ns 19 td(RSTL-LOWHIGHL) Delaytime,RESET lowtoLow/HighGroup low 0 20 ns 24 td(RSTL-ZIZ) Delaytime,RESET lowtoZ/InvalidGroup highimpedance 0 20 ns 10 td(RSTH-DDRZV) Delaytime,RESET hightoDDR2 Z Group valid (2) ns 11 td(RSTH-DDRLV) Delaytime,RESET hightoDDR2 Low Group valid (2) ns 12 td(RSTH-DDRHV) Delaytime,RESET hightoDDR2 HighGroup valid (2) ns 20 td(RSTH-DDRZHV) Delaytime,RESET hightoDDR2 Z/HighGroup validhigh 4000P ns 21 td(RSTH-DDRLHV) Delaytime,RESET hightoDDR2 Low/HighGroup validhigh 4000P ns 13 td(RSTH-ZV) Delaytime,RESET hightoZ Group valid (2) ns 14 td(RSTH-LOWV) Delaytime,RESET hightoLow Group valid (2) ns 15 td(RSTH-HIGHV) Delaytime,RESET hightoHighGroup valid (2) ns 22 td(RSTH-HIGHLOWV) Delaytime,RESET hightoHigh/LowGroup validlow 5100P ns 23 td(RSTH-LOWHIGHV) Delaytime,RESET hightoLow/HighGroup validhigh 5100P ns 25 td(RSTH-ZIIV) Delaytime,RESET hightoZ/InvalidGroup invalid 4000P ns (1) P = MXI/CLKIN cycletime,inns. (2) FollowingRESET high,thissignalgroupmaintainsthestatethepins(s)achievedwhileRESET was drivenlowuntiltheperipheralis enabledviathePSC. Forexample,theDDR2 Z Group goes highimpedance followingRESET lowand remainsinthehigh-impedance statefollowingRESET highuntiltheDDR2 controllerisenabledviathePSC.

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A. DDR2 Z Group: DDR_DQS[3:0], DDR_D[12:0] High Group: DMACK/UART_TXD1, EM_A[2]/(CLE), EM_A[1]/(ALE), , /( )/( )/EM_CS3 EM_WE WE IOWR DIOW Low Group: DMARQ/UART_RXD1, VCLK, RTCK, TDO, VPBECLK, YOUT0/G5/AEAW0, YOUT1/G6/AEAW1, YOUT2/G7/AEAW2, YOUT3/R3/AEAW3, YOUT4/R4/AEAW4, COUT3/B6/DSP_BT, COUT2/B5/EM_WIDTH, COUT1/B4/BTSEL1, COUT0/B3/BTSEL0, TRST DDR2 Low/High Group: DDR_BS[2:0] DDR2 Z/High Group: DDR_DQM[3:0] DDR2 High Group: DDR_CLK0 DDR_CS DDR_WE DDR_RAS DDR_CAS, , , , DDR2 Low Group: DDR_CLK0, DDR_CKE, DDR_A[12:0] Z/Invalid Group: EM_D[15:0] Low/High Group: EM_R/ /INTRQW High/Low Group: EM_BA[0]/DA0, , /( )/( )/EM_CS2 EM_OE RE IORD DIOR Z Group: All other pins not listed above, with the exception of power and ground pins.

• The following Z Group pins have an internal pullup (IPU): DMARQ/UART_RXD1, VPBECLK, HSYNC, VSYNC, , YI/CCD[7:0], CI[3:0]/CCD[11:8], CI4/CCD12/UART_RTS2, CI5/CCD13/UART_CTS2, CI6/CCD14/UART_TXD2, CI7/CCD15/UART_RXD2 TRST
• The following Z Group pins have an internal pulldown (IPD): EM_WAIT/ , TCK, TDI, TMS, EMU[1:0]IORDY RESET Boot Configuration Pins DDR2 Low Group (A) DDR2 Z Group (A) DDR2 High Group (A) DDR2 Low/High Group (A) DDR2 Z/High Group (A) Low Group (A) Z Group (A) High Group (A) High/Low Group (A) Low/High Group (A) Z/Invalid Group (A) TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-9.Reset Timing Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

1.8 V MXV DD RBIAS (optional) C L /C0043C 1C 2 (C 1 /C0041C 2) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

6.5 ExternalClock InputFrom MXI/CLKIN Pin

The DM6446 device has two inputpins foran externalclocksource,MXI/CLKIN and M24XI. The MXI/CLKIN pinprovidestheclocksourceforPLL1 and PLL2 whose optimalfrequencyis27 MHz. The M24XI pinprovidestheclocksourcefortheUSB PLL whose optimalfrequencyis24 MHz. The DM6446 deviceincludestwo optionstoprovidean externalclockinput: 1. Use an on-chiposcillatorwithexternalcrystalorceramicresonatorcircuit(onlysupporting parallel-resonantmode; itdoes notprovideovertonesupport).Formore details,see Section6.5.1, ClockInputOption1 – Crystal. InputOption2 – 1.8-VLVCMOS-Compatible ClockInput.

6.5.1 Clock InputOption 1 – Crystal

6.5.1.1 27-MHz CrystalforSystem Oscillator Inthisoption,a crystalisused as theexternalclockinputtotheDM6446 PLL1 and PLL2. The 27-MHz oscillatorprovidesthe referenceclockforallDM6446 subsystems and peripherals.The on-chiposcillatorrequiresan external27-MHz crystalconnectedacrossthe MXI and MXO pins,along with two load capacitors,as shown in Figure6-10. The externalcrystalload capacitorsmust be connectedonlytothe27-MHz oscillatorgroundpin(MXV SS ).Do not connecttoboardground(VSS ).The MXV DD pincan be connectedtothesame 1.8V power supplyas DV DD18 . Figure6-10.27-MHz System Oscillator The RBIAS resistoris optional.Ifthe RBIAS resistoris used, itshould equal 1 M Ω ±5%. The load capacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesareC1 = C2 = 10 pF).C L intheequationistheloadspecifiedby thecrystalmanufacturer.Alldiscretecomponents used toimplementtheoscillatorcircuitshouldbe placedas closeas possibletotheassociatedoscillatorpins (MXI and MXO) and totheMXV SS pin.

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M24XI M24XO M24V SS M24V DD C1 C2 Crystal 1.8 V RBIAS (optional) C L /C0043C 1C 2 (C 1 /C0041C 2) TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-10.CrystalRequirements fora 27-MHz System Oscillator PARAMETER MIN TYP MAX UNIT Start-uptime(frompower up untiloscillatingatstablefrequencyof27 MHz) 4 ms Oscillationfrequency 27 MHz ESR 60 Ω Frequencystability ±50 ppm 6.5.1.2 24-MHz CrystalforUSB Oscillator Inthisoption,a crystalisused as theexternalclockinputtotheDM6446 USB PLL. The 24-MHz oscillatorprovidesthereferenceclockfortheDM6446 USB peripheral.The on-chiposcillator requiresan external24-MHz crystalconnectedacrosstheM24XI and M24XO pins,alongwithtwo load capacitors,as shown inFigure6-11.The externalcrystalloadcapacitorsmust be connectedonlytothe 24-MHz oscillatorgroundpin(M24V SS ).Do not connecttoboardground(VSS ). Figure6-11.24-MHz USB Oscillator The RBIAS resistoris optional.Ifthe RBIAS resistoris used, itshould equal 1 M Ω ±5%. The load capacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesareC1 = C2 = 10 pF).C L intheequationistheloadspecifiedby thecrystalmanufacturer.Alldiscretecomponents used toimplementtheoscillatorcircuitshouldbe placedas closeas possibletotheassociatedoscillatorpins (M24XI and M24XO) and totheM24XV SS pin. Table6-11.CrystalRequirements fora 24-MHz USB Oscillator PARAMETER MIN TYP MAX UNIT Start-uptime(frompower up untiloscillatingatstablefrequencyof24 MHz) 4 ms Oscillationfrequency 24 MHz ESR 60 Ω Frequencystability ±50 ppm Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 101 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

1.8□V MXVDD TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.5.2 Clock InputOption 2 – 1.8-VLVCMOS-Compatible Clock Input Inthisoption,a 1.8-VLVCMOS-compatible clockinputisused as theexternalclockinputtotheDM6446 device.The externalconnectionsareshown inFigure6-12.The MXI/CLKIN pinisconnectedtothe1.8-V LVCMOS-compatible clocksource.The MXO pin isleftunconnected.The MXV SS pin isconnectedto board ground (VSS ).The MXV DD pincan be connectedtothesame 1.8-Vpower supplyas DV DD18 .The clocksourcemust meet theMXI/CLKIN timingrequirementsshown inTable6-16,TimingRequirements forMXI/CLKIN. Figure6-12.1.8-VLVCMOS-Compatible Clock Input Figure6-12alsoappliestotheUSB externalclockinput.When a 1.8-VLVCMOS-compatible clockinputis used as the externalclockinput,the M24XI pin isconnectedto the 1.8-VLVCMOS-compatible clock source.The M24XO pinisleftunconnected.The M24V SS pinisconnectedto board ground (VSS ).The M24V DD pincan be connectedtothesame 1.8-Vpower supplyas DV DDR2 .The clocksourcemust meet theMXI/CLKIN timingrequirementsshown inTable6-17,TimingRequirementsforM24XI (-594)Devices.

6.6 Clock PLLs

Therearetwo independentlycontrolledPLLs on DM6446. PLL1 generatesthefrequenciesrequiredforthe DSP, ARM, VICP, DMA, VPFE, and otherperipherals.PLL2 generatesthefrequenciesrequiredforthe DDR2 interfaceand theVPBE incertainmodes. The recommended referenceclockforbothPLLs isthe 27-MHz crystalinput.The USB2.0 PHY containsa thirdPLL embedded withinitand the24-MHz oscillator isitsreferenceclocksource.ThisparticularPLL isonlyusableforUSB operation,and isdiscussedfurther inthe TMS320DM644x DMSoC UniversalSerialBus (USB) ControllerUser'sGuide (literaturenumber SPRUE35 ). A summary of the PLL controllerregistersis shown in Table 6-12. For more details,see the TMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ). Table6-12.PLL and Reset ControllerRegistersMemory Map HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION PLL1 ControllerRegisters 0x01C4 0800 PID PeripheralIdentificationand RevisionInformationRegister 0x01C4 08E4 RSTYPE ResetType Register 0x01C4 0900 PLLC PLL Controller1 OperationsControlRegister 0x01C4 0910 PLLM PLL Controller1 MultiplierControlRegister 0x01C4 0918 PLLDIV1 PLL Controller1 Control-Divider1 Register(SYSCLK1) 0x01C4 091C PLLDIV2 PLL Controller1 Control-Divider2 Register(SYSCLK2) 0x01C4 0920 PLLDIV3 PLL Controller1 Control-Divider3 Register(SYSCLK3) 0x01C4 0928 POSTDIV PLL Controller1 Post-DividerControlRegister 0x01C4 092C BPDIV PLL Controller1 Bypass Control-DividerRegister(SYSCLKBP) 0x01C4 0938 PLLCMD PLL Controller1 Command Register 0x01C4 093C PLLSTAT PLL Controller1 StatusRegister(Shows PLLCTRL Status)

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-12.PLL and Reset ControllerRegistersMemory Map (continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION PLL Controller1 AlignmentControlRegister0x01C4 0940 ALNCTL (IndicatesWhich SYSCLKs Need tobe AlignedforProperDeviceOperation) PLL Controller1 DividerChange Register0x01C4 0944 DCHANGE (IndicatesifSYSCLK DivideRatiohas Been Modified) 0x01C4 0948 CKEN PLL Controller1 ClockEnableRegister 0x01C4 094C CKSTAT PLL Controller1 ClockStatusRegister(ForAllClocksExceptSYSCLKx) 0x01C4 0950 PLL Controller1 System ClockStatus1 Register(IndicatesSYSCLK on/offSYSTAT Status) 0x01C4 0960 PLLDIV4 PLL Controller1 Control-Divider4 Register(SYSCLK4) 0x01C4 0964 PLLDIV5 PLL Controller1 Control-Divider5 Register(SYSCLK5) 0x01C4 0C00 PID PeripheralIdentificationand RevisionInformationRegister 0x01C4 0D00 PLLC PLL Controller2 OperationsControlRegister 0x01C4 0D10 PLLM PLL Controller2 MultiplierControlRegister 0x01C4 0D18 PLLDIV1 PLL Controller2 Control-Divider1 Register(SYSCLK1) 0x01C4 0D1C PLLDIV2 PLL Controller2 Control-Divider2 Register(SYSCLK2) 0x01C4 0D20 -0x01C4 0D2B POSTDIV PLL Controller2 Post-DividerControlRegister 0x01C4 0D2C BPDIV PLL Controller2 Bypass Control-DividerRegister(SYSCLKBP) 0x01C4 0D38 PLLCMD PLL Controller2 Command Register 0x01C4 0D3C PLLSTAT PLL Controller2 StatusRegister(Shows PLLCTRL Status) PLL Controller2 AlignmentControlRegister0x01C4 0D40 ALNCTL (IndicatesWhich SYSCLKs Need tobe AlignedforProperDeviceOperation) PLL Controller2 DividerChange Register0x01C4 0D44 DCHANGE (IndicatesifSYSCLK DivideRatiohas Been Modified) 0x01C4 0D48 CKEN PLL Controller2 ClockEnableRegister 0x01C4 0D4C CKSTAT PLL Controller2 ClockStatusRegister(ForAllClocksExceptSYSCLKx) 0x01C4 0D50 SYSTAT PLL Controller2 System ClockStatus1 Register(IndicatesSYSCLK on/off Status)

6.6.1 PLL1 and PLL2

Both PLL1 and PLL2 power issuppliedexternallyviathe 1.8 V PLL power-supplypin(PLLVDD18 ).Itis recommended thatan externalEMI filtercircuitbe added toPLLV DD18 ,as shown inFigure6-13.The 1.8-V supplyof the EMI filtermust be from the same 1.8-Vpower plane supplyingthe device’s 1.8-VI/O power-supply pins (DVDD ). TI recommends EMI filtermanufacturer Murata, part number NFM18CC222R1C3. AllPLL externalcomponents (C1,C2, and the EMI Filter)should be placedas closeto the deviceas possible.For thebestperformance,TIrecommends thatallthePLL externalcomponents be on a single sideoftheboardwithoutjumpers,switches,orcomponents otherthantheones shown inFigure6-13.For reduced PLL jitter,maximize the spacingbetween switchingsignalsand the PLL externalcomponents (C1,C2, and theEMI Filter). Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 103 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

EMI□Filter +1.8□V DM644x PLL2 PLL1 0.1□µF 0.01□µF TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-13.PLL1 and PLL2 ExternalConnection The minimum CLKIN riseand falltimesshouldalsobe observed.For theinputclocktimingrequirements, see Section6.6.3,ClockPLL ElectricalData/Timing(Inputand OutputClocks). There isan allowablerange forPLL multiplier(PLLM). There isa minimum and maximum operating frequencyforMXI/CLKIN, PLLOUT, and the deviceclocks(SYSCLKs). The PLL Controllersmust be configurednot to exceed any of theseconstraintsdocumented inthissection(certaincombinationsof externalclockinputs,internaldividers,and PLL multiplyratiosmightnotbe supported). Table6-13.PLLC1 Clock Frequency Ranges CLOCK SIGNAL NAME MIN MAX UNIT MXI/CLKIN(1) 20 30 MHz At1.2-VCV DD 400 600 MHz PLLOUT At1.3-VCV DD (-810only) 400 810 MHz -594(commercialtemp) 600 MHz SYSCLK1 (CLKDIV1 Domain) -810(commercialtemp) 810 MHz A-513 (extendedtemp) 513 MHz (1) MXI/CLKIN inputclockisused forbothPLL Controllers(PLLC1 and PLLC2). Table6-14.PLLC2 Clock Frequency Ranges CLOCK SIGNAL NAME MIN MAX UNIT MXI/CLKIN(1) 20 30 MHz At1.2-VCV DD 400 900 MHz PLLOUT At1.3-VCV DD (-810only) 400 900 MHz (1) MXI/CLKIN inputclockisused forbothPLL Controllers(PLLC1 and PLLC2). BothPLL1 and PLL2 have stabilization,lock,and resettimingrequirementsthatmust be followed. The PLL stabilizationtimeistheamount oftimethatmust be allottedfortheinternalPLL regulatorsto become stableafterthe PLL is powered up (afterPLLCTL.PLLPWRDN bitgoes througha 1-to-0 transition).The PLL shouldnotbe operateduntilthisstabilizationtimehas expired.Thisstabilizationstep must be appliedafterthese resets— a Power-on Reset, a Warm Reset, or a Max Reset, as the PLLCTL.PLLPWRDN bitresetstoa "1".ForthePLL stabliziationtimevalue,see Table6-15. The PLL resettimeistheamount ofwaittimeneeded forthePLL toproperlyreset(writingPLLRST = 0) beforebringingthePLL outofreset(writingPLLRST = 1).ForthePLL resettimevalue,see Table6-15.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 The PLL locktimeistheamount oftimeneeded from when thePLL istakenoutofreset(PLLRST = 1 withPLLEN = 0)towhen towhen thePLL controllercan be switchedtoPLL mode (PLLEN = 1).For the PLL locktimevalue,see Table6-15. Table6-15.PLL1 and PLL2 Stabilization,Lock,and Reset Times PLL STABILIZATION/LOCK/RESET TIME MIN TYP MAX UNIT PLL StabilizationTime 150 ms PLL Lock Time 2000C (1) ns PLL ResetTime 128C (1) ns (1) C = CLKIN cycletimeinns.Forexample,when MXI/CLKIN frequencyis27 MHz, use C = 37.037 ns. Fordetailson thePLL initializationsoftwaresequence,see theTMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ).

6.6.2 Clock PLL ConsiderationswithExternalClock Sources

Iftheinternaloscillatorisbypassed,tominimizetheclockjittera singlecleanpower supplyshouldpower boththeDM6446 deviceand theexternalclockoscillatorcircuit.The minimum CLKIN riseand falltimes shouldalsobe observed.For theinputclocktimingrequirements,see Section6.6.3,ClockPLL Electrical Data/Timing(Inputand OutputClocks). Rise/falltimes,duty cycles(high/lowpulsedurations),and the load capacitanceof the externalclock sourcemust meet thedevicerequirementsinthisdatamanual (seeSection5.3,ElectricalCharacteristics Over Recommended Ranges of Supply Voltageand OperatingCase Temperature, and Section6.6.3, ClockPLL ElectricalData/Timing(Inputand OutputClocks).

6.6.3 Clock PLL ElectricalData/Timing(Inputand Output Clocks)

Table6-16.Timing Requirements forMXI/CLKIN (-594)Devices(1)(2)(3)(4)(seeFigure6-14) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(MXI) Cycletime,MXI/CLKIN 33.3 50 ns 2 tw(MXIH) Pulseduration,MXI/CLKIN high 0.45C 0.55C ns 3 tw(MXIL) Pulseduration,MXI/CLKIN low 0.45C 0.55C ns 4 tt(MXI) Transitiontime,MXI/CLKIN 0.05C ns 5 tJ(MXI) Periodjitter,MXI/CLKIN 0.02C ns (1) The MXI/CLKIN frequencyand PLL multiplyfactorshouldbe chosen such thattheresultingclockfrequencyiswithinthespecificrange forCPU operatingfrequency.Forexample,fora -594speed devicewitha 27 MHz CLKIN frequency,thePLL multiplyfactorshouldbe ≤ 22.Forexample,fora -810speed devicewitha 27 MHz CLKIN frequency,thePLL multiplyfactorshouldbe ≤ 30. (2) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (3) Formore detailson thePLL multiplierfactors,see theTMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ). (4) C = CLKIN cycletimeinns.Forexample,when MXI/CLKIN frequencyis27 MHz, use C = 37.037 ns. Figure6-14.MXI/CLKIN Timing Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 105 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-17.Timing Requirements forM24XI (-594)Devices(1)(2)(3)(seeFigure6-15) A-513, NO. -594, UNIT -810 MIN TYP MAX 1 tc(M24XI) Cycletime,M24XI 41.6 ns 2 tw(M24XIH) Pulseduration,M24XI high 0.45C 0.55C ns 3 tw(M24XIL) Pulseduration,M24XI low 0.45C 0.55C ns 4 tt(M24XI) Transitiontime,M24XI 0.05C ns 5 tJ(M24XI) Periodjitter,M24XI 0.02C ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (2) Formore detailson thePLL,see theTMS320DM644x DMSoC UniversalSerialBus (USB) ControllerUser's Guide (literaturenumber SPRUE35 ). (3) C = M24XI cycletimeinns.Forexample,when M24XI frequencyis24 MHz, use C = 41.6 ns. Figure6-15.M24XI Timing

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CLK_OUT0 (Divide-by-1) 2 4 CLKIN/MXI CLK_OUT0 (Divide-by-2) 5 6 7 8 TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-18.SwitchingCharacteristicsOver Recommended OperatingConditionsforCLK_OUT0 (1)(2) (seeFigure6-16) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 1 tC Cycletime,CLK_OUT0 37.037 74.074 ns 2 tw(CLKOUT0H) Pulseduration,CLK_OUT0 high 0.45P 0.55P ns 3 tw(CLKOUT0L) Pulseduration,CLK_OUT0 low 0.45P 0.55P ns 4 tt(CLKOUT0) Transitiontime,CLK_OUT0 0.05P ns 5 td(CLKINH-CLKO0H) Delaytime,CLKIN/MXI hightoCLK_OUT0 high(divide-by-1only) 1 8 ns 6 td(CLKINL-CLKO0L) Delaytime,CLKIN/MXI lowtoCLK_OUT0 low(divide-by-1only) 1 8 ns 7 td(CLKINH-CLKO0L) Delaytime,CLKIN/MXI hightoCLK_OUT0 low(divide-by-2only) 1 8 ns 8 td(CLKINH-CLKO0H) Delaytime,CLKIN/MXI hightoCLK_OUT0 high(divide-by-2only) 1 8 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) P = 1/CLK_OUT0 clockfrequencyinnanoseconds(ns).Forexample,when CLK_OUT0 frequencyis27 MHz, use P = 37.04ns. Figure6-16.CLK_OUT0 Timing Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 107 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

CLK_OUT1 (Divide-by-1) 2 4 CLKIN/MXI CLK_OUT1 (Divide-by-2) 5 6 7 8 TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-19.SwitchingCharacteristicsOver Recommended OperatingConditionsforCLK_OUT1 (1)(2) (seeFigure6-17) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 1 tc Cycletime,CLK_OUT1 41.667 83.33 ns 2 tw(CLKOUT1H) Pulseduration,CLK_OUT1 high 0.45P 0.55P ns 3 tw(CLKOUT1L) Pulseduration,CLK_OUT1 low 0.45P 0.55P ns 4 tt(CLKOUT1) Transitiontime,CLK_OUT1 0.05P ns 5 td(CLKINH-CLKO1H) Delaytime,CLKIN/MXI hightoCLK_OUT1 high(divide-by-1only) 1 8 ns 6 td(CLKINL-CLKO1L) Delaytime,CLKIN/MXI lowtoCLK_OUT1 low(divide-by-1only) 1 8 ns 7 td(CLKINH-CLKO1L) Delaytime,CLKIN/MXI hightoCLK_OUT1 low(divide-by-2only) 1 8 ns 8 td(CLKINH-CLKO1H) Delaytime,CLKIN/MXI hightoCLK_OUT1 high(divide-by-2only) 1 8 ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) P = 1/CLK_OUT1 clockfrequencyinnanoseconds(ns).Forexample,when CLK_OUT1 frequencyis24 MHz, use P = 41.6 ns. Figure6-17.CLK_OUT1 Timing

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010

6.7 Interrupts

The DM6446 devicehas a largenumber of interruptsto servicethe needs of itsmany peripheralsand subsystems.Both the ARM and C64x+ are capable of servicingthese interrupts.Allof the device interruptsare routedtotheARM interruptcontrollerwithonlya limitedsetroutedtotheC64x+ interrupt controller.The interruptscan be selectivelyenabled or disabledin eitherof the controllers.In typical applications,the ARM handlesmost of the peripheralinterruptsand grantscontrol,to the C64x+, of interruptsthatarerelevanttoDSP algorithms.Also,theARM and DSP can communicate witheach other throughinterrupts.

6.7.1 ARM CPU Interrupts

The ARM9 CPU core supports2 directinterrupts:FIQ and IRQ. The DM6446 ARM interruptcontroller prioritizesup to 64 interruptrequestsfrom variousperipheralsand subsystems,which are listedin Table 6-20, and interruptsthe ARM CPU. Each interruptisprogrammable forup to 8 levelsof priority. There are6 levelsforIRQ and 2 levelsforFIQ.Interruptsatthesame prioritylevelareservicedinorder by theARM InterruptNumber, withthelowestnumber havingthehighestpriority.Table6-21 shows the ARM interruptcontrollerregistersand memory locations.For more detailson ARM interruptcontrol,see theTMS320DM644x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUE14 ). Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 109 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-20.DM6446 ARM Interrupts ARM ARM INTERRUPT ACRONYM SOURCE INTERRUPT ACRONYM SOURCE NUMBER NUMBER

0 VDINT0 VPSS CCDC 0 32 TINT0 Timer0 – TINT12

1 VDINT1 VPSS CCDC 1 33 TINT1 Timer0 – TINT34

2 VDINT2 VPSS CCDC 2 34 TINT2 Timer1 – TINT12

3 HISTINT VPSS Histogram 35 TINT3 Timer1 – TINT34

4 H3AINT VPSS AE/AWB/AF 36 PWMINT0 PWM 0

5 PRVUINT VPSS Previewer 37 PWMINT1 PWM 1

6 RSZINT VPSS Resizer 38 PWMINT2 PWM 2

7 - Reserved 39 I2CINT I2C

8 VENCINT VPSS VPBE 40 UARTINT0 UART 0

9 ASQINT VICP Sqr (ARM int) 41 UARTINT1 UART 1

10 IMXINT VICP IMX 42 UARTINT2 UART 2

11 VLCDINT VICP VLCD 43 SPINT0 SPI

12 - Reserved 44 SPINT1 SPI

13 EMACINT EMAC Memory Controller 45 - Reserved

14 - Reserved 46 DSP2ARM0 DSP ControllertoARM 0 15 - Reserved 47 DSP2ARM1 DSP ControllertoARM 1

16 EDMA3CC_INT0 EDMA3 CC Region0 48 GPIO0 GPIO 0

17 EDMA3CC_ERRINT EDMA3 CC Error 49 GPIO1 GPIO 1

18 EDMA3TC_ERRINT0 EDMA3 TC 0 Error 50 GPIO2 GPIO 2

19 EDMA3TC_ERRINT1 EDMA3 TC 1 Error 51 GPIO3 GPIO 3

20 PSCINT PSC ALLINT 52 GPIO4 GPIO 4

21 - Reserved 53 GPIO5 GPIO 5

22 IDEINT ATA /IDE 54 GPIO6 GPIO 6

23 HPINT HPI 55 GPIO7 GPIO 7

24 ASPXINT ASP Transmit 56 GPIOBNK0 GPIO Bank 0

25 ASPRINT ASP Receive 57 GPIOBNK1 GPIO Bank 1

26 MMCINT MMC 58 GPIOBNK2 GPIO Bank 2

27 SDIOINT SD 59 GPIOBNK3 GPIO Bank 3

28 - Reserved 60 GPIOBNK4 GPIO Bank 4

29 DDRINT DDR2 Memory Controller 61 COMMTX ARMSS

30 EMIFAINT EMIFA 62 COMMRX ARMSS

31 VLQINT VLYNQ 63 EMUINT E2ICE

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-21.ARM InterruptControllerRegisters HEX ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C4 8000 FIQ0 FIQ InterruptStatus0 [InterruptStatusofINT[31:0](IfMapped toFIQ)] 0x01C4 8004 FIQ1 FIQ InterruptStatus1 [InterruptStatusofINT[63:32](IfMapped toFIQ)] 0x01C4 8008 IRQ0 IRQ InterruptStatus0 [InterruptStatusofINT[31:0](IfMapped toIRQ)] 0x01C4 800C IRQ1 IRQ InterruptStatus1 [InterruptStatusofINT[63:32](IfMapped toIRQ)] 0x01C4 8010 FIQENTRY EntryAddress[28:0]forValidFIQ Interrupt 0x01C4 8014 IRQENTRY EntryAddress[28:0]forValidIRQ Interrupt 0x01C4 8018 EINT0 InterruptEnableRegister0 0x01C4 801C EINT1 InterruptEnableRegister1 0x01C4 8020 INCTL InterruptOperationControlRegister 0x01C4 8024 EABASE InterruptEntryTableBase AddressRegister 0x01C4 8028 -0x01C4 802F - Reserved 0x01C4 8030 INTPRI0 Interrupt0-7PrioritySelect 0x01C4 8034 INTPRI1 Interrupt8-15PrioritySelect 0x01C4 8038 INTPRI2 Interrupt16-23PrioritySelect 0x01C4 803C INTPRI3 Interrupt24-31PrioritySelect 0x01C4 8040 INTPRI4 Interrupt32-39PrioritySelect 0x01C4 8044 INTPRI5 Interrupt40-47PrioritySelect 0x01C4 8048 INTPRI6 Interrupt48-55PrioritySelect 0x01C4 804C INTPRI7 Interrupt56-63PrioritySelect 0x01C4 8050 -0x01C4 83FF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 111 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.7.2 DSP Interrupts

The C64x+ DSP interruptcontrollercombines deviceeventsinto12 prioritizedinterrupts.The sourcefor each of the 12 CPU interruptsisuser programmable and islistedin Table 6-22. Also,the interrupt controllercontrolsthe generationof the CPU exception,NMI, and emulationinterrupts.Table 6-23 summarizes the C64x+ interruptcontrollerregistersand memory locations.For more detailson DSP interruptcontrol,see theTMS320DM644x DMSoC DSP Subsystem ReferenceGuide (literaturenumber SPRUE15 ). Table6-22.DM6446 DSP Interrupts DSP DSP INTERRUPT ACRONYM SOURCE INTERRUPT ACRONYM SOURCE NUMBER NUMBER

0 EVT0 C64x+ IntCtl0 64 Reserved

1 EVT1 C64x+ IntCtl1 65 Reserved

2 EVT2 C64x+ IntCtl2 66 Reserved

3 EVT3 C64x+ IntCtl3 67 Reserved

4 TINT0 Timer0 – TINT12 68 Reserved

5 TINT1 Timer0 – TINT34 69 Reserved

6 TINT2 Timer1 – TINT12 70 Reserved

7 TINT3 Timer1 – TINT34 71 Reserved

8 Reserved 72 Reserved

9 EMU_DTDMA C64x+ EMC 73 Reserved

10 Reserved 74 Reserved

11 EMU_RTDXRX C64x+ RTDX 75 Reserved

12 EMU_RTDXTX C64x+ RTDX 76 Reserved

13 IDMAINT0 C64x+ EMC 0 77 Reserved

14 IDMAINT1 C64x+ EMC 1 78 Reserved

15 Reserved 79 Reserved

16 ARM2DSP0 ARM toDSP Controller0 80 Reserved

17 ARM2DSP1 ARM toDSP Controller1 81 Reserved

18 ARM2DSP2 ARM toDSP Controller2 82 Reserved

19 ARM2DSP3 ARM toDSP Controller3 83 Reserved

20 Reserved 84 Reserved

21 Reserved 85 Reserved

22 Reserved 86 Reserved

23 Reserved 87 Reserved

24 Reserved 88 Reserved

25 Reserved 89 Reserved

26 Reserved 90 Reserved

27 Reserved 91 Reserved

28 Reserved 92 Reserved

29 Reserved 93 Reserved

30 Reserved 94 Reserved

31 Reserved 95 Reserved

Reserved INTERR C64x+ InterruptController32 96 Dropped CPU InterruptEvent Reserved EMC_IDMAERR C64x+ EMC InvalidIDMA33 97 Parameters

34 Reserved 98 Reserved

35 Reserved 99 Reserved

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-22.DM6446 DSP Interrupts(continued) DSP DSP INTERRUPT ACRONYM SOURCE INTERRUPT ACRONYM SOURCE NUMBER NUMBER EDMA3CC_INT1 EDMA3 CC Reserved36 100InterruptRegion1

37 EDMA3CC_ERRINT EDMA3 CC Error 101 Reserved

38 EDMA3TC_ERRINT0 EDMA3 TC0 Error 102 Reserved

39 EDMA3TC_ERRINT1 EDMA3 TC1 Error 103 Reserved

40 PSCINT PSC ALLINT 104 Reserved

41 Reserved 105 Reserved

42 Reserved 106 Reserved

43 Reserved 107 Reserved

44 Reserved 108 Reserved

45 Reserved 109 Reserved

46 Reserved 110 Reserved

47 Reserved 111 Reserved

48 ASPXINT ASP Transmit 112 PMC_ED C64x+ PMC

49 ASPRINT ASP Receive 113 Reserved

50 Reserved 114 Reserved

51 Reserved 115 Reserved

52 Reserved 116 UMCED1 C64x+ UMC 1

53 Reserved 117 UMCED2 C64x+ UMC 2

54 Reserved 118 PDCERR C64x+ PDC

55 Reserved 119 PVCINT C64x+ PDC

56 Reserved 120 PMCCMPA C64x+ PMC

57 Reserved 121 PMCDMPA C64x+ PMC

58 Reserved 122 DMCCMPA C64x+ DMC

59 Reserved 123 DMCDMPA C64x+ DMC

60 Reserved 124 UMCCMPA C64x+ UMC

61 Reserved 125 UMCDMPA C64x+ UMC

62 Reserved 126 EMCCMPA C64x+ EMC

63 Reserved 127 EMCDMPA C64x+ EMC

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SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-23.C64x+ InterruptControllerRegisters HEX ADDRESS ACRONYM REGISTER DESCRIPTION 0x0180 0000 EVTFLAG0 Eventflagregister0 0x0180 0004 EVTFLAG1 Eventflagregister1 0x0180 0008 EVTFLAG2 Eventflagregister2 0x0180 000C EVTFLAG3 Eventflagregister3 0x0180 0020 EVTSET0 Eventsetregister0 0x0180 0024 EVTSET1 Eventsetregister1 0x0180 0028 EVTSET2 Eventsetregister2 0x0180 002C EVTSET3 Eventsetregister3 0x0180 0040 EVTCLR0 Eventclearregister0 0x0180 0044 EVTCLR1 Eventclearregister1 0x0180 0048 EVTCLR2 Eventclearregister2 0x0180 004C EVTCLR3 Eventclearregister3 0x0180 0080 EVTMASK0 Eventmask register0 0x0180 0084 EVTMASK1 Eventmask register1 0x0180 0088 EVTMASK2 Eventmask register2 0x0180 008C EVTMASK3 Eventmask register3 0x0180 00A0 MEVTFLAG0 Masked eventflagregister0 0x0180 00A4 MEVTFLAG1 Masked eventflagregister1 0x0180 00A8 MEVTFLAG2 Masked eventflagregister2 0x0180 00AC MEVTFLAG3 Masked eventflagregister3 0x0180 00C0 EXPMASK0 Exceptionmask register0 0x0180 00C4 EXPMASK1 Exceptionmask register1 0x0180 00C8 EXPMASK2 Exceptionmask register2 0x0180 00CC EXPMASK3 Exceptionmask register3 0x0180 00E0 MEXPFLAG0 Masked exceptionflagregister0 0x0180 00E4 MEXPFLAG1 Masked exceptionflagregister1 0x0180 00E8 MEXPFLAG2 Masked exceptionflagregister2 0x0180 00EC MEXPFLAG3 Masked exceptionflagregister3 0x0180 0104 INTMUX1 Interruptmux register1 0x0180 0108 INTMUX2 Interruptmux register2 0x0180 010C INTMUX3 Interruptmux register3 0x0180 0140 -0x0180 0144 - Reserved 0x0180 0180 INTXSTAT Interruptexceptionstatus 0x0180 0184 INTXCLR Interruptexceptionclear 0x0180 0188 INTDMASK Dropped interruptmask register 0x0180 01C0 EVTASRT Eventassertregister

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6.7.3 ARM/DSP Communications Interrupts

The INTGEN registerisused forgeneratinginterruptsbetween theARM and DSP. The INTGEN register formatisshown inFigure6-18.Table6-24 describestheregisterbitfields.The ARM may generatean interruptto the DSP by settingone of the fourINTDSP[3:0]bitsor the INTNMI bit.The interruptbit automaticallyselfclearsand the correspondingDSP[3:0]STAT or NMISTAT bitisautomaticallyset to indicatethatthe interruptwas generated.Afterservicingthe interrupt,the DSP clearsthe statusbitby writing‘0’. The ARM may pollthe statusbitto determinewhen the DSP has completedservicingthe interrupt.The DSP may generatean interrupttotheARM inthesame manner usingtheINTARM[1:0]bits and monitorARM interruptservicingviatheARM[1:0]STAT bits. Figure6-18.INTGEN Register 31 30 29 28 27 24 23 22 21 20 19 17 16 ARM1 ARM0 DSP3 DSP2 DSP1 DSP0 NMIReserved Reserved ReservedSTAT STAT STAT STAT STAT STAT STAT R-00 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 R-000 R/W-0 15 14 13 12 11 8 7 6 5 4 3 1 0 INT INT INT INT INT INT INTReserved Reserved ReservedARM1 ARM0 DSP3 DSP2 DSP1 DSP0 NMI R-00 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0 R-000 R/W-0 LEGEND: R = Read, W = Write,n = valueatreset Table6-24.INTGEN RegisterBitFieldsDescriptions Name Description ARM1STAT DSP toARM Int1Status/Clear(1) ARM0STAT DSP toARM Int0Status/Clear(1) DSP3STAT ARM toDSP Int3Status/Clear(1) DSP2STAT ARM toDSP Int2Status/Clear(1) DSP1STAT ARM toDSP Int1Status/Clear(1) DSP0STAT ARM toDSP Int0Status/Clear(1) NMISTAT DSP NMI Status/Clear(1) INTARM1 DSP toARM Int1Set(2) INTARM0 DSP toARM Int0Set(2) INTDSP3 ARM toDSP Int3Set(2) INTDSP2 ARM toDSP Int2Set(2) INTDSP1 ARM toDSP Int1Set(2) INTDSP0 ARM toDSP Int0Set(2) INTNMI DSP NMI Set(2) (1) Write'0'toclear.Writing'1'has no effect. (2) Write'1'togeneratetheinterrupt.The registerbitautomaticallyclearstoa valueof'0'.Writinga '0'has no effect. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 115 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.8 General-PurposeInput/Output(GPIO)

The GPIO peripheralprovidesgeneral-purposepinsthatcan be configuredas eitherinputsor outputs. When configuredas an output,a writetoan internalregistercan controlthestatedrivenon theoutputpin. When configuredas an input,the stateof the inputisdetectableby readingthe stateof an internal register.In addition,the GPIO peripheralcan produce CPU interruptsand EDMA3 eventsin different interrupt/eventgenerationmodes. The GPIO peripheralprovidesgenericconnectionstoexternaldevices. The GPIO pinsaregroupedintobanks of16 pinsperbank (i.e.,bank 0 consistsofGPIO [0:15]). The DM6446 GPIO peripheralsupportsthefollowing:

• Up to54 1.8vGPIO pins,GPIO[0:53]
• Up to17 3.3vGPIO pins,GPIO3V[0:16](GPIO[54:70])
• Interrupts: – Up to8 uniqueGPIO[0:7]interruptsfromBank 0 – 5 GPIO bank (aggregated)interruptsignalsfromeach ofthe5 banks ofGPIOs – Interruptscan be triggeredby risingand/orfallingedge,specifiedforeach interruptcapableGPIO signal
• DMA events: – Up to8 uniqueGPIO DMA eventsfromBank 0 – 5 GPIO bank (aggregated)DMA eventsignalsfromeach ofthe5 banks ofGPIOs
• Set/clearfunctionality:Firmware writes1 to correspondingbitposition(s)to set or to clearGPIO signal(s).ThisallowsmultiplefirmwareprocessestotoggleGPIO outputsignalswithoutcriticalsection protection(disableinterrupts,program GPIO, re-enableinterrupts,to preventcontextswitchingto antherprocessduringGPIO programming).
• SeparateInput/Outputregisters
• Outputregisterinadditiontoset/clearso that,ifpreferredby firmware,some GPIO outputsignalscan be toggledby directwritetotheoutputregister(s).
• Outputregister,when read,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflecting pinstatusand open-drainI/Ocell,allowswiredlogicbe implemented. The memory map fortheGPIO registersisshown inTable6-25.For more detailedinformationon GPIOs, see theTMS320DM644x DMSoC General-PurposeInput/Output(GPIO) User'sGuide (literaturenumber SPRUE25 ).

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6.8.1 GPIO PeripheralRegisterDescription(s)

Table6-25.GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C6 7000 PID PeripheralIdentificationRegister 0x01C6 7004 - Reserved 0x01C6 7008 BINTEN GPIO interruptper-bankenable GPIO Banks 0 and 1 0x01C6 700C - Reserved 0x01C6 7010 DIR01 GPIO Banks 0 and 1 DirectionRegister(GPIO[0:31]) 0x01C6 7014 OUT_DATA01 GPIO Banks 0 and 1 OutputData Register(GPIO[0:31]) 0x01C6 7018 SET_DATA01 GPIO Banks 0 and 1 SetData Register(GPIO[0:31]) 0x01C6 701C CLR_DATA01 GPIO Banks 0 and 1 Cleardataforbanks 0 and 1 (GPIO[0:31]) 0x01C6 7020 IN_DATA01 GPIO Banks 0 and 1 InputData Register(GPIO[0:31]) 0x01C6 7024 SET_RIS_TRIG01 GPIO Banks 0 and 1 SetRisingEdge InterruptRegister(GPIO[0:31]) 0x01C6 7028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 ClearRisingEdge InterruptRegister(GPIO[0:31]) 0x01C6 702C SET_FAL_TRIG01 GPIO Banks 0 and 1 SetFallingEdge InterruptRegister(GPIO[0:31]) 0x01C6 7030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 ClearFallingEdge InterruptRegister(GPIO[0:31]) 0x01C6 7034 INSTAT01 GPIO Banks 0 and 1 InterruptStatusRegister(GPIO[0:31]) GPIO Banks 2 and 3 0x01C6 7038 DIR23 GPIO Banks 2 and 3 DirectionRegister(GPIO[32:63]) 0x01C6 703C OUT_DATA23 GPIO Banks 2 and 3 OutputData Register(GPIO[32:63]) 0x01C6 7040 SET_DATA23 GPIO Banks 2 and 3 SetData Register(GPIO[32:63]) 0x01C6 7044 CLR_DATA23 GPIO Banks 2 and 3 ClearData Register(GPIO[32:63]) 0x01C6 7048 IN_DATA23 GPIO Banks 2 and 3 InputData Register(GPIO[32:63]) 0x01C6 704C SET_RIS_TRIG23 GPIO Banks 2 and 3 SetRisingEdge InterruptRegister(GPIO[32:63]) 0x01C6 7050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 ClearRisingEdge InterruptRegister(GPIO[32:63]) 0x01C6 7054 SET_FAL_TRIG23 GPIO Banks 2 and 3 SetFallingEdge InterruptRegister(GPIO[32:63]) 0x01C6 7058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 ClearFallingEdge InterruptRegister(GPIO[32:63]) 0x01C6 705C INSTAT23 GPIO Banks 2 and 3 InterruptStatusRegister(GPIO[32:63]) GPIO Bank 4 0x01C6 7060 DIR4 GPIO Bank 4 DirectionRegister(GPIO[64:70]) 0x01C6 7064 OUT_DATA4 GPIO Bank 4 OutputData Register(GPIO[64:70]) 0x01C6 7068 SET_DATA4 GPIO Bank 4 SetData Register(GPIO[64:70]) 0x01C6 706C CLR_DATA4 GPIO Bank 4 ClearData Register(GPIO[64:70]) 0x01C6 7070 IN_DATA4 GPIO Bank 4 InputData Register(GPIO[64:70]) 0x01C6 7074 SET_RIS_TRIG4 GPIO Bank 4 SetRisingEdge InterruptRegister(GPIO[64:70]) 0x01C6 7078 CLR_RIS_TRIG4 GPIO Bank 4 ClearRisingEdge InterruptRegister(GPIO[64:70]) 0x01C6 707C SET_FAL_TRIG4 GPIO Bank 4 SetFallingEdge InterruptRegister(GPIO[64:70]) 0x01C6 7080 CLR_FAL_TRIG4 GPIO Bank 4 ClearFallingEdge InterruptRegister(GPIO[64:70]) 0x01C6 7084 INSTAT4 GPIO Bank 4 InterruptStatusRegister(GPIO[64:70]) 0x01C6 7088 -0x01C6 7FFF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 117 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.8.2 GPIO PeripheralInput/OutputElectricalData/Timing

Table6-26.Timing Requirements forGPIO Inputs(1)(seeFigure6-19) A-513, -594, NO. UNIT-810 MIN MAX 1 tw(GPIH) Pulseduration,GPIx high 52 ns 2 tw(GPIL) Pulseduration,GPIx low 52 ns (1) The pulsewidthgivenissufficienttogeneratea CPU interruptoran EDMA3 event.However,ifa userwantstohave DM6446 recognize theGPIx changes throughsoftwarepollingoftheGPIO register,theGPIx durationmust be extendedtoallowDM6446 enough timeto accesstheGPIO registerthroughtheinternalbus. Table6-27.SwitchingCharacteristicsOver Recommended OperatingConditionsforGPIO Outputs (seeFigure6-19) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 3 tw(GPOH) Pulseduration,GPOx high 26(1) ns 4 tw(GPOL) Pulseduration,GPOx low 26(1) ns (1) Thisparametervalueshouldnotbe used as a maximum performancespecification.Actualperformanceofback-to-backaccessesofthe GPIO isdependentupon internalbus activity. Figure6-19.GPIO PortTiming

6.8.3 GPIO PeripheralExternalInterruptsElectricalData/Timing

Table6-28.Timing Requirements forExternalInterrupts(1)(seeFigure6-20) A-513, -594, NO. UNIT-810 MIN MAX 1 tw(ILOW) Widthoftheexternalinterruptpulselow 52 ns 2 tw(IHIGH) Widthoftheexternalinterruptpulsehigh 52 ns (1) The pulsewidthgivenissufficienttogeneratean interruptoran EDMA3 event.However,ifa userwantstohave DM6446recognizethe GPIO changes throughsoftwarepollingoftheGPIO register,theGPIO durationmust be extendedtoallowDM6446 enough timeto accesstheGPIO registerthroughtheinternalbus. Figure6-20.GPIO ExternalInterruptTiming

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6.9 Enhanced DirectMemory Access (EDMA3) Controller

The EDMA3 controllerhandlesalldatatransfersbetween memories and thedeviceslaveperipheralson the DM6446 device.These data transfersincludecache servicing,non-cacheablememory accesses, user-programmeddatatransfers,and hostaccesses.These aresummarized as follows:

• Transferto/fromon-chipmemories – Coprocessorsharedmemory – DSP L1D memory – DSP L2 memory – ARM program/dataRAM
• Transferto/fromexternalstorage – DDR2 SDRAM – NAND flash – AsynchronousEMIF – Smart Media,SD, MMC, xD media storage – ATA/CF
• Transferto/fromperipherals/hosts – VLYNQ – ASP – SPI – PWM – UART The EDMA3 controllersupportstwo addressingmodes: constantaddressingmode and increment addressingmode. On theDM6446 device,constantaddressingmode isnotsupportedby any peripheral or internalmemory. For more informationon these two addressingmodes, see the TMS320DM644x DMSoC Enhanced DirectMemory Access (EDMA3) ControllerUser's Guide (literaturenumber SPRUE23 ).

6.9.1 EDMA3 Channel SynchronizationEvents

The EDMA3 supportsup to64 EDMA3 channelswhich serviceperipheraldevicesand externalmemory. Table6-29 liststhesourceofEDMA3 synchronizationeventsassociatedwitheach oftheprogrammable EDMA3 channels.For theDM6446 device,theassociationofan eventtoa channelisfixed;each ofthe EDMA3 channelshas one specificeventassociatedwithit.These specificeventsare capturedinthe EDMA3 eventregisters(ER,ERH) even iftheeventsaredisabledby theEDMA3 eventenableregisters (EER, EERH). For more detailedinformationon theEDMA3 module and how EDMA3 eventsareenabled, captured,processed,linked,chained,and cleared,etc.,see the TMS320DM644x DMSoC Enhanced DirectMemory Access (EDMA3) ControllerUser'sGuide (literaturenumber SPRUE23 ). Table6-29.DM6446 EDMA3 Channel SynchronizationEvents(1) EDMA3 EVENT NAME EVENT DESCRIPTIONCHANNEL 0-1 Reserved

2 XEVT ASP TransmitEvent

3 REVT ASP ReceiveEvent

4 HISTEVT VPSS HistogramEvent

5 H3AEVT VPSS H3A Event

6 PRVUEVT VPSS PreviewerEvent

7 RSZEVT VPSS ResizerEvent

(1) Inadditiontotheeventsshown inthistable,each ofthe64 channelscan alsobe synchronizedwiththetransfercompletionoralternate transfercompletionevents.Formore detailedinformationon EDMA3 event-transferchaining,see theTMS320DM644x DMSoC Enhanced DirectMemory Access (EDMA3) ControllerUser's Guide (literaturenumber SPRUE23 ). Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 119 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-29.DM6446 EDMA3 Channel SynchronizationEvents (continued) EDMA3 EVENT NAME EVENT DESCRIPTIONCHANNEL

8 IMXINT VICP Interrupt

9 VLCDINT VICP VLCD Interrupt

10 ASQINT VICP ASQ Interrupt

11 DSQINT VICP DSQ Interrupt

16 SPIXEVT SPI TransmitEvent

17 SPIREVT SPI ReceiveEvent

18 URXEVT0 UART 0 ReceiveEvent

19 UTXEVT0 UART 0 TransmitEvent

20 URXEVT1 UART 1 ReceiveEvent

21 UTXEVT1 UART 1 TransmitEvent

22 URXEVT2 UART 2 ReceiveEvent

23 UTXEVT2 UART 2 TransmitEvent

24 Reserved

25 Reserved

26 MMCRXEVT MMC ReceiveEvent

27 MMCTXEVT MMC TransmitEvent

28 I2CREVT I2C ReceiveEvent

29 I2CXEVT I2C TransmitEvent

32 GPINT0 GPIO 0 Interrupt

33 GPINT1 GPIO 1 Interrupt

34 GPINT2 GPIO 2 Interrupt

35 GPINT3 GPIO 3 Interrupt

36 GPINT4 GPIO 4 Interrupt

37 GPINT5 GPIO 5 Interrupt

38 GPINT6 GPIO 6 Interrupt

39 GPINT7 GPIO 7 Interrupt

40 GPBNKINT0 GPIO Bank 0 Interrupt

41 GPBNKINT1 GPIO Bank 1 Interrupt

42 GPBNKINT2 GPIO Bank 2 Interrupt

43 GPBNKINT3 GPIO Bank 3 Interrupt

44 GPBNKINT4 GPIO Bank 4 Interrupt

48 TINT0 Timer0 Interrupt

49 TINT1 Timer1 Interrupt

50 TINT2 Timer2 Interrupt

51 TINT3 Timer3 Interrupt

52 PWM0 PWM 0 Event

53 PWM1 PWM 1 Event

54 PWM2 PWM 2 Event

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6.9.2 EDMA3 PeripheralRegisterDescriptions

Table 6-30 liststhe EDMA3 registers,theircorrespondingacronyms, and DM6446 device memory locations. Table6-30.DM6446 EDMA3 Registers HEX ADDRESS ACRONYM REGISTER NAME Channel ControllerRegisters 0x01c0 0000 -0x01c0 0003 Reserved 0x01c0 0004 CCCFG EDMA3CC ConfigurationRegister 0x01c0 0008 -0x01c0 01FF Reserved GlobalRegisters 0x01c0 0200 QCHMAP0 QDMA Channel0 Mapping toPaRAM Register 0x01c0 0204 QCHMAP1 QDMA Channel1 Mapping toPaRAM Register 0x01c0 0208 QCHMAP2 QDMA Channel2 Mapping toPaRAM Register 0x01c0 020C QCHMAP3 QDMA Channel3 Mapping toPaRAM Register 0x01c0 0210 QCHMAP4 QDMA Channel4 Mapping toPaRAM Register 0x01c0 0214 QCHMAP5 QDMA Channel5 Mapping toPaRAM Register 0x01c0 0218 QCHMAP6 QDMA Channel6 Mapping toPaRAM Register 0x01c0 021C QCHMAP7 QDMA Channel7 Mapping toPaRAM Register 0x01c0 0240 DMAQNUM0 DMA Queue Number Register0 (Channels00 to07) 0x01c0 0244 DMAQNUM1 DMA Queue Number Register1 (Channels08 to15) 0x01c0 0248 DMAQNUM2 DMA Queue Number Register2 (Channels16 to23) 0x01c0 024C DMAQNUM3 DMA Queue Number Register3 (Channels24 to31) 0x01c0 0250 DMAQNUM4 DMA Queue Number Register4 (Channels32 to39) 0x01c0 0254 DMAQNUM5 DMA Queue Number Register5 (Channels40 to47) 0x01c0 0258 DMAQNUM6 DMA Queue Number Register6 (Channels48 to55) 0x01c0 025C DMAQNUM7 DMA Queue Number Register7 (Channels56 to63) 0x01c0 0260 QDMAQNUM CC QDMA Queue Number 0x01c0 0264 -0x01c0 0283 – Reserved 0x01c0 0284 QUEPRI Queue PriorityRegister 0x01c0 0288 -0x01c0 02FF – Reserved 0x01c0 0300 EMR EventMissedRegister 0x01c0 0304 EMRH EventMissedRegisterHigh 0x01c0 0308 EMCR EventMissedClearRegister 0x01c0 030C EMCRH EventMissedClearRegisterHigh 0x01c0 0310 QEMR QDMA EventMissedRegister 0x01c0 0314 QEMCR QDMA EventMissedClearRegister 0x01c0 0318 CCERR EDMA3CC ErrorRegister 0x01c0 031C CCERRCLR EDMA3CC ErrorClearRegister 0x01c0 0320 EEVAL ErrorEvaluateRegister 0x01c0 0340 DRAE0 DMA RegionAccess EnableRegisterforRegion0 0x01c0 0344 DRAEH0 DMA RegionAccess EnableRegisterHighforRegion0 0x01c0 0348 DRAE1 DMA RegionAccess EnableRegisterforRegion1 0x01c0 034C DRAEH1 DMA RegionAccess EnableRegisterHighforRegion1 0x01c0 0350 DRAE2 DMA RegionAccess EnableRegisterforRegion2 0x01c0 0354 DRAEH2 DMA RegionAccess EnableRegisterHighforRegion2 0x01c0 0358 DRAE3 DMA RegionAccess EnableRegisterforRegion3 0x01c0 035C DRAEH3 DMA RegionAccess EnableRegisterHighforRegion3 0x01c0 0360 -0x01c0 037C – Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 121 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c0 0380 QRAE0 QDMA RegionAccess EnableRegisterforRegion0 0x01c0 0384 QRAE1 QDMA RegionAccess EnableRegisterforRegion1 0x01c0 0388 QRAE2 QDMA RegionAccess EnableRegisterforRegion2 0x01c0 038C QRAE3 QDMA RegionAccess EnableRegisterforRegion3 0x01c0 0390 -0x01c0 039C – Reserved 0x01c0 0400 Q0E0 EventQ0 Entry0 Register 0x01c0 0404 Q0E1 EventQ0 Entry1 Register 0x01c0 0408 Q0E2 EventQ0 Entry2 Register 0x01c0 040C Q0E3 EventQ0 Entry3 Register 0x01c0 0410 Q0E4 EventQ0 Entry4 Register 0x01c0 0414 Q0E5 EventQ0 Entry5 Register 0x01c0 0418 Q0E6 EventQ0 Entry6 Register 0x01c0 041C Q0E7 EventQ0 Entry7 Register 0x01c0 0420 Q0E8 EventQ0 Entry8 Register 0x01c0 0424 Q0E9 EventQ0 Entry9 Register 0x01c0 0428 Q0E10 EventQ0 Entry10 Register 0x01c0 042C Q0E11 EventQ0 Entry11 Register 0x01c0 0430 Q0E12 EventQ0 Entry12 Register 0x01c0 0434 Q0E13 EventQ0 Entry13 Register 0x01c0 0438 Q0E14 EventQ0 Entry14 Register 0x01c0 043C Q0E15 EventQ0 Entry15 Register 0x01c0 0440 Q1E0 EventQ1 Entry0 Register 0x01c0 0444 Q1E1 EventQ1 Entry1 Register 0x01c0 0448 Q1E2 EventQ1 Entry2 Register 0x01c0 044C Q1E3 EventQ1 Entry3 Register 0x01c0 0450 Q1E4 EventQ1 Entry4 Register 0x01c0 0454 Q1E5 EventQ1 Entry5 Register 0x01c0 0458 Q1E6 EventQ1 Entry6 Register 0x01c0 045C Q1E7 EventQ1 Entry7 Register 0x01c0 0460 Q1E8 EventQ1 Entry8 Register 0x01c0 0464 Q1E9 EventQ1 Entry9 Register 0x01c0 0468 Q1E10 EventQ1 Entry10 Register 0x01c0 046C Q1E11 EventQ1 Entry11 Register 0x01c0 0470 Q1E12 EventQ1 Entry12 Register 0x01c0 0474 Q1E13 EventQ1 Entry13 Register 0x01c0 0478 Q1E14 EventQ1 Entry14 Register 0x01c0 047C Q1E15 EventQ1 Entry15 Register 0x01c0 0480 -0x01c0 05FF Reserved 0x01c0 0600 QSTAT0 Queue 0 StatusRegister 0x01c0 0604 QSTAT1 Queue 1 StatusRegister 0x01c0 0608 -0x01c0 061F Reserved 0x01c0 0620 QWMTHRA Queue Watermark ThresholdA RegisterforQ[3:0] 0x01c0 0624 – Reserved 0x01c0 0640 CCSTAT EDMA3CC StatusRegister 0x01c0 0644 -0x01c0 0FFF Reserved

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME GlobalChannel Registers 0x01c0 1000 ER EventRegister 0x01c0 1004 ERH EventRegisterHigh 0x01c0 1008 ECR EventClearRegister 0x01c0 100C ECRH EventClearRegisterHigh 0x01c0 1010 ESR EventSetRegister 0x01c0 1014 ESRH EventSetRegisterHigh 0x01c0 1018 CER ChainedEventRegister 0x01c0 101C CERH ChainedEventRegisterHigh 0x01c0 1020 EER EventEnableRegister 0x01c0 1024 EERH EventEnableRegisterHigh 0x01c0 1028 EECR EventEnableClearRegister 0x01c0 102C EECRH EventEnableClearRegisterHigh 0x01c0 1030 EESR EventEnableSetRegister 0x01c0 1034 EESRH EventEnableSetRegisterHigh 0x01c0 1038 SER SecondaryEventRegister 0x01c0 103C SERH SecondaryEventRegisterHigh 0x01c0 1040 SECR SecondaryEventClearRegister 0x01c0 1044 SECRH SecondaryEventClearRegisterHigh 0x01c0 1048 -0x01c0 104F Reserved 0x01c0 1050 IER InterruptEnableRegister 0x01c0 1054 IERH InterruptEnableRegisterHigh 0x01c0 1058 IECR InterruptEnableClearRegister 0x01c0 105C IECRH InterruptEnableClearRegisterHigh 0x01c0 1060 IESR InterruptEnableSetRegister 0x01c0 1064 IESRH InterruptEnableSetRegisterHigh 0x01c0 1068 IPR InterruptPendingRegister 0x01c0 106C IPRH InterruptPendingRegisterHigh 0x01c0 1070 ICR InterruptClearRegister 0x01c0 1074 ICRH InterruptClearRegisterHigh 0x01c0 1078 IEVAL InterruptEvaluateRegister 0x01c0 1080 QER QDMA EventRegister 0x01c0 1084 QEER QDMA EventEnableRegister 0x01c0 1088 QEECR QDMA EventEnableClearRegister 0x01c0 108C QEESR QDMA EventEnableSetRegister 0x01c0 1090 QSER QDMA SecondaryEventRegister 0x01c0 1094 QSECR QDMA SecondaryEventClearRegister 0x01c0 1098 -0x01c0 1FFF Reserved Shadow Region 0 Channel Registers 0x01c0 2000 ER EventRegister 0x01c0 2004 ERH EventRegisterHigh 0x01c0 2008 ECR EventClearRegister 0x01c0 200C ECRH EventClearRegisterHigh 0x01c0 2010 ESR EventSetRegister 0x01c0 2014 ESRH EventSetRegisterHigh 0x01c0 2018 CER ChainedEventRegister 0x01c0 201C CERH ChainedEventRegisterHigh Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 123 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c0 2020 EER EventEnableRegister 0x01c0 2024 EERH EventEnableRegisterHigh 0x01c0 2028 EECR EventEnableClearRegister 0x01c0 202C EECRH EventEnableClearRegisterHigh 0x01c0 2030 EESR EventEnableSetRegister 0x01c0 2034 EESRH EventEnableSetRegisterHigh 0x01c0 2038 SER SecondaryEventRegister 0x01c0 203C SERH SecondaryEventRegisterHigh 0x01c0 2040 SECR SecondaryEventClearRegister 0x01c0 2044 SECRH SecondaryEventClearRegisterHigh 0x01c0 2048 -0x01c0 204C - Reserved 0x01c0 2050 IER InterruptEnableRegister 0x01c0 2054 IERH InterruptEnableRegisterHigh 0x01c0 2058 IECR InterruptEnableClearRegister 0x01c0 205C IECRH InterruptEnableClearRegisterHigh 0x01c0 2060 IESR InterruptEnableSetRegister 0x01c0 2064 IESRH InterruptEnableSetRegisterHigh 0x01c0 2068 IPR InterruptPendingRegister 0x01c0 206C IPRH InterruptPendingRegisterHigh 0x01c0 2070 ICR InterruptClearRegister 0x01c0 2074 ICRH InterruptClearRegisterHigh 0x01c0 2078 IEVAL InterruptEvaluateRegister 0x01c0 207C - Reserved 0x01c0 2080 QER QDMA EventRegister 0x01c0 2084 QEER QDMA EventEnableRegister 0x01c0 2088 QEECR QDMA EventEnableClearRegister 0x01c0 208C QEESR QDMA EventEnableSetRegister 0x01c0 2090 QSER QDMA SecondaryEventRegister 0x01c0 2094 QSECR QDMA SecondaryEventClearRegister 0x01c0 2098 -0x01c0 21FC - Reserved Shadow Region 1 Channel Registers 0x01c0 2200 ER EventRegister 0x01c0 2204 ERH EventRegisterHigh 0x01c0 2208 ECR EventClearRegister 0x01c0 220C ECRH EventClearRegisterHigh 0x01c0 2210 ESR EventSetRegister 0x01c0 2214 ESRH EventSetRegisterHigh 0x01c0 2218 CER ChainedEventRegister 0x01c0 221C CERH ChainedEventRegisterHigh 0x01c0 2220 EER EventEnableRegister 0x01c0 2224 EERH EventEnableRegisterHigh 0x01c0 2228 EECR EventEnableClearRegister 0x01c0 222C EECRH EventEnableClearRegisterHigh 0x01c0 2230 EESR EventEnableSetRegister 0x01c0 2234 EESRH EventEnableSetRegisterHigh 0x01c0 2238 SER SecondaryEventRegister 0x01c0 223C SERH SecondaryEventRegisterHigh

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c0 2240 SECR SecondaryEventClearRegister 0x01c0 2244 SECRH SecondaryEventClearRegisterHigh 0x01c0 2248 -0x01c0 224C - Reserved 0x01c0 2250 IER InterruptEnableRegister 0x01c0 2254 IERH InterruptEnableRegisterHigh 0x01c0 2258 IECR InterruptEnableClearRegister 0x01c0 225C IECRH InterruptEnableClearRegisterHigh 0x01c0 2260 IESR InterruptEnableSetRegister 0x01c0 2264 IESRH InterruptEnableSetRegisterHigh 0x01c0 2268 IPR InterruptPendingRegister 0x01c0 226C IPRH InterruptPendingRegisterHigh 0x01c0 2270 ICR InterruptClearRegister 0x01c0 2274 ICRH InterruptClearRegisterHigh 0x01c0 2278 IEVAL InterruptEvaluateRegister 0x01c0 227C - Reserved 0x01c0 2280 QER QDMA EventRegister 0x01c0 2284 QEER QDMA EventEnableRegister 0x01c0 2288 QEECR QDMA EventEnableClearRegister 0x01c0 228C QEESR QDMA EventEnableSetRegister 0x01c0 2290 QSER QDMA SecondaryEventRegister 0x01c0 2294 QSECR QDMA SecondaryEventClearRegister 0x01c0 2298 -0x01c0 23FC - Reserved Shadow Region 2 Channel Registers 0x01c0 2400 ER EventRegister 0x01c0 2404 ERH EventRegisterHigh 0x01c0 2408 ECR EventClearRegister 0x01c0 240C ECRH EventClearRegisterHigh 0x01c0 2410 ESR EventSetRegister 0x01c0 2414 ESRH EventSetRegisterHigh 0x01c0 2418 CER ChainedEventRegister 0x01c0 241C CERH ChainedEventRegisterHigh 0x01c0 2420 EER EventEnableRegister 0x01c0 2424 EERH EventEnableRegisterHigh 0x01c0 2428 EECR EventEnableClearRegister 0x01c0 242C EECRH EventEnableClearRegisterHigh 0x01c0 2430 EESR EventEnableSetRegister 0x01c0 2434 EESRH EventEnableSetRegisterHigh 0x01c0 2438 SER SecondaryEventRegister 0x01c0 243C SERH SecondaryEventRegisterHigh 0x01c0 2440 SECR SecondaryEventClearRegister 0x01c0 2444 SECRH SecondaryEventClearRegisterHigh 0x01c0 2448 -0x01c0 244C - Reserved 0x01c0 2450 IER InterruptEnableRegister 0x01c0 2454 IERH InterruptEnableRegisterHigh 0x01c0 2458 IECR InterruptEnableClearRegister 0x01c0 245C IECRH InterruptEnableClearRegisterHigh 0x01c0 2460 IESR InterruptEnableSetRegister Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 125 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c0 2464 IESRH InterruptEnableSetRegisterHigh 0x01c0 2468 IPR InterruptPendingRegister 0x01c0 246C IPRH InterruptPendingRegisterHigh 0x01c0 2470 ICR InterruptClearRegister 0x01c0 2474 ICRH InterruptClearRegisterHigh 0x01c0 2478 IEVAL InterruptEvaluateRegister 0x01c0 247C - Reserved 0x01c0 2480 QER QDMA EventRegister 0x01c0 2484 QEER QDMA EventEnableRegister 0x01c0 2488 QEECR QDMA EventEnableClearRegister 0x01c0 248C QEESR QDMA EventEnableSetRegister 0x01c0 2490 QSER QDMA SecondaryEventRegister 0x01c0 2494 QSECR QDMA SecondaryEventClearRegister 0x01c0 2498 -0x01c0 25FC - Reserved Shadow Region 3 Channel Registers 0x01c0 2600 ER EventRegister 0x01c0 2604 ERH EventRegisterHigh 0x01c0 2608 ECR EventClearRegister 0x01c0 260C ECRH EventClearRegisterHigh 0x01c0 2610 ESR EventSetRegister 0x01c0 2614 ESRH EventSetRegisterHigh 0x01c0 2618 CER ChainedEventRegister 0x01c0 261C CERH ChainedEventRegisterHigh 0x01c0 2620 EER EventEnableRegister 0x01c0 2624 EERH EventEnableRegisterHigh 0x01c0 2628 EECR EventEnableClearRegister 0x01c0 262C EECRH EventEnableClearRegisterHigh 0x01c0 2630 EESR EventEnableSetRegister 0x01c0 2634 EESRH EventEnableSetRegisterHigh 0x01c0 2638 SER SecondaryEventRegister 0x01c0 263C SERH SecondaryEventRegisterHigh 0x01c0 2640 SECR SecondaryEventClearRegister 0x01c0 2644 SECRH SecondaryEventClearRegisterHigh 0x01c0 2648 -0x01c0 264C - Reserved 0x01c0 2650 IER InterruptEnableRegister 0x01c0 2654 IERH InterruptEnableRegisterHigh 0x01c0 2658 IECR InterruptEnableClearRegister 0x01c0 265C IECRH InterruptEnableClearRegisterHigh 0x01c0 2660 IESR InterruptEnableSetRegister 0x01c0 2664 IESRH InterruptEnableSetRegisterHigh 0x01c0 2668 IPR InterruptPendingRegister 0x01c0 266C IPRH InterruptPendingRegisterHigh 0x01c0 2670 ICR InterruptClearRegister 0x01c0 2674 ICRH InterruptClearRegisterHigh 0x01c0 2678 IEVAL InterruptEvaluateRegister 0x01c0 267C - Reserved 0x01c0 2680 QER QDMA EventRegister

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c0 2684 QEER QDMA EventEnableRegister 0x01c0 2688 QEECR QDMA EventEnableClearRegister 0x01c0 268C QEESR QDMA EventEnableSetRegister 0x01c0 2690 QSER QDMA SecondaryEventRegister 0x01c0 2694 QSECR QDMA SecondaryEventClearRegister 0x01c0 2698 -0x01c0 27FC - Reserved 0x01c0 2800 -0x01c0 29FC - Reserved 0x01c0 2A00 -0x01c0 2BFC - Reserved 0x01c0 2C00 -0x01c0 2DFC - Reserved 0x01c0 2E00 -0x01c0 2FFC - Reserved 0x01c0 2FFD -0x01c0 3FFF - Reserved 0x01c0 4000 -0x01c0 4FFF - ParameterSetRAM (seeTable6-31) 0x01c0 5000 -0x01c0 7FFF - Reserved 0x01c0 8000 -0x01c0 FFFF - Reserved TransferController0 Registers 0x01c1 0000 - Reserved 0x01c1 0004 TCCFG EDMA3 TC0 ConfigurationRegister 0x01c1 0008 -0x01c1 00FF - Reserved 0x01c1 0100 TCSTAT EDMA3 TC0 ChannelStatusRegister 0x01c1 0104 -0x01c1 0110 - Reserved 0x01c1 0114 -0x01c1 011F - Reserved 0x01c1 0120 ERRSTAT EDMA3 TC0 ErrorStatusRegister 0x01c1 0124 ERREN EDMA3 TC0 ErrorEnableRegister 0x01c1 0128 ERRCLR EDMA3 TC0 ErrorClearRegister 0x01c1 012C ERRDET EDMA3 TC0 ErrorDetailsRegister 0x01c1 0130 ERRCMD EDMA3 TC0 ErrorInterruptCommand Register 0x01c1 0134 -0x01c1 013F - Reserved 0x01c1 0140 RDRATE EDMA3 TC0 Read Rate Register 0x01c1 0144 -0x01c1 01FF - Reserved 0x01c1 0200 -0x01c1 023F - Reserved 0x01c1 0240 SAOPT EDMA3 TC0 SourceActiveOptionsRegister 0x01c1 0244 SASRC EDMA3 TC0 SourceActiveSourceAddressRegister 0x01c1 0248 SACNT EDMA3 TC0 SourceActiveCount Register 0x01c1 024C SADST EDMA3 TC0 SourceActiveDestinationAddressRegister 0x01c1 0250 SABIDX EDMA3 TC0 SourceActiveSourceB-IndexRegister 0x01c1 0254 SAMPPRXY EDMA3 TC0 SourceActiveMemory ProtectionProxyRegister 0x01c1 0258 SACNTRLD EDMA3 TC0 SourceActiveCount ReloadRegister 0x01c1 025C SASRCBREF EDMA3 TC0 SourceActiveSourceAddressB-ReferenceRegister 0x01c1 0260 SADSTBREF EDMA3 TC0 SourceActiveDestinationAddressB-ReferenceRegister 0x01c1 0264 -0x01c1 027F - Reserved 0x01c1 0280 DFCNTRLD EDMA3 TC0 DestinationFIFO SetCount ReloadRegister 0x01c1 0284 DFSRCBREF EDMA3 TC0 DestinationFIFO SetSourceAddressB-ReferenceRegister EDMA3 TC0 DestinationFIFO SetDestinationAddressB-Reference0x01c1 0288 DFDSTBREF Register 0x01c1 028C -0x01c1 02FF - Reserved 0x01c1 0300 DFOPT0 EDMA3 TC0 DestinationFIFO OptionsRegister0 0x01c1 0304 DFSRC0 EDMA3 TC0 DestinationFIFO SourceAddressRegister0 0x01c1 0308 DFCNT0 EDMA3 TC0 DestinationFIFO Count Register0 Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 127 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c1 030C DFDST0 EDMA3 TC0 DestinationFIFO DestinationAddressRegister0 0x01c1 0310 DFBIDX0 EDMA3 TC0 DestinationFIFO BIDX Register0 0x01c1 0314 DFMPPRXY0 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister0 0x01c1 0318 -0x01c1 033F - Reserved 0x01c1 0340 DFOPT1 EDMA3 TC0 DestinationFIFO OptionsRegister1 0x01c1 0344 DFSRC1 EDMA3 TC0 DestinationFIFO SourceAddressRegister1 0x01c1 0348 DFCNT1 EDMA3 TC0 DestinationFIFO Count Register1 0x01c1 034C DFDST1 EDMA3 TC0 DestinationFIFO DestinationAddressRegister1 0x01c1 0350 DFBIDX1 EDMA3 TC0 DestinationFIFO BIDX Register1 0x01c1 0354 DFMPPRXY1 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister1 0x01c1 0358 -0x01c1 037F - Reserved 0x01c1 0380 DFOPT2 EDMA3 TC0 DestinationFIFO OptionsRegister2 0x01c1 0384 DFSRC2 EDMA3 TC0 DestinationFIFO SourceAddressRegister2 0x01c1 0388 DFCNT2 EDMA3 TC0 DestinationFIFO Count Register2 0x01c1 038C DFDST2 EDMA3 TC0 DestinationFIFO DestinationAddressRegister2 0x01c1 0390 DFBIDX2 EDMA3 TC0 DestinationFIFO BIDX Register2 0x01c1 0394 DFMPPRXY2 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister2 0x01c1 0398 -0x01c1 03BF - Reserved 0x01c1 03C0 DFOPT3 EDMA3 TC0 DestinationFIFO OptionsRegister3 0x01c1 03C4 DFSRC3 EDMA3 TC0 DestinationFIFO SourceAddressRegister3 0x01c1 03C8 DFCNT3 EDMA3 TC0 DestinationFIFO Count Register3 0x01c1 03CC DFDST3 EDMA3 TC0 DestinationFIFO DestinationAddressRegister3 0x01c1 03D0 DFBIDX3 EDMA3 TC0 DestinationFIFO BIDX Register3 0x01c1 03D4 DFMPPRXY3 EDMA3 TC0 DestinationFIFO Memory ProtectionProxyRegister3 0x01c1 03D8 -0x01c1 03FF - Reserved TransferController1 Registers 0x01c1 0400 - Reserved 0x01c1 0404 TCCFG EDMA3 TC1 ConfigurationRegister 0x01c1 0408 -0x01c1 04FF - Reserved 0x01c1 0500 TCSTAT EDMA3 TC1 ChannelStatusRegister 0x01c1 0504 -0x01c1 0510 - Reserved 0x01c1 0514 -0x01c1 051F - Reserved 0x01c1 0520 ERRSTAT EDMA3 TC1 ErrorStatusRegister 0x01c1 0524 ERREN EDMA3 TC1 ErrorEnableRegister 0x01c1 0528 ERRCLR EDMA3 TC1 ErrorClearRegister 0x01c1 052C ERRDET EDMA3 TC1 ErrorDetailsRegister 0x01c1 0530 ERRCMD EDMA3 TC1 ErrorInterruptCommand Register 0x01c1 0534 -0x01c1 053F - Reserved 0x01c1 0540 RDRATE EDMA3 TC1 Read Rate Register 0x01c1 0544 -0x01c1 05FF - Reserved 0x01c1 0600 -0x01c1 063F - Reserved 0x01c1 0640 SAOPT EDMA3 TC1 SourceActiveOptionsRegister 0x01c1 0644 SASRC EDMA3 TC1 SourceActiveSourceAddressRegister 0x01c1 0648 SACNT EDMA3 TC1 SourceActiveCount Register 0x01c1 064C SADST EDMA3 TC1 SourceActiveDestinationAddressRegister 0x01c1 0650 SABIDX EDMA3 TC1 SourceActiveSourceB-IndexRegister 0x01c1 0654 SAMPPRXY EDMA3 TC1 SourceActiveMemory ProtectionProxyRegister

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-30.DM6446 EDMA3 Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x01c1 0658 SACNTRLD EDMA3 TC1 SourceActiveCount ReloadRegister 0x01c1 065C SASRCBREF EDMA3 TC1 SourceActiveSourceAddressB-ReferenceRegister 0x01c1 0660 SADSTBREF EDMA3 TC1 SourceActiveDestinationAddressB-ReferenceRegister 0x01c1 0664 -0x01c1 067F - Reserved 0x01c1 0680 DFCNTRLD EDMA3 TC1 DestinationFIFO SetCount ReloadRegister 0x01c1 0684 DFSRCBREF EDMA3 TC1 DestinationFIFO SetSourceAddressB-ReferenceRegister EDMA3 TC1 DestinationFIFO SetDestinationAddressB-Reference0x01c1 0688 DFDSTBREF Register 0x01c1 068C -0x01c1 06FF - Reserved 0x01c1 0700 DFOPT0 EDMA3 TC1 DestinationFIFO OptionsRegister0 0x01c1 0704 DFSRC0 EDMA3 TC1 DestinationFIFO SourceAddressRegister0 0x01c1 0708 DFCNT0 EDMA3 TC1 DestinationFIFO Count Register0 0x01c1 070C DFDST0 EDMA3 TC1 DestinationFIFO DestinationAddressRegister0 0x01c1 0710 DFBIDX0 EDMA3 TC1 DestinationFIFO BIDX Register0 0x01c1 0714 DFMPPRXY0 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister0 0x01c1 0718 -0x01c1 073F - Reserved 0x01c1 0740 DFOPT1 EDMA3 TC1 DestinationFIFO OptionsRegister1 0x01c1 0744 DFSRC1 EDMA3 TC1 DestinationFIFO SourceAddressRegister1 0x01c1 0748 DFCNT1 EDMA3 TC1 DestinationFIFO Count Register1 0x01c1 074C DFDST1 EDMA3 TC1 DestinationFIFO DestinationAddressRegister1 0x01c1 0750 DFBIDX1 EDMA3 TC1 DestinationFIFO BIDX Register1 0x01c1 0754 DFMPPRXY1 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister1 0x01c1 0758 -0x01c1 077F - Reserved 0x01c1 0780 DFOPT2 EDMA3 TC1 DestinationFIFO OptionsRegister2 0x01c1 0784 DFSRC2 EDMA3 TC1 DestinationFIFO SourceAddressRegister2 0x01c1 0788 DFCNT2 EDMA3 TC1 DestinationFIFO Count Register2 0x01c1 078C DFDST2 EDMA3 TC1 DestinationFIFO DestinationAddressRegister2 0x01c1 0790 DFBIDX2 EDMA3 TC1 DestinationFIFO BIDX Register2 0x01c1 0794 DFMPPRXY2 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister2 0x01c1 0798 -0x01c1 07BF - Reserved 0x01c1 07C0 DFOPT3 EDMA3 TC1 DestinationFIFO OptionsRegister3 0x01c1 07C4 DFSRC3 EDMA3 TC1 DestinationFIFO SourceAddressRegister3 0x01c1 07C8 DFCNT3 EDMA3 TC1 DestinationFIFO Count Register3 0x01c1 07CC DFDST3 EDMA3 TC1 DestinationFIFO DestinationAddressRegister3 0x01c1 07D0 DFBIDX3 EDMA3 TC1 DestinationFIFO BIDX Register3 0x01c1 07D4 DFMPPRXY3 EDMA3 TC1 DestinationFIFO Memory ProtectionProxyRegister3 0x01c1 07D8 -0x01c1 07FF - Reserved Table 6-31 shows an abbreviationof the setof registerswhich make up the parametersetforeach of 128 EDMA3 events.Each of the parameterregistersetsconsistof 8 32-bitword entries.Table 6-32 shows the parameterset entryregisterswithrelativememory address locationswithineach of the parametersets. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 129 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-31.EDMA3 Parameter Set RAM HEX ADDRESS RANGE DESCRIPTION 0x01c0 4000 -0x01c0 401F ParametersSet0 (832-bitwords) 0x01c0 4020 -0x01c0 403F ParametersSet1 (832-bitwords) 0x01c0 4040 -0x01c0 405F ParametersSet2 (832-bitwords) 0x01c0 4060 -0x01c0 407F ParametersSet3 (832-bitwords) 0x01c0 4080 -0x01c0 409F ParametersSet4 (832-bitwords) 0x01c0 40A0 -0x01c0 40BF ParametersSet5 (832-bitwords) 0x01c0 4FC0 -0x01c0 4FDF ParametersSet126 (832-bitwords) 0x01c0 4FE0 -0x01c0 4FFF ParametersSet127 (832-bitwords) Table6-32.Parameter Set Entries HEX OFFSET ADDRESS ACRONYM PARAMETER ENTRYWITHIN THE PARAMETER SET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT A Count,B Count 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceB Index,DestinationB Index 0x0014 LINK_BCNTRLD LinkAddress,B Count Reload 0x0018 SRC_DST_CIDX SourceC Index,DestinationC Index 0x001C CCNT C Count

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6.10 ExternalMemory Interface(EMIF)

DM6446 supportsseveralmemory and externaldeviceinterfaces,including:

• AsynchronousEMIF (EMIFA)forinterfacingtoNOR Flash,SRAM, etc.
• NAND Flash
• ATA/CF

6.10.1 Asynchronous EMIF (EMIFA)

The DM6446 AsynchronousEMIF (EMIFA) providesan 8-bitor16-bitdatabus,an addressbus widthup to24-bits,and 4 dedicatedchipselects,alongwithmemory controlsignals.These signalsaremultiplexed between threeperipherals:

• EMIFA and NAND interfaces
• ATA/CF
• HostPortInterface 6.10.1.1NAND (NAND, SmartMedia,xD) The EMIFA interfaceprovidesboththeasynchronousEMIF and NAND interfaces.Four chipselectsare providedand each are individuallyconfigurableto provideeitherEMIFA or NAND support.The NAND featuressupportedareas follows.
• NAND flashon up to4 asynchronouschipselects.
• 8 and 16-bitdatabus widths.
• Programmable cycletimings.
• PerformsECC calculation.
• NAND Mode alsosupportsSmartMedia/SSFDC (SolidStateFloppyDiskController)and xD memory cards
• ARM ROM supportsbootingoftheDM6446 ARM processorfromNAND flashlocatedatCS2 The memory map forEMIFA and NAND registersisshown inTable6-33.For more detailson theEMIFA and NAND interfaces,see theTMS320DM644x DMSoC PeripheralsOverviewReferenceGuide (literature number SPRUE19 ) and the TMS320DM644x DMSoC AsynchronousExternalMemory Interface(EMIF) ReferenceGuide (literaturenumber SPRUE20 ). Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 131 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-33.EMIFA/NAND Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E0 0000 -0x01E0 0003 Reserved 0x01E0 0004 AWCCR AsynchronousWaitCycleConfigurationRegister 0x01E0 0008 -0x01E0 000F Reserved 0x01E0 0010 A1CR Asynchronous1 ConfigurationRegister(CS2 Space) 0x01E0 0014 A2CR Asynchronous2 ConfigurationRegister(CS3 Space) 0x01E0 0018 A3CR Asynchronous3 ConfigurationRegister(CS4 Space) 0x01E0 001C A4CR Asynchronous4 ConfigurationRegister(CS5 Space) 0x01E0 0020 -0x01E0 003F - Reserved 0x01E0 0040 EIRR EMIF InterruptRaw Register 0x01E0 0044 EIMR EMIF InterruptMask Register 0x01E0 0048 EIMSR EMIF InterruptMask SetRegister 0x01E0 004C EIMCR EMIF InterruptMask ClearRegister 0x01E0 0050 -0x01E0 005F - Reserved 0x01E0 0060 NANDFCR NAND FlashControlRegister 0x01E0 0064 NANDFSR NAND FlashStatusRegister 0x01E0 0070 NANDF1ECC NAND Flash1 ECC Register(CS2 Space) 0x01E0 0074 NANDF2ECC NAND Flash2 ECC Register(CS3 Space) 0x01E0 0078 NANDF3ECC NAND Flash3 ECC Register(CS4 Space) 0x01E0 007C NANDF4ECC NAND Flash4 ECC Register(CS5 Space) 0x01E0 0080 -0x01E0 0FFF - Reserved

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6.10.1.2 EMIFA ElectricalData/Timing

Table6-34.Timing Requirements forAsynchronous Memory Cycles forEMIFA Module (1) (seeFigure6-21and Figure6-22) A-513, -594, NO. UNIT-810 MIN MAX READS and WRITES 2 tw(EM_WAIT) Pulseduration,EM_WAIT assertionand deassertion 2E ns READS 12 tsu(EMDV-EMOEH) Setuptime,EM_D[15:0]validbeforeEM_OE high 10.5 ns 13 th(EMOEH-EMDIV) Holdtime,EM_D[15:0]validafterEM_OE high 0 ns 14 tsu (EMWAIT-EMOEH) Setuptime,EM_WAIT assertedbeforeEM_OE high(2) 4E + 10.4 ns WRITES 28 tsu(EMWAIT-EMWEH) Setuptime,EM_WAIT assertedbeforeEM_WE high(2) 4E + 10.4 ns (1) E = SYSCLK5 periodinns forEMIFA. Forexample,when runningtheDSP CPU at594 MHz, use E = 10.1ns.Forexample,when runningtheDSP CPU at810 MHz, use E = 7.4ns. (2) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEM_WAIT must be assertedtoadd extended waitstates.Figure6-23and Figure6-24describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringtheSTROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestartofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 133 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-35.SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Memory Cycles forEMIFA Module (1)(2)(seeFigure6-21and Figure6-22) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX READS and WRITES 1 td(TURNAROUND) Turn-aroundtime (TA + 1)*E -2 (TA + 1)*E + 2 ns READS (RS + RST + RH + (RS + RST + RH + TA +EMIF readcycletime(EW = 0) nsTA + 4)*E -0.5 4)*E + 0.5 3 tc(EMRCYCLE) (RS + RST + RH +EMIF readcycletime(EW = 1) 4184 *E + 0.5 nsTA + 4)*E -0.5 Outputsetuptime,EM_CS[5:2]lowtoEM_OE low (RS + 1)*E -1 (RS + 1)*E + 1.4 ns(SS = 0) 4 tsu(EMCSL-EMOEL) Outputsetuptime,EM_CS[5:2]lowtoEM_OE low -1 ns(SS = 1) Outputholdtime,EM_OE hightoEM_CS[5:2]high (RH + 1)*E -2.1 (RH + 1)*E + 1.4 ns(SS = 0) 5 th(EMOEH-EMCSH) Outputholdtime,EM_OE hightoEM_CS[5:2]high -2.2 ns(SS = 1) 6 tsu(EMBAV-EMOEL) Outputsetuptime,EM_BA[1:0]validtoEM_OE low (RS + 1)*E -1.8 (RS + 1)*E + 1.3 ns 7 th(EMOEH-EMBAIV) Outputholdtime,EM_OE hightoEM_BA[1:0]invalid (RH + 1)*E -2.3 (RH + 1)*E + 1.1 ns 8 tsu(EMAV-EMOEL) Outputsetuptime,EM_A[21:0]validtoEM_OE low (RS + 1)*E -1.9 (RS + 1)*E + 1.5 ns 9 th(EMOEH-EMAIV) Outputholdtime,EM_OE hightoEM_A[21:0]invalid (RH + 1)*E -2.6 (RH + 1)*E + 1.2 ns EM_OE activelowwidth(EW = 0) (RST + 1)*E -2 (RST + 1)*E + 2 ns 10 tw(EMOEL) EM_OE activelowwidth(EW = 1) (RST + 1)*E -2 (RST + 4097)*E + 2 ns 11 td(EMWAITH-EMOEH) DelaytimefromEM_WAIT deassertedtoEM_OE high 4E + 10.4 ns WRITES (WS + WST + WH (WS + WST + WH + TAEMIF writecycletime(EW = 0) ns+ TA + 4)*E -0.5 + 4)*E + 0.5 15 tc(EMWCYCLE) (WS + WST + WHEMIF writecycletime(EW = 1) 4184 *E + 0.5 ns+ TA + 4)*E -0.5 Outputsetuptime,EM_CS[5:2]lowtoEM_WE low (WS + 1)*E -0.9 (WS + 1)*E + 1.4 ns(SS = 0) 16 tsu(EMCSL-EMWEL) Outputsetuptime,EM_CS[5:2]lowtoEM_WE low -1 ns(SS = 1) Outputholdtime,EM_WE hightoEM_CS[5:2]high (WH + 1)*E -2.1 (WH + 1)*E + 1.1 ns(SS = 0) 17 th(EMWEH-EMCSH) Outputholdtime,EM_WE hightoEM_CS[5:2]high -2.1 ns(SS = 1) 18 tsu(EMRNW-EMWEL) Outputsetuptime,EM_R/ W validtoEM_WE low (WS + 1)*E -0.7 (WS + 1)*E + 0.9 ns 19 th(EMWEH-EMRNW) Outputholdtime,EM_WE hightoEM_R/ W invalid (WH + 1)*E -0.9 (WH + 1)*E + 0.9 ns 20 tsu(EMBAV-EMWEL) Outputsetuptime,EM_BA[1:0]validtoEM_WE low (WS + 1)*E -1.7 (WS + 1)*E + 1.5 ns 21 th(EMWEH-EMBAIV) Outputholdtime,EM_WE hightoEM_BA[1:0]invalid (WH + 1)*E -2.3 (WH + 1)*E + 0.9 ns 22 tsu(EMAV-EMWEL) Outputsetuptime,EM_A[21:0]validtoEM_WE low (WS + 1)*E -1.8 (WS + 1)*E + 1.7 ns 23 th(EMWEH-EMAIV) Outputholdtime,EM_WE hightoEM_A[21:0]invalid (WH + 1)*E -2.6 (WH + 1)*E + 1 ns EM_WE activelowwidth(EW = 0) (WST + 1)*E -2 (WST + 1)*E + 2 ns 24 tw(EMWEL) EM_WE activelowwidth(EW = 1) (WST + 1)*E -2 (WST + 4097)*E + 2 ns (1) RS = Read setup,RST = Read STrobe,RH = Read Hold,WS = WriteSetup,WST = WriteSTrobe,WH = WriteHold,TA = Turn Around,EW = ExtendWaitmode, SS = SelectStrobemode. These parametersareprogrammed viatheAsynchronousBank and AsynchronousWaitCycleConfigurationRegistersand supportthefollowingrangeofvalues:TA[3:0],RS[15:0],RST[63:0],RH[7:0], WS[15:0],WST[63:0],WH[7:0],and EW[255:0].Formore information,see theTMS320DM644x DMSoC AsynchronousExternalMemory Interface(EMIF)ReferenceGuide (literaturenumber SPRUE20 ). (2) E = SYSCLK5 periodinns forEMIFA. Forexample,when runningtheDSP CPU at594 MHz, use E = 10.1ns.Forexample,when runningtheDSP CPU at810 MHz, use E = 7.4ns.

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EM_CS[5:2] EM_BA[1:0] EM_A[21:0] EM_OE EM_D[15:0] EM_WE EM_R/W TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-35.SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Memory Cycles forEMIFA Module (seeFigure6-21and Figure6-22)(continued) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 25 td(EMWAITH-EMWEH) DelaytimefromEM_WAIT deassertedtoEM_WE high 4E + 10.4 ns 26 tsu(EMDV-EMWEL) Outputsetuptime,EM_D[15:0]validtoEM_WE low (WS + 1)*E -2.2 (WS + 1)*E + 1.4 ns 27 th(EMWEH-EMDIV) Outputholdtime,EM_WE hightoEM_D[15:0]invalid (WH + 1)*E -2.2 (WH + 1)*E + 1.4 ns Figure6-21.Asynchronous Memory Read Timing forEMIF Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 135 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

EM_CS[5:2] EM_BA[1:0] EM_A[21:0] EM_WE EM_D[15:0] EM_OE EM_R/W EM_CS[5:2] Asserted Deasserted EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_OE EM_WAIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-22.Asynchronous Memory WriteTiming forEMIF Figure6-23.EM_WAIT Read Timing Requirements

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EM_CS[5:2] Asserted Deasserted EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_WE EM_WAIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-24.EM_WAIT WriteTiming Requirements

6.10.2 DDR2 Memory Controller

The DDR2 Memory Controlleris a dedicatedinterfaceto DDR2 SDRAM. ItsupportsJESD79D-2A standardcompliantDDR2 SDRAM Devicesand can interfaceto either16-bitor 32-bitDDR2 SDRAM devices.For detailson the DDR2 Memory Controller,see the TMS320DM644x DMSoC Peripherals Overview Reference Guide (literaturenumber SPRUE19 ) and the TMS320DM644x DMSoC DDR2 Memory ControllerUser'sGuide (literaturenumber SPRUE22 ). DDR2 SDRAM playsa key rolein a DaVinci-basedsystem.Such a system isexpectedto requirea significantamount ofhigh-speedexternalmemory for:

• Bufferingofinputimage datafromsensorsorvideosources
• Intermediatebufferingforprocessing/resizingofimage dataintheVPFE
• Numerous OSD displaybuffers
• Intermediatebufferingforlargeraw Bayer data image fileswhileperformingimage processing functions
• Bufferingforintermediatedatawhileperformingvideoencode and decode functions
• Storageofexecutablecode forboththeARM and DSP A memory map oftheDDR2 Memory Controllerregistersisshown inTable6-36. Table6-36.DDR2 Memory ControllerRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C4 004C DDRVTPER DDR2 VTP EnableRegister 0x01C4 2030 DDRVTPR DDR2 VTP Register 0x2000 0000 -0x2000 0003 - Reserved 0x2000 0004 SDRSTAT SDRAM StatusRegister 0x2000 0008 SDBCR SDRAM Bank ConfigurationRegister 0x2000 000C SDRCR SDRAM RefreshControlRegister 0x2000 0010 SDTIMR SDRAM TimingRegister 0x2000 0014 SDTIMR2 SDRAM TimingRegister2 0x2000 0020 PBBPR PeripheralBus BurstPriorityRegister 0x2000 0024 -0x2000 00BF - Reserved 0x2000 00C0 IRR InterruptRaw Register 0x2000 00C4 IMR InterruptMasked Register 0x2000 00C8 IMSR InterruptMask SetRegister Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 137 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

DDR_CLK0 TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-36.DDR2 Memory ControllerRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x2000 00CC IMCR InterruptMask ClearRegister 0x2000 00D0 -0x2000 00E3 - Reserved 0x2000 00E4 DDRPHYCR DDR PHY ControlRegister 0x2000 00E8 -0x2000 00EF - Reserved 0x2000 00F0 VTPIOCR VTP IO ControlRegister 0x2000 00F4 -0x2000 7FFF - Reserved 6.10.2.1DDR2 Memory ControllerElectricalData/Timing The ImplementingDDR2 PCB Layouton theTMS320DM644x DSP applicationreport(literaturenumber SPRAAC5 ) specifiesa completeDDR2 interfacesolutionfortheDM6446 as wellas a listofcompatible DDR2 devices.TIhas performedthesimulationand system characterizationtoensureallDDR2 interface timingsinthissolutionaremet. TIonlysupportsboarddesignsthatfollowtheguidelinesoutlinedintheImplementingDDR2 PCB Layout on theTMS320DM644x DSP applicationreport(literaturenumber SPRAAC5 ). Table6-37.SwitchingCharacteristicsOver Recommended OperatingConditionsforDDR2 Memory Controller(1)(2)(seeFigure6-25) A-513,-810 -594NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(DDR_CLK0) Cycletime,DDR_CLK0 5.29 8 6 8 ns 2 f(DDR_CLK0) Frequency,DDR_CLK0 125 189 125 167 MHz (1) DDR_CLK0 cycletime= 2 x PLL2 -SYSCLK2 cycletime. (2) The PLL2 Controllermust be programmed such thattheresultingDDR_CLK0 clockfrequencyiswithinthespecifiedrange. Figure6-25.DDR2 Memory ControllerClock Timing

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6.11 ATA/CF

The ATA/CF peripheralsupportsthefollowingfeatures:

• PIO,multiwordDMA, and UltraATA 33/66
• Up tomode 4 timingson PIO mode
• Up tomode 2 timingson multiwordDMA
• Up tomode 4 timingson UltraATA
• Programmable timingparameters
• SupportsTrueIDEmode forCompact Flash In addition,the Host IDE ControllersupportsmultiwordDMA transfersbetween externalIDE/ATAPI devicesand a systemmemory bus interface.

6.11.1 ATA/CF PeripheralRegisterDescription(s)

The ATA registersareshown inTable6-38. Table6-38.ATA RegisterMemory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME ATA Bus Master InterfaceDMA Engine Registers 0x01C6 6000 BMICP PrimaryIDE ChannelDMA ControlRegister 0x01C6 6002 BMISP PrimaryIDE ChannelDMA StatusRegister 0x01C6 6004 BMIDTP PrimaryIDE ChannelDMA DescriptorTablePointerRegister 0x01C6 6008 - 0x01C6 600A - Reserved 0x01C6 600C - ATA ConfigurationRegisters 0x01C6 6040 IDETIMP PrimaryIDE ChannelTimingRegister 0x01C6 6042 - 0x01C6 6044 - Reserved 0x01C6 6045 - 0x01C6 6047 IDESTAT IDE ControllerStatusRegister 0x01C6 6048 UDMACTL Ultra-DMAControlRegister 0x01C6 604A - Reserved 0x01C6 6050 MISCCTL MiscellaneousControlRegister 0x01C6 6054 REGSTB Task FileRegisterStrobeTimingRegister 0x01C6 6058 REGRCVR Task FileRegisterRecoveryTimingRegister 0x01C6 605C DATSTB Data RegisterAccess PIO StrobeTimingRegister 0x01C6 6060 DATRCVR Data RegisterAccess PIO RecoveryTimingRegister 0x01C6 6064 DMASTB MultiwordDMA StrobeTimingRegister 0x01C6 6068 DMARCVR MultiwordDMA RecoveryTimingRegister 0x01C6 606C UDMASTB Ultra-DMAStrobeTimingRegister 0x01C6 6070 UDMATRP Ultra-DMAReady-to-PauseTimingRegister 0x01C6 6074 UDMATENV Ultra-DMATimingEnvelopeRegister 0x01C6 6078 IORDYTMP PrimaryIO Ready TimerConfigurationRegister 0x01C6 607C -0x01C6 67FF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 139 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.11.2 ATA/CF ElectricalData/Timing

devicepins.Formore details,see Section6.1,ParameterInformation. configurationof the ATA/CF memory-mapped controlregistersforthe selectedATA/CF frequencyof operation. 6.11.2.1ATA/CF PIO Data TransferAC Timing Table6-39.Timings forATA/CF Module — PIO Data Transfer(1)(2)(seeFigure6-26) A-513, -594, NO. MODE UNIT-810 MIN MAX 1 t0 Cycletime 0-4(3) (DATSTB + DATRCVR + 2)P -0.5 ns 2 t1 AddressvalidtoDIOW/ DIOR setup 0-4(3) 12P -1.6 ns 3 t2 DIOW/ DIOR pulsedurationlow 0-4(3) (DATSTB + 1)P -1 ns 0-2 – ns 4 t2i DIOW/ DIOR recoverytime,pulsedurationhigh 3-4(3) (DATRCVR + 1)P -1 ns DIOW datasetuptime,DD[15:0]validbefore5 t3 0-4(3) (DATSTB + 1)P nsDIOW risingedge DIOW dataholdtime,DD[15:0]validafterDIOW6 t4 0-4(3) (HWNHLD + 1)P + 1 nsrisingedge 0 50 ns DIOR datasetuptime,DD[15:0]validbeforeDIOR7 t5 1 35 nsrisingedge 2-4(3) 20 ns DIOR dataholdtime,DD[15:0]validafterDIOR8 t6 0-4(3) 5 nsrisingedge Outputdata3-state,DD[15:0]3-stateafterDIOR9 t6Z 0-4(3) 30 nsrisingedge 10 t9 DIOW/ DIOR toaddressvalidhold 0-4(3) (HWNHLD + 1)P -2.1 ns Read datasetuptime,DD[15:0]validbefore11 tRD 0-4(3) 0 nsIORDY active 12 tA IORDY setup 0-4(3)(4) 35 ns 13 tB IORDY pulsewidth 0-4(3) 1250 ns 14 tC IORDY assertiontorelease 0-4(3) 5 ns (1) P = SYSCLK5 period,inns,forATA. Forexample,when runningtheDSP CPU at594 MHz, use P = 10.1ns.Forexample,when runningtheDSP CPU at810 MHz, use P = 7.4ns. (2) DATSTB equalsthevalueprogrammed intheDATSTBxP bitfieldintheDATSTB register.DATRCVR equalsthevalueprogrammed in theDATRCVRxP bitfieldintheDATRCVR register.HWNHLD equalsthevalueprogrammed intheHWNHLDxP bitfieldinthe MISCCTL register.Formore detailedinformation,see theTMS320DM644x DMSoC ATA ControllerUser's Guide (literaturenumber SPRUE21 ). (3) The sustainedthroughputforPIO modes 3 and 4 islimitedtothethroughputequivalentofPIO mode 2.Formore detailedinformation, see theTMS320DM644x DMSoC ATA ControllerUser's Guide (literaturenumber SPRUE21 ). (4) The tA parametermust be met onlywhen theIORDY timerisenabledtoallowa devicetoinsertwaitstatesduringa transaction.Inorder tomeet thetA parameter,a minimum frequencyforSYSCLK5 isspecifiedforeach PIO as follows:

• PIO mode 0,MIN frequency= 15 MHz
• PIO mode 1,MIN frequency= 22 MHz
• PIO mode 2,MIN frequency= 31 MHz
• PIO mode 3,MIN frequency= 45 MHz
• PIO mode 4,MIN frequency= 57 MHz

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DA[2:0], ATA_CS0 , ATA_CS1 IORDY (A) DIOW /DIOR DD15:0 DD[15:0] (IN) IORDY (B) IORDY (C) t1 t2 t9 t2i t6t5 t6Z tRD tC tA tC tB A. IORDY is not negated for transfer (no wait generated) B. IORDY is negative but is re-asserted before tA (no wait is generated) C. IORDY is negative before tA and remains asserted until tB; data is driven valid at tRD (wait is generated) TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-26.ATA/CF PIO Data TransferTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 141 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.11.2.2ATA/CF MultiwordDMA Timing Table6-40.Timings forATA/CF Module — MultiwordDMA AC Timing(1)(2)(seeFigure6-27) A-513, -594, NO. MODE UNIT-810 MIN MAX 1 t0 Cycletime 0-2 (DMASTB + DMARCVR + 2)P -0.5 ns 2 tD DIOW/ DIOR activelowpulseduration 0-2 (DMASTB + 1)P -1 ns 0 150 ns DIOR dataaccess,DIOR fallingedge toDD[15:0]3 tE 1 60 nsvalid 2 50 ns DIOR dataholdtime,DD[15:0]validafterDIOR4 tF 0-2 5 nsrisingedge DIOW/ DIOR datasetuptime,DD[15:0](OUT )valid 0-2 (DMASTB)P nsbeforeDIOW/ DIOR risingedge 0 100 ns5 tG DIOW/ DIOR datasetuptime,DD15:0valid 1 30 nsbeforeDIOW/ DIOR risingedge 2 20 ns DIOW dataholdtime,DD[15:0]validafterDIOW6 tH 0-2 (HWNHLD + 1)P + 1 nsrisingedge 7 tI DMACK toDIOW/ DIOR setup 0-2 (DMARCVR + 1)P -1.7 ns 8 tJ DIOW/ DIOR toDMACK hold 0-2 5P -5.9 ns 9 tKR DIOR negatedpulsewidth 0-2 (DMARCVR + 1)P -1 ns 10 tKW DIOW negatedpulsewidth 0-2 (DMARCVR + 1)P -1 ns 0 120 ns 11 tLR DIOR toDMARQ delay 1 45 ns 2 35 ns 0-1 40 ns 12 tLW DIOW toDMARQ delay 2 35 ns 13 tM ATA_CSx validtoDIOW/ DIOR setup 0-2 (DATRCVR)P -1.7 ns 14 tN ATA_CSx validafterDIOW/ DIOR risingedge hold 0-2 5P -1.7 ns 0 20 ns 15 tZ DMACK toreaddata(DD[15:0])released 1-2 25 ns (1) P = SYSCLK5 period,inns,forATA. Forexample,when runningtheDSP CPU at594 MHz, use P = 10.1ns.Forexample,when runningtheDSP CPU at810 MHz, use P = 7.4ns. (2) DMASTB equalsthevalueprogrammed intheDMASTBxP bitfieldintheDMASTB register.DMARCVR equalsthevalueprogrammed intheDMARCVRxP bitfieldintheDMARCVR register.HWNHLD equalsthevalueprogrammed intheHWNHLDxP bitfieldinthe MISCCTL register.Formore detailedinformation,see theTMS320DM644x DMSoC ATA ControllerUser's Guide (literaturenumber SPRUE21 ).

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DA[2:0], ATA_CS0 , ATA_CS1 tM t0 tN tL tJ tZ tK tH tF tD tI tG tE tG DMARQ DMACK DIOW /DIOR DD15:0 DD[15:0] (IN) TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-27.ATA/CF MultiwordDMA Timing Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.11.2.3ATA/CF UltraDMA Timing Table6-41.Timings forATA/CF Module — UltraDMA AC Timing(1)(2) (seeFigure6-28through Figure6-37) A-513, -594, NO. MODE UNIT-810 MIN MAX 28 f(SYSCLK5) Operatingfrequency,SYSCLK5 0-4 25 MHz 0 240 ns 1 160 ns 1 t2CYCTYP Typicalsustainedaveragetwo cycletime 2 120 ns 3 90 ns 4 60 ns 2 tCYC Cycletime,Strobeedge toStrobeedge 0-4 (UDMASTB + 1)P ns Two cycletime,risingtorisingedge orfallingto3 t2CYC 0-4 2(UDMASTB + 1)P nsfallingedge 0 15 ns 1 10 ns 4 tDS Data setup,datavalidbeforeSTROBE edge 2-3 7 ns 4 5 ns 5 tDH Data hold,datavalidafterSTROBE edge 0-4 5 ns 0 70 ns 1 48 ns Data validINPUT setuptime,datavalidbefore 2 31 nsSTROBE 6 tDVS 3 20 ns 4 6.7 ns Data validOUTPUT setuptime,datavalidbefore 0-4 (UDMASTB)P -3.1 nsSTROBE Data validINPUT holdtime,datavalidafter 0-4 6.2 nsSTROBE 7 tDVH Data validOUTPUT holdtime,datavalidafter 0-4 1P -2 nsSTROBE CRC word validsetuptimeathost,CRC valid10 tCVS 0-4 (UDMASTB)P nsbeforeDMACK negation CRC word validholdtimeatsender,CRC valid11 tCVH 0-4 2P nsafterDMACK negation Time fromSTROBE outputreleased-to-driving12 tZFS 0-4 0 nsuntilthefirsttransitionofcriticaltiming 0 70 ns 1 48 ns Time fromdataoutputreleased-to-drivinguntil13 tDZFS 2 31 nsthefirsttransitionofcriticaltiming 3 20 ns 4 6.7 ns (1) P = SYSCLK5 period,inns,forATA. Forexample,when runningtheDSP CPU at594 MHz, use P = 10.1ns.Forexample,when runningtheDSP CPU at810 MHz, use P = 7.4ns. (2) UDMASTB equalsthevalueprogrammed intheUDMSTBxP bitfieldintheUDMASTB register.UDMATRP equalsthevalue programmed intheUDMTRPxP bitfieldintheUDMATRP register.TENV equalsthevalueprogrammed intheUDMATNVxP bitfieldin theUDMATENV register.Formore detailedinformation,see theTMS320DM644x DMSoC ATA ControllerUser's Guide (literature number SPRUE21 ).

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-41.Timings forATA/CF Module — UltraDMA AC Timing (seeFigure6-28through Figure6-37)(continued) A-513, -594, NO. MODE UNIT-810 MIN MAX 0 230 ns 1 200 ns 14 tFS FirstSTROBE time 2 170 ns 3 130 ns 4 120 ns 15 tLI Limitedinterlocktime 0-4 0 150 ns 16 tMLI Interlocktimewithminimum 0-4 20 ns 17 tUI Unlimitedinterlocktime 0-4 0 ns Maximum timeallowedforoutputdriversto18 tAZ 0-4 10 nsrelease 19 tZAH Minimum delaytimerequiredforoutput 0-4 20 ns Minimum delaytimefordrivertoassertornegate20 tZAD 0-4 0 ns(fromreleased) Envelopetime,DMACK toSTOP and DMACK to 21 tENV HDMARDY duringin-burstinitiationand from 0-4 (TENV + 1)P -0.5 (TENV + 1)P + 1.4 ns DMACK toSTOP duringdataoutburstinitiation 0 75 ns 22 tRFS Ready-to-final-STROBEtime 1 70 ns 2-4 60 ns Ready topause time,(HDMARDY (DIOR) to 0-4 (UDMATRP + 1)P -0.8 nsSTOP (DIOW)) 0 160 ns23 tRP Ready topause time,(DDMARDY (IORDY) to 1 125 nsDMARQ) 2-4 100 ns 24 tIORDYZ Maximum timebeforereleasingIORDY 0-4 20 ns 25 tZIORDY Minimum timebeforedrivingIORDY 0-4 0 ns Setupand holdtimeforDMACK (before26 tACK 0-4 20 nsassertionornegation) STROBE edge tonegationofDMARQ or 27 tSS assertionofSTOP (when senderterminatesa 0-4 50 ns burst) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

DSTROBE (IORDY) (A) STOP (DIOW )(A) HDMARDY (DIOR )(A) DD[15:0] DA[2:0], ATA_CS0 , ATA_CS1 tFS tENV tZFS tDZFS tDVS tZAD tZAD tFS tUI tACK tACK tZIORDY tAZ tACK DMACK t2CYC tDH tDS tDH tDS tDH DSTROBE (IORDY) DD[15:0] tCYC (A) tCYC (A) DMARQ tRP DSTROBE (IORDY) STOP (DIOW ) HDMARDY (DIOR) DD[15:0] DMACK tRFS TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com A. The definitionsforthe DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signallinesare not in effectuntil DMARQ and DMACK areasserted. Figure6-28.ATA/CF Initiatingan UltraDMA Data-InBurstTiming A. While DSTROBE (IORDY) timingistCYC at the device,itmay be differentat the host due to propagationdelay differenceson thecable. Figure6-29.ATA/CF SustainedUltraDMA Data-InData TransferTiming Figure6-30.ATA/CF Host Pausing an UltraDMA Data-InBurstTiming

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(IORDY) STOP (DIOW ) HDMARDY (DIOR) DD[15:0] DMACK DA[2:0], ATA_CS0 , ATA_CS 1 tACK tACK tIORDYZ tCVH tCVS CRC tACK tZAH tAZ tLI tLI tLI tSS DMARQ DSTROBE (IORDY) STOP (DIOW ) HDMARDY (DIOR) DD[15:0] DMACK DA[2:0], ATA_CS0 , ATA_CS1 tCVH tLI CRC tIORDYZ tAZ tMLI tZAH tACK tACK tLI tRP tRFS tACK tCVS tMLI TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-31.ATA/CF Device Terminatingan UltraDMA Data-InBurstTiming Figure6-32.ATA/CF Host Terminatingan UltraDMA Data-InBurstTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

HSTROBE (DIOR )(A) STOP (DIOW )(A) DDMARDY (IORDY) (A) DD[15:0] DMACK DA[2:0], ATA_CS0 , ATA_CS1 tUI tZIORDY tENV tACK tACK tACK tDZFS tLI tUI tDVS tDVH HSTROBE (DIOR ) DD[15:0] (OUT) t2CYC tCYC (A) tCYC (A) t2CYC tDVH tDVS tDVH tDVS tDVH TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com A. The definitionsforthe DIOW:STOP, IORDY:DDMARDY, and DIOR:HSTROBE signallinesare not in effectuntil DMARQ and DMACK areasserted. Figure6-33.ATA/CF Initiatingan UltraDMA Data-OutBurstTiming A. While HSTROBE (DIOR) timingistCYC at the host,itmay be differentat the devicedue to propagationdelay differenceson thecable. Figure6-34.ATA/CF SustainedUltraDMA Data-OutTransferTiming

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STOP (DIOW ) DDMARDY (IORDY ) HSTROBE (DIOR) DD[15:0] DMARQ DMACK tLI STOP (DIOW ) DDMARDY (IORDY) HSTROBE (DIOR ) DD[15:0] tLI tLI tSS tMLI tACK tIORDYZ tACK tCVS tCVH CRC DA[2:0], ATA_CS0 , ATA_CS1 tACK TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-35.ATA/CF Device Pausing an UltraDMA Data-OutBurstTiming Figure6-36.ATA/CF Host Terminatingan UltraDMA Data-OutBurstTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

STOP (DIOW ) DDMARDY (IORDY) HSTROBE (DIOR) DD[15:0] tMLI DA[2:0], ATA_CS0, ATA_CS1 tLI tRP tRFS tLI tMLI tCVS tIORDYZ tACK tACK tACK tCVH CRC TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-37.ATA/CF Device Terminatingan UltraDMA Data-OutBurstTiming

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DA[2:0], ATA_CS0 , ATA_CS1 tC (A) HDDIR DIOW DD[15:0] (OUT) tC (A) A. tC ≥ one cycle DA[2:0], ATA_CS0 , ATA_CS1 HDDIR DIOW DD[15:0] (OUT) tC (A) tC (A) A. tC ≥ one cycle TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.11.2.4ATA/CF HDDIR Timing Figure6-38throughFigure6-41show thebehaviorofHDDIR forthedifferenttypesoftransfers. Table6-42.Timing Requirements forHDDIR (1) A-513, -594, NO. UNIT-810 MIN MAX 1 tc Cycletime,ATA_CS[1:0]toHDDIR low E -3.1 2.1 ns (1) E = ATA clockcycle Figure6-38.ATA/CF HDDIR TaskfileWrite/SinglePIO WriteTiming Figure6-39.ATA/CF HDDIR PIO PostwriteStartTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

DA[2:0], ATA_CS0, ATA_CS1 tC (A) HDDIR DIOW DD[15:0] (OUT) DMACK tC (A) A. tC ≥ one cycle DA[2:0], ATA_CS0 , ATA_CS1 HDDIR DIOW DD[15:0] (OUT) DMACK CRC tC (A) A. tC ≥ one cycle TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-40.ATA/CF HDDIR MultiwordDMA WriteTransferTiming Figure6-41.ATA/CF HDDIR UltraDMA WriteTransferTiming

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6.12 MMC/SD/SDIO

The DM6446 MMC/SD/SDIO Controllerhas followingfeatures:

• MultiMediaCard(MMC).
• SecureDigital(SD)memory cardwithSecureData I/O(SDIO).
• MMC/SD/SDIO protocolsupport.
• Programmable clockfrequency.
• 256 bitRead/WriteFIFO tolowersystemoverhead.
• SlaveDMA transfercapability. SDIO is only supportedforWLAN operationthrough TI thirdparties.For more informationabout third-partyWLAN products,go tohttp://www.ti.com.davinciwlan. The MMC/SD/SDIO registermemory mapping isshown inTable6-43.

6.12.1 MMC/SD/SDIO PeripheralDescription(s)

Table6-43.MMC/SD/SDIO RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E1 0000 MMCCTL MMC ControlRegister 0x01E1 0004 MMCCLK MMC Memory ClockControlRegister 0x01E1 0008 MMCST0 MMC StatusRegister0 0x01E1 000C MMCST1 MMC StatusRegister1 0x01E1 0010 MMCIM MMC InterruptMask Register 0x01E1 0014 MMCTOR MMC Response Time-OutRegister 0x01E1 0018 MMCTOD MMC Data Read Time-OutRegister 0x01E1 001C MMCBLEN MMC BlockLengthRegister 0x01E1 0020 MMCNBLK MMC Number ofBlocksRegister 0x01E1 0024 MMCNBLC MMC Number ofBlocksCounterRegister 0x01E1 0028 MMCDRR MMC Data ReceiveRegister 0x01E1 002C MMCDXR MMC Data TransmitRegister 0x01E1 0030 MMCCMD MMC Command Register 0x01E1 0034 MMCARGHL MMC Argument Register 0x01E1 0038 MMCRSP01 MMC Response Register0 and 1 0x01E1 003C MMCRSP23 MMC Response Register2 and 3 0x01E1 0040 MMCRSP45 MMC Response Register4 and 5 0x01E1 0044 MMCRSP67 MMC Response Register6 and 7 0x01E1 0048 MMCDRSP MMC Data Response Register 0x01E1 004C -0x01E1 004F - Reserved 0x01E1 0050 MMCCIDX MMC Command IndexRegister 0x01E1 0054 -0x01E1 0063 - Reserved 0x01E1 0064 SDIOCTL SDIO ControlRegister 0x01E1 0068 SDIOST0 SDIO StatusRegister0 0x01E1 006C SDIOIEN SDIO InterruptEnableRegister 0x01E1 0070 SDIOIST SDIO InterruptStatusRegister 0x01E1 0074 MMCFIFOCTL MMC FIFO ControlRegister 0x01E1 0078 -0x01E1 FFFF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

START XMIT Valid Valid Valid END SD_CLK SD_CMD 13 13 13 START XMIT Valid Valid Valid END SD_CLK SD_CMD 1097 TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

6.12.2 MMC/SD/SDIO ElectricalData/Timing

Table6-44.Timing Requirements forMMC/SD/SDIO Module (seeFigure6-43and Figure6-45) A-513, -594, -810NO. UNIT STANDARD MODE MIN MAX 1 tsu(CMDV-CLKH) Setuptime,SD_CMD validbeforeSD_CLK high 5 ns 2 th(CLKH-CMDV) Holdtime,SD_CMD validafterSD_CLK high 5 ns 3 tsu(DATV-CLKH) Setuptime,SD_DATx validbeforeSD_CLK high 5 ns 4 th(CLKH-DATV) Holdtime,SD_DATx validafterSD_CLK high 5 ns Table6-45.SwitchingCharacteristicsOver Recommended OperatingConditionsforMMC/SD/SDIO Module (1)(seeFigure6-42through Figure6-45) A-513, -594, -810NO. PARAMETER UNIT STANDARD MODE MIN MAX 7 f(CLK) Operatingfrequency,SD_CLK 0 25 MHz 8 f(CLK_ID) Identificationmode frequency,SD_CLK 0 400 KHz 9 tW(CLKL) Pulsewidth,SD_CLK low 10 ns 10 tW(CLKH) Pulsewidth,SD_CLK high 10 ns 11 tr(CLK) Risetime,SD_CLK 10 ns 12 tf(CLK) Falltime,SD_CLK 10 ns 13 td(CLKLL-CMD) Delaytime,SD_CLK lowtoSD_CMD transition -7.5 13 ns 14 tdis(CLKL-DAT) Disabletime,SD_CLK lowtoSD_DATx transition -7.5 13 ns (1) P = PeriodofSD_CLK (SYSCLK5), innanoseconds(ns). Figure6-42.MMC/SD/SDIO Host Command Timing Figure6-43.MMC/SD/SDIO Card Response Timing

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SD_CLK SD_DATx 1414 14 14 Start D0 D1 Dx End SD_CLK SD_DATx 3 3 TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-44.MMC/SD/SDIO Host WriteTiming Figure6-45.MMC/SD/SDIO Host Read and Card CRC StatusTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

MHz5795454545. 3264 35MHz27 /c61/c247 /c248 /c246/c231 /c232 /c230/c61/c45 ntscscf MHz4332628318. 41017 167MHz27 /c61/c247 /c248 /c246/c231 /c232 /c230/c61/c45 palscf TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

6.13 Video ProcessingSub-System (VPSS) Overview

The DM6446 VideoProcessingSub-System (VPSS) providesa VideoProcessingFrontEnd (VPFE) input interfaceforexternalimaging peripherals(i.e.,image sensors,video decoders,etc.)and a Video ProcessingBack End (VPBE) outputinterfacefordisplaydevices,such as analogSDTV displays,digital LCD panels,HDTV videoencoders,etc. Note:The VPSS module issupportedwithLinuxApplicationPeripheralInterfaces(APIs)commonly used by videoapplicationdevelopers.Video forLinux2 or V4L2 uses APIs commonly used forvideocapture. The typicaluse cases oftheVPSS VideoFront-End(VPFE) have been portedtothisLinuxAPI structure. V4L2 supportsstandardvideointerfacessuch as:BT.656 and Y/C mode. Othermodules withintheVPSS VPFE forexample, the Preview Engine,H3A, and Histogramare not currentlysupportedwithinthe softwareAPIs.The VPSS Back-End (VPBE) uses FBDev/DirectFBas the APIs.Certainfunctionalities withinthe VPBE have not been implemented in the FBDev/DirectFBAPIs. For modes/functionsnot implementedinsoftware,itistheuser'sresponsibilitytomodifythesoftwaredrivers/APIs. The VPSS registermemory mapping isshown inTable6-46. Table6-46.VPSS RegisterDescriptions HEX ADDRESS REGISTER ACRONYM DESCRIPTIONRANGE 0x01C7 3400 PID PeripheralRevisionand ClassInformation 0x01C7 3404 PCR VPSS ControlRegister 0x01C7 3408 - Reserved 0x01C7 3508 SDR_REG_EXP SDRAM Non Real-TimeRead RequestExpand 0x01C7 350C - - Reserved 0x01C7 3FFF To ensureNTSC- and PAL-compliantoutputvideo,thestabilityoftheinputclocksourceisveryimportant. TI recommends a 27-MHz, 50-ppm crystal.Ceramic oscillatorsare not recommended. The NTSC/PAL colorsub-carrierfrequencyisderivedfrom the27-MHz clock.Therefore,ifthe27-MHz clockdrifts,then thecolorsub-carrierfrequencywilldriftas well.Assuming no 27-MHz frequencydrift,thecolorsub-carrier frequencyisgeneratedas follows: To ensure the colorsub-carrierfrequencywillnot driftout of spec, the user must followthe crystal requirementsdiscussedinSection6.5.1,ClockInputOption1 – Crystal.Alternatively,iftheVPBE input clockissourcedfromtheVPBECLK orVPFE clockinputs,theseclocksmust have a frequencystabilityof ±50 ppm toensuretheNTSC and PAL compliantoutputvideo.

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6.13.1 Video ProcessingFront-End(VPFE)

The Video ProcessingFront-End(VPFE) consistsof the CCD Controller(CCDC), Preview Engine, Resizer,Hardware 3A (H3A) StatisticGenerator,and Histogramblocks.Together,thesemodules provide DM6446 witha powerfuland flexiblefront-endinterface.These modules arebrieflydescribedbelow:

• The CCDC providesan interfacetoimage sensorsand digitalvideosources.
• The PreviewEngineisa parameterizedhardwiredimage processingblockwhichisused forconverting RAW colordatafroma BayerpatterntoYUV 4:2:2.
• The Resizermodule re-sizestheinputimage datatothedesireddisplayorvideoencodingresolution
• The H3A module providescontrolloopsforAutoFocus (AF),AutoWhiteBalance(AWB) and Auto Exposure(AE).
• The Histogrammodule binsinputcolorpixels,dependingon theamplitude,and providesstatistics requiredtoimplementvarious3A (AE/AF/AWB) algorithmsand tunethefinalimage/videooutput. The VPFE registermemory mapping isshown inTable6-47. Table6-47.VPFE RegisterAddress Range Descriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C7 0400 – 0x01C7 07FF CCDC VPFE – CCD Controller 0x01C7 0800 – 0x01C7 0BFF PREV VPFE – PreviewEngine/ImageSignalProcessor 0x01C7 0C00 – 0x01C7 09FF RESZ VPFE – Resizer 0x01C7 1000 – 0x01C7 13FF HIST VPFE – Histogram 0x01C7 1400 – 0x01C7 17FF H3A VPFE – Hardware 3A (Auto-Focus/WB/Exposure) 0x01C7 3400 – 0x01C7 3FFF VPSS VPSS Shared BufferLogicRegisters 6.13.1.1CCD Controller(CCDC) The CCDC receivesraw image/videodatafromsensors(CMOS orCCD) orYUV videodatainnumerous formatsfromvideodecoderdevices.The followingfeaturesaresupportedby theCCDC module.
• ConventionalBayerpatternformats.
• GeneratesHD/VD timingsignalsand fieldID toan externaltiminggeneratororcan synchronizetoan externaltiminggenerator.
• Interfacetoprogressiveand interlacedsensors.
• REC656/CCIR-656 standard(YCbCr 4:2:2format,either8-or16-bit).
• YCbCr 4:2:2format,either8-or16-bitwithdiscreteH and VSYNC signals.
• Up to16-bitinput.
• Opticalblackclampingsignalgeneration.
• Shuttersignalcontrol.
• Digitalclampingand blacklevelcompensation.
• 10-bitto8-bitA-lawcompression.
• Low-passfilterpriortowritingtoSDRAM. Ifthisfilterisenabled,2 pixelseach intheleftand right edges ofeach linearecroppedfromtheoutput.
• Outputrangefrom16-bitsto8-bitswide(8-bitswideallowsfor50% savinginstoragearea).
• Downsampling viaprogrammablecullingpatterns.
• ControloutputtotheDDR2 viaan externalwriteenablesignal.
• Up to16K pixels(imagesize)inboththehorizontaland verticaldirection. The CCDC registermemory mapping isshown inTable6-48. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 157 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-48.CCDC RegisterDescriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0400 PID PeripheralRevisionand ClassInformation 0x01C7 0404 PCR PeripheralControlRegister 0x01C7 0408 SYN_MODE SYNC and Mode SetRegister 0x01C7 040C HD_VD_WID HD and VD SignalWidth 0x01C7 0410 PIX_LINES Number ofPixelsina HorizontalLineand Number ofLinesina Frame 0x01C7 0414 HORZ_INFO HorizontalPixelInformation 0x01C7 0418 VERT_START VerticalLine-SettingsfortheStartingPixel 0x01C7 041C VERT_LINES Number ofVerticalLines 0x01C7 0420 CULLING CullingInformationinHorizontaland VerticalDirections 0x01C7 0424 HSIZE_OFF HorizontalSize 0x01C7 0428 SDOFST SDRAM/DDRAM LineOffset 0x01C7 042C SDR_ADDR SDRAM Address 0x01C7 0430 CLAMP OpticalBlackClampingSettings 0x01C7 0434 DCSUB DC Clamp 0x01C7 0438 COLPTN CCD ColorPattern 0x01C7 043C BLKCMP BlackCompensation 0x01C7 0440 - Reserved 0x01C7 0444 - Reserved 0x01C7 0448 VDINT VD InterruptTiming 0x01C7 044C ALAW A-Law Setting 0x01C7 0450 REC656IF REC656 Interface 0x01C7 0454 CCDCFG CCD Configuration 0x01C7 0458 FMTCFG Data Reformatter/VideoPortConfiguration 0x01C7 045C FMT_HORZ Data Reformatter/VideoInputInterfaceHorizontalInformation 0x01C7 0460 FMT_VERT Data Reformatter/VideoInputInterfaceVerticalInformation 0x01C7 0464 FMT_ADDR0 AddressPointer0 Setup 0x01C7 0468 FMT_ADDR1 AddressPointer1 Setup 0x01C7 046C FMT_ADDR2 AddressPointer2 Setup 0x01C7 0470 FMT_ADDR3 AddressPointer3 Setup 0x01C7 0474 FMT_ADDR4 AddressPointer4 Setup 0x01C7 0478 FMT_ADDR5 AddressPointer5 Setup 0x01C7 047C FMT_ADDR6 AddressPointer6 Setup 0x01C7 0480 FMT_ADDR7 AddressPointer7 Setup 0x01C7 0484 PRGEVEN_0 Program Entries0-7forEven Line 0x01C7 0488 RRGEVEN_1 Program Entries8-15forEven Line 0x01C7 048C PRGGODD_0 Program Entries0-7forOdd Line 0x01C7 0490 PRGGODD_1 Program Entries8-15forOdd Line 0x01C7 0494 VP_OUT VideoPortOutputSettings

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.13.1.2Preview Engine The previewenginetransformsraw unprocessedimage/videodata from a sensor(CMOS or CCD) into YCbCr 4:2:2data.The outputof the previewengineisused forboth videocompressionand external displaydevicessuch as a NTSC/PAL analog encoder or a digitalLCD. The followingfeaturesare supportedby thepreviewengine.

• AcceptsconventionalBayerpatternformats.
• Inputimage/videodatafromeithertheCCD/CMOS controllerortheDDR2 memory.
• Outputwidthup to1280 pixelswide.
• Automatic/mandatorycroppingofpixels/lineswhen edge processingisperformed.Ifallthe correspondingmodules areenabled,a totalof14 pixelsperline(7leftmost and 7 rightmost)and 8 lines(4topmost and 4 bottommost)willnotbe output.
• Simplehorizontalaveraging(byfactorsof2,4,or8)tohandleinputwidthsthataregreaterthan1280 (plusthecroppednumber)pixelswide.
• Dark framecapturetoDDR2.
• Dark framesubtractionforeveryinputraw dataframe,fetchedfromDDR2, pixel-by-pixeltoimprove videoquality.
• Lens shadingcompensation.Each inputpixelismultipliedwitha corresponding8-bitgainvalueand theresultisrightshiftedby a programmableparameter(0-7bits).
• A-lawdecompressiontotransformnon-linear8-bitdatato10-bitlineardata.Thisfeatureallowsdatain DDR2 tobe 8-bits,whichsaves50% oftheareaiftheinputtothepreviewengineisfromtheDDR2.
• Horizontalmedian filterforreducingtemperatureinducednoiseinpixels.
• Programmable noisefilterthatoperateson a 3x3 gridofthesame color(effectively,thisisa fiveline storagerequirement).
• Digitalgainand whitebalance(colorseparategainforwhitebalance).
• Programmable CFA interpolationthatoperateson a 5x5 grid.
• ConventionalBayerpatternRGB and complementarycolorsensors.
• Supportforan image thatisdownsampled by 2x inthehorizontaldirection(withand withoutphase correction).Inthiscase,theimage is2/3populatedinsteadoftheconventional1/3colors.
• Supportforan image thatisdownsampled by 2x inboththehorizontaland verticaldirection.Inthis case,theimage isfullypopulatedinsteadoftheconventional1/3colors.
• Programmable RGB-to-RGB blendingmatrix(9coefficientsforthe3x3 matrix).
• Fullyprogrammablegamma correction(1024entriesforeach colorheldinan on-chipRAM).
• Programmable colorconversion(RGB toYUV) coefficients(9coefficientsforthe3x3 matrix).
• Luminance enhancement (non-linear)and chrominancesuppression& offset. The PreviewEngineregistermemory mapping isshown inTable6-49. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-49.Preview Engine RegisterDescriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0800 PID PeripheralRevisionand ClassInformation 0x01C7 0804 PCR PeripheralControlRegister 0x01C7 0808 HORZ_INFO HorizontalInformation/Setup 0x01C7 080C VERT_INFO VerticalInformation/Setup 0x01C7 0810 RSDR_ADDR Read AddressFrom SDRAM 0x01C7 0814 RADR_OFFSET LineOffsetfortheRead Data 0x01C7 0818 DSDR_ADDR Dark Frame AddressFrom SDRAM 0x01C7 081C DRKF_OFFSET LineOffsetfortheDark Frame Data 0x01C7 0820 WSDR_ADDR WriteAddresstotheSDRAM 0x01C7 0824 WADD_OFFSET LineOffsetfortheWriteData 0x01C7 0828 AVE InputFormatter/Averager 0x01C7 082C HMED HorizontalMedian Filter 0x01C7 0830 NF NoiseFilter 0x01C7 0834 WB_DGAIN WhiteBalanceDigitalGain 0x01C7 0838 WBGAIN WhiteBalanceCoefficients 0x01C7 083C WBSEL WhiteBalanceCoefficientsSelection 0x01C7 0840 CFA CFA Register 0x01C7 0844 BLKADJOFF BlackAdjustmentOffset 0x01C7 0848 RGB_MAT1 RGB2RGB BlendingMatrixCoefficients 0x01C7 084C RGB_MAT2 RGB2RGB BlendingMatrixCoefficients 0x01C7 0850 RGB_MAT3 RGB2RGB BlendingMatrixCoefficients 0x01C7 0854 RGB_MAT4 RGB2RGB BlendingMatrixCoefficients 0x01C7 0858 RGB_MAT5 RGB2RGB BlendingMatrixCoefficients 0x01C7 085C RGB_OFF1 RGB2RGB BlendingMatrixOffsets 0x01C7 0860 RGB_OFF2 RGB2RGB BlendingMatrixOffsets 0x01C7 0864 CSC0 ColorSpace ConversionCoefficients 0x01C7 0868 CSC1 ColorSpace ConversionCoefficients 0x01C7 086C CSC2 ColorSpace ConversionCoefficients 0x01C7 0870 CSC_OFFSET ColorSpace ConversionOffsets 0x01C7 0874 CNT_BRT Contrastand BrightnessSettings 0x01C7 0878 CSUP ChrominanceSuppressionSettings 0x01C7 087C SETUP_YC Maximum/Minimum Y and C Settings 0x01C7 0880 SET_TBL_ADDRESS SetupTableAddresses 0x01C7 0884 SET_TBL_DATA SetupTableData

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.13.1.3Resizer The resizermodule can acceptinputimage/videodata from eitherthe previewengine or DDR2. The outputoftheresizermodule issenttoDDR2. The followingfeaturesaresupportedby theresizermodule.

• An outputwidthup to1280 horizontalpixels.
• InputfromexternalDDR2.
• Up to4x upsampling(digitalzoom).
• Bi-cubicinterpolation(4-taphorizontal,4-tapvertical)can be implementedwiththeprogrammablefilter coefficients.
• 8 phases offiltercoefficients.
• Optionalbi-linearinterpolationforthechrominancecomponents.
• Up to1/4xdownsampling
• 4-taphorizontaland 4-tapverticalfiltercoefficients(with8-phases)for1x to1/2xdownsampling
• 1/2xto1/4xdownsampling,for7-tapmode with4-phases.
• ResizingeitherYUV 4:2:2packed data(16-bits)orcolorseparatedata(8-bitdatawithinDDR) thatis contiguous.
• Separate/independentresizingfactorforthehorizontaland verticaldirections.
• Upsamplingand downsamplingratiosthatareavailableare:256/N,withN rangingfrom64 to1024.
• Programmable luminancesharpeningafterthehorizontalresizingand beforetheverticalresizingstep. The Resizerregistermemory mapping isshown inTable6-50. Table6-50.ResizerRegisterDescriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0C00 PID PeripheralRevisionand ClassInformation 0x01C7 0C04 PCR PeripheralControlRegister 0x01C7 0C08 RSZ_CNT ResizerControlBits 0x01C7 0C0C OUT_SIZE OutputWidthand HeightAfterResizing 0x01C7 0C10 IN_START InputStartingInformation 0x01C7 0C14 IN_SIZE InputWidthand HeightBeforeResizing 0x01C7 0C18 SDR_INADD InputSDRAM Address 0x01C7 0C1C SDR_INOFF SDRAM OffsetfortheInputLine 0x01C7 0C20 SDR_OUTADD OutputSDRAM Address 0x01C7 0C24 SDR_OUTOFF SDRAM OffsetfortheOutputLine 0x01C7 0C28 HFILT10 HorizontalFilterCoefficients1 and 0 0x01C7 0C2C HFILT32 HorizontalFilterCoefficients3 and 2 0x01C7 0C30 HFILT54 HorizontalFilterCoefficients5 and 4 0x01C7 0C34 HFILT76 HorizontalFilterCoefficients7 and 6 0x01C7 0C38 HFILT98 HorizontalFilterCoefficients9 and 8 0x01C7 0C3C HFILT1110 HorizontalFilterCoefficients11 and 10 0x01C7 0C40 HFILT1312 HorizontalFilterCoefficients13 and 12 0x01C7 0C44 HFILT1514 HorizontalFilterCoefficients15 and 14 0x01C7 0C48 HFILT1716 HorizontalFilterCoefficients17 and 16 0x01C7 0C4C HFILT1918 HorizontalFilterCoefficients19 and 18 0x01C7 0C50 HFILT2120 HorizontalFilterCoefficients21 and 20 0x01C7 0C54 HFILT2322 HorizontalFilterCoefficients23 and 22 0x01C7 0C58 HFILT2524 HorizontalFilterCoefficients25 and 24 0x01C7 0C5C HFILT2726 HorizontalFilterCoefficients27 and 26 0x01C7 0C60 HFILT2928 HorizontalFilterCoefficients29 and 28 0x01C7 0C64 HFILT3130 HorizontalFilterCoefficients31 and 30 Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-50.ResizerRegisterDescriptions(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 0C68 VFILT10 VerticalFilterCoefficients1 and 0 0x01C7 0C6C VFILT32 VerticalFilterCoefficients3 and 2 0x01C7 0C70 VFILT54 VerticalFilterCoefficients5 and 4 0x01C7 0C74 VFILT76 VerticalFilterCoefficients7 and 6 0x01C7 0C78 VFILT98 VerticalFilterCoefficients9 and 8 0x01C7 0C7C VFILT1110 VerticalFilterCoefficients11 and 10 0x01C7 0C80 VFILT1312 VerticalFilterCoefficients13 and 12 0x01C7 0C84 VFILT1514 VerticalFilterCoefficients15 and 14 0x01C7 0C88 VFILT1716 VerticalFilterCoefficients17 and 16 0x01C7 0C8C VFILT1918 VerticalFilterCoefficients19 and 18 0x01C7 0C90 VFILT2120 VerticalFilterCoefficients21 and 20 0x01C7 0C94 VFILT2322 VerticalFilterCoefficients23 and 22 0x01C7 0C98 VFILT2524 VerticalFilterCoefficients25 and 24 0x01C7 0C9C VFILT2726 VerticalFilterCoefficients27 and 26 0x01C7 0CA0 VFILT2928 VerticalFilterCoefficients29 and 28 0x01C7 0CA4 VFILT3130 VerticalFilterCoefficients31 and 30 0x01C7 0CA8 YENH Luminance Enhancer 6.13.1.4Hardware 3A (H3A) The Hardware 3A (H3A) module providescontrolloopsforAuto Focus,Auto White Balance and Auto Exposure.Thereare2 main components oftheH3A module:

• AutoFocus (AF)Engine
• AutoExposure(AE)& AutoWhiteBalance(AWB) Engine The AF engineextractsand filtersthe red,green,and bluedata from the inputimage/videodata and provideseithertheaccumulationorpeaks ofthedataina specifiedregion.The specifiedregionisa two dimensionalblockofdataand isreferredtoas a “paxel”forthecase ofAF. The AE/AWB Engine accumulatesthevaluesand checks forsaturatedvaluesina sub samplingofthe videodata.Inthecase oftheAE/AWB, thetwo-dimensionalblockofdataisreferredtoas a “window”. The number,dimensions,and startingpositionoftheAF paxelsand theAE/AWB windows areseparately programmable. The H3A registermemory mapping isshown inTable6-51.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-51.H3A RegisterDescriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 1400 PID PeripheralRevisionand ClassInformation 0x01C7 1404 PCR PeripheralControlRegister 0x01C7 1408 AFPAX1 SetupfortheAF EnginePaxelConfiguration 0x01C7 140C AFPAX2 SetupfortheAF EnginePaxelConfiguration 0x01C7 1410 AFPAXSTART StartPositionforAF EnginePaxels 0x01C7 1414 AFIIRSH StartPositionforIIRSH 0x01C7 1418 AFBUFST SDRAM/DDRAM StartAddressforAF Engine 0x01C7 141C AFCOEF010 IIRFilterCoefficientData forSET 0 0x01C7 1420 AFCOEF032 IIRFilterCoefficientData forSET 0 0x01C7 1424 AFCOEFF054 IIRFilterCoefficientData forSET 0 0x01C7 1428 AFCOEFF076 IIRFilterCoefficientData forSET 0 0x01C7 142C AFCOEFF098 IIRFilterCoefficientData forSET 0 0x01C7 1430 AFCOEFF0010 IIRFilterCoefficientData forSET 0 0x01C7 1434 AFCOEF110 IIRFilterCoefficientData forSET 1 0x01C7 1438 AFCOEF132 IIRFilterCoefficientData forSET 1 0x01C7 143C AFCOEFF154 IIRFilterCoefficientData forSET 1 0x01C7 1440 AFCOEFF176 IIRFilterCoefficientData forSET 1 0x01C7 1444 AFCOEFF198 IIRFilterCoefficientData forSET 1 0x01C7 1448 AFCOEFF1010 IIRFilterCoefficientData forSET 1 0x01C7 144C AEWWIN1 ConfigurationforAE/AWB Windows 0x01C7 1450 AEWINSTART StartPositionforAE/AWB Windows 0x01C7 1454 AEWINBLK StartPositionand HeightforBlackLineofAE/AWB Windows 0x01C7 1458 AEWSUBWIN ConfigurationforSubsample Data inAE/AWB Window 0x01C7 145C AEWBUFST SDRAM/DDRAM StartAddressforAE/AWB Engine Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.13.1.4.1Auto Focus (AF)Engine The followingfeaturesaresupportedby theAutoFocus (AF)Engine.

• Peak Mode ina Paxel(aPaxelisdefinedas a two dimensionalblockofpixels).
• Accumulatethemaximum Focus Valueofeach lineina Paxel
• Accumulation/SumMode (insteadofPeak mode).
• AccumulateFocus Valueina Paxel.
• Up to36 Paxelsinthehorizontaldirectionand up to128 Paxelsintheverticaldirection.
• Programmable widthand heightforthePaxel.Allpaxelsintheframewillbe ofsame size.
• Programmable red,green,and bluepositionwithina 2x2 matrix.
• Separatehorizontalstartforpaxeland filtering.
• Programmable verticallineincrementswithina paxel.
• ParallelIIRfiltersconfiguredina dual-biquadconfigurationwithindividualcoefficients(2filterswith11 coefficientseach).The filtersareintendedtocompute thesharpness/peaksintheframetofocuson. 6.13.1.4.2Auto Exposure (AE)and Auto White Balance (AWB) Engine The followingfeaturesaresupportedby theAutoExposure(AE)and AutoWhiteBalance(AWB) Engine.
• Accumulateclippedpixelsalongwithallnon-saturatedpixels.
• Up to36 horizontalwindows.
• Up to128 verticalwindows.
• Programmable widthand heightforthewindows.Allwindows intheframewillbe ofsame size.
• Separateverticalstartcoordinateand heightfora blackrow ofpaxelsthatisdifferentthanthe remainingcolorpaxels.
• Programmable HorizontalSamplingPointsina window.
• Programmable VerticalSamplingPointsina window.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.13.1.5Histogram The histogrammodule acceptsraw image/videodataand binsthepixelson a value(andcolorseparate) basis.The valueofthepixelitselfisnotstored,buteach bincontainsthenumber ofpixelsthatarewithin theappropriatesetrange.The sourceoftheraw dataforthehistogramistypicallya CCD/CMOS sensor (viatheCCDC module)or optionallyfrom DDR2. The followingfeaturesare supportedby thehistogram module.

• Up tofourregions/areas.
• Separatehorizontal/verticalstartand end positionforeach region.
• Pixelsfromoverlappingregionsareaccumulatedintothehighestpriorityregion. The priorityis:region0> region1> region2> region3.
• InterfacetoconventionalBayerpattern.Each regioncan accumulateeither3 or4 colors.
• 32,64,128,or256 binspercolorperregion.
• 32,64,or128 binspercolorfor2 regions.
• 32 or64 binspercolorfor3 or4 regions.
• AutomaticclearofhistogramRAM afteran ARM read.
• Saturationofthepixelcountifthecountexceedsthemaximum value(eachmemory locationis20-bit wide).
• Downshiftrangingfrom0 to7 bits(maximum binrange128).
• The lastbin(highestrangeofvalues)willaccumulateany valuethatishigherthanthelowerbound. The Histogramregistermemory mapping isshown inTable6-52. Table6-52.Histogram RegisterDescriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 1000 PID PeripheralRevisionand ClassInformationRegister 0x01C7 1004 PCR PeripheralControlRegister 0x01C7 1008 HIST_CNT HistogramControlBitsRegister 0x01C7 100C WB_GAIN White/ChannelBalanceSettingsRegister 0x01C7 1010 R0_HORZ Region0 HorizontalInformationRegister 0x01C7 1014 R0_VERT Region0 VerticalInformationRegister 0x01C7 1018 R1_HORZ Region1 HorizontalInformationRegister 0x01C7 101C R1_VERT Region1 VerticalInformationRegister 0x01C7 1020 R2_HORZ Region2 HorizontalInformationRegister 0x01C7 1024 R2_VERT Region2 VerticalInformationRegister 0x01C7 1028 R3_HORZ Region3 HorizontalInformationRegister 0x01C7 102C R3_VERT Region3 VerticalInformationRegister 0x01C7 1030 HIST_ADDR HistogramAddressforData tobe Read Register 0x01C7 1034 HIST_DATA HistogramData ThatisRead From theMemory Register 0x01C7 1038 RADD Read AddressFrom DDR2 Memory Register 0x01C7 103C RADD_OFF Read AddressOffsetforEach LineintheDDR2 Memory Register 0x01C7 1040 H_V_INFO Horizontal/VerticalInformationRegister(Horizontal/VerticalNumber of PixelsWhen Data isRead From DDR2 Memory InformationRegister) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 165 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.13.1.6VPFE ElectricalData/Timing Table6-53.Timing Requirements forVPFE PCLK Master/SlaveMode (seeFigure6-46) A-513, -594, NO. UNIT-810 MIN MAX (A-513and -594devices) 10.204or13.33(1) ns 1 tc(PCLK) Cycletime,PCLK (-810devices) 9.25or13.33(1) ns 2 tw(PCLKH) Pulseduration,PCLK high 4.4 ns 3 tw(PCLKL) Pulseduration,PCLK low 4.4 ns 4 tt(PCLK) Transitiontime,PCLK 3 ns (1) When PCLK sourcestheclockforboththeVPFE and VPBE, theminimum cycletimeof13.33ns (specifiedinTable6-60,Timing RequirementsforVPBE CLK InputsforVPBE) must be met.When PCLK sourcestheclockforonlytheVPFE, a minimum cycletimeof 10.2ns may be used forA-513 and -594devicesand a minimum cycletimeof9.25ns may be used for-810devices. Figure6-46.VPFE PCLK Timing Table6-54.Timing Requirements forVPFE (CCD) SlaveMode (1)(seeFigure6-47) A-513, -594, NO. UNIT-810 MIN MAX 5 tsu(CCDV-PCLK) Setuptime,CCD validbeforePCLK edge 3 ns 6 th(PCLK-CCDV) Holdtime,CCD validafterPCLK edge 2 ns 7 tsu(HDV-PCLK) Setuptime,HD validbeforePCLK edge 3 ns 8 th(PCLK-HDV) Holdtime,HD validafterPCLK edge 2 ns 9 tsu(VDV-PCLK) Setuptime,VD validbeforePCLK edge 3 ns 10 th(PCLK-VDV) Holdtime,VD validafterPCLK edge 2 ns 11 tsu(C_WEV-PCLK) Setuptime,C_WE validbeforePCLK edge 3 ns 12 th(PCLK-C_WEV) Holdtime,C_WE validafterPCLK edge 2 ns 13 tsu(C_FIELDV-PCLK) Setuptime,C_FIELD validbeforePCLK edge 3 ns 14 th(PCLK-C_FIELDV) Holdtime,C_FIELD validafterPCLK edge 2 ns (1) The VPFE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode the risingedge ofPCLK isreferenced.When innegativeedge clockingmode thefallingedge ofPCLK isreferenced.

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(Positive Edge Clocking) PCLK (Negative Edge Clocking) 7, 9 HD/VD CCD[15:0] 8, 10 11, 13 12, 14 C_WE/C_FIELD PCLK (Positive Edge Clocking) 15 16 23 24 CCD[15:0] C_WE PCLK (Negative Edge Clocking) TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Figure6-47.VPFE (CCD) SlaveMode InputData Timing Table6-55.Timing Requirements forVPFE (CCD) Master Mode (1)(seeFigure6-48) A-513, -594, NO. UNIT-810 MIN MAX 15 tsu(CCDV-PCLK) Setuptime,CCD validbeforePCLK edge 3 ns 16 th(PCLK-CCDV) Holdtime,CCD validafterPCLK edge 2 ns 23 tsu(CWEV-PCLK) Setuptime,C_WE validbeforePCLK edge 3 ns 24 th(PCLK-CWEV) Holdtime,C_WE validafterPCLK edge 2 ns (1) The VPFE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode the risingedge ofPCLK isreferenced.When innegativeedge clockingmode thefallingedge ofPCLK isreferenced. Figure6-48.VPFE (CCD) Master Mode InputData Timing Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 167 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

(Negative Edge Clocking) HD VD C_FIELD PCLK (Positive Edge Clocking) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-56.SwitchingCharacteristicsOver Recommended OperatingConditionsforVPFE (CCD) Master Mode (1)(seeFigure6-49) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 18 td(PCLK-HDV) Delaytime,PCLK edge toHD valid 0.5 8 ns 20 td(PCLK-VDV) Delaytime,PCLK edge toVD valid 0.5 8 ns 22 td(PCLK-C_FIELDV) Delaytime,PCLK edge toC_FIELD valid 0.5 8.3 ns (1) The VPFE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode the risingedge ofPCLK isreferenced.When innegativeedge clockingmode thefallingedge ofPCLK isreferenced. Figure6-49.VPFE (CCD) Master Mode ControlOutput Data Timing

6.13.2 Video ProcessingBack-End (VPBE)

The Video ProcessingBack-End (VPBE) consistsof the On-Screen Display(OSD) module,the Video Encoder (VENC) includingtheDigitalLCD (DLCD) and Analog (i.e.,DAC) interfaces.The videoencoder generatesanalogvideooutput.The DLCD controllergeneratesdigitalRGB/YCbCr dataoutputand timing signals. The VPBE registermemory mapping isshown inTable6-57. Table6-57.VPBE RegisterDescriptions Address Register Description 0x01C7 2780 PID PeripheralRevisionand ClassInformationRegister 0x01C7 2784 PCR PeripheralControlRegister 6.13.2.1On-Screen Display(OSD) The majorfunctionoftheOSD module istogatherand blendvideodataand display/bitmapdatabefore feedingitto the Video Encoder (VENC) inYCbCr format.The videoand displaydata isread from an externalmemory, typicallyDDR2. The OSD isprogrammed viacontroland parameterregisters.The followingaretheprimaryfeaturesthataresupportedby theOSD.

• Simultaneousdisplayoftwo videowindows and two OSD windows (VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1). – Separateenableforeach window – Programmable width,height,and base startingcoordinatesforeach window – Externalmemory addressand offsetregistersforeach window – Supportforx2 and x4 zoom inboththehorizontaland verticaldirection – OSDWIN1 can be used as an attributewindow forOSDWIN0

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 – Attributewindow blinkingintervals – Field/framemode forthewindows (interlaced/progressive) – Eightstepblendingprocessbetween theOSD and videowindows – TransparencysupportfortheOSD and videodata(when a bitmappixeliszero,therewillbe no blendingforthatcorrespondingvideopixel) – ResizefromVGA toNTSC/PAL (640x480to720x576)forboththeOSD and videowindows – Reads inYCbCr datain4:2:2formatfromexternalmemory, withthecapabilityforswappingthe orderoftheCbCr component inthe32-bitword (thisisrelevanttothetwo videowindows) – Supportfora ping-pongbufferscheme thatcan be used forVIDWIN0 (allowsforvideodatatobe accessedfromtwo differentlocationsinDDR2) – Each OSD window (eitherone,butnotbothatthesame time)iscapableofreadinginRGB data (16-bitdatawithsixbitsforthegreenand fivebitseach fortheredand bluecolors)insteadof bitmapdatainYCbCr formatrestrictedtoa maximum of8-bits – The OSD bitmapdatawidthisselectablebetween 1,2,4,or8-bits. – Each OSD window supports16 entriesforthebitmap(toindexintoa 256 entryRAM/ROM CLUT table). – Indirectsupportfor24-bitRGB inputdata(whichwillbe transformedinto16-bitYCbCr video window data)viathewrapperinterfaceintheVPBE.

• Supportfora rectangularcursorwindow and a programmablebackgroundcolorselection. – Programmable colorpalettewiththeabilitytoselectbetween a RAM/ROM tablewithsupportfor 256 colors. – The width,height,and colorofthecursorisprogrammable. – The displaypriorityis:Rectangular-Cursor> OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 > backgroundcolor
• SupportforattenuationoftheYCbCr valuesfortheREC601 standard. The followingrestrictionsexistintheOSD module.
• BoththeOSD windows and VIDWIN1 shouldbe fullycontainedinsideVIDWIN0.
• When one oftheOSD windows issetinRGB mode, itcannotoverlapwithVIDWIN1.
• The OSD cannotsupportmore than256 colorentriesintheCLUT RAM/ROM. Some applications requirehighernumber ofentries,and one workaroundistouse VIDWIN1 as an overlaymimickingthe OSD window.Anotheroptionistouse theRGB mode forone oftheOSD windows whichallowsfora totalof16-bitsfortheR, G, and B colors(64K colors).
• The OSD can onlyreadYCbCr in4:2:2interleavedformatforthevideowindows.Otherformats,either colorseparatestorageor4:4:4/4:2:0interleaveddataisnotsupported.
• Iftheverticalresizefilterisenabledforeitherofthevideowindows,themaximum horizontalwindow dimensioncannotbe greaterthan720 currently.
• Itisnotpossibletouse bothoftheCLUT ROMs atthesame time.However,one window can use RAM whileanotheruses ROM.
• The 24-bitRGB inputmode isonlyvalidforone ofthetwo videowindows (programmable)and does notapplytotheOSD windows. The OSD registermemory mapping isshown inTable6-58. Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 169 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-58.OSD RegisterDescriptions Address Register Description 0x01C7 2600 MODE OSD Mode Register 0x01C7 2604 VIDWINMD VideoWindow Mode Setup 0x01C7 2608 OSDWIN0MD OSD Window Mode Setup 0x01C7 260C OSDWIN1MD OSD Window 1 Mode Setup(when used as a second OSD window) 0x01C7 260C OSDATRMD OSD AttributeWindow Mode Setup(when used as an attributewindow) 0x01C7 2610 RECTCUR RectangularCursorSetup 0x01C7 2614 RSV0 Reserved 0x01C7 2618 VIDWIN0OFST VideoWindow 0 Offset 0x01C7 261C VIDWIN1OFST VideoWindow 1 Offset 0x01C7 2620 OSDWIN0OFST OSD Window 0 Offset 0x01C7 2624 OSDWIN1OFST OSD Window 1 Offset 0x01C7 2628 RSV1 Reserved 0x01C7 262C VIDWIN0ADR VideoWindow 0 Address 0x01C7 2630 VIDWIN1ADR VideoWindow 1 Address 0x01C7 2634 RSV2 Reserved 0x01C7 2638 OSDWIN0ADR OSD Window 0 Address 0x01C7 263C OSDWIN1ADR OSD Window 1 Address 0x01C7 2640 BASEPX Base PixelX 0x01C7 2644 BASEPY Base PixelY 0x01C7 2648 VIDWIN0XP VideoWindow 0 X-Position 0x01C7 264C VIDWIN0YP VideoWindow 0 Y-Position 0x01C7 2650 VIDWIN0XL VideoWindow 0 X-Size 0x01C7 2654 VIDWIN0YL VideoWindow 0 Y-Size 0x01C7 2658 VIDWIN1XP VideoWindow 1 X-Position 0x01C7 265C VIDWIN1YP VideoWindow 1 Y-Position 0x01C7 2660 VIDWIN1XL VideoWindow 1 X-Size 0x01C7 2664 VIDWIN1YL VideoWindow 1 Y-Size 0x01C7 2668 OSDWIN0XP OSD BitmapWindow 0 X-Position 0x01C7 266C OSDWIN0YP OSD BitmapWindow 0 Y-Position 0x01C7 2670 OSDWIN0XL OSD BitmapWindow 0 X-Size 0x01C7 2674 OSDWIN0YL OSD BitmapWindow 0 Y-Size 0x01C7 2678 OSDWIN1XP OSD BitmapWindow 1 X-Position 0x01C7 267C OSDWIN1YP OSD BitmapWindow 1 Y-Position 0x01C7 2680 OSDWIN1XL OSD BitmapWindow 1 X-Size 0x01C7 2684 OSDWIN1YL OSD BitmapWindow 1 Y-Size 0x01C7 2688 CURXP RectangularCursorWindow X-Position 0x01C7 268C CURYP RectangularCursorWindow Y-Position 0x01C7 2690 CURXL RectangularCursorWindow X-Size 0x01C7 2694 CURYL RectangularCursorWindow Y-Size 0x01C7 2698 RSV3 Reserved 0x01C7 269C RSV4 Reserved 0x01C7 26A0 W0BMP01 Window 0 BitmapValuetoPaletteMap 0/1 0x01C7 26A4 W0BMP23 Window 0 BitmapValuetoPaletteMap 2/3 0x01C7 26A8 W0BMP45 Window 0 BitmapValuetoPaletteMap 4/5 0x01C7 26AC W0BMP67 Window 0 BitmapValuetoPaletteMap 6/7 0x01C7 26B0 W0BMP89 Window 0 BitmapValuetoPaletteMap 8/9 0x01C7 26B4 W0BMPAB Window 0 BitmapValuetoPaletteMap A/B

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-58.OSD RegisterDescriptions(continued) 0x01C7 26B8 W0BMPCD Window 0 BitmapValuetoPaletteMap C/D 0x01C7 26BC W0BMPEF Window 0 BitmapValuetoPaletteMap E/F 0x01C7 26C0 W1BMP01 Window 1 BitmapValuetoPaletteMap 0/1 0x01C7 26C4 W1BMP23 Window 1 BitmapValuetoPaletteMap 2/3 0x01C7 26C8 W1BMP45 Window 1 BitmapValuetoPaletteMap 4/5 0x01C7 26CC W1BMP67 Window 1 BitmapValuetoPaletteMap 6/7 0x01C7 26D0 W1BMP89 Window 1 BitmapValuetoPaletteMap 8/9 0x01C7 26D4 W1BMPAB Window 1 BitmapValuetoPaletteMap A/B 0x01C7 26D8 W1BMPCD Window 1 BitmapValuetoPaletteMap C/D 0x01C7 26DC W1BMPEF Window 1 BitmapValuetoPaletteMap E/F 0x01C7 26E0 - Reserved 0x01C7 26E4 RSV5 Reserved 0x01C7 26E8 MISCCTL MiscellaneousControl 0x01C7 26EC CLUTRAMYCB CLUT RAMYCB Setup 0x01C7 26F0 CLUTRAMCR CLUT RAM Setup 0x01C7 26F4 TRANSPVAL CLUT RAM Setup 0x01C7 26F8 RSV6 Reserved 0x01C7 26FC PPVWIN0ADR Ping-PongVideoWindow 0 Address 6.13.2.2Video Encoder (VENC) Analog/DACs interfaceoftheVideoEncoder(VENC) supportsthefollowingfeatures.

• MasterClockInput-27MHz (x2Upsampling)
• SDTV Support – CompositeNTSC-M, PAL-B/D/G/H/I – S-Video(Y/C) – Component YPbPr (SMPTE/EBU N10, Betacam,MII) – RGB – Non-Interlace – CGMS/WSS – Line21 ClosedCaptionData Encoding – Chroma Low Pass Filter1.5MHz/3MHz – Programmable SC-H phase
• HDTV Support – ProgressiveOutput(525p/625p) – Component YPbPr – RGB – CGMS/WSS
• 4 10-bitOver-SamplingD/A Converters
• Optional7.5% Pedestal
• 16-235/0-255InputAmplitudeSelectable
• Programmable Luma Delay
• Master/SlaveOperation
• InternalColorBar Generation(100%/75%) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 171 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com The DigitalLCD Controller(DLCD) oftheVENC supportsthefollowingfeatures.

• Programmable DCLK
• VariousOutputFormats – YCbCr 16bit – YCbCr 8bit – ITU-R BT. 656 – ParallelRGB 24bit
• Low Pass FilterforDigitalRGB Output
• Programmable TimingGenerator
• Master/SlaveOperation
• InternalColorBar Generation(100%/75%) The VENC registermemory mapping includingtheDigitalLCD and DACs isshown inTable6-59. Table6-59.VENC (IncludingDigitalLCD and DACs) RegisterDescriptions ADDRESS REGISTER DESCRIPTION 0x01C7 2400 VMOD VideoMode 0x01C7 2404 VIDCTL VideoInterfaceI/OControl 0x01C7 2408 VDPRO VideoData Processing 0x01C7 240C SYNCCTL Sync Control 0x01C7 2410 HSPLS HorizontalSync PulseWidth 0x01C7 2414 VSPLS VerticalSync PulseWidth 0x01C7 2418 HINT HorizontalInterval 0x01C7 241C HSTART HorizontalValidData StartPosition 0x01C7 2420 HVALID HorizontalData ValidRange 0x01C7 2424 VINT VerticalInterval 0x01C7 2428 VSTART VerticalValidData StartPosition 0x01C7 242C VVALID VerticalData ValidRange 0x01C7 2430 HSDLY HorizontalSync Delay 0x01C7 2434 VSDLY VerticalSync Delay 0x01C7 2438 YCCTL YCbCr Control 0x01C7 243C RGBCTL RGB Control 0x01C7 2440 RGBCLP RGB LevelClipping 0x01C7 2444 LINECTL LineID Control 0x01C7 2448 CULLLINE CullingLineControl 0x01C7 244C LCDOUT LCD OutputSignalControl 0x01C7 2450 BRTS BrightnessStartPositionSignalControl 0x01C7 2454 BRTW BrightnessWidthSignalControl 0x01C7 2458 ACCTL LCD_AC SignalControl 0x01C7 245C PWMP PWM StartPositionSignalControl 0x01C7 2460 PWMW PWM WidthSignalControl 0x01C7 2464 DCLKCTL DCLK Control 0x01C7 2468 DCLKPTN0 DCLK Pattern0 0x01C7 246C DCLKPTN1 DCLK Pattern1 0x01C7 2470 DCLKPTN2 DCLK Pattern2 0x01C7 2474 DCLKPTN3 DCLK Pattern3 0x01C7 2478 DCLKPTN0A DCLK AuxiliaryPattern0 0x01C7 247C DCLKPTN1A DCLK AuxiliaryPattern1 0x01C7 2480 DCLKPTN2A DCLK AuxiliaryPattern2

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-59.VENC (IncludingDigitalLCD and DACs) RegisterDescriptions(continued) ADDRESS REGISTER DESCRIPTION 0x01C7 2484 DCLKPTN3A DCLK AuxiliaryPattern3 0x01C7 2488 DCLKHS HorizontalDCLK Mask Start 0x01C7 248C DCLKHSA HorizontalAuxiliaryDCLK Mask Start 0x01C7 2490 DCLKHR HorizontalDCLK Mask Range 0x01C7 2494 DCLKVS VerticalDCLK Mask Start 0x01C7 2498 DCLKVR VerticalDCLK Mask Range 0x01C7 249C CAPCTL CaptionControl 0x01C7 24A0 CAPDO CaptionData Odd Field 0x01C7 24A4 CAPDE CaptionData Even Field 0x01C7 24A8 ATR0 VideoAttributeData # 0 0x01C7 24AC ATR1 VideoAttributeData # 1 0x01C7 24B0 ATR2 VideoAttributeData # 2 0x01C7 24B4 0x01C7 24B4 Reserved 0x01C7 24B4 0x01C7 24B4 0x01C7 24B8 VSTAT VideoStatus 0x01C7 24BC Reserved 0x01C7 24C0 0x01C7 24C4 DACTST DAC Test 0x01C7 24C8 YCOLVL YOUT and COUT Levels 0x01C7 24CC SCPROG Sub-CarrierProgramming 0x01C7 24D0 0x01C7 24D4 Reserved 0x01C7 24D8 0x01C7 24DC CVBS CompositeMode 0x01C7 24E0 CMPNT Component Mode 0x01C7 24E4 ETMG0 CVBS TimingControl0 0x01C7 24E8 ETMG1 CVBS TimingControl1 0x01C7 24EC ETMG2 Component TimingControl0 0x01C7 24F0 ETMG3 Component TimingControl1 0x01C7 24F4 DACSEL DAC OutputSelect 0x01C7 24F8 Reserved 0x01C7 24FC 0x01C7 2500 ARGBX0 AnalogRGB Matrix0 0x01C7 2504 ARGBX1 AnalogRGB Matrix1 0x01C7 2508 ARGBX2 AnalogRGB Matrix2 0x01C7 250C ARGBX3 AnalogRGB Matrix3 0x01C7 2510 ARGBX4 AnalogRGB Matrix4 0x01C7 2514 DRGBX0 DigitalRGB Matrix0 0x01C7 2518 DRGBX1 DigitalRGB Matrix1 0x01C7 251C DRGBX2 DigitalRGB Matrix2 0x01C7 2520 DRGBX3 DigitalRGB Matrix3 0x01C7 2524 DRGBX4 DigitalRGB Matrix4 0x01C7 2528 VSTARTA VerticalData ValidStartPositionforEven Field 0x01C7 252C OSDCLK0 OSD ClockControl0 0x01C7 2530 OSDCLK1 OSD ClockControl1 Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 173 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-59.VENC (IncludingDigitalLCD and DACs) RegisterDescriptions(continued) ADDRESS REGISTER DESCRIPTION 0x01C7 2534 HVLDCL0 HorizontalValidCullingControl0 0x01C7 2538 HVLDCL1 HorizontalValidCullingControl1 0x01C7 253C OSDHADV OSD HorizontalSync Advance 6.13.2.3VPBE ElectricalData/Timing Table6-60.Timing Requirements forVPBE CLK Inputs(seeFigure6-50) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(PCLK) Cycletime,PCLK 13.33 160 ns 2 tw(PCLKH) Pulseduration,PCLK high 5.7 ns 3 tw(PCLKL) Pulseduration,PCLK low 5.7 ns 4 tt(PCLK) Transitiontime,PCLK 3 ns 5 tc(VPBECLK) Cycletime,VPBECLK 13.33 160 ns 6 tw(VPBECLKH) Pulseduration,VPBECLK high 5.7 ns 7 tw(VPBECLKL) Pulseduration,VPBECLK low 5.7 ns 8 tt(VPBECLK) Transitiontime,VPBECLK 3 ns Figure6-50.VPBE PCLK and VPBECLK Timing

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(Positive Edge Clocking) PCLK (Negative Edge Clocking) VCTL (A) A. VCTL = HSYNC and VSYNC VPBECLK LCD_FIELD TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-61.Timing Requirements forVPBE ControlInputWith Respect toPCLK and VPBECLK (1)(see Figure6-51) A-513, -594, NO. UNIT-810 MIN MAX 9 tsu(VCTLV-PCLK) Setuptime,VCTL validbeforePCLK edge 2 ns 10 th(PCLK-VCTLV) Holdtime,VCTL validafterPCLK edge 0.5 ns 27 tsu(VCTLV-VPBECLK) Setuptime,VCTL validbeforeVPBECLK risingedge 2 ns 28 th(VPBECLK-VCTLV) Holdtime,VCTL validafterVPBECLK risingedge 0.5 ns 33 tsu(FIELD-PCLK) Setuptime,LCD_FIELD validbeforePCLK edge 5P (2) ns 34 th(PCLK-FIELD) Holdtime,LCD_FIELD validafterPCLK edge 5P (2) ns 35 tsu(FIELD-VPBECLK) Setuptime,LCD_FIELD validbeforeVPBECLK edge 5P (2) ns 36 th(VPBECLK-FIELD) Holdtime,LCD_FIELD validafterVPBECLK edge 5P (2) ns (1) PCLK may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode, therising edge ofPCLK isreferenced.When innegativeedge clockingmode, thefallingedge ofPCLK isreferenced. (2) P = 1/(VCLKINclockfrequency)inns.VCLKIN iseitherPCLK orVPBECLK, whicheverisused. Figure6-51.VPBE InputTiming With Respect toPCLK and VPBECLK Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 175 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

(Positive Edge Clocking) 13, 31 PCLK (Negative Edge Clocking) 11, 29 VCTL (A) A. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE B. VDAT A = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] VDATA (B) 14, 32 12, 30 VPBECLK TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-62.SwitchingCharacteristicsOver Recommended OperatingConditionsforVPBE Controland Data Output With Respect toPCLK and VPBECLK (1)(seeFigure6-52) -594A-513 -810NO. PARAMETER UNIT MIN MAX MIN MAX 11 td(PCLK-VCTLV) Delaytime,PCLK edge toVCTL valid 13.3 13.3 ns 12 td(PCLK-VCTLIV) Delaytime,PCLK edge toVCTL invalid 2 2 ns 13 td(PCLK-VDATAV) Delaytime,PCLK edge toVDATA valid 13.6 13.3 ns 14 td(PCLK-VDATAIV) Delaytime,PCLK edge toVDATA invalid 2 2 ns 29 td(VPBECLK-VCTLV) Delaytime,VPBECLK risingedge toVCTL valid 13.3 13.3 ns 30 td(VPBECLK-VCTLIV) Delaytime,VPBECLK risingedge toVCTL invalid 2 2 ns 31 td(VPBECLK-VDATAV) Delaytime,VPBECLK risingedge toVDATA valid 13.6 13.3 ns 32 td(VPBECLK-VDATAIV) Delaytime,VPBECLK risingedge toVDATA invalid 2 2 ns (1) PCLK may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode, therising edge ofPCLK isreferenced.When innegativeedge clockingmode, thefallingedge ofPCLK isreferenced. Figure6-52.VPBE Output Timing With Respect toPCLK and VPBECLK

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(Positive Edge Clocking) VCLK (Negative Edge Clocking) VCTL (B) VDATA (C) 1922 23 24 25 26 VCLKIN (A) A. VCLKIN = PCLK or VPBECLK B. VCTL = HSYNC, VSYNC, LCD_FIELD, and LCD_OE C. VDAT A = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] 2020 TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-63.SwitchingCharacteristicsOver Recommended OperatingConditionsforVPBE Controland Data Output With Respect toVCLK (1)(2)(seeFigure6-53) A-513, -594, NO. PARAMETER MODE (3) UNIT-810 MIN MAX 17 tc(VCLK) Cycletime,VCLK 13.33 160 ns Pulseduration,VCLK high(positive-edgeclocking) H -1.3(4) H -0.3(4) ns 18 tw(VCLKH) Pulseduration,VCLK high(negative-edgeclocking) L -1.3(4) L -0.3(4) ns Pulseduration,VCLK low(positive-edgeclocking) L + 0.3(4) L + 1.3(4) ns 19 tw(VCLKL) Pulseduration,VCLK low(negative-edgeclocking) H + 0.3(4) H + 1.3(4) ns 20 tt(VCLK) Transitiontime,VCLK 3 ns 21 td(VCLKINH-VCLKH) Delaytime,VCLKIN hightoVCLK high 2 12 ns 22 td(VCLKINL-VCLKL) Delaytime,VCLKIN lowtoVCLK low 2 12 ns Delaytime,VCLK negativeedge toVCTL valid 7.5 ns 23 td(VCLK-VCTLV) Delaytime,VCLK positiveedge toVCTL valid 6.9 ns Delaytime,VCLK negativeedge toVCTL invalid 2 ns 24 td(VCLKL-VCTLIV) Delaytime,VCLK positiveedge toVCTL invalid 1.5 ns Delaytime,VCLK negativeedge toVDATA valid 6.8 ns 25 td(VCLK-VDATAV) Delaytime,VCLK positiveedge toVDATA valid 6.3 ns RGB 2.1 ns Delaytime,VCLK negativeedge toVDATA invalid YCC 2.5 ns 26 td(VCLKL-VDATAIV) RGB 1.9 ns Delaytime,VCLK positiveedge toVDATA invalid YCC 2.1 ns (1) The VPBE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode, the risingedge ofVCLK isreferenced.When innegativeedge clockingmode, thefallingedge ofVCLK isreferenced. (2) VCLKIN = PCLK orVPBECLK (3) RGB and YCC modes utilizedifferentdatapins.RGB mode uses datapins:R[7:0],G[7:0],and B[7:0].YCC mode uses datapins: COUT[7:0]and YOUT[7:0]. (4) H and L arethehighand lowpulsewidthsoftheinputclocktotheVPBE, respectively.Forexample,ifVPBECLK isused as theinput clockand ithas a highpulsedurationof6.67ns,theresultinghighpulsedurationofVCLK, ifpositive-edgeclockingisselected,willbe a MAX of6.37ns and a MIN of5.27ns. Figure6-53.VPBE Controland Data Output Timing With Respect toVCLK Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 177 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

Low-Pass□Filter =□6.5□MHz ~R =□500 fc LOAD Ω DAC 75 Ω 75 Ω IOUT Amplifier Gain□=□5.6□V/V TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.13.2.4DAC ElectricalData/Timing Table6-64.SwitchingCharacteristicsOver Recommended OperatingConditionsforDAC Static Specifications A-513, -594, NO. PARAMETER TEST CONDITIONS UNIT-810 MIN TYP MAX DC Accuracy -1.0 1.0 LSBIntegralNon-Linearity(INL) -0.5 0.5 LSBDifferentialNon-Linearity(DNL) Analog Output 0.5 LSBOffsetError 5 %F SGain Error 500 mV PPFull-ScaleOutputVoltage R LOAD = 500 Ω OutputCapacitance 200 pF Table6-65.SwitchingCharacteristicsOver Recommended OperatingConditionsforDAC Dynamic Specifications A-513, -594, NO. PARAMETER TEST CONDITIONS UNIT-810 MIN TYP MAX OutputUpdate Rate (FCLK ) 27 60 MHz SignalBandwidth 6 MHz FCLK = 27 MHz 60 dB FOUT = 2.0MHz SFDR toNyquist FCLK = 60 MHz 60 dB FOUT = 2.0MHz FCLK = 27 MHz 60 dB FOUT = 2.0MHz SFDR withinBandwidth FCLK = 60 MHz 60 dB FOUT = 2.0MHz PSRR Over Temp vs Power Supply 50 dB The DM6446's analogvideoDAC outputsare designedto drivea 500-Ω load.Figure6-54 describesa typicalcircuitthatwillpermitconnectingthe analogvideooutputfrom the DM6446 deviceto standard 75-Ω impedance videosystems.Anothersolutionisto use a Video Amplifierwithan integratedfilterto providea completesolutiontothetypicaloutputcircuitshown inFigure6-54. Figure6-54.TypicalOutput CircuitforNTSC/PAL Video From DACs

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6.14 Host-PortInterface(HPI)

The Host PortInterface(HPI)providesa parallelportthroughwhich an externalhost processorcan accesstheDM6446 memory space.The hostdeviceisasynchronoustotheDM6446 clocksand functions as a mastertotheHPI interface.The HPI enablesa hostdeviceand DM6446 toexchange informationvia internalor externalmemory. Both thehostand DM6446 can access theHPI controlregister(HPIC)and theHPI addressregisters(HPIAR, HPIAW). The hostcan access theHPI dataregister(HPID)and the HPIC by usingtheexternaldataand interfacecontrolsignals. The HPI interfaceshares the DaVinciEMIFA 16-bitdata bus pins formultiplexedaddress/dataand supportsthefollowingmodes:

• 16 BitMultiplexedmode /dualhalf-wordcycles(16bithostdatabus/32bitmemory width)
• ARM ROM supportsbootingofDM6446 ARM processorfroman externalprocessor The HPI registersaresummarized inTable6-66.For more detailedinformationon theHPI peripheral,see theTMS320DM644x DMSoC HostPortInterface(HPI)User'sGuide (literaturenumber SPRUE97 ). Table6-66.Host-PortInterface(HPI)RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C4 0030 HPI_CTL Host-PortInterfaceConfigurationRegister 0x01C6 7800 HPI_PID 0x01C6 7804 HPIPWREMU HPI Power and EmulationManagement Register 0x01C6 7808 -0x01C6 782F – Reserved 0x01C6 7830 HPIC Host-PortInterfaceControlRegister 0x01C6 7834 HPIAW Host-PortInterfaceWriteAddressRegister 0x01C6 7838 HPIAR Host-PortInterfaceRead AddressRegister 0x01C6 783C -0x01C6 7FFF – Reserved The HPI_CTL registersetstheowner ofHPIA(R/W) and HPIC registersforHPI addressand control.The detailsforHPI_CTL areshown inFigure6-55and Table6-67. Figure6-55.HPI_CTL Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved R-0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTL ADDReserved TIMOUTMODE MODE R-0 R/W-0 R/W-0 R/W-10000000 LEGEND: R = Read, W = Write,n = valueatreset Table6-67.HPI_CTL RegisterDescription Name Description CTLMODE HPIC registerwriteaccess 0 = ExternalHost 1 = DM6446 (ifADDMODE = 1) ADDMODE HPIA registerwriteaccess 0 = ExternalHost 1 = DM6446 TIMOUT Hostburstwritetimeoutvalue Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 179 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.14.1 Host-PortInterface(HPI)ElectricalData/Timing

Table6-68.Timing Requirements forHost-PortInterfaceCycles(1)(2)(seeFigure6-56through Figure6-57) A-513, -594, NO. UNIT-810 MIN MAX 1 tsu(SELV-HSTBL) Setuptime,selectsignals(3)validbeforeHSTROBE low 5 ns 2 th(HSTBL-SELV) Holdtime,selectsignals(3)validafterHSTROBE low 2 ns 3 tw(HSTBL) Pulseduration,HSTROBE low 15 ns 4 tw(HSTBH) Pulseduration,HSTROBE highbetween consecutiveaccesses 2P ns 12 tsu(HDV-HSTBH) Setuptime,hostdatavalidbeforeHSTROBE high 5 ns 13 th(HSTBH-HDV) Holdtime,hostdatavalidafterHSTROBE high 0 ns Holdtime,HSTROBE highafterHRDY low.HSTROBE shouldnotbe 14 th(HRDYL-HSTBH) inactivateduntilHRDY isactive(low);otherwise,HPI writeswillnotcomplete 2 ns properly. (1) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (2) P = 1/CPU clockfrequencyinns.Forexample,when runningpartsat594 MHz, use P = 1.68ns;when runningpartsat810 MHz, use P = 1.23ns. (3) Selectsignalsinclude:HCNTL[1:0]and HR/W. ForHPI16 mode only,selectsignalsalsoincludeHHWIL. Table6-69.SwitchingCharacteristicsOver Recommended OperatingConditionsDuring Host-Port InterfaceCycles(1)(seeFigure6-56through Figure6-57) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 6 td(HSTBL-HRDYH) Delaytime,HSTROBE lowtoHRDY high(2) 0 12 ns 7 td(HSTBL-HDLZ) Delaytime,HSTROBE lowtoHD lowimpedance foran HPI read 0 ns 8 td(HDV-HRDYL) Delaytime,HD validtoHRDY low 0 ns 9 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 1.5 ns 15 td(HSTBH-HDHZ) Delaytime,HSTROBE hightoHD highimpedance 7 ns Delaytime,HSTROBE lowtoHD valid16 td(HSTBL-HDV) 15 ns(HPI16mode, 2nd half-wordonly) 20 td(HCSL-HRDYH) Delaytime,HCS lowtoHRDY high 0 12 ns (1) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (2) Thisparameterisused duringHPID readsand writes.Forreads,atthebeginningofthefirsthalf-wordtransfer(HPI16)on thefalling edge ofHSTROBE, theHPI sends therequesttotheEDMA3 internaladdressgenerationhardware,and HRDY remainshighuntilthe EDMA3 internaladdressgenerationhardwareloadstherequesteddataintoHPID. Forwrites,HRDY goes highiftheinternalwritebuffer isfull.

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1st half-word 2nd half-word86 916 2121 2121 HCNTL[1:0] HR/W HHWIL HSTROBE (A) HCS HD[15:0] (output) HRDY 1st half-word 2nd half-word HCNTL[1:0] HR/W HHWIL HSTROBE (A) HCS HD[15:0] (input) HRDY 620 TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 A. HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure6-56.HPI16 Read Timing A. HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure6-57.HPI16 WriteTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 181 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.15 USB 2.0 The DM6446 USB2.0 peripheralsupportsthefollowingfeatures:

• USB 2.0peripheralatspeeds highspeed (HS:480 Mb/s)and fullspeed (FS:12 Mb/s)
• USB 2.0hostatspeeds HS, FS, and lowspeed (LS:1.5Mb/s)
• Alltransfermodes (control,bulk,interrupt,and isochronous)
• 4 Transmit(TX)and 4 Receive(RX)endpointsinadditiontoendpoint0
• FIFO RAM – 4K endpoint – Programmable size
• Connectstoa standardUTMI+ PHY witha 60 MHz, 8-bitinterface
• Connectstoa standardCharge Pump forVBUS 5 V generation
• RNDIS mode foracceleratingRNDIS typeprotocolsusingshortpacketterminationoverUSB

6.15.1 USBPHY_CTL RegisterDescription

The USB physicalinterfacecontrolregisterUSBPHY_CTL isdescribedinFigure6-58and Table6-70. Figure6-58.USBPHY_CTL Register 31 9 8 Reserved PHYCLKGD R-0000 0000 0000 0000 0000 000 R-0 7 6 5 4 3 2 1 0 SESNDEN VBDTCTEN Reserved PHYPLLON CLKO1SEL OSCPDWN Reserved PHYPDWN R/W-1 R/W-1 R-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 LEGEND: R = Read, W = Write,n = valueatreset Table6-70.USBPHY_CTL RegisterDescriptions Name Description PHYCLKGD USB PHY Power and ClockGood 0 = Phy power notramped orPLL notlocked 1 = Phy power isgood and PLL islocked SESNDEN SessionEnd Comparatorenable 0 = comparatordisabled 1 = comparatorenabled VBDTCTEN vbus comparatorenable 0 = comparators(exceptsessionend)disabled 1 = comparators(exceptsessionend)enabled PHYPLLON USB PHY PLL suspend override 0 = Normal PLL operation 1 = OverridePLL suspend state CLKO1SEL CLK_OUT1 frequencyselect 0 = 24 MHz 1 = 12 MHz OSCPDWN USB PHY oscillatorpower down control 0 = PHY oscillatorpowered 1 = PHY oscillatorpower off PHYPDWN USB PHY power down control 0 = PHY powered 1 = PHY power off

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.15.2 USB2.0 PeripheralRegisterDescription(s) The USB registermemory mapping isshown inTable6-71. Table6-71.USB 2.0RegisterDescriptions Address Acronym RegisterDescription 0x01C6 4000 REVR RevisionRegister 0x01C6 4004 CTRLR ControlRegister 0x01C6 4008 STATR StatusRegister 0x01C6 4010 RNDISR RNDIS Register 0x01C6 4014 AUTOREQ AutoRequestRegister 0x01C6 4020 INTSRCR USB InterruptSourceRegister 0x01C6 4024 INTSETR USB InterruptSourceSetRegister 0x01C6 4028 INTCLRR USB InterruptSourceClearRegister 0x01C6 402C INTMSKR USB InterruptMask Register 0x01C6 4030 INTMSKSETR USB InterruptMask SetRegister 0x01C6 4034 INTMSKCLRR USB InterruptMask ClearRegister 0x01C6 4038 INTMASKEDR USB InterruptSourceMasked Register 0x01C6 403C EOIR USB End ofInterruptRegister 0x01C6 4040 INTVECTR USB InterruptVectorRegister 0x01C6 4080 TCPPICR TX CPPI ControlRegister 0x01C6 4084 TCPPITDR TX CPPI Teardown Register 0x01C6 4088 TCPPIEOIR TX CPPI DMA ControllerEnd ofInterruptRegister 0x01C6 408C TCPPIIVECTR TX CPPI DMA ControllerInterruptVectorRegister 0x01C6 4090 TCPPIMSKSR TX CPPI Masked StatusRegister 0x01C6 4094 TCPPIRAWSR TX CPPI Raw StatusRegister 0x01C6 4098 TCPPIIENSETR TX CPPI InterruptEnableSetRegister 0x01C6 409C TCPPIIENCLRR TX CPPI InterruptEnableClearRegister 0x01C6 40C0 RCPPICR RX CPPI ControlRegister 0x01C6 40D0 RCPPIMSKSR RX CPPI Masked StatusRegister 0x01C6 40D4 RCPPIRAWSR RX CPPI Raw StatusRegister 0x01C6 40D8 RCPPIENSETR RX CPPI InterruptEnableSetRegister 0x01C6 40DC RCPPIIENCLRR RX CPPI InterruptEnableClearRegister 0x01C6 40E0 RBUFCNT0 RX BufferCount 0 Register 0x01C6 40E4 RBUFCNT1 RX BufferCount 1 Register 0x01C6 40E8 RBUFCNT2 RX BufferCount 2 Register 0x01C6 40EC RBUFCNT3 RX BufferCount 3 Register TX/RX CCPI Channel 0 StateBlock 0x01C6 4100 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 4104 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 4108 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 410C TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 4110 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 4114 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 4118 TCPPIDMASTATEW6 TX CPPI DMA StateWord 6 0x01C6 411C TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 4120 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 4124 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 4128 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 412C RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 183 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-71.USB 2.0RegisterDescriptions(continued) Address Acronym RegisterDescription 0x01C6 4130 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 4134 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 4138 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 413C RCPPICOMPPTR RX CPPI CompletionPointer TX/RX CCPI Channel 1 StateBlock 0x01C6 4140 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 4144 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 4148 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 414C TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 4150 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 4154 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 4158 TCPPIDMASTATEW6 TX CPPI DMA StateWord 6 0x01C6 415C TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 4160 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 4164 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 4168 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 416C RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 4170 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 4174 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 4178 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 417C RCPPICOMPPTR RX CPPI CompletionPointer TX/RX CCPI Channel 2 StateBlock 0x01C6 4180 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 4184 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 4188 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 418C TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 4190 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 4194 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 4198 TCPPIDMASTATEW6 TX CPPI DMA StateWord 6 0x01C6 419C TCPPICOMPPTR TX CPPI CompletionPointer 0x01C6 41A0 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 41A4 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 41A8 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 41AC RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 41BA RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 41B4 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 41B8 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 41BC RCPPICOMPPTR RX CPPI CompletionPointer TX/RX CCPI Channel 3 StateBlock 0x01C6 41C0 TCPPIDMASTATEW0 TX CPPI DMA StateWord 0 0x01C6 41C4 TCPPIDMASTATEW1 TX CPPI DMA StateWord 1 0x01C6 41C8 TCPPIDMASTATEW2 TX CPPI DMA StateWord 2 0x01C6 41CC TCPPIDMASTATEW3 TX CPPI DMA StateWord 3 0x01C6 41D0 TCPPIDMASTATEW4 TX CPPI DMA StateWord 4 0x01C6 41D4 TCPPIDMASTATEW5 TX CPPI DMA StateWord 5 0x01C6 41D8 TCPPIDMASTATEW6 TX CPPI DMA StateWord 6 0x01C6 41DC TCPPICOMPPTR TX CPPI CompletionPointer

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-71.USB 2.0RegisterDescriptions(continued) Address Acronym RegisterDescription 0x01C6 41E0 RCPPIDMASTATEW0 RX CPPI DMA StateWord 0 0x01C6 41E4 RCPPIDMASTATEW1 RX CPPI DMA StateWord 1 0x01C6 41E8 RCPPIDMASTATEW2 RX CPPI DMA StateWord 2 0x01C6 41EC RCPPIDMASTATEW3 RX CPPI DMA StateWord 3 0x01C6 41F0 RCPPIDMASTATEW4 RX CPPI DMA StateWord 4 0x01C6 41F4 RCPPIDMASTATEW5 RX CPPI DMA StateWord 5 0x01C6 41F8 RCPPIDMASTATEW6 RX CPPI DMA StateWord 6 0x01C6 41FC RCPPICOMPPTR RX CPPI CompletionPointer Core Registers 0x01C6 4400 FADDR FunctionAddressRegister 0x01C6 4401 POWER Power Management Register 0x01C6 4402 INTRTX InterruptRegisterforEndpoint0 plusTX Endpoints1 to4 0x01C6 4404 INTRRX InterruptRegisterforRX Endpoints1 to4 0x01C6 4406 INTRTXE InterruptEnableRegisterforINTRTX 0x01C6 4408 INTRRXE InterruptEnableRegisterforINTRRX 0x01C6 440A INTRUSB InterruptRegisterforCommon USB Interrupts 0x01C6 440B INTRUSBE InterruptEnableRegisterforINTRUSB 0x01C6 440C FRAME Frame Number Register 0x01C6 440E INDEX Indexregisterforselectingtheendpointstatusand controlregisters 0x01C6 440F TESTMODE RegistertoenabletheUSB 2.0testmodes 0x01C6 4410 TXMAXP Maximum packetsizeforperipheral/hostTX endpoint(Indexregistersettoselect Endpoints1 -4 only) PERI_CSR0 ControlStatusregisterforEndpoint0 inPeripheralmode. (Indexregistersetto selectEndpoint0) HOST_CSR0 ControlStatusregisterforEndpoint0 inHostmode. (Indexregistersettoselect Endpoint0) 0x01C6 4412 PERI_TXCSR ControlStatusregisterforperipheralTX endpoint.(Indexregistersettoselect Endpoints1 -4) HOST_TXCSR ControlStatusregisterforhostTX endpoint.(Indexregistersettoselect Endpoints1 -4) 0x01C6 4414 RXMAXP Maximum packetsizeforperipheral/hostRX endpoint(Indexregistersettoselect Endpoints1 -4 only) PERI_RXCSR ControlStatusregisterforperipheralRX endpoint.(Indexregistersettoselect Endpoints1 -4) 0x01C6 4416 HOST_RXCSR ControlStatusregisterforhostRX endpoint.(Indexregistersettoselect Endpoints1 -4) COUNT0 Number ofreceivedbytesinEndpoint0 FIFO.(Indexregistersettoselect Endpoint0) 0x01C6 4418 RXCOUNT Number ofbytesinhostRX endpointFIFO.(Indexregistersettoselect Endpoints1 -4) 0x01C6 441A HOST_TYPE0 Definesthespeed ofEndpoint0 0x01C6 441A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostTX endpoint.(IndexregistersettoselectEndpoints1 -4 only) 0x01C6 441B HOST_NAKLIMIT0 SetstheNAK responsetimeouton Endpoint0.(Indexregistersettoselect Endpoint0) 0x01C6 441B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTX endpoint.(Indexregistersettoselect Endpoints1 -4 only) 0x01C6 441C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostRX endpoint.(IndexregistersettoselectEndpoints1 -4 only) 0x01C6 441D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostRX endpoint.(Indexregistersettoselect Endpoints1 -4 only) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 185 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-71.USB 2.0RegisterDescriptions(continued) Address Acronym RegisterDescription 0x01C6 441F CONFIGDATA Returnsdetailsofcoreconfiguration(IndexregistersettoselectEndpoint0) 0x01C6 4420 FIFO0 TX and RX FIFO RegisterforEndpoint0 0x01C6 4424 FIFO1 TX and RX FIFO RegisterforEndpoint1 0x01C6 4428 FIFO2 TX and RX FIFO RegisterforEndpoint2 0x01C6 442C FIFO3 TX and RX FIFO RegisterforEndpoint3 0x01C6 4430 FIFO4 TX and RX FIFO RegisterforEndpoint4 0x01C6 4462 TXFIFOSZ TX EndpointFIFO Size(IndexregistersettoselectEndpoints0 -4 only) 0x01C6 4463 RXFIFOSZ RX EndpointFIFO Size(IndexregistersettoselectEndpoints0 -4 only) 0x01C6 4464 TXFIFOADDR TX EndpointFIFO Address(IndexregistersettoselectEndpoints0 -4 only) 0x01C6 4466 RXFIFOADDR RX EndpointFIFO Address(IndexregistersettoselectEndpoints0 -4 only) TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG0 0x01C6 4480 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX Endpoint 0x01C6 4482 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 4483 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This isused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high speed hub 0x01C6 4484 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX Endpoint 0x01C6 4486 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 4487 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG1 0x01C6 4488 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX Endpoint 0x01C6 448A TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 448B TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This isused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high speed hub 0x01C6 448C RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX Endpoint 0x01C6 448E RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 448F RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG2 0x01C6 4490 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX Endpoint 0x01C6 4492 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 4493 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This isused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high speed hub 0x01C6 4494 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX Endpoint

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-71.USB 2.0RegisterDescriptions(continued) Address Acronym RegisterDescription 0x01C6 4496 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 4497 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG3 0x01C6 4498 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX Endpoint 0x01C6 449A TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 449B TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This isused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high speed hub 0x01C6 449C RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX Endpoint 0x01C6 449E RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 449F RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub TargetEndpoint ControlRegisters(ValidOnly inHost Mode) -EPTRG4 0x01C6 44A0 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedTX Endpoint 0x01C6 44A2 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 44A3 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTX Endpoint.This isused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high speed hub 0x01C6 44A4 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociatedRX Endpoint 0x01C6 44A6 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub 0x01C6 44A7 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedRX Endpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 highspeed hub Controland StatusRegisterforEndpoint 0 -EOCSR0 0x01C6 4502 PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralmode HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostmode 0x01C6 4508 COUNT0 Number ofReceivedBytesinEndpoint0 FIFO 0x01C6 450A HOST_TYPE0 DefinestheSpeed ofEndpoint0 0x01C6 450B HOST_NAKLIMIT0 SetstheNAK responsetimeouton Endpoint0. 0x01C6 450F CONFIGDATA Returnsdetailsofcoreconfiguration Controland StatusRegisterforEndpoint 1 -EOCSR1 0x01C6 4510 TXMAXP Maximum PacketsizeforPeripheral/HostTX Endpoint 0x01C6 4512 PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4514 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint 0x01C6 4516 PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4518 RXCOUNT Number ofBytesinHostRX EndpointFIFO Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 187 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-71.USB 2.0RegisterDescriptions(continued) Address Acronym RegisterDescription 0x01C6 451A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostTX endpoint. 0x01C6 451B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTX endpoint. 0x01C6 451C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostRX endpoint. 0x01C6 451D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostRX endpoint. Controland StatusRegisterforEndpoint 2 -EOCSR2 0x01C6 4520 TXMAXP Maximum PacketSizeforPeripheral/HostTX Endpoint 0x01C6 4522 PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4524 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint 0x01C6 4526 PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4528 RXCOUNT Number ofBytesinHostRX EndpointFIFO 0x01C6 452A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostTX endpoint. 0x01C6 452B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTX endpoint. 0x01C6 452C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostRX endpoint. 0x01C6 452D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostRX endpoint. Controland StatusRegisterforEndpoint 3 -EOCSR3 0x01C6 4530 TXMAXP Maximum PacketSizeforPeripheral/HostTX Endpoint 0x01C6 4532 PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4534 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint 0x01C6 4536 PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4538 RXCOUNT Number ofBytesinHostRX EndpointFIFO 0x01C6 453A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostTX endpoint. 0x01C6 453B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTX endpoint. 0x01C6 453C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostRX endpoint. 0x01C6 453D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostRX endpoint. Controland StatusRegisterforEndpoint 4 -EOCSR4 0x01C6 4540 TXMAXP Maximum PacketSizeforPeripheral/HostTX Endpoint 0x01C6 4542 PERI_TXCSR ControlStatusRegisterforPeripheralTX Endpoint HOST_TXCSR ControlStatusRegisterforHostTX Endpoint 0x01C6 4544 RXMAXP Maximum PacketSizeforPeripheral/HostRX Endpoint 0x01C6 4546 PERI_RXCSR ControlStatusRegisterforPeripheralRX Endpoint HOST_RXCSR ControlStatusRegisterforHostRX Endpoint 0x01C6 4548 RXCOUNT Number ofBytesinHostRX EndpointFIFO 0x01C6 454A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostTX endpoint. 0x01C6 454B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTX endpoint.

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90% VOH 10% VOL USB_DM USB_DP tper − tjr TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-71.USB 2.0RegisterDescriptions(continued) Address Acronym RegisterDescription 0x01C6 454C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber forthehostRX endpoint. 0x01C6 454D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostRX endpoint. 6.15.3 USB2.0 ElectricalData/Timing Table6-72.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB2.0 (see Figure6-59) A-513, -594, -810 NO. PARAMETER UNITLOW SPEED FULL SPEED HIGH SPEED 1.5Mbps 12 Mbps 480 Mbps MIN MAX MIN MAX MIN MAX 1 tr(D) Risetime,USB_DP and USB_DM signals(1) 75 300 4 20 0.5 ns 2 tf(D) Falltime,USB_DP and USB_DM signals(1) 75 300 4 20 0.5 ns 3 trfM Rise/Falltime,matching(2) 80 125 90 111.11 – – % 4 VCRS Outputsignalcross-overvoltage(1) 1.3 2 1.3 2 – – V 5 tjr(source)NT Source(Host)Driverjitter,nexttransition 2 2 (3) ns tjr(FUNC)NT FunctionDriverjitter,nexttransition 25 2 (3) ns 6 tjr(source)PT Source(Host)Driverjitter,pairedtransition(4) 1 1 (3) ns tjr(FUNC)PT FunctionDriverjitter,pairedtransition 10 1 (3) ns 7 tw(EOPT) Pulseduration,EOP transmitter 1250 1500 160 175 – – ns 8 tw(EOPR) Pulseduration,EOP receiver(5) 670 82 – ns 9 t(DRATE) Data Rate 1.5 12 480 Mb/s 10 ZDRV DriverOutputResistance – – 28 49.5 40.5 49.5 Ω (1) Low Speed:C L = 200 pF,FullSpeed:C L = 50 pF,HighSpeed:C L = 50 pF (2) tRFM = (tr/tf)x 100.[ExcludingthefirsttransactionfromtheIdlestate.] (3) Formore detailedinformation,see theUniversalSerialBus SpecificationRevision2.0,Chapter7,Electrical. (4) tjr= tpx(1)-tpx(0) (5) Must acceptas validEOP Figure6-59.USB2.0 IntegratedTransceiverInterfaceTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 189 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

USB_VSSREF USB_R1 USB 10□K ±1%Ω (A) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-60.USB ReferenceResistorRouting

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6.16 UniversalAsynchronous Receiver/Transmitter(UART)

DM6446 has 3 UART peripherals.Each UART has thefollowingfeatures:

• 16-bytestoragespace forboththetransmitterand receiverFIFOs
• 1,4,8,or14 byteselectablereceiverFIFO triggerlevelforautoflowcontroland DMA
• DMA signalingcapabilityforbothreceivedand transmitteddata
• Programmable auto-rtsand auto-ctsforautoflowcontrol
• Frequencypre-scalevaluesfrom1 to65,535togenerateappropriatebaud rates
• Prioritizedinterrupts
• Programmable serialdataformats – 5,6,7,or8-bitcharacters – Even,odd,orno paritybitgenerationand detection – 1,1.5,or2 stopbitgeneration
• Falsestartbitdetection
• Linebreakgenerationand detection
• Internaldiagnosticcapabilities – Loopback controlsforcommunicationslinkfaultisolation – Break,parity,overrun,and framingerrorsimulation
• Modem controlfunctions(CTS,RTS) on UART2 only. The UART0/1/2 registersarelistedinTable6-73,Table6-74,and Table6-75.

6.16.1 UART PeripheralRegisterDescription(s)

Table6-73.UART0 RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 0000 RBR UART0 ReceiverBufferRegister(Read Only) 0x01C2 0000 THR UART0 TransmitterHoldingRegister(WriteOnly) 0x01C2 0004 IER UART0 InterruptEnableRegister 0x01C2 0008 IIR UART0 InterruptIdentificationRegister(Read Only) 0x01C2 0008 FCR UART0 FIFO ControlRegister(WriteOnly) 0x01C2 000C LCR UART0 LineControlRegister 0x01C2 0010 MCR UART0 Modem ControlRegister 0x01C2 0014 LSR UART0 LineStatusRegister 0x01C2 0018 - Reserved 0x01C2 001C - Reserved 0x01C2 0020 DLL UART0 DivisorLatch(LSB) 0x01C2 0024 DLH UART0 DivisorLatch(MSB) 0x01C2 0028 PID1 PeripheralIdentificationRegister1 0x01C2 002C PID2 PeripheralIdentificationRegister2 0x01C2 0030 PWREMU_MGMT UART0 Power and EmulationManagement Register 0x01C2 0034 -0x01C2 03FF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 191 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-74.UART1 RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 0400 RBR UART1 ReceiverBufferRegister(Read Only) 0x01C2 0400 THR UART1 TransmitterHoldingRegister(WriteOnly) 0x01C2 0404 IER UART1 InterruptEnableRegister 0x01C2 0408 IIR UART1 InterruptIdentificationRegister(Read Only) 0x01C2 0408 FCR UART1 FIFO ControlRegister(WriteOnly) 0x01C2 040C LCR UART1 LineControlRegister 0x01C2 0410 MCR UART1 Modem ControlRegister 0x01C2 0414 LSR UART1 LineStatusRegister 0x01C2 0418 - Reserved 0x01C2 041C - Reserved 0x01C2 0420 DLL UART1 DivisorLatch(LSB) 0x01C2 0424 DLH UART1 DivisorLatch(MSB) 0x01C2 0428 PID1 PeripheralIdentificationRegister1 0x01C2 042C PID2 PeripheralIdentificationRegister2 0x01C2 0430 PWREMU_MGMT UART1 Power and EmulationManagement Register 0x01C2 0434 -0x01C2 07FF - Reserved Table6-75.UART2 RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 0800 RBR UART2 ReceiverBufferRegister(Read Only) 0x01C2 0800 THR UART2 TransmitterHoldingRegister(WriteOnly) 0x01C2 0804 IER UART2 InterruptEnableRegister 0x01C2 0808 IIR UART2 InterruptIdentificationRegister(Read Only) 0x01C2 0808 FCR UART2 FIFO ControlRegister(WriteOnly) 0x01C2 080C LCR UART2 LineControlRegister 0x01C2 0810 MCR UART2 Modem ControlRegister 0x01C2 0814 LSR UART2 LineStatusRegister 0x01C2 0818 - Reserved 0x01C2 081C - Reserved 0x01C2 0820 DLL UART2 DivisorLatch(LSB) 0x01C2 0824 DLH UART2 DivisorLatch(MSB) 0x01C2 0828 PID1 PeripheralIdentificationRegister1 0x01C2 082C PID2 PeripheralIdentificationRegister2 0x01C2 0830 PWREMU_MGMT UART2 Power and EmulationManagement Register 0x01C2 0834 -0x01C2 0BFF - Reserved

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UART_TXDn UART_RXDn Data Bits Bit Start TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010

6.16.2 UART ElectricalData/Timing

Table6-76.Timing Requirements forUARTx Receive(1)(seeFigure6-61) A-513, -594, NO. UNIT-810 MIN MAX 4 tw(URXDB) Pulseduration,receivedatabit(RXDn) [15/30/100pF] 0.96U 1.05U ns 5 tw(URXSB) Pulseduration,receivestartbit[15/30/100pF] 0.96U 1.05U ns (1) U = UART baud time= 1/programmedbaud rate. Table6-77.SwitchingCharacteristicsOver Recommended OperatingConditionsforUARTx Transmit(1) (seeFigure6-61) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 1 f(baud) Maximum programmablebaud rate 128 kHz 2 tw(UTXDB) Pulseduration,transmitdatabit(TXDn) [15/30/100pF] U -2 U + 2 ns 3 tw(UTXSB) Pulseduration,transmitstartbit[15/30/100pF] U -2 U + 2 ns (1) U = UART baud time= 1/programmedbaud rate. Figure6-61.UART Transmit/ReceiveTiming Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 193 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.17 SerialPeripheralInterface(SPI)

The DM6446 SPI peripheralprovidesa programmable length shiftregisterwhich allows serial communicationwithotherSPI devicesthrougha 3 or 4 wireinterface.The SPI supportsthe following features:

• Mastermode operation
• 2 chipselectsforinterfacingtomultipleslaveSPI devices.
• 3 or4 wireinterface The SPI registersareshown inTable6-78.

6.17.1 SPI PeripheralRegisterDescription(s)

Table6-78.SPI RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C6 6800 SPIGCR0 SPI GlobalControlRegister0 0x01C6 6804 SPIGCR1 SPI GlobalControlRegister1 0x01C6 6808 SPIINT SPI InterruptRegister 0x01C6 680C SPILVL SPI InterruptLevelRegister 0x01C6 6810 SPIFLG SPI FlagStatusRegister 0x01C6 6814 SPIPC0 SPI PinControlRegister0 0x01C6 6818 – Reserved 0x01C6 681C SPIPC2 SPI PinControlRegister2 0x01C6 6820 -0x01C6 6838 – Reserved 0x01C6 683C SPIDAT1 SPI ShiftRegister1 0x01C6 6840 SPIBUF SPI BufferRegister 0x01C6 6844 SPIEMU SPI EmulationRegister 0x01C6 6848 SPIDELAY SPI DelayRegister 0x01C6 684C SPIDEF SPI DefaultChipSelectRegister 0x01C6 6850 SPIFMT0 SPI Data FormatRegister0 0x01C6 6854 SPIFMT1 SPI Data FormatRegister1 0x01C6 6858 SPIFMT2 SPI Data FormatRegister2 0x01C6 685C SPIFMT3 SPI Data FormatRegister3 0x01C6 6860 INTVEC0 SPI InterruptVectorRegister0 0x01C6 6864 INTVEC1 SPI InterruptVectorRegister1 0x01C6 6868 -0x01C6 6FFF Reserved

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SPIx_CLK (Clock Polarity = 0) SPIx_CLK (Clock Polarity = 1) TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010

6.17.2 SPI ElectricalData/Timing

Table6-79.Timing Requirements forSPI (AllModes) (1)(seeFigure6-62) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(CLK) Cycletime,SPI_CLK 30.3 56888.89 ns 2 tw(CLKH) Pulseduration,SPI_CLK high(AllMasterModes) 0.45*T 0.55*T ns 3 tw(CLKL) Pulseduration,SPI_CLK low(AllMasterModes 0.45*T 0.55*T ns (1) T = tc(CLK) [SPI_CLK periodisequaltotheSPI module clockdividedby a configurabledivider.] Figure6-62.SPI_CLK Timing Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 195 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPI_CLK (Clock Polarity = 0) SPI_CLK (Clock Polarity = 1) SPI_DI (Input) SPI_DO (Output) MSB IN DATA LSB IN LSB OUTMSB OUT DATA SPI_EN TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com 6.17.2.1SPI Master Mode Timings (ClockPhase = 0) Table6-80.Timing Requirements forSPI Master Mode [ClockPhase = 0] (1)(seeFigure6-63) A-513, -594, NO. UNIT-810 MIN MAX Setuptime,SPI_DI(input)validbeforeSPI_CLK (output)4 tsu(DIV-CLKL) ClockPolarity= 0 0.5P+ 9.4 nsfallingedge Setuptime,SPI_DI(input)validbeforeSPI_CLK (output)5 tsu(DIV-CLKH) ClockPolarity= 1 0.5P+ 9.4 nsrisingedge Holdtime,SPI_DI(input)validafterSPI_CLK (output)6 th(CLKL-DIV) ClockPolarity= 0 0.5P-4.5 nsfallingedge Holdtime,SPI_DI(input)validafterSPI_CLK (output)7 th(CLKH-DIV) ClockPolarity= 1 0.5P-4.5 nsrisingedge (1) P = PeriodoftheSPI module clockinnanoseconds(SYSCLK5). Table6-81.SwitchingCharacteristicsOver Recommended OperatingConditionsforSPI Master Mode ClockPhase = 0 A-513, -594, NO. PARAMETER UNIT-810 MIN MAX Delaytime,SPI_CLK (output)risingedge toSPI_DO8 td(CLKH-DOV) ClockPolarity= 0 -4 5 ns(output)transition Delaytime,SPI_CLK (output)fallingedge toSPI_DO9 td(CLKL-DOV) ClockPolarity= 1 -4 5 ns(output)transition Delaytime,SPI_EN1:0fallingedge tofirstSPI_CLK (output)risingor10 td(ENL-CLKH/L) 2P -2.3 nsfallingedge(1)(2) Delaytime,SPI_CLK (output)risingorfallingedge toSPI_EN1:011 td(CLKH/L-ENH) 1P + 0.5C -0.2 nsrisingedge(1)(2)(3) (1) P = PeriodoftheSPI module clockinnanoseconds(SYSCLK5). (2) Thisdelaycan be increasedundersoftwarecontrolby theC2TDELAY registerbitfieldintheSPIDELAY register. (3) C = PeriodofSPI_CLK signalinns. Figure6-63.SPI Master Mode ExternalTiming (ClockPhase = 0)

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SPI_CLK (Clock Polarity = 0) SPI_CLK (Clock Polarity = 1) SPI_DI (Input) SPI_DO (Output) MSB IN DATA LSB IN LSB OUTMSB OUT DATA SPI_EN TMS320DM6446 www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.17.2.2SPI Master Mode Timings (ClockPhase = 1) Table6-82.Timing Requirements forSPI Master Mode ClockPhase = 1(seeFigure6-64) A-513, -594, NO. UNIT-810 MIN MAX Setuptime,SPI_DI(input)validbeforeSPI_CLK13 tsu(DIV-CLKL) ClockPolarity= 0 0.5P+ 9.4 ns(output)risingedge Setuptime,SPI_DI(input)validbeforeSPI_CLK14 tsu(DIV-CLKH) ClockPolarity= 1 0.5P+ 9.4 ns(output)fallingedge Holdtime,SPI_DI(input)validafterSPI_CLK15 th(CLKL-DIV) ClockPolarity= 0 0.5P-4.5 ns(output)risingedge Holdtime,SPI_DI(input)validafterSPI_CLK16 th(CLKH-DIV) ClockPolarity= 1 0.5P-4.5 ns(output)fallingedge (1) P = PeriodoftheSPI module clockinnanoseconds(SYSCLK5). Table6-83.SwitchingCharacteristicsOver Recommended OperatingConditionsforSPI Master Mode ClockPhase = 1 A-513, -594, NO. PARAMETER UNIT-810 MIN MAX Delaytime,SPI_CLK (output)fallingedge toSPI_DO17 td(CLKL-DOV) ClockPolarity= 0 -4 5 ns(output)transition Delaytime,SPI_CLK (output)risingedge toSPI_DO18 td(CLKH-DOV) ClockPolarity= 1 -4 5 ns(output)transition Delaytime,SPI_EN1:0fallingedge tofirstSPI_CLK (output)risingor19 td(ENL-CLKH/L) 2P + 0.5C -2.3 nsfallingedge(1)(2)(3) Delaytime,SPI_CLK (output)risingorfallingedge toSPI_EN1:020 td(CLKH/L-ENH) 1P -0.2 nsrisingedge(1)(2) (1) P = PeriodoftheSPI module clockinnanoseconds(SYSCLK5). (2) Thisdelaycan be increasedundersoftwarecontrolby theC2TDELAY registerbitfieldintheSPIDELAY register. (3) C = PeriodofSPI_CLK signalinns. Figure6-64.SPI Master Mode ExternalTiming (ClockPhase = 1) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 197 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.18 Inter-IntegratedCircuit(I2C)

The inter-integratedcircuit(I2C)module providesan interfacebetween DM6446 and otherdevices compliantwith PhilipsSemiconductorsInter-ICbus (I2C-bus™ ) specificationversion2.1. External components attachedto this2-wireserialbus can transmit/receiveup to 8-bitdata to/fromthe DSP throughtheI2C module.The I2C portdoes notsupportCBUS compatibledevices. The I2C portsupports:

• CompatiblewithPhilipsI2C SpecificationRevision2.1(January2000)
• FastMode up to400 Kbps (nofail-safeI/Obuffers)
• NoiseFiltertoRemove Noise50 ns orless
• Seven-and Ten-BitDeviceAddressingModes
• Master(Transmit/Receive)and Slave(Transmit/Receive)Functionality
• Events:DMA, Interrupt,orPolling
• Slew-RateLimitedOpen-DrainOutputBuffers For more detailedinformationon the I2C peripheral,see the TMS320DM644x DMSoC Peripherals OverviewReferenceGuide (literaturenumber SPRUE19 ). CAUTION The DM6446 I2C pinsuse a standard±4-mA LVCMOS buffer,nottheslow I/Obuffer definedintheI2C specification.Seriesresistorsmay be necessarytoreducenoiseat thesystemlevel.

6.18.1 I2C PeripheralRegisterDescription(s)

Table6-84.I2C Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x1c2 1000 ICOAR I2C Own AddressRegister 0x1c2 1004 ICIMR I2C InterruptMask Register 0x1c2 1008 ICSTR I2C InterruptStatusRegister 0x1c2 100C ICCLKL I2C ClockDividerLow Register 0x1c2 1010 ICCLKH I2C ClockDividerHighRegister 0x1c2 1014 ICCNT I2C Data Count Register 0x1c2 1018 ICDRR I2C Data ReceiveRegister 0x1c2 101C ICSAR I2C SlaveAddressRegister 0x1c2 1020 ICDXR I2C Data TransmitRegister 0x1c2 1024 ICMDR I2C Mode Register 0x1c2 1028 ICIVR I2C InterruptVectorRegister 0x1c2 102C ICEMDR I2C ExtendedMode Register 0x1c2 1030 ICPSC I2C PrescalerRegister 0x1c2 1034 ICPID1 I2C PeripheralIdentificationRegister1 0x1c2 1038 ICPID2 I2C PeripheralIdentificationRegister2

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6.18.2 I2C ElectricalData/Timing

6.18.2.1 Inter-IntegratedCircuits(I2C)Timing

Table6-85.Timing Requirements forI2C Timings(1)(seeFigure6-65) A-513, -594, -810 NO. UNITSTANDARD FAST MODEMODE MIN MAX MIN MAX 1 tc(SCL) Cycletime,SCL 10 2.5 µs Setuptime,SCL highbeforeSDA low2 tsu(SCLH-SDAL) 4.7 0.6 µs(fora repeatedSTART condition) Holdtime,SCL lowafterSDA low3 th(SCLL-SDAL) 4 0.6 µs(fora START and a repeatedSTART condition) 4 tw(SCLL) Pulseduration,SCL low 4.7 1.3 µs 5 tw(SCLH) Pulseduration,SCL high 4 0.6 µs 6 tsu(SDAV-SCLH) Setuptime,SDA validbeforeSCL high 250 100(2) ns 7 th(SDA-SCLL) Holdtime,SDA validafterSCL low 0(3) 0(3) 0.9(4) µs Pulseduration,SDA highbetween STOP and START8 tw(SDAH) 4.7 1.3 µsconditions 9 tr(SDA) Risetime,SDA 1000 20 + 0.1Cb (5) 300 ns 10 tr(SCL) Risetime,SCL 1000 20 + 0.1Cb (5) 300 ns 11 tf(SDA) Falltime,SDA 300 20 + 0.1Cb (5) 300 ns 12 tf(SCL) Falltime,SCL 300 20 + 0.1Cb (5) 300 ns Setuptime,SCL highbeforeSDA high(forSTOP13 tsu(SCLH-SDAH) 4 0.6 µscondition) 14 tw(SP) Pulseduration,spike(mustbe suppressed) 0 50 ns

15 C b

(5) Capacitiveloadforeach bus line 400 400 pF (1) The I2C pinsSDA and SCL do notfeaturefail-safeI/Obuffers.These pinscouldpotentiallydraw currentwhen thedeviceispowered down. (2) A Fast-modeI2C-bus™ devicecan be used ina Standard-modeI2C-bus system,buttherequirementtsu(SDA-SCLH) ≥ 250 ns must then be met.Thiswillautomaticallybe thecase ifthedevicedoes notstretchtheLOW periodoftheSCL signal.Ifsuch a devicedoes stretch theLOW periodoftheSCL signal,itmust outputthenextdatabittotheSDA linetr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (accordingtotheStandard-modeI2C-Bus Specification)beforetheSCL lineisreleased. (3) A devicemust internallyprovidea holdtimeofatleast300 ns fortheSDA signal(referredtotheVIHmin oftheSCL signal)tobridgethe undefinedregionofthefallingedge ofSCL. (4) The maximum th(SDA-SCLL) has onlytobe met ifthedevicedoes notstretchthelowperiod[tw(SCLL)]oftheSCL signal. (5) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. Figure6-65.I2C Receive Timings Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 199 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-86.SwitchingCharacteristicsforI2C Timings (seeFigure6-66) A-513, -594, -810 NO. PARAMETER UNITSTANDARD FAST MODE MODE MIN MAX MIN MAX 16 tc(SCL) Cycletime,SCL 10 2.5 µs Delaytime,SCL hightoSDA low17 td(SCLH-SDAL) 4.7 0.6 µs(fora repeatedSTART condition) Delaytime,SDA lowtoSCL low18 td(SDAL-SCLL) 4 0.6 µs(fora START and a repeatedSTART condition) 19 tw(SCLL) Pulseduration,SCL low 4.7 1.3 µs 20 tw(SCLH) Pulseduration,SCL high 4 0.6 µs 21 td(SDAV-SCLH) Delaytime,SDA validtoSCL high 250 100 ns 22 tv(SCLL-SDAV) Validtime,SDA validafterSCL low 0 0 0.9 µs 23 tw(SDAH) Pulseduration,SDA highbetween STOP and START conditions 4.7 1.3 µs 28 td(SCLH-SDAH) Delaytime,SCL hightoSDA high(forSTOP condition) 4 0.6 µs

29 C p Capacitanceforeach I2C pin 10 10 pF

Figure6-66.I2C TransmitTimings CAUTION The DM6446 I2C pinsuse a standard±4-mA LVCMOS buffer,nottheslow I/Obuffer definedintheI2C specification.Seriesresistorsmay be necessarytoreducenoiseat thesystemlevel.

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6.19 Audio SerialPort(ASP)

The ASP providesthesefunctions:

• Full-duplexcommunication
• Double-buffereddataregisters,whichallowa continuousdatastream
• Independentframingand clockingforreceiveand transmit
• Directinterfacetoindustry-standardcodecs,analoginterfacechips(AICs),and otherserially connectedanalog-to-digital(A/D)and digital-to-analog(D/A)devices
• Externalshiftclockoran internal,programmablefrequencyshiftclockfordatatransfer For more detailedinformationon theASP peripheral,see theTMS320DM644x DMSoC AudioSerialPort (ASP) User'sGuide (literaturenumber SPRUE29 ).

6.19.1 ASP PeripheralRegisterDescription(s)

Table6-87.ASP RegisterDescriptions HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E0 2000 DRR ASP Data ReceiveRegister 0x01E0 2004 DXR ASP Data TransmitRegister 0x01E0 2008 SPCR ASP SerialPortControlRegister 0x01E0 200C RCR ASP ReceiveControlRegister 0x01E0 2010 XCR ASP TransmitControlRegister 0x01E0 2014 SRGR ASP Sample Rate GeneratorRegister 0x01E0 2024 PCR ASP PinControlRegister Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 201 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

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6.19.2 ASP ElectricalData/Timing

6.19.2.1 Audio SerialPort(ASP) Timing

Table6-88.Timing Requirements forASP (1)(seeFigure6-67) A-513, -594, NO. UNIT-810 MIN MAX 2 tc(CKRX) Cycletime,CLKR/X CLKR/X ext 38.5or2P (2)(3) ns 19.25orP (2)(3) 3 tw(CKRX) Pulseduration,CLKR/X highorCLKR/X low CLKR/X ext ns(4) CLKR int 11.8 5 tsu(FRH-CKRL) Setuptime,externalFSR highbeforeCLKR low ns CLKR ext 1.3 CLKR int 6 6 th(CKRL-FRH) Holdtime,externalFSR highafterCLKR low ns CLKR ext 3 CLKR int 10.7 7 tsu(DRV-CKRL) Setuptime,DR validbeforeCLKR low ns CLKR ext 0.9 CLKR int 3 8 th(CKRL-DRV) Holdtime,DR validafterCLKR low ns CLKR ext 3.1 CLKX int 12.2 10 tsu(FXH-CKXL) Setuptime,externalFSX highbeforeCLKX low ns CLKX ext 1.4 CLKX int 6 11 th(CKXL-FXH) Holdtime,externalFSX highafterCLKX low ns CLKX ext 3 (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) P = 1/SYSCLK5 clockfrequencyinns.Forexample,when runningpartsatDSP frequencyof594 MHz, use P = 10.1ns;when running partsatDSP frequencyof810 MHz, use P = 7.4ns. (3) Use whichevervalueisgreater. (4) The ASP does not requirea dutycyclespecification,justensuretheminimum pulsedurationspecificationismet.

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-89.SwitchingCharacteristicsOver Recommended OperatingConditionsforASP (1)(2) (seeFigure6-67) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 2 tc(CKRX) Cycletime,CLKR/X CLKR/X int 38.5(3) ns 3 tw(CKRX) Pulseduration,CLKR/X highorCLKR/X low CLKR/X int C -1(4) C + 1(4) ns 4 td(CKRH-FRV) Delaytime,CLKR hightointernalFSR valid CLKR int -2.1 3 ns CLKX int -1.7 3 9 td(CKXH-FXV) Delaytime,CLKX hightointernalFSX valid ns CLKX ext 1.7 14.4 CLKX int -3.9 4Disabletime,DX highimpedance followinglastdata12 tdis(CKXH-DXHZ) nsbitfromCLKX high CLKX ext 2.1 13 CLKX int -3.9+ D1 (5) 4 + D2 (5) ns 13 td(CKXH-DXV) Delaytime,CLKX hightoDX valid CLKX ext 2.1+ D1 (5) 14.5+ D2 (5) ns Delaytime,FSX hightoDX valid FSX int -2.3+ D1 (6) 4 + D2 (6) 14 td(FXH-DXV) ONLY applieswhen indata ns FSX ext 1.9+ D1 (6) 12.1+ D2 (6) delay0 (XDATDLY = 00b)mode (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimum delaytimesalsorepresentminimum outputholdtimes. (3) Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclocksource.Minimum CLKR/X cycletimes arebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA3 limitationsand AC timingrequirements. (4) C = H orL S = sample rategeneratorinputclock= 4P ifCLKSM = 1 (P = 1/CPU clockfrequency[SYSCLK1]) S = sample rategeneratorinputclock= Not SupportedifCLKSM = 0 (noCLKS pinon DM6446) H = CLKX highpulsewidth= (CLKGDV/2 + 1)*S ifCLKGDV iseven H = (CLKGDV + 1)/2*S ifCLKGDV isodd orzero L = CLKX lowpulsewidth= (CLKGDV/2) *S ifCLKGDV iseven L = (CLKGDV + 1)/2*S ifCLKGDV isodd orzero CLKGDV shouldbe setappropriatelytoensuretheASP bitratedoes notexceed themaximum limit[seefootnote(3)above]. (5) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 4P,D2 = 8P (6) ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 4P,D2 = 8P Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 203 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 13(A) 13(A) A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0. CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) DX TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Figure6-67.ASP Timing

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6.20 EthernetMedia Access Controller(EMAC)

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween DM6446 and the network.The DM6446 EMAC supportboth10Base-T and 100Base-TX,or 10 Mbits/second(Mbps) and

100 Mbps ineitherhalf-or full-duplexmode, withhardware flowcontroland qualityof service(QOS)

support. The EMAC controlsthe flowof packetdata from the DM6446 deviceto the PHY. The MDIO module controlsPHY configurationand statusmonitoring. Both theEMAC and theMDIO modules interfacetotheDM6446 devicethrougha custom interfacethat allowsefficientdatatransmissionand reception.Thiscustom interfaceisreferredtoas theEMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts. For more detailedinformationon theEMAC peripheral,see theTMS320DM644x DMSoC EthernetMedia Access Controller(EMAC)/Management Data Input/Output(MDIO) Module User's Guide (literature number SPRUE24 ).For a listof supportedregistersand registerfields,see Table 6-90 [EthernetMAC (EMAC) ControlRegisters]and Table6-91[EMAC StatisticsRegisters]inthisdatamanual.

6.20.1 EMAC PeripheralRegisterDescription(s)

Table6-90.EthernetMAC (EMAC) ControlRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0000 TXIDVER TransmitIdentificationand VersionRegister 01C8 0004 TXCONTROL TransmitControlRegister 01C8 0008 TXTEARDOWN TransmitTeardown Register 01C8 0010 RXIDVER ReceiveIdentificationand VersionRegister 01C8 0014 RXCONTROL ReceiveControlRegister 01C8 0018 RXTEARDOWN ReceiveTeardown Register 01C8 0080 TXINTSTATRAW TransmitInterruptStatus(Unmasked) Register 01C8 0084 TXINTSTATMASKED TransmitInterruptStatus(Masked)Register 01C8 0088 TXINTMASKSET TransmitInterruptMask SetRegister 01C8 008C TXINTMASKCLEAR TransmitInterruptMask ClearRegister 01C8 0090 MACINVECTOR MAC InputVectorRegister 01C8 00A0 RXINTSTATRAW ReceiveInterruptStatus(Unmasked) Register 01C8 00A4 RXINTSTATMASKED ReceiveInterruptStatus(Masked)Register 01C8 00A8 RXINTMASKSET ReceiveInterruptMask SetRegister 01C8 00AC RXINTMASKCLEAR ReceiveInterruptMask ClearRegister 01C8 00B0 MACINTSTATRAW MAC InterruptStatus(Unmasked) Register 01C8 00B4 MACINTSTATMASKED MAC InterruptStatus(Masked)Register 01C8 00B8 MACINTMASKSET MAC InterruptMask SetRegister 01C8 00BC MACINTMASKCLEAR MAC InterruptMask ClearRegister 01C8 0100 RXMBPENABLE ReceiveMulticast/Broadcast/PromiscuousChannelEnableRegister 01C8 0104 RXUNICASTSET ReceiveUnicastEnableSetRegister 01C8 0108 RXUNICASTCLEAR ReceiveUnicastClearRegister 01C8 010C RXMAXLEN ReceiveMaximum LengthRegister 01C8 0110 RXBUFFEROFFSET ReceiveBufferOffsetRegister 01C8 0114 RXFILTERLOWTHRESH ReceiveFilterLow PriorityFrame ThresholdRegister 01C8 0120 RX0FLOWTHRESH ReceiveChannel0 Flow ControlThresholdRegister 01C8 0124 RX1FLOWTHRESH ReceiveChannel1 Flow ControlThresholdRegister 01C8 0128 RX2FLOWTHRESH ReceiveChannel2 Flow ControlThresholdRegister 01C8 012C RX3FLOWTHRESH ReceiveChannel3 Flow ControlThresholdRegister Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 205 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-90.EthernetMAC (EMAC) ControlRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0130 RX4FLOWTHRESH ReceiveChannel4 Flow ControlThresholdRegister 01C8 0134 RX5FLOWTHRESH ReceiveChannel5 Flow ControlThresholdRegister 01C8 0138 RX6FLOWTHRESH ReceiveChannel6 Flow ControlThresholdRegister 01C8 013C RX7FLOWTHRESH ReceiveChannel7 Flow ControlThresholdRegister 01C8 0140 RX0FREEBUFFER ReceiveChannel0 FreeBufferCount Register 01C8 0144 RX1FREEBUFFER ReceiveChannel1 FreeBufferCount Register 01C8 0148 RX2FREEBUFFER ReceiveChannel2 FreeBufferCount Register 01C8 014C RX3FREEBUFFER ReceiveChannel3 FreeBufferCount Register 01C8 0150 RX4FREEBUFFER ReceiveChannel4 FreeBufferCount Register 01C8 0154 RX5FREEBUFFER ReceiveChannel5 FreeBufferCount Register 01C8 0158 RX6FREEBUFFER ReceiveChannel6 FreeBufferCount Register 01C8 015C RX7FREEBUFFER ReceiveChannel7 FreeBufferCount Register 01C8 0160 MACCONTROL MAC ControlRegister 01C8 0164 MACSTATUS MAC StatusRegister 01C8 0168 EMCONTROL EmulationControlRegister 01C8 016C FIFOCONTROL FIFO ControlRegister(Transmitand Receive) 01C8 0170 MACCONFIG MAC ConfigurationRegister 01C8 0174 SOFTRESET SoftResetRegister 01C8 01D0 MACSRCADDRLO MAC SourceAddressLow BytesRegister(Lower16-bits) 01C8 01D4 MACSRCADDRHI MAC SourceAddressHighBytesRegister(Upper32-bits) 01C8 01D8 MACHASH1 MAC Hash AddressRegister1 01C8 01DC MACHASH2 MAC Hash AddressRegister2 01C8 01E0 BOFFTEST Back OffTestRegister 01C8 01E4 TPACETEST TransmitPacingAlgorithmTestRegister 01C8 01E8 RXPAUSE ReceivePause TimerRegister 01C8 01EC TXPAUSE TransmitPause TimerRegister 01C8 0200 -01C8 02FC (seeTable6-91) EMAC StatisticsRegisters 01C8 0500 MACADDRLO MAC AddressLow BytesRegister 01C8 0504 MACADDRHI MAC AddressHighBytesRegister 01C8 0508 MACINDEX MAC IndexRegister 01C8 0600 TX0HDP TransmitChannel0 DMA Head DescriptorPointerRegister 01C8 0604 TX1HDP TransmitChannel1 DMA Head DescriptorPointerRegister 01C8 0608 TX2HDP TransmitChannel2 DMA Head DescriptorPointerRegister 01C8 060C TX3HDP TransmitChannel3 DMA Head DescriptorPointerRegister 01C8 0610 TX4HDP TransmitChannel4 DMA Head DescriptorPointerRegister 01C8 0614 TX5HDP TransmitChannel5 DMA Head DescriptorPointerRegister 01C8 0618 TX6HDP TransmitChannel6 DMA Head DescriptorPointerRegister 01C8 061C TX7HDP TransmitChannel7 DMA Head DescriptorPointerRegister 01C8 0620 RX0HDP ReceiveChannel0 DMA Head DescriptorPointerRegister 01C8 0624 RX1HDP ReceiveChannel1 DMA Head DescriptorPointerRegister 01C8 0628 RX2HDP ReceiveChannel2 DMA Head DescriptorPointerRegister 01C8 062C RX3HDP ReceiveChannel3 DMA Head DescriptorPointerRegister 01C8 0630 RX4HDP ReceiveChannel4 DMA Head DescriptorPointerRegister 01C8 0634 RX5HDP ReceiveChannel5 DMA Head DescriptorPointerRegister 01C8 0638 RX6HDP ReceiveChannel6 DMA Head DescriptorPointerRegister 01C8 063C RX7HDP ReceiveChannel7 DMA Head DescriptorPointerRegister TransmitChannel0 CompletionPointer(InterruptAcknowledge)01C8 0640 TX0CP Register

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-90.EthernetMAC (EMAC) ControlRegisters(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME TransmitChannel1 CompletionPointer(InterruptAcknowledge)01C8 0644 TX1CP Register TransmitChannel2 CompletionPointer(InterruptAcknowledge)01C8 0648 TX2CP Register TransmitChannel3 CompletionPointer(InterruptAcknowledge)01C8 064C TX3CP Register TransmitChannel4 CompletionPointer(InterruptAcknowledge)01C8 0650 TX4CP Register TransmitChannel5 CompletionPointer(InterruptAcknowledge)01C8 0654 TX5CP Register TransmitChannel6 CompletionPointer(InterruptAcknowledge)01C8 0658 TX6CP Register TransmitChannel7 CompletionPointer(InterruptAcknowledge)01C8 065C TX7CP Register ReceiveChannel0 CompletionPointer(InterruptAcknowledge)01C8 0660 RX0CP Register ReceiveChannel1 CompletionPointer(InterruptAcknowledge)01C8 0664 RX1CP Register ReceiveChannel2 CompletionPointer(InterruptAcknowledge)01C8 0668 RX2CP Register ReceiveChannel3 CompletionPointer(InterruptAcknowledge)01C8 066C RX3CP Register ReceiveChannel4 CompletionPointer(InterruptAcknowledge)01C8 0670 RX4CP Register ReceiveChannel5 CompletionPointer(InterruptAcknowledge)01C8 0674 RX5CP Register ReceiveChannel6 CompletionPointer(InterruptAcknowledge)01C8 0678 RX6CP Register ReceiveChannel7 CompletionPointer(InterruptAcknowledge)01C8 067C RX7CP Register Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 207 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-91.EMAC StatisticsRegisters HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0200 RXGOODFRAMES Good ReceiveFrames Register BroadcastReceiveFrames Register01C8 0204 RXBCASTFRAMES (Totalnumber ofgood broadcastframesreceived) MulticastReceiveFrames Register01C8 0208 RXMCASTFRAMES (Totalnumber ofgood multicastframesreceived) 01C8 020C RXPAUSEFRAMES Pause ReceiveFrames Register ReceiveCRC ErrorsRegister(Totalnumber offramesreceivedwith01C8 0210 RXCRCERRORS CRC errors) ReceiveAlignment/CodeErrorsRegister01C8 0214 RXALIGNCODEERRORS (Totalnumber offramesreceivedwithalignment/codeerrors) ReceiveOversizedFrames Register01C8 0218 RXOVERSIZED (Totalnumber ofoversizedframesreceived) ReceiveJabberFrames Register01C8 021C RXJABBER (Totalnumber ofjabberframesreceived) ReceiveUndersizedFrames Register01C8 0220 RXUNDERSIZED (Totalnumber ofundersizedframesreceived) 01C8 0224 RXFRAGMENTS ReceiveFrame FragmentsRegister 01C8 0228 RXFILTERED FilteredReceiveFrames Register 01C8 022C RXQOSFILTERED ReceivedQOS FilteredFrames Register ReceiveOctetFrames Register01C8 0230 RXOCTETS (Totalnumber ofreceivedbytesingood frames) Good TransmitFrames Register01C8 0234 TXGOODFRAMES (Totalnumber ofgood framestransmitted) 01C8 0238 TXBCASTFRAMES BroadcastTransmitFrames Register 01C8 023C TXMCASTFRAMES MulticastTransmitFrames Register 01C8 0240 TXPAUSEFRAMES Pause TransmitFrames Register 01C8 0244 TXDEFERRED DeferredTransmitFrames Register 01C8 0248 TXCOLLISION TransmitCollisionFrames Register 01C8 024C TXSINGLECOLL TransmitSingleCollisionFrames Register 01C8 0250 TXMULTICOLL TransmitMultipleCollisionFrames Register 01C8 0254 TXEXCESSIVECOLL TransmitExcessiveCollisionFrames Register 01C8 0258 TXLATECOLL TransmitLateCollisionFrames Register 01C8 025C TXUNDERRUN TransmitUnderrunErrorRegister 01C8 0260 TXCARRIERSENSE TransmitCarrierSense ErrorsRegister 01C8 0264 TXOCTETS TransmitOctetFrames Register 01C8 0268 FRAME64 Transmitand Receive64 OctetFrames Register 01C8 026C FRAME65T127 Transmitand Receive65 to127 OctetFrames Register 01C8 0270 FRAME128T255 Transmitand Receive128 to255 OctetFrames Register 01C8 0274 FRAME256T511 Transmitand Receive256 to511 OctetFrames Register 01C8 0278 FRAME512T1023 Transmitand Receive512 to1023 OctetFrames Register 01C8 027C FRAME1024TUP Transmitand Receive1024 to1518 OctetFrames Register 01C8 0280 NETOCTETS NetworkOctetFrames Register 01C8 0284 RXSOFOVERRUNS ReceiveFIFO orDMA StartofFrame OverrunsRegister 01C8 0288 RXMOFOVERRUNS ReceiveFIFO orDMA MiddleofFrame OverrunsRegister ReceiveDMA StartofFrame and MiddleofFrame Overruns01C8 028C RXDMAOVERRUNS Register

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 Table6-92.EMAC ControlModule Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 1004 EWCTL Interruptcontrolregister 0x01C8 1008 EWINTTCNT Interrupttimercount Table6-93.EMAC ControlModule RAM HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 2000 -0x01C8 3FFF EMAC ControlModule DescriptorMemory

6.20.2 EMAC ElectricalData/Timing

Table6-94.Timing Requirements forMRCLK (seeFigure6-68) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(MRCLK) Cycletime,MRCLK 40 ns 2 tw(MRCLKH) Pulseduration,MRCLK high 14 ns 3 tw(MRCLKL) Pulseduration,MRCLK low 14 ns Figure6-68.MRCLK Timing (EMAC -Receive) Table6-95.Timing Requirements forMTCLK (seeFigure6-69) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(MTCLK) Cycletime,MTCLK 40 ns 2 tw(MTCLKH) Pulseduration,MTCLK high 14 ns 3 tw(MTCLKL) Pulseduration,MTCLK low 14 ns Figure6-69.MTCLK Timing (EMAC -Transmit) Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 209 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

MRCLK (Input) MRXD3−MRXD0, MRXDV , MRXER (Inputs) MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-96.Timing Requirements forEMAC MIIReceive 10/100Mbit/s(1)(seeFigure6-70) A-513, -594, NO. UNIT-810 MIN MAX 1 tsu(MRXD-MRCLKH) Setuptime,receiveselectedsignalsvalidbeforeMRCLK high 8 ns 2 th(MRCLKH-MRXD) Holdtime,receiveselectedsignalsvalidafterMRCLK high 8 ns (1) Receiveselectedsignalsinclude:MRXD3-MRXD0, MRXDV, and MRXER. Figure6-70.EMAC Receive InterfaceTiming Table6-97.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC MIITransmit 10/100Mbit/s(1)(seeFigure6-71) A-513, -594, NO. UNIT-810 MIN MAX 1 td(MTCLKH-MTXD) Delaytime,MTCLK hightotransmitselectedsignalsvalid 5 25 ns (1) Transmitselectedsignalsinclude:MTXD3-MTXD0, and MTXEN. Figure6-71.EMAC TransmitInterfaceTiming

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6.21 Management Data Input/Output(MDIO)

The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerateallPHY devicesinthesystem. The Management Data Input/Output(MDIO) module implementsthe802.3serialmanagement interfaceto interrogateand controlEthernetPHY(s) usinga shared two-wirebus. Host softwareuses the MDIO module to configurethe auto-negotiationparametersof each PHY attachedto the EMAC, retrievethe negotiationresults,and configurerequiredparametersinthe EMAC module forcorrectoperation.The module is designed to allow almost transparentoperationof the MDIO interface,with very little maintenancefromthecoreprocessor.Onlyone PHY may be connectedatany giventime. For more detailedinformationon theMDIO peripheral,see theTMS320DM644x DMSoC EthernetMedia Access Controller(EMAC)/ Management Data Input/Output(MDIO) Module User'sGuide (literature number SPRUE24 ).For a listofsupportedregistersand registerfields,see Table6-98[MDIO Registers] inthisdatamanual.

6.21.1 PeripheralRegisterDescription(s)

Table6-98.MDIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C8 4000 – Reserved 0x01C8 4004 CONTROL MDIO ControlRegister 0x01C8 4008 ALIVE MDIO PHY AliveStatusRegister 0x01C8 400C LINK MDIO PHY LinkStatusRegister 0x01C8 4010 LINKINTRAW MDIO LinkStatusChange Interrupt(Unmasked) Register 0x01C8 4014 LINKINTMASKED MDIO LinkStatusChange Interrupt(Masked)Register 0x01C8 4018 – Reserved 0x01C8 4020 USERINTRAW MDIO User Command CompleteInterrupt(Unmasked) Register 0x01C8 4024 USERINTMASKED MDIO User Command CompleteInterrupt(Masked)Register 0x01C8 4028 USERINTMASKSET MDIO User Command CompleteInterruptMask SetRegister 0x01C8 402C USERINTMASKCLEAR MDIO User Command CompleteInterruptMask ClearRegister 0x01C8 4030 -0x01C8 407C – Reserved 0x01C8 4080 USERACCESS0 MDIO User Access Register0 0x01C8 4084 USERPHYSEL0 MDIO User PHY SelectRegister0 0x01C8 4088 USERACCESS1 MDIO User Access Register1 0x01C8 408C USERPHYSEL1 MDIO User PHY SelectRegister1 0x01C8 4090 -0x01C8 47FF – Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 211 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

(input) 3 3 MDCLK MDIO (output) TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

6.21.2 Management Data Input/Output(MDIO) ElectricalData/Timing

Table6-99.Timing Requirements forMDIO Input(seeFigure6-72and Figure6-73) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 ns 2 tw(MDCLK) Pulseduration,MDCLK high/low 180 ns 3 tt(MDCLK) Transitiontime,MDCLK 5 ns 4 tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMDCLK high 15 ns 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK high 0 ns Figure6-72.MDIO InputTiming Table6-100.SwitchingCharacteristicsOver Recommended OperatingConditionsforMDIO Output (seeFigure6-73) A-513, -594, NO. UNIT-810 MIN MAX 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutputvalid -0.6 100 ns Figure6-73.MDIO Output Timing

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6.22 Timer

The DM6446 devicehas 3 64-bitgeneral-purposetimerswhichhave thefollowingfeatures:

• 64-bitcount-upcounter
• Timermodes: – 64-bitgeneral-purposetimermode – Dual32-bitgeneral-purposetimermode (Timer0 and 1) – Watchdog timermode (Timer2)
• 2 possibleclocksources: – Internalclock – ExternalclockinputviatimerinputpinTIM_IN (Timer0 only)
• 2 operationmodes: – One-timeoperation(timerrunsforone periodthenstops) – Continuousoperation(timerautomaticallyresetsaftereach period)
• GeneratesinterruptstoboththeDSP and theARM CPUs
• GeneratessynceventtoEDMA3 For more detailedinformation,see the TMS320DM644x DMSoC 64-BitTimer User'sGuide (literature number SPRUE26 ).

6.22.1 Timer PeripheralRegisterDescription(s)

Table6-101.Timer 0 Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C2 1400 - Reserved 0x01C2 1404 EMUMGT_CLKSPD Timer0 EmulationManagement/ClockSpeed Register 0x01C2 1410 TIM12 Timer0 CounterRegister12 0x01C2 1414 TIM34 Timer0 CounterRegister34 0x01C2 1418 PRD12 Timer0 PeriodRegister12 0x01C2 141C PRD34 Timer0 PeriodRegister34 0x01C2 1420 TCR Timer0 ControlRegister 0x01C2 1424 TGCR Timer0 GlobalControlRegister 0x01C2 1428 -0x01C2 17FF - Reserved Table6-102.Timer 1 Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C2 1800 - Reserved 0x01C2 1804 EMUMGT_CLKSPD Timer1 EmulationManagement/ClockSpeed Register 0x01C2 1810 TIM12 Timer1 CounterRegister12 0x01C2 1814 TIM34 Timer1 CounterRegister34 0x01C2 1818 PRD12 Timer1 PeriodRegister12 0x01C2 181C PRD34 Timer1 PeriodRegister34 0x01C2 1820 TCR Timer1 ControlRegister 0x01C2 1824 TGCR Timer1 GlobalControlRegister 0x01C2 1828 -0x01C2 1BFF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 213 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

TIM_IN TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-103.Timer 2 (Watchdog) Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01C2 1C00 - Reserved 0x01C2 1C04 EMUMGT_CLKSPD Timer2 EmulationManagement/ClockSpeed Register 0x01C2 1C10 TIM12 Timer2 CounterRegister12 0x01C2 1C14 TIM34 Timer2 CounterRegister34 0x01C2 1C18 PRD12 Timer2 PeriodRegister12 0x01C2 1C1C PRD34 Timer2 PeriodRegister34 0x01C2 1C20 TCR Timer2 ControlRegister 0x01C2 1C24 TGCR Timer2 GlobalControlRegister 0x01C2 1C28 WDTCR Timer2 Watchdog TimerControlRegister 0x01C2 1C2C -0x01C2 1FFF - Reserved

6.22.2 Timer ElectricalData/Timing

Table6-104.Timing Requirements forTimer Input(1)(2)(seeFigure6-74) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(TIN) Cycletime,TIM_IN 4P ns 2 tw(TINPH) Pulseduration,TIM_IN high 0.45C 0.55C ns 3 tw(TINPL) Pulseduration,TIM_IN low 0.45C 0.55C ns 4 tt(TIN) Transitiontime,TIM_IN 0.05C ns (1) P = MXI/CLKIN cycletimeinns.Forexample,when MXI/CLKIN frequencyis27 MHz, use P = 37.037 ns. (2) C = TIM_IN cycletimeinns.Forexample,when TIM_IN frequencyis27 MHz, use C = 37.037 ns Figure6-74.Timer Timing

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6.23 Pulse Width Modulator(PWM)

The 3 DM6446 PulseWidthModulator(PWM) peripheralssupportthefollowingfeatures:

• Periodcounter
• First-phasedurationcounter
• Repeat countforone-shotoperation
• Configurabletooperateineitherone-shotorcontinuousmode
• Bufferedperiodand first-phasedurationregisters
• One-shotoperationtriggerableby hardwareeventswithprogrammableedge transitions.(low-to-highor high-to-low).
• One-shotoperationgeneratesN+1 periodsofwaveform,N beingtherepeatcountregistervalue
• Emulationsupport The registermemory maps forPWM0/1/2 areshown inTable6-105,Table6-106,and Table6-107. Table6-105.PWM0 RegisterMemory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 2000 Reserved 0x01C2 2004 PCR PWM0 PeripheralControlRegister 0x01C2 2008 CFG PWM0 ConfigurationRegister 0x01C2 200C START PWM0 StartRegister 0x01C2 2010 RPT PWM0 Repeat Count Register 0x01C2 2014 PER PWM0 PeriodRegister 0x01C2 2018 PH1D PWM0 First-PhaseDurationRegister 0x01C2 201C -0x01C2 23FF - Reserved Table6-106.PWM1 RegisterMemory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 2400 Reserved 0x01C2 2404 PCR PWM1 PeripheralControlRegister 0x01C2 2408 CFG PWM1 ConfigurationRegister 0x01C2 240C START PWM1 StartRegister 0x01C2 2410 RPT PWM1 Repeat Count Register 0x01C2 2414 PER PWM1 PeriodRegister 0x01C2 2418 PH1D PWM1 First-PhaseDurationRegister 0x01C2 241C -0x01C2 27FF - Reserved Table6-107.PWM2 RegisterMemory Map HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01C2 2800 Reserved 0x01C2 2804 PCR PWM2 PeripheralControlRegister 0x01C2 2808 CFG PWM2 ConfigurationRegister 0x01C2 280C START PWM2 StartRegister 0x01C2 2810 RPT PWM2 Repeat Count Register 0x01C2 2814 PER PWM2 PeriodRegister 0x01C2 2818 PH1D PWM2 First-PhaseDurationRegister 0x01C2 281C -0x01C2 2BFF - Reserved Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 215 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

VD(CCDC) INVALID INVALID INVALID VALID VALID VALID PWM0 PWM1 PWM2 TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com

6.23.1 PWM0/1/2 Electrical/TimingData

Table6-108.SwitchingCharacteristicsOver Recommended OperatingConditionsforPWM0/1/2 Outputs (seeFigure6-75and Figure6-76) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 1 tw(PWMH) Pulseduration,PWMx high 37 ns 2 tw(PWML) Pulseduration,PWMx low 37 ns 3 tt(PWM) Transitiontime,PWMx 5 ns 4 td(CCDC-PWMV) Delaytime,CCDC(VD) triggereventtoPWMx valid 2 10 ns Figure6-75.PWM Output Timing Figure6-76.PWM Output Delay Timing

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6.24 VLYNQ

The DM6446 VLYNQ peripheralprovidesa highspeed serialcommunicationsinterfacewiththefollowing features.

• Low PinCount
• ScalablePerformance/Support
• SimplePacketBased TransferProtocolforMemory Mapped Access – WriteRequest/Data Packet – Read RequestPacket – Read Response Data Packet – InterruptRequestPacket
• SupportsbothSymmetricand AsymmetricOperation – Tx pinson firstdeviceconnecttoRx pinson second deviceand viceversa – Data pinwidthsareautomaticallydetectedafterreset – Requestpackets,responsepackets,and flowcontrolinformationareallmultiplexedand sent acrossthesame physicalpins – SupportsbothHost/Peripheraland Peer toPeer communication
• SimpleBlockCode PacketFormatting(8b/10b)
• InBand Flow Control – No extrapinsneeded – Allowsreceivertomomentarilythrottleback transmitterwhen overflowisabouttooccur – Uses builtinspecialcode capabilityofblockcode toseamlesslyinterleaveflowcontrolinformation withuserdata – Allowssystemdesignertobalancecostofdatabufferingversusperformance
• Multipleoutstandingtransactions
• Automaticpacketformattingoptimizations
• Internalloop-backmode

6.24.1 VLYNQ PeripheralRegisterDescription(s)

Table6-109.VLYNQ Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E0 1000 - Reserved 0x01E0 1004 CTRL VLYNQ LocalControlRegister 0x01E0 1008 STAT VLYNQ LocalStatusRegister 0x01E0 100C INTPRI VLYNQ LocalInterruptPriorityVectorStatus/ClearRegister 0x01E0 1010 INTSTATCLR VLYNQ LocalUnmasked InterruptStatus/ClearRegister 0x01E0 1014 INTPENDSET VLYNQ LocalInterruptPending/SetRegister 0x01E0 1018 INTPTR VLYNQ LocalInterruptPointerRegister 0x01E0 101C XAM VLYNQ LocalTransmitAddressMap Register 0x01E0 1020 RAMS1 VLYNQ LocalReceiveAddressMap Size1 Register 0x01E0 1024 RAMO1 VLYNQ LocalReceiveAddressMap Offset1 Register 0x01E0 1028 RAMS2 VLYNQ LocalReceiveAddressMap Size2 Register 0x01E0 102C RAMO2 VLYNQ LocalReceiveAddressMap Offset2 Register 0x01E0 1030 RAMS3 VLYNQ LocalReceiveAddressMap Size3 Register 0x01E0 1034 RAMO3 VLYNQ LocalReceiveAddressMap Offset3 Register 0x01E0 1038 RAMS4 VLYNQ LocalReceiveAddressMap Size4 Register 0x01E0 103C RAMO4 VLYNQ LocalReceiveAddressMap Offset4 Register 0x01E0 1040 CHIPVER VLYNQ LocalChipVersionRegister Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 217 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-109.VLYNQ Registers(continued) HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E0 1044 AUTNGO VLYNQ LocalAutoNegotiationRegister 0x01E0 1048 - Reserved 0x01E0 104C - Reserved 0x01E0 1050 -0x01E0 105C - Reserved 0x01E0 1060 - Reserved 0x01E0 1064 - Reserved 0x01E0 1068 -0x01E0 107C - Reservedforfutureuse 0x01E0 1080 RREVID VLYNQ Remote RevisionRegister 0x01E0 1084 RCTRL VLYNQ Remote ControlRegister 0x01E0 1088 RSTAT VLYNQ Remote StatusRegister 0x01E0 108C RINTPRI VLYNQ Remote InterruptPriorityVectorStatus/ClearRegister 0x01E0 1090 RINTSTATCLR VLYNQ Remote Unmasked InterruptStatus/ClearRegister 0x01E0 1094 RINTPENDSET VLYNQ Remote InterruptPending/SetRegister 0x01E0 1098 RINTPTR VLYNQ Remote InterruptPointerRegister 0x01E0 109C RXAM VLYNQ Remote TransmitAddressMap Register 0x01E0 10A0 RRAMS1 VLYNQ Remote ReceiveAddressMap Size1 Register 0x01E0 10A4 RRAMO1 VLYNQ Remote ReceiveAddressMap Offset1 Register 0x01E0 10A8 RRAMS2 VLYNQ Remote ReceiveAddressMap Size2 Register 0x01E0 10AC RRAMO2 VLYNQ Remote ReceiveAddressMap Offset2 Register 0x01E0 10B0 RRAMS3 VLYNQ Remote ReceiveAddressMap Size3 Register 0x01E0 10B4 RRAMO3 VLYNQ Remote ReceiveAddressMap Offset3 Register 0x01E0 10B8 RRAMS4 VLYNQ Remote ReceiveAddressMap Size4 Register 0x01E0 10BC RRAMO4 VLYNQ Remote ReceiveAddressMap Offset4 Register VLYNQ Remote ChipVersionRegister(valueson thedevice_idand0x01E0 10C0 RCHIPVER device_revpinsofremoteVLYNQ) 0x01E0 10C4 RAUTNGO VLYNQ Remote AutoNegotiationRegister 0x01E0 10C8 RMANNGO VLYNQ Remote Manual NegotiationRegister 0x01E0 10CC RNGOSTAT VLYNQ Remote NegotiationStatusRegister 0x01E0 10D0 -0x01E0 10DC - Reserved VLYNQ Remote InterruptVectors3 -0 (sourcedfromvlynq_int_i[3:0]portof0x01E0 10E0 RINTVEC0 remoteVLYNQ) VLYNQ Remote InterruptVectors7 -4 (sourcedfromvlynq_int_i[7:4]portof0x01E0 10E4 RINTVEC1 remoteVLYNQ) 0x01E0 10E8 -0x01E0 10FC - Reservedforfutureuse 0x01E0 1100 -0x01E0 1FFF - Reserved

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6.24.2 VLYNQ ElectricalData/Timing

Table6-110.Timing Requirements forVLYNQ_CLK forVLYNQ (seeFigure6-77) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(VCLK) Cycletime,VLYNQ_CLK 10 ns Pulseduration,VLYNQ_CLK high[CLK External] 3 ns 2 tw(VCLKH) Pulseduration,VLYNQ_CLK high[CLK Internal] 4 ns Pulseduration,VLYNQ_CLK low[CLK External] 3 ns 3 tw(VCLKL) Pulseduration,VLYNQ_CLK low[CLK Internal] 4 ns 4 tt(VCLK) Transitiontime,VLYNQ_CLK 3 ns Figure6-77.VLYNQ_CLK Timing forVLYNQ Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 219 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

VLYNQ_CLK VLYNQ_TXD[3:0] VLYNQ_RXD[3:0] 3 4 Data Data TMS320DM6446 SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-111.SwitchingCharacteristicsOver Recommended OperatingConditionsforTransmitData for theVLYNQ Module (seeFigure6-78) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX Delaytime,VLYNQ_CLK hightoVLYNQ_TXD[3:0] invalid 1 ns[SLOW Mode] 1 td(VCLKH-TXDI) Delaytime,VLYNQ_CLK hightoVLYNQ_ TXD[3:0]invalid 0.5 ns[FAST Mode] 2 td(VCLKH-TXDV) Delaytime,VLYNQ_CLK toVLYNQ_TXD[3:0] valid 9.75 ns Table6-112.Timing Requirements forReceive Data fortheVLYNQ Module (seeFigure6-78) A-513, -594, NO. UNIT-810 MIN MAX RTM disabled,RTM sample = 3 0.8 ns RTM enabled,RXD Flop= 0 2.2 ns RTM enabled,RXD Flop= 1 1.9 ns RTM enabled,RXD Flop= 2 1.4 ns Setuptime,VLYNQ_RXD[3:0] validbefore3 tsu(RXDV-VCLKH) RTM enabled,RXD Flop= 3 0.8 nsVLYNQ_CLK high RTM enabled,RXD Flop= 4 0.4 ns RTM enabled,RXD Flop= 5 0.1 ns RTM enabled,RXD Flop= 6 -0.2 ns RTM enabled,RXD Flop= 7 -0.4 ns RTM disabled,RTM sample = 3 2 ns RTM enabled,RXD Flop= 0 0.6 ns RTM enabled,RXD Flop= 1 1.0 ns RTM enabled,RXD Flop= 2 1.5 ns Holdtime,VLYNQ_RXD[3:0] validafter4 th(VCLKH-RXDV) RTM enabled,RXD Flop= 3 2.0 nsVLYNQ_CLK high RTM enabled,RXD Flop= 4 2.5 ns RTM enabled,RXD Flop= 5 3.0 ns RTM enabled,RXD Flop= 6 3.5 ns RTM enabled,RXD Flop= 7 4.0 ns Figure6-78.VLYNQ Transmit/ReceiveTiming

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www.ti.com SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 6.25 IEEE 1149.1JTAG The JTAG (1)interfaceisused forBSDL testingand emulationoftheDM6446 device. The DM6446 devicerequiresthatboth TRST and RESET be assertedupon power up to be properly initialized.While RESET initializesthe device,TRST initializesthe device'semulationlogic.Both resets arerequiredforproperoperation. WhilebothTRST and RESET need tobe assertedupon power up,onlyRESET needs tobe releasedfor thedevicetobootproperly.TRST may be assertedindefinitelyfornormaloperation,keepingtheJTAG portinterfaceand device'semulationlogicintheresetstate. TRST onlyneeds tobe releasedwhen itisnecessarytouse a JTAG controllertodebug thedeviceor exercisethedevice'sboundaryscan functionality. RESET must be releasedonlyin orderforboundary-scanJTAG to read the variantfieldof IDCODE correctly.Otherboundary-scaninstructionswork correctlyindependentofcurrentstateofRESET. For maximum reliability,DM6446 includesan internalpulldown(IPD)on the TRST pin to ensure that TRST willalways be assertedupon power up and the device'sinternalemulationlogicwillalways be properlyinitialized. JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay notdriveTRST highbutexpecttheuse ofa pullupresistoron TRST. When usingthistypeofJTAG controller,assertTRST toinitializethedeviceafterpowerup and externally driveTRST highbeforeattemptingany emulationorboundaryscan operations. Note:The sequencingofalltheJTAG signalsmust followtheIEEE.1149.1JTAG standard.

6.25.1 JTAG PeripheralRegisterDescription(s)– JTAG ID Register

Table6-113.JTAG ID Register HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Read-only.Provides32-bit0x01C4 0028 JTAGID JTAG IdentificationRegister JTAG ID ofthedevice. (1) IEEE Standard1149.1-1990Standard-Test-AccessPortand BoundaryScan Architecture. The JTAG ID registerisa read-onlyregisterthatidentifiestothecustomertheJTAG/Device ID.For the DM6446 device,theJTAG ID registerresidesataddresslocation0x01C4 0028.The registerhex valuefor DM6446 is:0x0B70 002F forsiliconrevisions1.3and earlier,and 0x1B70 002F forsiliconrevisions 2.1and later.For theactualregisterbitnames and theirassociatedbitfielddescriptions,see Figure6-79 and Table6-114. 31-28 27-12 11-1 0 VARIANT PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB(4-Bit)(A) R-000x R-1011 0111 0000 0000 R-0000 0010 111 R-1 LEGEND: R = Read, W = Write,n = valueatreset (A)For siliconrevisions1.3and earlier,VARIANT = 0000.For siliconrevisions2.1and later,VARIANT = 0001. Figure6-79.JTAG ID RegisterDescription-DM6446 RegisterValue -0xXB70 002F Copyright© 2005–2010,Texas InstrumentsIncorporated Peripheraland ElectricalSpecifications 221 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

SPRS283H –DECEMBER 2005–REVISED SEPTEMBER 2010 www.ti.com Table6-114.JTAG ID RegisterSelectionBitDescriptions BIT NAME DESCRIPTION Variant(4-Bit)value.DM6446 value:0000 forsiliconrevisions1.3and earlier,and 0001 for31:28 VARIANT siliconrevisions2.1and later. 27:12 PART NUMBER PartNumber (16-Bit)value.DM6446 value:1011 0111 0000 0000. 11-1 MANUFACTURER Manufacturer(11-Bit)value.DM6446 value:0000 0010 111. 0 LSB LSB. Thisbitisreadas a "1"forDM6446.

6.25.2 JTAG Test-PortElectricalData/Timing

Table6-115.Timing Requirements forJTAG TestPort(seeFigure6-80) A-513, -594, NO. UNIT-810 MIN MAX 1 tc(TCK) Cycletime,TCK 20 ns 2 tw(TCKH) Pulseduration,TCK high 8 ns 3 tw(TCKL) Pulseduration,TCK low 8 ns 4 tc(RTCK) Cycletime,RTCK 20 ns 5 tw(RTCKH) Pulseduration,RTCK high 10 ns 6 tw(RTCKL) Pulseduration,RTCK low 10 ns 7 tsu(TDIV-RTCKH) Setuptime,TDI/TMS validbeforeRTCK high 10 ns 8 th(RTCKH-TDIV) Holdtime,TDI/TMS validafterRTCK high 1 ns Table6-116.SwitchingCharacteristicsOver Recommended OperatingConditionsforJTAG TestPort (seeFigure6-80) A-513, -594, NO. PARAMETER UNIT-810 MIN MAX 9 td(RTCKL-TDOV) Delaytime,RTCK lowtoTDO valid 15 ns Figure6-80.JTAG Test-PortTiming

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7 MechanicalPackaging and OrderableInformation

The followingtable(s)show the thermalresistancecharacteristicsfor the PBGA –ZWT mechanical package.

7.1 Thermal Data forZWT

Table7-1.Thermal ResistanceCharacteristics(PBGA Package) [ZWT] NO. °C/W (1) AIR FLOW (m/s)(2) 1 R ΘJC Junction-to-case 6.54 N/A 2 R ΘJB Junction-to-board 15.62 N/A 3 29.75 0.00 4 26.78 1.0 R ΘJA Junction-to-freeair 5 26.20 2.00 6 25.80 3.00 7 0.11 0.00 8 0.15 1.0 PsiJT Junction-to-packagetop 9 0.16 2.00 10 0.16 3.00 11 14.79 0.00 12 14.66 1.0 PsiJB Junction-to-board 13 14.66 2.00 14 14.66 3.00 (1) These measurements were conductedina JEDEC defined1S2P systemand willchange based on environmentas wellas application. Formore information,see theseEIA/JEDEC standards– EIA/JESD51-2,IntegratedCircuitsThermalTestMethod Environment Conditions-NaturalConvection(StillAir)and JESD51-7,HighEffectiveThermalConductivityTestBoard forLeaded SurfaceMount Packages. (2) m/s = meterspersecond

7.2 Packaging Information

The followingpackaging informationand addendum reflectthe most currentdata availableforthe designateddevice(s).Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument. Copyright© 2005–2010,Texas InstrumentsIncorporated MechanicalPackagingand OrderableInformation 223 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM6446

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DM6446ANB6C2127VC NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446AZWT TMS320 DAVINCI DM6446AZWTKEDACOM NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446AZWT TMS320 DAVINCI DM6446GB6C0121MV NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446AZWT TMS320 DAVINCI TMS320DM6446AZWT NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446AZWT TMS320 DAVINCI TMS320DM6446AZWTA NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR -40 to 105 DM6446AZWTA TMS320 DAVINCI TMS320DM6446BZWT NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446BZWT TMS320 DAVINCI TMS320DM6446BZWT8 NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446BZWT8 TMS320 189 DAVINCI TMS320DM6446BZWTA NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR -40 to 105 DM6446BZWTA TMS320 DAVINCI TMSDM6446AZWT-COM NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446AZWT TMS320 DAVINCI TNETV6446AINZWT NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446AZWT TMS320 DAVINCI TNETV6446AINZWT8 NRND NFBGA ZWT 361 90 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR 0 to 85 DM6446BZWT8 TMS320 189 DAVINCI

www.ti.com 15-Apr-2017 Addendum-Page 2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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