DM365ZCES

TMS320DM365_17 TI1 | Alldatasheet

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 TMS320DM365 DigitalMediaSystem-on-Chip(DMSoC) Check forSamples: TMS320DM365

1 TMS320 DM365 DigitalMedia System-on-Chip (DMSoC)

1.1 Features

– Support for32-Bitand 16-Bit• Highlights (Thumb ® Mode) InstructionSets– High-PerformanceDigitalMedia – DSP InstructionExtensionsand SingleCycleSystem-on-Chip (DMSoC) MAC– Up to300-MHz ARM926EJ-S Clock Rate – ARM ® Jazelle® Technology– Two Video Image Co-processors – Embedded ICE-RT Logic forReal-Time(HDVICP, MJCP) Engines Debug– Supports a Range ofEncode, Decode, and

• ARM9 Memory ArchitectureVideo QualityOperations – 16K-Byte InstructionCache– Video ProcessingSubsystem – 8K-Byte Data Cache• HW Face DetectEngine – 32K-Byte RAM• ResizeEngine from 1/16xto8x – 16K-Byte ROM• 16-BitParallelAFE (AnalogFront-End) InterfaceUp to120 MHz – LittleEndian
• 4:2:2(8-/16-bit)Interface • Two Video Image Co-processors (HDVICP, MJCP) Engines• 8-/16-bitYCC and Up to24-BitRGB888 DigitalOutput – Support a Range ofEncode and Decode Operations,up toD1 on 216-MHz deviceand• 3 DACs forHD Analog Video Output up to720p on the270-and 300-MHz parts• Hardware On-Screen Display(OSD) – H.264,MPEG4, MPEG2, MJPEG, JPEG,– Capable of720p 30fpsH.264 video WMV9/VC1processing
• Video ProcessingSubsystemNote:216-MHz isonlycapableofD1 processing – FrontEnd Provides: – PeripheralsincludeEMAC, USB 2.0OTG, • HW Face DetectEngine DDR2/NAND, 5 SPIs,2 UARTs, 2 • Hardware IPIPEforReal-TimeImage MMC/SD/SDIO, Key Scan Processing – 8 DifferentBoot Modes and Configurable – ResizeEngine Power-Saving Modes – ResizeImages From 1/16xto8x – Pin-to-pinand softwarecompatiblewith – SeparateHorizontal/VerticalDM368 Control – Extended temperature(-40ºC – 85ºC) – Two Simultaneous Output Pathsavailablefor300-MHz device • IPIPEInterface(IPIPEIF)– 3.3-Vand 1.8-VI/O,1.2-V/1.35-VCore • Image Sensor Interface(ISIF)and CMOS– 338-PinBallGridArrayat65nm Process Imager InterfaceTechnology • 16-BitParallelAFE (AnalogFrontEnd)• High-PerformanceDigitalMedia InterfaceUp to120 MHzSystem-on-Chip (DMSoC) • GluelessInterfacetoCommon Video– 216-,270-,300-MHz ARM926EJ-S Clock Rate Decoders – FullySoftware-CompatibleWith ARM9 ™ • BT.601/BT.656/BT.1120DigitalYCbCr – Extended temperatureavailablefor300-MHz 4:2:2(8-/16-Bit)Interface device • Histogram Module
• ARM926EJ-S ™ Core • Lens distortioncorrectionmodule (LDC) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas of publicationdate. Copyright© 2009–2011,Texas InstrumentsIncorporatedProducts conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

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• Hardware 3A statisticscollectionmodule • Four 64-BitGeneral-PurposeTimers (each (H3A) configurableas two 32-bittimers) – Back End Provides: • One 64-BitWatch Dog Timer
• Hardware On-Screen Display(OSD) • Two UARTs (One fastUART withRTS and CTS Flow Control)• Composite NTSC/PAL videoencoder output • FiveSerialPortInterfaces(SPI)each withtwo Chip-Selects• 8-/16-bitYCC and Up to24-BitRGB888 DigitalOutput • One Master/SlaveInter-IntegratedCircuit (I2C) Bus ™• 3 DACs forHD Analog Video Output
• One Multi-ChannelBufferedSerialPort• LCD Controller (McBSP)• BT.601/BT.656DigitalYCbCr 4:2:2 – I2S(8-/16-Bit)Interface – AC97 Audio Codec Interface• Analog-to-DigitalConvertor(ADC) – S/PDIF viaSoftware• Power Management and Real Time Clock Subsystem (PRTCSS) – Standard Voice Codec Interface(AIC12) – Real Time Clock – SPI Protocol(MasterMode Only)
• 16-BitHost-PortInterface(HPI) – DirectInterfacetoT1/E1 Framers
• 10/100Mb/s EthernetMedia Access Controller – Time DivisionMultiplexedMode (TDM) (EMAC) -DigitalMedia – 128 Channel Mode – IEEE 802.3Compliant • Four Pulse Width Modulator(PWM) Outputs – Supports Media IndependentInterface(MII) • Four RTO (RealTime Out)Outputs – Management Data I/O(MDIO) Module • Up to104 General-PurposeI/O(GPIO)Pins
• Key Scan (MultiplexedwithOther Device Functions)
• Voice Codec • Boot Modes
• ExternalMemory Interfaces(EMIFs) – On-Chip ARM ROM Bootloader(RBL) toBoot From NAND Flash,MMC/SD, UART, USB,– DDR2 and mDDR SDRAM 16-bitwide EMIF SPI,EMAC, or HPIWith 256 MByte Address Space (1.8-VI/O) – AEMIF (NOR and OneNAND)– Asynchronous16-/8-bitWide EMIF (AEMIF)
• ConfigurablePower-Saving Modes• FlashMemory Interfaces
• Crystalor ExternalClock Input(typically– NAND (8-/16-bitWide Data) 19.2MHz, 24 MHz, 27 MHz or 36 MHz)– 16 MB NOR Flash,SRAM
• FlexiblePLL Clock Generators– OneNAND(16-bit Wide Data)
• Debug InterfaceSupport• FlashCard Interfaces – IEEE-1149.1(JTAG ™)– Two MultimediaCard (MMC) /Secure Digital Boundary-Scan-Compatible(SD/SDIO) – ETB (Embedded Trace Buffer)with4K-Bytes– SmartMedia/xD Trace Buffermemory• Enhanced Direct-Memory-Access(EDMA) – Device RevisionID Readable by ARMController(64IndependentChannels)
• 338-PinBallGridArray(BGA) Package• USB PortwithIntegrated2.0High-Speed PHY (ZCE Suffix),0.65-mm BallPitchthatSupports
• 65nm Process Technology– USB 2.0High-Speed Device
• Community Resourcessupportingone externaldevice) – TIE2E Community– USB On The Go (HS-USB OTG) – TIEmbedded Processors Wiki

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1.2 Description

Developerscan now deliverpixel-perfectimages atup to720p H.264 at30fpsintheirdigitalvideodesigns withoutconcernsofvideoformatsupport,constrainednetworkbandwidth,limitedsystem storagecapacity or costwiththe new TMS320DM365 digitalmedia processorbased on DaVincitechnologyfrom Texas InstrumentsIncorporated(TI).Withmulti-formatHD video,theDM365 alsofeaturesa suiteofperipherals savingdeveloperson systemcosts. ThisARM9-based DM365 deviceoffersspeeds up to300 MHz and supportsproduction-qualifiedH.264, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providingcustomerswiththeflexibilitytoselectthe rightvideo codec fortheirapplication.These codecs are drivenfrom video acceleratorsoffloading compressionneeds fromtheARM coreso thatdeveloperscan utilizethemost performancefromtheARM fortheirapplication.Video surveillancedesignersachievegreatercompressionefficiencyprovidingmore storagewithoutstrainingthe network bandwidth.Developersof media playbackand camera-driven applications,such as videodoorbells,digitalsignage,digitalvideorecorders,portablemedia playersand more can ensure interoperabilityas wellas productscalabilityby takingadvantageof the fullsuiteof codecssupportedon theDM365. Along withmulti-formatHD video,the DM365 enablesseamless interfaceto most additionalexternal devicesrequiredforvideoapplications.The image sensorinterfaceisflexibleenough to supportCCD, CMOS, and variousotherinterfacessuch as BT.656,BT1120. The DM365 alsooffersa highlevelof integrationwith HD displaysupportincluding,3 built-in10-bitHD Analog Video Digitalto Analog Converters(DACs),DDR2/mDDR, EthernetMAC, USB 2.0,integratedaudio,Host PortInterface(HPI), AnalogtoDigitalConverter,and many more featuressavingdeveloperson overallsystemcostsas wellas realestateon theircircuitboardsallowingfora slimmer,sleekerdesign. Copyright© 2009–2011,Texas InstrumentsIncorporated TMS320 DM365 DigitalMedia System-on-Chip(DMSoC) 3 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Lens□DistFace□Det IPIPE ResizerISIF Video□FE 3Ch DAC Video Encoder OSD Video□BE Buffer SDTV/HDTV Analog□Video Digital RGB/YUV Camera AFE VPSS DDR2 ControllerEDMA NAND/SM Memory I/F HPI 16-Bit DDR2/ mDDR NAND/ OneNAND/ NOR□Flash, SmartMedia/ xD Host□CPU 16□Bit 8/16□Bit 16□Bit USB2.0□HS□w/OTG MMC/SD□(x2) SPI□(x5) UART□(x2) I2C Timer□(x4-64b) WDT□(x1-64b) GIO PWM□(x4) RTO McBSP EMAC ADC Key□Scan Voice□Codec System I/O Interface I-Cache 16□KB D-Cache 8□KB RAM 32□KB ROM 16□KB ARM926EJ-S ARM□INTC PRTCSSCLOCK□Ctrl PLL JTAG I/F HDVICP MJCP DMA/Data□and□Configuration□Bus 19.2□MHz,□24□MHz 27□MHz□or□36□MHz 32.768 kHz PMIC/ SW TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

1.3 FunctionalBlock Diagram

Figure1-1shows thefunctionalblockdiagramoftheTMS320 DM365 device. Figure1-1.FunctionalBlock Diagram

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1 TMS320 DM365 DigitalMedia System-on-Chip 6 PeripheralInformationand Electrical

6.14 UniversalAsynchronousReceiver/Transmitter

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SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. highlightsthe technicalchanges made to the SPRS457D device-specificdata sheet to make itan SPRS457 E revision. RevisionE Updates See Additions/Changes/Deletions Global Removed sentencestating"micro-viasarenotrequired." Figure2-2 CorrectedJ5 pinname. Table2-5 Changed TYPE ofVREF pinfromA I/OtoA I. Table2-5 Changed TYPE ofVCOM pinfromAItoAO. Section3.2.1 Added 24 MHz referenceclocktoARM ROM Boot-UART mode. Table6-21 Updated firsttablenote. Table6-22 Updated second tablenote. Table6-26 Updated tableand added tablenote.

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2 Device Overview

2.1 Device Characteristics

Table 2-1 providesan overviewof the DMSoC. The tableshows significantfeaturesof the device, includingtheperipherals,capacityofon-chipRAM, ARM operatingfrequency,thepackage typewithpin count,etc. Table2-1.CharacteristicsoftheProcessor HARDWARE FEATURES DEVICE DDR2 /mDDR Memory Controller DDR2 /mDDR (16-bitbus width) Asynchronous(8/16-bitbus width)RAM,AsynchronousEMIF (AEMIF) Flash(NOR, NAND, OneNAND) Two MMC/SDFlashCard Interfaces One SmartMedia/xD 64 independentDMA channelsEDMA EightQDMA channels Four64-BitGeneralPurpose(each Timers configurableas two separate32-bittimers) One 64-BitWatch Dog UART Two (onewithRTS and CTS flowcontrol) SPI Five(eachsupportstwo slavedevices) Peripherals I2C One (Master/Slave) Not allperipheralspinsare 10/100EthernetMAC withManagement Data I/O Oneavailableatthesame time(For Multi-ChannelBufferedSerialPort[McBSP] One McBSPmore detail,see theDevice Configurationsection). Power Management and RealTime ClockSubsystem RTC (32.768kHz),GPIO(PRTCSS) Key Scan 4 x 4 Matrix,5 x 3 Matrix VoiceCodec One Analog-to-DigitalConverter(ADC) 6-channel,10-bitInterface General-PurposeInput/OutputPort Up to104 Pulsewidthmodulator(PWM) Fouroutputs One Input(VPFE)ConfigurableVideoPorts One Output(VPBE) HighSpeed Device USB 2.0 HighSpeed Host On The Go (HS-USB-OTG) WirelessInterfaces ThroughSDIO RTO FourChannels ARM On-ChipCPU Memory Organization 16-KB I-cache,8-KB D-cache,32-KB RAM, 16-KB ROM See Section6.27.1,JTAG RegisterJTAG BSDL_ID JTAGID register(addresslocation:0x01C4 0028) Description(s) CPU Frequency(Maximum) MHz ARM: 216-MHz, 270-MHz, 300-MHz Core (V) 1.2V or1.35V Voltage I/O(V) 3.3V,1.8V Referencefrequencyoptions 19.2MHz, 24 MHz, 27 MHz, 36 MHzPLL Options ConfigurablePLL controller PLL bypass,programmablePLL ProcessTechnology 65 nm Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 7 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-1.CharacteristicsoftheProcessor (continued) HARDWARE FEATURES DEVICE ProductPreview(PP), ProductStatus(1) Advance Information(AI), PD orProductionData (PD) (1) PRODUCTION DATA informationiscurrentas ofpublicationdate.ProductsconformtospecificationsperthetermsofTexas Instrumentsstandardwarranty.Productionprocessingdoes notnecessarilyincludetestingofallparameters.

2.2 Device Compatibility

The ARM926EJ-S RISC CPU iscompatiblewithotherARM9 CPUs fromARM Holdingsplc.

2.3 ARM Subsystem Overview

The ARM Subsystem containscomponents requiredtoprovidetheARM926EJ-S (ARM) mastercontrolof the overalldevicesystem,includingthe components of the ARM Subsystem,the peripherals,and the externalmemories. The ARM isresponsibleforhandlingsystem functionssuch as system-levelinitialization,configuration, user interface,user command execution,connectivityfunctions,interfaceand controlof the subsystem, etc.The ARM ismasterand performsthesefunctionsbecause ithas a largeprogram memory space and fastcontextswitchingcapability,and isthus suitableforcomplex,multi-tasking,and general-purpose controltasks.

2.3.1 Components oftheARM Subsystem

The ARM Subsystem consistsofthefollowingcomponents:

• ARM926EJ-S RISC processor,including: – coprocessor15 (CP15) – MMU – 16KB Instructioncache – 8KB Data cache – WriteBuffer – Java accelerator
• ARM InternalMemories – 32KB InternalRAM (32-bitwideaccess) – 16KB InternalROM (ARM bootloaderfornon-AEMIF bootmodes)
• Embedded TraceModule and Embedded TraceBuffer(ETM/ETB)
• System ControlPeripherals – ARM InterruptController – PLL Controller – Power and SleepController – System ControlModule The ARM alsomanages/controlsallthedeviceperipherals. Figure2-1shows thefunctionalblockdiagramoftheARM Subsystem.

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16K□I$ 8K□D$ MMU CP15 Arbiter Arbiter I-AHB D-AHB Master IF DMA Bus I-TCM D-TCM 16K RAM0RAM1 16K ROM 16K Arbiter Slave IF Master□IF CFG□Bus ARM Interrupt Controller (AINTC) Control System PLLC2 PLLC1 (PSC) Controller Sleep Power Peripherals... TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure2-1.ARM Subsystem Block Diagram

2.3.2 ARM926EJ-S RISC CPU

The ARM Subsystem integratestheARM926EJ-S processor.The ARM926EJ-S processorisa member of ARM9 familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplications where fullmemory management, highperformance,low diesize,and low power are allimportant.The ARM926EJ-S processorsupportsthe32-bitARM and 16 bitTHUMB instructionsets,enablingtheuserto tradeoffbetween high performanceand high code density.Specifically,the ARM926EJ-S processor supportstheARMv5TEJ instructionset,whichincludesfeaturesforefficientexecutionofJava bytecodes, providingJava performancesimilarto JustinTime (JIT)Java interpreter,but withoutassociatedcode overhead. The ARM926EJ-S processorsupportsthe ARM debug architectureand includeslogicto assistinboth hardware and softwaredebug. The ARM926EJ-S processorhas a Harvardarchitectureand providesa completehighperformancesubsystem,including:

• ARM926EJ -S integercore
• CP15 systemcontrolcoprocessor
• Memory Management Unit(MMU)
• Separateinstructionand dataCaches
• Writebuffer
• Separateinstructionand dataTightly-CoupledMemories (TCMs) [internalRAM] interfaces
• Separateinstructionand dataAHB bus interfaces
• Embedded TraceModule and Embedded TraceBuffer(ETM/ETB) For more completedetailson theARM9, refertotheARM926EJ-S TechnicalReferenceManual,available athttp://www.arm.com Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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2.3.3 CP15

The ARM926EJ-S system controlcoprocessor(CP15) isused to configureand controlinstructionand data caches,Tightly-CoupledMemories (TCMs), Memory Management Unit(MMU), and otherARM subsystem functions.The CP15 registersare programmed usingthe MRC and MCR ARM instructions, when theARM ina privilegedmode such as supervisororsystemmode.

2.3.4 MMU

The ARM926EJ-S MMU providesvirtualmemory featuresrequiredby operatingsystems such as Linux, WindowCE, ultron,ThreadX,etc.A singlesetoftwo levelpage tablesstoredinmain memory isused to controlthe address translation,permissionchecks and memory regionattributesforboth data and instructionaccesses.The MMU uses a singleunifiedTranslationLookasideBuffer(TLB) to cache the informationheldinthepage tables.The MMU featuresare:

• StandardARM architecturev4 and v5 MMU mapping sizes,domains and accessprotectionscheme.
• Mapping sizesare: – 1MB (sections) – 64KB (largepages) – 4KB (smallpages) – 1KB (tinypages)
• Access permissionsforlargepages and smallpages can be specifiedseparatelyforeach quarterof thepage (subpagepermissions)
• Hardware page tablewalks
• InvalidateentireTLB, usingCP15 register8
• InvalidateTLB entry,selectedby MVA, usingCP15 register8
• Lockdown ofTLB entries,usingCP15 register10

2.3.5 Caches and WriteBuffer

The sizeoftheInstructionCache is16KB, Data cache is8KB. Additionally,theCaches have thefollowing features:

• Virtualindex,virtualtag,and addressedusingtheModifiedVirtualAddress(MVA)
• Four-waysetassociative,witha cache linelengthofeightwords perline(32-bytesperline)and with two dirtybitsintheDcache
• Dcache supportswrite-throughand write-back(orcopy back)cache operation,selectedby memory regionusingtheC and B bitsintheMMU translationtables.
• Critical-wordfirstcache refilling
• Cache lockdownregistersenablecontroloverwhich cache ways are used forallocationon a linefill, providinga mechanism forbothlockdown,and controllingcache corruption
• Dcache storesthePhysicalAddress TAG (PA TAG) correspondingtoeach Dcache entryintheTAG RAM foruse duringthe cache linewrite-backs,inadditionto the VirtualAddress TAG storedinthe TAG RAM. Thismeans thattheMMU isnotinvolvedinDcache write-backoperations,removingthe possibilityofTLB missesrelatedtothewrite-backaddress.
• Cache maintenanceoperationsprovideefficientinvalidationof,theentireDcache orIcache,regionsof theDcache orIcache,and regionsofvirtualmemory. The writebufferisused forallwritestoa noncachablebufferableregion,write-throughregionand write misses toa write-backregion.A separatebufferisincorporatedintheDcache forholdingwrite-backfor cache lineevictionsorcleaningofdirtycache lines.The main writebufferhas 16-worddatabufferand a four-addressbuffer.The Dcache write-backhas eightdataword entriesand a singleaddressentry.

2.3.6 TightlyCoupled Memory (TCM)

ARM internalRAM isprovidedforstoringreal-timeand performance-criticalcode/dataand theInterrupt

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Vectortable.ARM internalROM bootmodes includeNAND, MMC/SD, UART, USB, SPI,EMAC, and HPI. The RAM and ROM memories interfacedto the ARM926EJ-S viathe tightlycoupledmemory interface thatprovidesforseparateinstructionand data bus connections.Since the ARM TCM does not allow instructionson the D-TCM bus or data on the I-TCM bus,an arbiterisincludedso thatboth data and instructionscan be storedintheinternalRAM/ROM. The arbiteralsoallowsaccessestotheRAM/ROM from extra-ARM sources(e.g.,EDMA or othermasters).The ARM926EJ-S has built-inDMA supportfor directaccessestotheARM internalmemory froma non-ARM master.Because ofthetime-criticalnature of the TCM linkto the ARM internalmemory, allaccesses from non-ARM devicesare treatedas DMA transfers. Instructionand Data accesses are differentiatedviaaccessingdifferentmemory map regions,withthe instructionregionfrom 0x0000 through0x7FFF and data from 0x10000 through0x17FFF. Placingthe instructionregionat0x0000 isnecessarytoallowtheARM InterruptVectortabletobe placedat0x0000, as requiredby the ARM architecture.The internal32-KB RAM issplitintotwo physicalbanks of 16KB each,which allowssimultaneousinstructionand dataaccessestobe accomplishedifthecode and data areinseparatebanks.

2.3.7 Advanced High-performanceBus (AHB)

The ARM Subsystem uses theAHB portoftheARM926EJ-S toconnecttheARM totheconfigurationbus and theexternalmemories.Arbitersare employed toarbitrateaccess totheseparateD-AHB and I-AHB by theconfigurationbus and theexternalmemories bus.

2.3.8 Embedded Trace Macrocell(ETM) and Embedded Trace Buffer(ETB)

To supportreal-timetrace,theARM926EJ-S processorprovidesan interfacetoenableconnectionofan Embedded Trace Macrocell(ETM). The ARM926ES-J Subsystem alsoincludesthe Embedded Trace Buffer(ETB).The ETM consistsoftwo parts:

• TracePortprovidesreal-timetracecapabilityfortheARM9.
• Triggeringfacilitiesprovidetriggerresources,which includeaddressand data comparators,counter, and sequencers. The devicetraceportisnotpinnedoutand isinsteadonlyconnectedtotheEmbedded TraceBuffer.The ETB has a 4KB buffermemory. ETB enableddebug toolsarerequiredtoread/interpretthecapturedtrace data.

2.3.9 ARM Memory Mapping

The ARM memory map isshown inTable2-3 and Table2-4.Thissectiondescribesthememories and interfaceswithintheARM's memory map.

2.3.9.1 ARM InternalMemories

The ARM has accesstothefollowingARM internalmemories:

• 32KB ARM InternalRAM on TCM interface,logicallyseparatedintotwo 16KB pages to allow simultaneousaccesson any givencycleifthereareseparateaccessesforcode (I-TCMbus)and data (D-TCM) tothedifferentmemory regions.
• 16KB ARM InternalROM

2.3.9.2 ExternalMemories

The ARM has accesstothefollowingExternalmemories:

• DDR2 /mDDR SynchronousDRAM
• AsynchronousEMIF /OneNAND /NOR
• NAND Flash Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 11 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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• Flashcarddevices: – MMC/SD – xD – SmartMedia

2.3.10 Peripherals

The ARM has accesstoalloftheperipheralson thedevice.

2.3.11 ARM InterruptController(AINTC)

The deviceARM InterruptController(AINTC)has thefollowingfeatures:

• Supportsup to64 interruptchannels(16externalchannels)
• Interruptmask foreach channel
• Each interruptchannelcan be mapped toa FastInterruptRequest (FIQ)or toan InterruptRequest (IRQ)typeofinterrupt.
• Hardware prioritizationofsimultaneousinterrupts
• Configurableinterruptpriority(2levelsofFIQ and 6 levelsofIRQ)
• Configurableinterruptentrytable(FIQand IRQ prioritytableentry)toreduceinterruptprocessingtime The ARM core supportstwo interrupttypes:FIQ and IRQ. See the ARM926EJ-S TechnicalReference Manual fordetailedinformationabout the ARM ’s FIQ and IRQ interrupts.Each interruptchannel is mappable toan FIQ or toan IRQ typeofinterrupt,and each channelcan be enabledor disabled.The INTC supportsuser-configurableinterrupt-priorityand interruptentryaddresses.Entryaddressesminimize thetimespentjumpingtointerruptserviceroutines(ISRs).When an interruptoccurs,thecorresponding highestpriorityISR’s addressisstoredintheINTC’s ENTRY register.The IRQ orFIQ interruptroutinecan read theENTRY registerand jump tothecorrespondingISR directly.Thus,theARM does notrequirea softwaredispatchertodeterminetheassertedinterrupt.

2.4 System ControlModule

The system controlmodule isa system-levelmodule containingstatusand top-levelcontrollogicrequired by thedevice.The system controlmodule consistsofa miscellaneoussetofstatusand controlregisters, accessibleby theARM and supportingallofthefollowingsystemfeaturesand operations:

• Deviceidentification
• Deviceconfiguration – Pinmultiplexingcontrol – Devicebootconfigurationstatus
• ARM interruptand EDMA eventmultiplexingcontrol
• Specialperipheralstatusand control – Timer64 – USB PHY control – VPSS clockand videoDAC controland status – DDR VTP control – Clockoutcircuitry – GIO de-bouncecontrol
• Power management – Deep sleep
• BandwidthManagement – Bus masterDMA prioritycontrol For more informationon theSystem ControlModule refertoSection3,DeviceConfigurationsand the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

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2.5 Power Management

The device is designed for minimal power consumption.There are two components to power consumption:activepower and leakagepower.Activepower isthepower consumed toperformwork and scaleswithclockfrequencyand the amount of computationsbeing performed.Activepower can be reducedby controllingtheclocksinsuch a way as toeitheroperateata clocksettingjusthighenough to completethe requiredoperationin the requiredtime-lineor to run at a clocksettinguntilthe work is completeand then drasticallycutthe clocks(e.g.to PLL Bypass mode) untiladditionalwork must be performed.Leakage power is due to staticcurrentleakage and occurs regardlessof the clockrate. Leakage,or standbypower,isunavoidablewhilepower isappliedand scalesroughlywiththeoperating junctiontemperatures.Leakage power can onlybe avoidedby removingpower completelyfroma device or subsystem.The deviceincludesseveralpower management modes which are brieflydescribedin Table 2-2. See the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literaturenumber SPRUFG5 )formore informationon power management. Table2-2.Power Management Conditions GIO, SPI,POWER MGMT. OTHER DDRCORE OSC. PLL ARM926 UART, PWM,APPLICATION PRTCSS PERIPH. CLOCK/ DESCRIPTIONPOWER POWER CNTRLR. CLOCK I2C TIMERSCENARIO CLOCKS MODECLOCKS CLOCKS Thiscondition consumes thelowestPRTCSS Active Off Off Off Off Off Off Off Off possiblepower,except forthePRTCSS. Thismode consumes thesecond lowestBypass Suspend / possiblepower,exceptModeDeep SleepMode (1) Active On Off Off Off Off Off "Self- forPRTCSS and core(not Refresh" power,where onlytheActive) deep sleepcircuitison inthismode. Thisconditionkeeps theminimum possible modules powered-on Suspend / inordertowake up theBypassStandby Active On On Off On Off Off "Self- device.ClocksareMode Refresh" suspended exceptfor GIO (interrupts), UART, and I2C (in slavemode). Most clocksare suspended,exceptfor ARM, GIO, UART, SPI,I2C,PWM, andSuspend /Low-power Bypass timers.SinceARM willActive On On On On /Off On /Off On /Off "Self-(PLL Bypass Mode) Mode nothave accesstoRefresh" DDR, itsinternal Cache willbe either frozenornot accessed. The device,including Nominal systemPLLs,areon.System Running Active On On PLL Mode On On /Off On /Off On /Off Clock/ Thiscondition(PLL Mode) Operation conservestheleast amount ofpower. (1) Formore details,see TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ) Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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2.6 Memory Map Summary

Table2-3shows thememory map addressrangesofthedevice.Table2-4depictstheexpanded map of theConfigurationSpace (0x01C0 0000 through0x01FF FFFF).The devicehas multipleon-chipmemories associatedwithitsprocessorand varioussubsystems.To helpsimplifysoftwaredevelopmenta unified memory map isused where possibleto maintaina consistentview of deviceresourcesacrossallbus masters.The bus masters are the ARM, EDMA, EMAC, USB, HPI, MJCP, HDVICP and VPSS. The MasterPeripheralsareEMAC, USB, and HPI.PleaserefertoSection4 formore details. Table2-3.Memory Map StartAddress End Address Size(Bytes) ARM EDMA Master Periph VPSS Mem Map Mem Map Mem Map Mem Map 0x0000 0000 0x0000 3FFF 16K ARM RAM0 (Instruction) 0x0000 4000 0x0000 7FFF 16K ARM RAM1 Reserved Reserved(Instruction) 0x0000 8000 0x0000 BFFF 16K ARM ROM (Instruction) 0x0000 C000 0x0000 FFFF 16K Reserved 0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1 0x0001 8000 0x0001 BFFF 16K ARM ROM ARM ROM ARM ROM 0x0001 C000 0x000F FFFF 912K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x01C0 0000 0x01FF FFFF 4M CFG Bus CFG Bus CFG Bus Peripherals Peripherals Peripherals 0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data) 0x0A00 0000 0x11EF FFFF 127M -16K Reserved Reserved 0x11F0 0000 0x11F1 FFFF 128K MJCP DMA Port MJCP DMA Port 0x11F2 0000 0x11FF FFFF 896K Reserved Reserved 0x1200 0000 0x1207 FFFF 512K HDVICP DMA Port1 HDVICP DMA Port1 HDVICP DMA Port1 0x1208 0000 0x120F FFFF 512K Reserved HDVICP DMA Port2 Reserved 0x1210 0000 0x1217 FFFF 512K HDVICP DMA Port3 0x1218 0000 0x1FFF FFFF 222.5M Reserved 0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control Regs Regs 0x2000 8000 0x41FF FFFF 544M-32K 0x4200 0000 0x49FF FFFF 128M Reserved Reserved 0x4A00 0000 0x7FFF FFFF 864M 0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-4.ARM ConfigurationBus Access toPeripherals Address Region Start End Size EDMA CC 0x01C0 0000 0x01C0 FFFF 64K EDMA TC0 0x01C1 0000 0x01C1 03FF 1K EDMA TC1 0x01C1 0400 0x01C1 07FF 1K EDMA TC2 0x01C1 0800 0x01C1 0BFF 1K EDMA TC3 0x01C1 0C00 0x01C1 0FFF 1K Reserved 0x01C1 1000 0x01C1 FFFF 60 K UART0 0x01C2 0000 0x01C2 03FF 1K Reserved 0x01C2 0400 0x01 20 7FFF 1K Timer3 0x01C2 0800 0x01C2 0BFF 1K Real-timeout 0x01C2 0C00 0x01C2 0FFF 1K I2C 0x01C2 1000 0x01C2 13FF 1K Timer0 0x01C2 1400 0x01C2 17FF 1K Timer1 0x01C2 1800 0x01C2 1BFF 1K Timer2 0x01C2 1C00 0x01C2 1FFF 1K PWM0 0x01C2 2000 0x01C2 23FF 1K PWM1 0x01C2 2400 0x01C2 27FF 1K PWM2 0x01C2 2800 0x01C2 2BFF 1K PWM3 0x01C2 2C00 0x01C2 2FFF 1K SPI4 0x01C2 3000 0x01C2 37FF 2K Timer4 0x01C2 3800 0x01C2 3BFF 1K ADCIF 0x01C2 3C00 0x01C2 3FFF 1K Reserved 0x01C2 4000 0x01C3 4FFF 112K System Module 0x01C4 0000 0x01C4 07FF 2K PLL Controller1 0x01C4 0800 0x01C4 0BFF 1K PLL Controller2 0x01C4 0C00 0x01C4 0FFF 1K Power/SleepController 0x01C4 1000 0x01C4 1FFF 4K Reserved 0x01C4 2000 0x01C4 7FFF 24K ARM InterruptController 0x01C4 8000 0x01C4 83FF 1K Reserved 0x01 C4 8400 0x01C63FFF 111K USB OTG 2.0Regs /RAM 0x01C6 4000 0x01C6 5FFF 8K SPI0 0x01C6 6000 0x01C6 67FF 2K SPI1 0x01C6 6800 0x01C6 6FFF 2K GPIO 0x01C6 7000 0x01C6 77FF 2K SPI2 0x01C6 7800 0x01C6 FFFF 2K SPI3 0x01C6 8000 0x01C6 87FF 2K Reserved 0x01C6 8800 0x01C6 87FF 2K PRTCSS InterfaceRegisters 0x01C6 9000 0x01C6 93FF 1K KEYSCAN 0x01C6 9400 0x01C6 97FF 1K HPI 0x01C6 9800 0x01C6 9FFF 2K Reserved 0x01C6 A000 0x01C6 FFFF 24K VPSS Subsystem ISP System ConfigurationRegisters 0x01C7 0000 0x01C7 00FF 256 VPBE ClockControlRegister 0x01C7 0200 0x01C7 02FF 256 ResizerRegisters 0x01C7 0400 0x01C7 07FF 1K IPIPERegisters 0x01C7 0800 0x01C7 0FFF 2K ISIFRegisters 0x01C7 1000 0x01C7 11FF 512 Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-4.ARM ConfigurationBus Access toPeripherals(continued) Address IPIPEIFRegisters 0x01C7 1200 0x01C7 12FF 768 H3A Registers 0x01C7 1400 0x01C7 14FF 256 Reserved 0x01C7 1600 0x01C7 17FF 512 FDIF Registers 0x01C7 1800 0x01C7 1BFF 1K OSD Registers 0x01C7 1C00 0x01C7 1CFF 256 Reserved 0x01C7 1D00 0x01C7 1DFF 256 VENC Registers 0x01C7 1E00 0x01C7 1FFF 512 Reserved 0x01C7 2000 0x01CF FFFF 568K Multimedia/SD 1 0x01D0 0000 0x01D0 1FFF 8K McBSP 0x01D0 2000 0x01D0 3FFF 8K Reserved 0x01D0 4000 0x01D0 5FFF 8K UART1 0x01D0 6000 0x01D0 63FF 1K Reserved 0x01D0 6400 0x01D0 7FFF 3K EMAC ControlRegisters 0x01D0 7000 0x01D0 9FFF 0x01D0 7FFF4K EMAC ControlModule RAM 0x01D0 8000 8K EMAC ControlModule Registers 0x01D0 A000 0x01D0 AFFF 4K EMAC MDIO ControlRegisters 0x01D0 B000 0x01D0 B7FF 2K VoiceCodec 0x01D0 C000 0x01D0 C3FF 1K Reserved 0x01D0 C400 0x01D0 FFFF 17K ASYNC EMIF Control 0x01D1 0000 0x01D1 0FFF 4K Multimedia/SD 0 0x01D1 1000 0x01D1 FFFF 60K Reserved 0x01D2 0000 0x01D3 FFFF 128K Reserved 0x01D4 0000 0x01DF FFFF 768K Reserved 0x01E0 0000 0x01FF FFFF 2M ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M Reserved 0x0600 0000 0x09FF FFFF 64M Reserved 0x0A00 0000 0x0FFF FFFF 96M

2.7 Pin Assignments

Extensiveuse ofpinmultiplexingisused toaccommodate thelargestnumber ofperipheralfunctionsin the smallestpossiblepackage. Pin multiplexingis controlledusing a combinationof hardware configurationatdeviceresetand softwareprogrammableregistersettings.

2.7.1 Pin Map (Bottom View)

Figure2-2throughFigure2-5show thepinassignmentsinfourquadrants(A,B,C, and D).

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J 8765431 H G VDD12_ PRTCSS F E D PWCTRIO3 C B A VDDS18PWCTRIO4PECTRIO0 VSSVDDS33EMU1RESETRTCXO VDDA18_ADCCVDDEMU0N.B.RTCXI VSSA_ADCVDDS33TDITCKGIO21GIO20 VDDA18_VCADC_CH0GIO44GPIO46VDD18_SLDOGIO17GIO19GIO16 VSSA33_VCADC_CH3GIO1GIO49GIO13GIO14 LINEOMICINN.B.GIO47GIO3GIO2N.B.GIO12 SPPMICIPADC_CH1GPIO45GIO0GIO5GIO6GIO1 1 SPNVCOMADC_CH2ADC_CH5GIO48GIO4GIO7RSV0 PWCTRIO1 VSS_32K TMS RTCK GIO18 GIO15 GIO9 GIO10 GIO8 PWCTRIO2 CVDD VSSA18_VC ADC_CH4VDDRAM VDDS33 TDO N.B. CVDDCVDDTRST CVDD VSS A B C D TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 (1) N.B standsforNo-Ball. Figure2-2.ZCE Pin Map [QuadrantA] Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

W DDR_ DQ6 DDR_ DQ8 7654 GIO36 GIO32 V GIO38GIO34GIO23 U DDR_ DQSN0 T GIO24 R P N M L K DDR_ DQ12 DDR_ DQM1GIO41VSS DDR_ DQ5 DDR_ DQ1 1 DDR_ DQ14 DDR_ DQ15GIO33GIO28 DDR_DQ9N.B.DDR_ DQSN1GIO40 GIO35 GIO31N.B.GIO29GIO26 DDR_ DQGA TE1 DDR_ DQGA TE0GIO43GIO37GIO27GIO25 DDR_DQ7DDR_DQ10DDR_DQ13GIO42GIO39RSV2VPPGIO22RSV1 VDD18_DDRVSSVDDS33VDDA33_USBVSSA33_USBVSSA18_USBUSB_DM VDD18_DDRVSSVDDS33VDD18_USBN.B.USB_VBUSUSB_DP VSSVSSVDDA12LDO_ USBVSSAPWRSTPWRCNTONUSB_ID VSSVDDMXIPWCTRO1PWCTRO2PWCTRO3VSS_MX1MXI1 VSSCVDDVDD18_PRTCSSPWCTRIO5N.B.PWCTRO0MXO1 VDDS18 PWCTRIO6 VDD12_PRTCSS VSSVSS VSS N.B.VDDA18_PLL VDDS33 GIO30 DDR_DQS1 CVDD A B C D TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com (1) N.B standsforNo-Ball. Figure2-3.ZCE Pin Map [QuadrantB]

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W DDR_A1 1 DDR_A8 DDR_A6 DDR_A2 DDR_BA0 DDR_WE DDR_CLK 1 1 DDR_CLK DDR_DQ4 EM_A1 1 VEM_A13DDR_A12DDR_A10DDR_A5DDR_A1DDR_BA2DDR_CASDDR_DQ1DDR_DQ3 EM_A8 TEM_A9EM_A7DDR_A7DDR_A3DDR_CSDDR_DQM0 EM_A4 REM_A6EM_BA1EM_A5EM_A3VDD_ AEMIF1_18_33 DDR_CKEVDD18_DDRDDR_ P ADREFPDDR_DQ2 EM_D13 PEM_D15EM_BA0EM_D14EM_D12VDD18_DDR EM_D9 NEM_D10N.B.EM_D8VSSVDD18_DDR EM_A1 MEM_A2EM_CE[0]EM_ADVEM_CLKVDDS18 EM_D5 LEM_D6EM_A0EM_D7EM_D4VSS EM_D2 KEM_D0N.B. DDR_VREF V DD18_DDR VDD_ AEMIF1_18_33 VDDS33 CVDD VSS CVDD VDD_ AEMIF2_18_33 EM_D3 EM_D1N.B.VSS VSS CVDDCVDDVSSCVDD EM_D1 1N.B.VSSN.B. VSS DDR_A13DDR_BA1DDR_DQS0 VDD_ AEMIF2_18_33 A B C D TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 (1) N.B standsforNo-Ball. Figure2-4.ZCE Pin Map [QuadrantC] Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

EM_OE J MMCSD0_ DA T A1 H YOUT6 G F E D C VDDS18 B A EM_WAITEM_CE[1]MMCSD0_CLKEM_WEVSS MMCSD0_ DA T A0 MMCSD0_ DA T A3 MMCSD0_ CMD VSYNCN.B.HSYNC YOUT2YOUT4YOUT1YOUT3YOUT5 COUT6COUT7COUT4C_WE_ FIELDVDDA12_DACVSSA18_ DAC VDDA33_VC COUT2COUT1COUT0YIN0YIN1YIN4VREF VCLK CIN1 CIN5 CIN4 CIN0 CIN3 YIN2 CIN7 VD YIN3 YIN5 YIN6 COMPY COMPPB IDACOUT IREF VDDS18 CVDD VDDS33 VDDS18 MMCSD0_ DA T A2 VSSVDD_ISIF18_33VDD_ISIF18_33VSSA12_DACVDDS33 COUT5 EXTCLKVFB VSSTVOUT VDDA18_DAC PCLK COUT3 YOUT0VSS YOUT7N.B.VSSVSSN.B. VSS CVDD CVDDVSSVSS A B C D TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com (1) N.B standsforNo-Ball. Figure2-5.ZCE Pin Map [QuadrantD]

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011

2.8 TerminalFunctions

Table2-5providesa completepindescriptionlistwhichshows externalsignalnames, theassociatedpin (ball)numbers along withthe mechanicalpackage designator,the pin type,whether the pin has any internalpullupor pulldownresistors,and a functionalpindescription.For more detailedinformationon deviceconfiguration,peripheralselection,multiplexed/sharedpins,and debugging considerations,see Section3. Table2-5.Pin Descriptions Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State CIN7 (5) A15 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[7] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[07] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[07] CIN6(5) C15 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[6] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[06] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[06] CIN5(5) B16 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[5] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[05] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[05] CIN4(5) A16 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[4] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[04] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[04] CIN3 (5) A17 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[3] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[03] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[03] CIN2(5) C16 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[2] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[02] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[02] (1) I= Input,O = Output,Z = Highimpedance,S = Supplyvoltage,GND = Ground,A = Analogsignal. (2) SpecifiestheoperatingI/Osupplyvoltageforeach signal.See Section6.3 ,Power Suppliesformore detail. (3) PD = pull-down,PU = pull-up.(Topullup a signaltotheoppositesupplyrail,a 1 kΩ resistorshouldbe used.) (4) To reduceEMI and reflections,dependingon thetracelength,approximately22 Ω to50 Ω damping resistorsarerecommend on the followingoutputsplacednearthedevice:YOUT(0-7),COUT(0-7),HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK.The tracelengthsshould be minimized. (5) The Y input(YIN[7:0])and C input(CIN[7:0])buses can be swapped by programmingthefieldbitYCINSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h). IFYCINSWP bitis0 (default)YIN[7:0]= Y signal/CIN[7:0]= C signal. IFYCINSWP bitis1 YIN[7:0]= C signal/CIN[7:0]= Y signal Formore information,see theTMS320DM36x VideoProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8 ). Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State CIN1(5) A18 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[1] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[01] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[01] CIN0(5) B17 I/O ISIF VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[0] YCC 16-bit:timemultiplexedbetween chroma: CB/CR[00] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma oftheupperchannel.Y/CB/CR[00] YIN7(5)/GIO103 C12 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[15] /SPI3_SCLK GIO / SPI3 YCC 16-bit:timemultiplexedbetween luma:Y[07] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[07] GIO: GIO[103] SPI3:Clock YIN6(5)/GIO102 A13 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[14] /SPI3_SIMO GIO / SPI3 YCC 16-bit:timemultiplexedbetween luma:Y[06] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[06] GIO: GIO[102] SPI3:SlaveInputMasterOutputData Signal YIN5(6)/GIO101 B13 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[13] /SPI3_SCS[0] GIO / SPI3 YCC 16-bit:timemultiplexedbetween luma:Y[05] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[05] GIO: GIO[101] SPI3:ChipSelect0 YIN4(6)/GIO100 / D12 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[12] SPI3_SOMI / GIO / SPI3_SCS[1] SPI3 YCC 16-bit:timemultiplexedbetween luma:Y[04] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[04] GIO: GIO[100] SPI3:SlaveOutputMasterInputData Signal SPI3:ChipSelect1 (6) The Y input(YIN[7:0])and C input(CIN[7:0])buses can be swapped by programmingthefieldbitYCINSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h). IFYCINSWP bitis0 (default)YIN[7:0]= Y signal/CIN[7:0]= C signal. IFYCINSWP bitis1 YIN[7:0]= C signal/CIN[7:0]= Y signal Formore information,see theTMS320DM36x VideoProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8 ).

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State YIN3(6)/GIO99 A14 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[11] GIO YCC 16-bit:timemultiplexedbetween luma:Y[03] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[03] GIO: GIO[99] YIN2(6)/GIO98 B15 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[10] GIO YCC 16-bit:timemultiplexedbetween luma:Y[02] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[02] GIO: GIO[98] YIN1(6)/GIO97 D14 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[09] GIO YCC 16-bit:timemultiplexedbetween luma:Y[01] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[01] GIO: GIO[97] YIN0(7)/GIO96 D15 I/O ISIF/ VDD_ISIF18_33 IPD Input StandardISIFAnalogFrontEnd (AFE):raw[08] GIO YCC 16-bit:timemultiplexedbetween luma:Y[00] YCC 08-bit(whichallowsfor2 simultaneousdecoder inputs),itistimemultiplexedbetween luma and chroma ofthelowerchannel.Y/CB/CR[00] GIO: GIO[96] HD /GIO95 C14 I/O ISIF/ VDD_ISIF18_33 IPD Input Horizontalsynchronizationsignalthatcan be either GIO an input(slavemode) oran output(mastermode). TellstheISIFwhen a new linestarts. GIO: GIO[95] VD /GIO94 B14 I/O ISIF/ VDD_ISIF18_33 IPD Input Verticalsynchronizationsignalthatcan be eitheran GIO input(slavemode) oran output(mastermode).Tells theISIFwhen a new framestarts. GIO: GIO[94] C_WE_FIELD / E13 I/O ISIF/ VDD_ISIF18_33 IPD Input Writeenableinputsignalisused by externaldevice GIO93 /CLKOUT0 GIO / (AFE/TG)togatetheDDR outputoftheISIFmodule. /USBDRVVBUS CLKOU T /USB Alternately,thefieldidentificationinputsignalisused by externaldevice(AFE/TG)toindicatethewhichof two framesisinputtotheISIFmodule forsensors withinterlacedoutput.ISIFhandles1-or2-field sensorsinhardware. GIO: GIO[93] CLKOUT0: ClockOutput USB: Digitaloutputtocontrolexternal5 V supply PCLK D13 I/O/Z ISIF VDD_ISIF18_33 IPD Input Pixelclockinput(strobeforlinesCI7 throughYI0) (7) The Y input(YIN[7:0])and C input(CIN[7:0])buses can be swapped by programmingthefieldbitYCINSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h). IFYCINSWP bitis0 (default)YIN[7:0]= Y signal/CIN[7:0]= C signal. IFYCINSWP bitis1 YIN[7:0]= C signal/CIN[7:0]= Y signal Formore information,see theTMS320DM36x VideoProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8 ). Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State YOUT7(R7) (8) G16 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(9). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT6(R6) (8) G19 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(9). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT5(R5) (8) F15 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(9). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT4(R4) (8) F18 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(9). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT3(R3) (8) F16 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(9). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT2(G7) (8) F19 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(9). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT1(G6) (10) F17 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(11). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). YOUT0(G5) (10) E16 I/O VENC VDDS33 Input DigitalVideoOut:VENC settingsdetermine function(11). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). HSYNC /GIO84 G15 I/O VENC / VDDS33 Input VideoEncoder:HorizontalSync(11) GIO GIO: GIO[84] VSYNC /GIO83 G18 I/O VENC / VDDS33 Input VideoEncoder:VerticalSync(11) GIO GIO: GIO[83] LCD_OE /GIO82 C19 I/O VENC / VDDS33 Output VideoEncoder:Data validduration(11) GIO GIO: GIO[82] (8) The Y output(YOUT[7:0])and C output(COUT[7:0])buses can be swapped by programmingthefieldbitYCOUTSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h).IftheYCOUTSWP bitis0 (default),YOUT[7:0]= Y signal/COUT[7:0]= C signal.IftheYCOUTSWP bitis1,YOUT[7:0]= C signal/COUT[7:0]= Y signal.Formore information,see theTMS320DM36x Video ProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8). (9) To reduceEMI and reflections,dependingon thetracelength,approximately22 Ω to50 Ω damping resistorsarerecommend on the followingoutputsplacednearthedevice:YOUT(0-7),COUT(0-7),HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK.The tracelengthsshould be minimized. (10)The Y output(YOUT[7:0])and C output(COUT[7:0])buses can be swapped by programmingthefieldbitYCOUTSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h).IftheYCOUTSWP bitis0 (default),YOUT[7:0]= Y signal/COUT[7:0]= C signal.IftheYCOUTSWP bitis1,YOUT[7:0]= C signal/COUT[7:0]= Y signal.Formore information,see theTMS320DM36x Video ProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8). (11)To reduceEMI and reflections,dependingon thetracelength,approximately22 Ω to50 Ω damping resistorsarerecommend on the followingoutputsplacednearthedevice:YOUT(0-7),COUT(0-7),HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK.The tracelengthsshould be minimized.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State GIO80 /EXTCLK / B19 I/O GIO / VDDS33 IPD Input GIO: GIO[80] B2 /PWM3 VENC / PWM3 VideoEncoder:ExternalclockInput,used ifclock rates> 27 MHz areneeded,e.g.74.25MHz for HDTV digitaloutput. DigitalVideoOut:B2 (11). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM3: PWM3 Output VCLK /GIO79 B18 I/O VENC / VDDS33 Input VideoEncoder:VideoOutputClock(11) GIO GIO: GIO[79] GIO92 / E18 I/O GIO / VDDS33 Input GIO: GIO[92] COUT7(G4) (10)/ VENC / PWM0 PWM0 DigitalVideoOut:VENC settingsdetermine function(11). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM0: PWM0 Output GIO91 / E19 I/O GIO / VDDS33 Input GIO: GIO[91] COUT6(G3) (10)/ VENC / PWM1 PWM1 DigitalVideoOut:VENC settingsdetermine function(11). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM1: PWM1 Output GIO90 / E15 I/O GIO / VDDS33 Input GIO: GIO[90] COUT5(G2) (10)/ VENC PWM2 /RTO0 /PWM2 /RTO0 DigitalVideoOut:VENC settingsdetermine function(11). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM2: PWM2 Output RTO0: RTO0 Output GIO89 / E17 I/O GIO / VDDS33 Input GIO: GIO[89] COUT4(B7) (12)/ VENC / PWM2 /RTO1 PWM2 / RTO1 DigitalVideoOut:VENC settingsdetermine function(13). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM2: PWM2 Output RTO1: RTO1 Output (12)The Y output(YOUT[7:0])and C output(COUT[7:0])buses can be swapped by programmingthefieldbitYCOUTSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h).IftheYCOUTSWP bitis0 (default),YOUT[7:0]= Y signal/COUT[7:0]= C signal.IftheYCOUTSWP bitis1,YOUT[7:0]= C signal/COUT[7:0]= Y signal.Formore information,see theTMS320DM36x Video ProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8). (13)To reduceEMI and reflections,dependingon thetracelength,approximately22 Ω to50 Ω damping resistorsarerecommend on the followingoutputsplacednearthedevice:YOUT(0-7),COUT(0-7),HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK.The tracelengthsshould be minimized. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State GIO88 / D16 I/O GIO / VDDS33 Input GIO: GIO[88] COUT3(B6) (12)/ VENC / PWM2 /RTO2 PWM2 / RTO2 DigitalVideoOut:VENC settingsdetermine function(13). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM2: PWM2 Output RTO2: RTO2 Output GIO87 / D19 I/O GIO / VDDS33 Input GIO: GIO[87] COUT2(B5) (12)/ VENC PWM2 /RTO3 /PWM2 /RTO3 DigitalVideoOut:VENC settingsdetermine function(13). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM2: PWM2 Output RTO3: RTO3 Output GIO86 / D18 I/O GIO / VDDS33 Input GIO: GIO[86] COUT1(B4) (12)/ VENC / PWM3 /STTRIG PWM3 DigitalVideoOut:VENC settingsdetermine function(13). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM3: PWM3 Output STTRIG: Camera FLASH controltriggersignal GIO85 / D17 I/O GIO / VDDS33 Input GIO: GIO[85] COUT0(B3) (14)/ VENC / PWM3 PWM3 DigitalVideoOut:VENC settingsdetermine function(15). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). PWM3: PWM3 Output GIO81(OSCCFG) / C18 I/O GIO / VDDS33 Input GIO: GIO[81] LCD_FIELD /R2 / VENC / Note:Thispinwillbe used as oscillatorconfigurationPWM3 PWM3 (OSCCFG). The GIO81(OSCCFG) stateislatched duringreset,and itspecifiestheoscillationfrequency rangemode ofthepin.See Section3.7.6formore details. VideoEncoder:Fieldidentifierforinterlaceddisplay formats(15). Formore details,see theDM36x DMSoC Video ProcessorBack End User'sGuide (SPRUFG9 ). DigitalVideoOut:R2 (15) PWM3: PWM3 Output (14)The Y output(YOUT[7:0])and C output(COUT[7:0])buses can be swapped by programmingthefieldbitYCOUTSWP intheVPFE CCD Configuration(CCDCFG) register(0x01C7 0136h).IftheYCOUTSWP bitis0 (default),YOUT[7:0]= Y signal/COUT[7:0]= C signal.IftheYCOUTSWP bitis1,YOUT[7:0]= C signal/COUT[7:0]= Y signal.Formore information,see theTMS320DM36x Video ProcessingFrontEnd (VPFE) ReferenceGuide (literaturenumber SPRUFG8). (15)To reduceEMI and reflections,dependingon thetracelength,approximately22 Ω to50 Ω damping resistorsarerecommend on the followingoutputsplacednearthedevice:YOUT(0-7),COUT(0-7),HSYNC,VSYNC,LCD_OE,FIELD, and,VCLK.The tracelengthsshould be minimized.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State VREF D11 A I Video VDDA18_DAC VideoDAC: ReferencevoltageforDAC. DAC Formore details,see Section6.12.2.4,DAC and VideoBufferElectricalData/Timing. Note:IftheDAC peripheralisnotused,thispinmust be tieddirectlytoVSS forproperdeviceoperation. IREF A11 A I/O Video VDDA18_DAC VideoDAC: SetsreferencecurrentforDAC. An DAC externalresistorwithnominalvalue,2400 ohms, is connectedbetween IREF and VSS . Formore details,see Section6.12.2.4,DAC and VideoBufferElectricalData/Timing. Note:IftheDAC peripheralisnotused,thispinmust be tieddirectlytoVSS forproperdeviceoperation. IDACOUT B11 A I/O Video VDDA18_DAC VideoDAC: CurrentsourceinputfromDAC. An DAC externalresistorwithnominalvalue,2100 ohms, is connectedbetween IDACOUT and VFB. Formore details,see Section6.12.2.4,DAC and VideoBufferElectricalData/Timing. Note:IftheDAC peripheralisnotused atallinthe application,thispincan eitherbe connectedtoVSS or be leftopen. VFB B10 A I/O Video VDDA18_DAC VideoDAC: Amplifierfeedbacknode.An external DAC resistorwithnominalvalue,2150 ohms, isconnected between VFB and TVOUT. Formore details,see Section6.12.2.4,DAC and VideoBufferElectricalData/Timing. Note:IftheDAC peripheralisnotused atallinthe application,thispincan eitherbe connectedtoVSS or be leftopen. TVOUT A10 A I/O Video VDDA18_DAC VideoDAC: DAC1video output.An externalresistor DAC withnominalvalue,2150 ohms, isconnected between TVOUT and VFB. Thisistheoutputnode thatdrivestheload(75ohms). Formore details,see Section6.12.2.4,DAC and VideoBufferElectricalData/Timing. Note:IftheDAC peripheralisnotused atallinthe application,thispincan eitherbe connectedtoVSS or be leftopen. COMPY B12 A O Video VDDA18_DAC VideoDAC: Analogvideosignalcomponent outputY DAC Note:IftheDAC peripheralisnotused atallinthe application,thispincan eitherbe connectedtoVSS or be leftopen. COMPPB A12 A O Video VDDA18_DAC VideoDAC: Analogvideosignalcomponent output DAC Pb Note:IftheDAC peripheralisnotused atallinthe application,thispincan eitherbe connectedtoVSS or be leftopen. COMPPR C11 A O Video VDDA18_DAC VideoDAC: Analogvideosignalcomponent output DAC Pr Note:IftheDAC peripheralisnotused atallinthe application,thispincan eitherbe connectedtoVSS or be leftopen. VDDA18_DAC D10 PWR Video VDDA18_DAC VideoDAC: Analog1.8-Vpower DAC Note:IftheDAC peripheralisnotused,thispinmust be tieddirectlytoVSS forproperdeviceoperation. VDDA12_DAC E12 PWR Video VDDA12_DAC VideoDAC: Analog1.2-Vpower Dac Note:IftheDAC peripheralisnotused,thispinmust be tieddirectlytoVSS forproperdeviceoperation. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State VSSA18_DAC E11 GND Video VideoDAC: Analog1.8-Vground DAC Note:IftheDAC peripheralisnotused,thispinmust be tieddirectlytoVSS forproperdeviceoperation. VSSA12_DAC F11 GND Video VideoDAC: Analog1.2-Vground DAC Note:IftheDAC peripheralisnotused,thispinmust be tieddirectlytoVSS forproperdeviceoperation. DDR_CLK W11 O DDR VDD18_DDR DDR Data Clock DDR_CLK W12 O DDR VDD18_DDR DDR ComplementaryData Clock DDR_RAS U12 O DDR VDD18_DDR DDR Row AddressStrobe DDR_CAS V12 O DDR VDD18_DDR DDR Column AddressStrobe DDR_WE W13 O DDR VDD18_DDR DDR WriteEnable DDR_CS T12 O DDR VDD18_DDR DDR ChipSelect DDR_CKE R13 O DDR VDD18_DDR DDR ClockEnable DDR_DQM[1] W6 O DDR VDD18_DDR Data mask inputforDDR_DQ[15:8] DDR_DQM[0] T11 O DDR VDD18_DDR Data mask inputforDDR_DQ[7:0] DDR_DQS[1] T7 I/O DDR VDD18_DDR Data strobeinput/outputsforeach byteofthe16-bit databus used tosynchronizethedatatransfers. OutputtoDDR2 when writingand inputswhen reading.They areused tosynchronizethedata transfers. DDR_DQS1: ForDDR_DQ[15:8] DDR_DQS[0] T10 I/O DDR VDD18_DDR Data strobeinput/outputsforeach byteofthe16-bit databus used tosynchronizethedatatransfers. OutputtoDDR2 when writingand inputswhen reading.They areused tosynchronizethedata transfers. DDR_DQS0: ForDDR_DQ[7:0] DDR_DQSN[1] U6 I/O DDR VDD18_DDR DDR: Complimentarydatastrobeinput/outputsfor each byteofthe16-bitdatabus.They areoutputsto theDDR2 when writingand inputswhen reading. They areused tosynchronizethedatatransfers. Note:Thissignalisused indoubleended differential memory interfacessupportedby thedevice. DDR_DQSN[0] U9 I/O DDR VDD18_DDR DDR: Complimentarydatastrobeinput/outputsfor each byteofthe16-bitdatabus.They areoutputsto theDDR2 when writingand inputswhen reading. They areused tosynchronizethedatatransfers. Note:Thissignalisused indoubleended differential memory interfacessupportedby thedevice. DDR_BA[2] V13 O DDR VDD18_DDR Bank selectoutputs.Two arerequiredfor1Gb DDR2 memories. DDR_BA[1] T13 O DDR VDD18_DDR Bank selectoutputs.Two arerequiredfor1Gb DDR2 memories. DDR_BA[0] W14 O DDR VDD18_DDR Bank selectoutputs.Two arerequiredfor1Gb DDR2 memories. DDR_A13 T16 O DDR VDD18_DDR DDR AddressBus bit13 DDR_A12 V17 O DDR VDD18_DDR DDR AddressBus bit12 DDR_A11 W18 O DDR VDD18_DDR DDR AddressBus bit11 DDR_A10 V16 O DDR VDD18_DDR DDR AddressBus bit10 DDR_A9 U16 O DDR VDD18_DDR DDR AddressBus bit09 DDR_A8 W17 O DDR VDD18_DDR DDR AddressBus bit08 DDR_A7 T15 O DDR VDD18_DDR DDR AddressBus bit07 DDR_A6 W16 O DDR VDD18_DDR DDR AddressBus bit06

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State DDR_A5 V15 O DDR VDD18_DDR DDR AddressBus bit05 DDR_A4 U15 O DDR VDD18_DDR DDR AddressBus bit04 DDR_A3 T14 O DDR VDD18_DDR DDR AddressBus bit03 DDR_A2 W15 O DDR VDD18_DDR DDR AddressBus bit02 DDR_A1 V14 O DDR VDD18_DDR DDR AddressBus bit01 DDR_A0 U14 O DDR VDD18_DDR DDR AddressBus bit00 DDR_DQ15 V6 I/O DDR VDD18_DDR DDR Data Bus bit15 DDR_DQ14 V7 I/O DDR VDD18_DDR DDR Data Bus bit14 DDR_DQ13 R7 I/O DDR VDD18_DDR DDR Data Bus bit13 DDR_DQ12 W7 I/O DDR VDD18_DDR DDR Data Bus bit12 DDR_DQ11 V8 I/O DDR VDD18_DDR DDR Data Bus bit11 DDR_DQ10 R8 I/O DDR VDD18_DDR DDR Data Bus bit10 DDR_DQ9 U8 I/O DDR VDD18_DDR DDR Data Bus bit09 DDR_DQ8 W8 I/O DDR VDD18_DDR DDR Data Bus bit08 DDR_DQ7 R9 I/O DDR VDD18_DDR DDR Data Bus bit07 DDR_DQ6 W9 I/O DDR VDD18_DDR DDR Data Bus bit06 DDR_DQ5 V9 I/O DDR VDD18_DDR DDR Data Bus bit05 DDR_DQ4 W10 I/O DDR VDD18_DDR DDR Data Bus bit04 DDR_DQ3 V10 I/O DDR VDD18_DDR DDR Data Bus bit03 DDR_DQ2 R10 I/O DDR VDD18_DDR DDR Data Bus bit02 DDR_DQ1 V11 I/O DDR VDD18_DDR DDR Data Bus bit01 DDR_DQ0 U11 I/O DDR VDD18_DDR DDR Data Bus bit00 DDR_ T8 O DDR VDD18_DDR DDR: Loopback signalforexternalDQS gating. DQGATE0 Route toDDR and back toDDR_DQGATE1 with same constraintsas used forDDR clockand data. DDR_ T9 I DDR VDD18_DDR DDR: Loopback signalforexternalDQS gating. DQGATE1 Route toDDR and back toDDR_DQGATE0 with same constraintsas used forDDR clockand data. DDR_VREF P11 PWR DDR VDD18_DDR DDR: DDR_VREF is.5*VDD18_DDR = 0.9VforSSTL2 specificreferencevoltage. DDR_PADREFP R11 O DDR VDD18_DDR DDR: Externalresistor(50 ohm toground) EM_A13 /GIO78 / V18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: AddressBus bit[13] BTSEL[2] GIO / 33 disable BTSEL[ d by 2] default GIO: GIO[78] BTSEL[2]:See Section3.2,DeviceBootModes for systemusage ofthesepins. EM_A12 /GIO77 / U18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: AddressBus bit[12] BTSEL[1] GIO / 33 disable BTSEL[ d by 1] default GIO: GIO[77] BTSEL[1]:See Section3.2,DeviceBootModes for systemusage ofthesepins. EM_A11 /GIO76 / V19 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: AddressBus bit[11] BTSEL[0] GIO / 33 disable BTSEL[ d by 0] default GIO: GIO[76] BTSEL[0]:See Section3.2,DeviceBootModes for systemusage ofthesepins. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State EM_A10 /GIO75 / U19 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: AddressBus bit[10] AECFG[2] GIO / 33 disable AECFG d by [2] default GIO: GIO[75] AECFG[2]:See Section3.2,DeviceBootModes and Table3-14,AECFG (AsyncEMIF Configuration)for systemusage ofthesepins. EM_A9 /GIO74 / T18 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: AddressBus bit[09] AECFG[1] GIO / 33 disable AECFG d by [1] default GIO: GIO[74] AECFG[1]:See Section3.2,DeviceBootModes and Table3-14,AECFG (AsyncEMIF Configuration)for systemusage ofthesepins. EM_A8 /GIO73 / T19 I/O/Z AEMIF / VDD_AEMIF1_18_ IPU/IPD Input Async EMIF: AddressBus bit[08] AECFG[0] GIO / 33 disable AECFG d by [0] default GIO: GIO[73] AECFG[0]:See Section3.2,DeviceBootModes and Table3-14,AECFG (AsyncEMIF Configuration)for systemusage ofthesepins. EM_A7 /GIO72 / T17 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: AddressBus bit[07] KEYA3 GIO / 33 KEYSC AN GIO: GIO[72] Keyscan:A3 EM_A6 /GIO71 / R18 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: AddressBus bit[06] KEYA2 GIO / 33 KEYSC AN GIO: GIO[71] Keyscan:A2 EM_A5 /GIO70 / R16 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: AddressBus bit[05] KEYA1 GIO / 33 KEYSC AN GIO: GIO[70] Keyscan:A1 EM_A4 /GIO69 / R19 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: AddressBus bit[04] KEYA0 GIO/KE 33 YSCAN GIO: GIO[69] Keyscan:A0 EM_A3 /GIO68 / R15 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: AddressBus bit[03] KEYB3 GIO/ 33 KEYSC AN GIO: GIO[68] Keyscan:B3

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State EM_A2 /HCNTLA M18 I/O/Z AEMIF/ VDD_AEMIF2_18_ Output Async EMIF: AddressBus bit[02] HPI 33 HPI:The stateofHCNTLA and HCNTLB determines ifaddress,data,orcontrolinformationisbeing transmittedbetween an externalhostand thedevice. Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_A1 /HHWIL M19 I/O/Z AEMIF/ VDD_AEMIF2_18_ Output Async EMIF: AddressBus bit[01] HPI 33 HPI:Thispinishalf-wordidentificationinputHHWIL. Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_A0 /GIO67 / L17 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: AddressBus bit[00]Note thatthe KEYB2 /HCNTLB GIO / 33 EM_A0 isalwaysa 32-bitaddress KEYSC AN / HPI GIO: GIO[56] Keyscan:B2 HPI:The stateofHCNTLA and HCNTLB determines ifaddress,data,orcontrolinformationisbeing transmittedbetween an externalhostand thedevice. Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_BA1 /GIO66 / R17 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Bank Address1 signal= 16-bit KEYB1 /HINTN GIO / 33 address. KEYSC In16-bitmode, lowestaddressbit. AN / In8-bitmode, second lowestaddressbit HPI GIO: GIO[66] Keyscan:B1 HPI:ThispinishostinterruptoutputHINT Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_BA0 /EM_A14 P17 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Bank Address0 signal= 8-bitaddress. /GIO65 /KEYB0 GIO / 33 In8-bitmode, lowestaddressbit. KEYSC AN Async EMIF: Addressline(bit[14]when using16-bit memories. GIO: GIO[65] Keyscan:B0 EM_D15 /GIO64 / P18 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[15] HD15 GIO / 33 HPI GIO: GIO[64] HPI:Data bus bit[15] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State EM_D14 /GIO63 / P16 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[14] HD14 GIO / 33 HPI GIO: GIO[63] HPI:Data bus bit[14] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D13 /GIO62 / P19 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[13] HD13 GIO / 33 HPI GIO: GIO[62] HPI:Data bus bit[13] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D12 /GIO61 / P15 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[12] HD12 GIO / 33 HPI GIO: GIO[61] HPI:Data bus bit[12] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D11 /GIO60 / N16 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[11] HD11 GIO / 33 HPI GIO: GIO[60] HPI:Data bus bit[11] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D10 /GIO59 / N18 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[10] HD10 GIO / 33 HPI GIO: GIO[59] HPI:Data bus bit[10] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D9 /GIO58 / N19 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[09] HD9 GIO / 33 HPI GIO: GIO[58] HPI:Data bus bit[9] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D8 /GIO57 / N15 I/O/Z AEMIF / VDD_AEMIF1_18_ Input Async EMIF: Data Bus bit[08] HD8 GIO / 33 HPI GIO: GIO[57]

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State HPI:Data bus bit[8] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D7 /HD7 L16 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[07] HPI 33 HPI:Data bus bit[7] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D6 /HD6 L18 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[06] HPI 33 HPI:Data bus bit[6] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D5 /HD5 L19 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[05] HPI 33 HPI:Data bus bit[5] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D4 /HD4 L15 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[04] HPI 33 HPI:Data bus bit[4] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D3 /HD3 K15 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[03] HPI 33 HPI:Data bus bit[3] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D2 /HD2 K19 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[02] HPI 33 HPI:Data bus bit[2] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D1 /HD1 K16 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[01] HPI 33 HPI:Data bus bit[1] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_D0 /HD0 K18 I/O/Z AEMIF / VDD_AEMIF2_18_ Input Async EMIF: Data Bus bit[00] HPI 33 HPI:Data bus bit[0] Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State EM_CE[0] /GIO56 M17 I/O/Z AEMIF / VDD_AEMIF1_18_ Output Async EMIF: Lowestnumbered ChipSelect.Can be /HCS GIO / 33 programmed tobe used forstandardasynchronous HPI memories (example:flash),OneNand orNAND memory. Used forthedefaultbootand ROM boot modes. GIO: GIO[56] HPI:thispinisHPI chipselectinput. Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_CE[1] /GIO55 J17 I/O/Z AEMIF / VDD_AEMIF2_18_ Output Async EMIF: Second ChipSelect.,Can be /HAS GIO / 33 programmed tobe used forstandardasynchronous HPI memories (example:flash),OneNand orNAND memory. GIO: GIO[55] HPI:Thispinishostaddressstrobe. Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_WE /GIO54 / J15 I/O/Z AEMIF / VDD_AEMIF2_18_ Output Async EMIF: WriteEnable HDS2 GIO / 33 HPI GIO: GIO[54] HPI:Thispinishostdatastrobeinput2. Note:HPI ispinmultiplexedwithAsynchronous EMIF attheoutputpin.HPI isavailableonlywhen bootmode selectedisHPI bootmode. Inthis configuration,thedevicewillalwaysactas a slave. EM_OE /GIO53 / J19 I/O/Z AEMIF / VDD_AEMIF2_18_ Output Async EMIF: OutputEnable HDS1 GIO / 33 HPI GIO: GIO[53] HPI:Thispinishostdatastrobeinput1. EM_WAIT /GIO52 J18 I/O/Z AEMIF / VDD_AEMIF2_18_ IPU Input Async EMIF: Async WAIT /HRDY GIO / 33 HPI GIO: GIO[52] HPI:ThispinishostreadyoutputfromDSP tohost. EM_ADV /GIO51 / M16 I/O/Z AEMIF / VDD_AEMIF1_18_ Output Async EMIF: AddressValidDetectforOneNAND HR/W GIO / 33 interface HPI GIO: GIO[51] HPI:Thispinishostreadorwriteselectinput. EM_CLK /GIO50 M15 I/O/Z AEMIF / VDD_AEMIF1_18_ Output Async EMIF: ClocksignalforOneNAND flash GIO 33 interface GIO: GIO[50] GIO49 / D5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[49] McBSP_DX McBSP McBSP: TransmitData GIO48 / A5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[48] McBSP_CLKX McBSP McBSP: TransmitClock

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State GIO47 / C6 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[47] McBSP_FSX McBSP McBSP: TransmitFrame Sync GIO46 / E6 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[46] McBSP_DR McBSP McBSP: ReceiveData GIO45 / B6 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[45] McBSP_CLKR McBSP McBSP: ReceiveClock GIO44 / E7 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[44] McBSP_FSR McBSP McBSP: ReceiveFrame Sync GIO43 / T6 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[43] MMCSD1_CLK / MMCS EM_A20 D1 / AEMIF MMCSD1: Clock Async EMIF: Addressbit[20] GIO42 / R6 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[42] MMCSD1_CMD / MMCS EM_A19 D1 / AEMIF MMCSD1: Command Async EMIF: Addressbit[19] GIO41 / W5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[41] MMCSD1_DATA3 / MMCS EM_A18 D / AEMIF MMCSD1: DATA3 Async EMIF: Addressbit[18] GIO40 / U5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[40] MMCSD1_DATA2 / MMCS EM_A17 D1 / AEMIF MMCSD1: DATA2 Async EMIF: Addressbit[17] GIO39 / R5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[39] MMCSD1_DATA1 / MMCS EM_A16 D1 / AEMIF MMCSD1: DATA1 Async EMIF: Addressbit[16] GIO38 / V5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[38] MMCSD1_DATA0 / MMCS EM_A15 D1 / AEMIF MMCSD1: DATA0 Async EMIF: Addressbit[15] GIO37 / T5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[37] SPI4_SCS[0]/ SPI4 / McBSP_CLKS / McBSP CLKOUT0 / CLKOU T SPI4:SPI4 ChipSelect0 Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State McBSP: CLKS pintosourcean externalclock CLKOUT: OutputClock0 GIO36 / W4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[36] SPI4_SCLK / SPI4 / EM_A21 /EM_A14 AEMIF SPI4:Clock Async EMIF: Addressbit[21] Async EMIF: Addressbit[14] GIO35 / W3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[35] SPI4_SOMI / SPI4 SPI4_SCS[1]/ /CLKO CLKOUT1 UT SPI4:SlaveOut MasterIndata SPI4:SPI4 ChipSelect1 CLKOUT: OutputClock1 GIO34 / V4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[34] SPI4_SIMO / SPI4 / SPI4_SOMI / UART1 UART1_RXD SPI4:SlaveInMasterOut data SPI4:SlaveOut MasterIndata. UART1: RXD GIO33 / V3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[33] SPI2_SCS[0]/ SPI2 / USBDRVVBUS / USB R1 /VENC SPI3:SPI3 ChipSelect0 USB: USB: Digitaloutputtocontrolexternal5 V supply VENC: Red outputdatabit1 GIO32 / W2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[32] SPI2_SCLK /R0 SPI2 / VENC SPI2:Clock VENC: Red outputdatabit0 GIO31 / U4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[31] SPI2_SOMI / SPI2 / SPI2_SCS[1]/ CLKOU CLKOUT2 T SPI2:SlaveOut MasterIndata SPI2:SPI2 ChipSelect1 CLKOUT: OutputClock2 GIO30 / T4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[30] SPI2_SIMO /G1 SPI2 / VENC SPI2:SlaveInMasterOut data VENC: Green outputdatabit1 GIO29 / U2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[29] SPI1_SCS[0]/G0 SPI1 / VENC SPI1:SPI1 ChipSelect0 VENC: Green outputdatabit0

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State GIO28 / V1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[28] SPI1_SCLK /B1 SPI1 / VENC SPI1:Clock VENC: Blueoutputdatabit1 GIO27 / T2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[27] SPI1_SOMI / SPI1 / SPI1_SCS[1]/B0 VENC SPI1:SlaveOut MasterIndata SPI1:SPI1 ChipSelect1 VENC: Blueoutputdatabit1 GIO26 / U1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[26] SPI1_SIMO SPI1 SPI1:SlaveInMasterOut data GIO25 / T1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[25] SPI0_SCS[0]/ SPI0 / PWM1 / PWM1 / UART1_TXD UART1 SPI0:SPI0 ChipSelect0 PWM1: Output UART1: Transmitdata GIO24 / T3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[24] SPI0_SCLK SPI0 SPI0:Clock GIO23 / V2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[23] SPI0_SOMI / SPI0 / SPI0_SCS[1]/ PWM0 PWM0 SPI0:SlaveOut MasterIndata SPI0:SPI0 ChipSelect1 PWM0: Output GIO22 / R2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[22] SPI0_SIMO SPI0 SPI0:SlaveInMasterOut data GIO21 / F3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[21] UART1_RTS / UART1 I2C_SDA /I2C UART1: RTS I2C:SerialData GIO20 / F1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[20] UART1_CTS / UART1 I2C_SCL /I2C UART1: CTS I2C:SerialClock GIO19 / E3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[19] UART0_RXD UART0 UART0: Receivedata GIO18 / E2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[18] UART0_TXD UART0 UART0: Transmitdata GIO17 / E4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[17] EMAC_TX_EN / EMAC / UART1_RXD UART1 Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State EMAC: Transmitenableoutput UART1: ReceiveData GIO16 / E1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[16] EMAC_TX_CLK / EMAC / UART1_TXD UART1 EMAC: Transmitclock UART1: TransmitData GIO15 / D2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[15] EMAC_COL EMAC EMAC: CollisionDetectinput GIO14 / D1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[14] EMAC_TXD3 EMAC EMAC: TransmitData 3 output GIO13 / D3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[13] EMAC_TXD2 EMAC EMAC: TransmitData 2 output GIO12 / C1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[12] EMAC_TXD1 EMAC EMAC: TransmitData 1 output GIO11 / B1 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[11] EMAC_TXD0 EMAC EMAC: TransmitData 0 output GIO10 / B2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[10] EMAC_RXD3 EMAC EMAC: ReceiveData 3 output GIO9 / C2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[09] EMAC_RXD2 EMAC EMAC: ReceiveData 2 output GIO8 / A2 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[08] EMAC_RXD1 EMAC EMAC: ReceiveData 1 output GIO7 / A3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[07] EMAC_RXD0 EMAC EMAC: ReceiveData 0 output GIO6 / B3 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[06] EMAC_RX_CLK EMAC EMAC: Receiveclock GIO5 / B4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[05] EMAC_RX_DV EMAC EMAC: Receivedatavalidinput GIO4 / A4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[04] EMAC_RX_ER EMAC EMAC: Receiveerrorinput GIO3 / C5 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[03] EMAC_CRS EMAC EMAC: Carriersense input GIO2 /MDIO C4 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[02] EMAC EMAC: Management Data I/O GIO1 /MDCLK D6 I/O/Z GIO / VDDS33 IPD Input GIO: GIO[01] EMAC EMAC: Management Data clockoutput

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State GIO0 B5 I/O/Z GIO VDDS33 IPD Input GIO: GIO[00] USB_DP N1 A I/O USBPH VDDA33_USB USB D+ (differentialsignalpair) Y Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedto3.3V. USB_DM P1 A I/O USBPH VDDA33_USB USB D- (differentialsignalpair) Y Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedtoVSS . VDDA33_USB P4 PWR 3.3-VUSB analogpower supply Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedto3.3V. VSSA33_USB P3 GND 3.3-VUSB ground Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedtoVSS . VDDA12LDO_USB M5 PWR Output Forproperdeviceoperation,even iftheUSB peripheralisnotused,a 0.22µF capacitormust be connectedas closeas possibletothepackage,and thecapacitormst be connectedtoVSSA . VDDA18_USB N5 PWR 1.8-VUSB analogpower supply Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedto1.8V. VSSA18_USB P2 GND 1.8-VUSB ground Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedtoVSS . USB_ID M1 A I USBPH VDDA33_USB USB operatingmode identificationpin. Y Fordevicemode operationonly,pullup thispinto VDD witha 1.5Kohm resistor. Forhostmode operationonly,pulldown thispinto ground(VSS )witha 1.5Kohm resistor. Ifusingan OTG ormini-USBconnector,thispinwill be setproperlyviathecable/connectorconfiguration. Note:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedto3.3V. USB_VBUS N2 A I/O USBPH USB_VBUS Thispinisused by theUSB Controllertodetecta Y presenceof5V power (4.4Visthethreshold)on the USB_VBUS linefornormaloperation.Thispower is sourcedby theUSB Component thatisassumingthe roleofa Host.Inotherwords,thepower on the USB_VBUS lineisnotsourcedby theDevice.From DM365 perspective,when operatingas a Host,it ensuresthattheexternalpower supplythatthe DM365 has sourcediswithintherequiredvoltage level(>= 4.4V)and when DM365 isoperatingas a Device,thepresenceofa 5V power on theVBUS Lineisused tosignifythepresenceofan external Host. Note 1:When theDM365 isoperatingas a Device,it uses thepower on theUSB_VBUS linetopower up itsinternalpull-upresistoron theD+ line. Note2:IftheUSB peripheralisnotused atallinthe application,thispinshouldbe connectedtoVSS . MMCSD0_CLK J16 O MMCS VDDS33 out MMCSD0: Clock MMCSD0_CMD H15 I/O/Z MMCS VDDS33 Input MMCSD0: Command MMCSD0_DATA3 H16 I/O/Z MMCS VDDS33 Input MMCSD0: DATA3 Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 39 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State MMCSD0_DATA2 H17 I/O/Z MMCS VDDS33 Input MMCSD0: DATA2 MMCSD0_DATA1 H19 I/O/Z MMCS VDDS33 Input MMCSD0: DATA1 MMCSD0_DATA0 H18 I/O/Z MMCS VDDS33 Input MMCSD0: DATA0 MICIP B8 AI VCODE VDDA33_VC MIC positiveinput C or Note:IftheVoiceCodec peripheralisnotused,thisVDDA18_VC pinmust be tieddirectlytoVSS forproperdevice operation. MICIN C8 AI VCODE VDDA33_VC MIC negativeinput C or Note:IftheVoiceCodec peripheralisnotused,thisVDDA18_VC pinmust be tieddirectlytoVSS forproperdevice operation. LINEO C9 AO VCODE VDDA33_VC Linedriveroutput C or Note:IftheVoiceCodec peripheralisnotused,thisVDDA18_VC pincan be leftopen orcan be connecteddirectlyto Vss forproperdeviceoperation. SPP B9 AO VCODE VDDA33_VC Speakeramplifierpositiveoutput C or VDDA18_VC Note:IftheVoiceCodec peripheralisnotused,this pincan be leftopen or can be connecteddirectlyto Vss forproperdeviceoperation. SPN A9 AO VCODE VDDA33_VC Speakeramplifiernegativeoutput C or Note:IftheVoiceCodec peripheralisnotused,thisVDDA18_VC pincan be leftopen orcan be connecteddirectlyto Vss forproperdeviceoperation. VCOM A8 AO VCODE VDDA33_VC Analogblockcommon voltage. C or Itisrecommended thata 10µF capacitorbe VDDA18_VC connectedbetween thispinand groundtoprovide cleanvoltage. Note:IftheVoiceCodec peripheralisnotused,this pinmust be tieddirectlytoVSS forproperdevice operation. VDDA18_VC E9 PWR 1.8-VVoiceCodec module analogpower supply Note:IftheVoiceCodec peripheralisnotused,this pinmust be tieddirectlytoVSS forproperdevice operation. VSSA18_VC F9 GND 1.8-VVoiceCodec module ground Note:IftheVoiceCodec peripheralisnotused,this pinmust be tieddirectlytoVSS forproperdevice operation. VDDA33_VC E10 PWR 3.3-VVoiceCodec module power supply Note:IftheVoiceCodec peripheralisnotused,this pinmust be tieddirectlytoVSS forproperdevice operation. VSSA33_VC D9 GND 3.3-VVoiceCodec module ground Note:IftheVoiceCodec peripheralisnotused,this pinmust be tieddirectlytoVSS forproperdevice operation.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State ADC_CH0 E8 AI ADC VDDA18_ADC Analog-to-Digitalconverterchannel0 Note:IftheADC isnotused,itisrecommended to eitherleavethispinopen,as no connect,ortiethis pinalongwiththeotherADC_CHs togethertoa singleresistortoground. ADC_CH1 B7 AI ADC VDDA18_ADC Analog-to-Digitalconverterchannel1 Note:IftheADC isnotused,itisrecommended to eitherleavethispinopen,as no connect,ortiethis pinalongwiththeotherADC_CHs togethertoa singleresistortoground. ADC_CH2 A7 AI ADC VDDA18_ADC Analog-to-Digitalconverterchannel Note:IftheADC isnotused,itisrecommended to eitherleavethispinopen,as no connect,ortiethis pinalongwiththeotherADC_CHs togethertoa singleresistortoground. ADC_CH3 D8 AI ADC VDDA18_ADC Analog-to-Digitalconverterchannel3 Note:IftheADC isnotused,itisrecommended to eitherleavethispinopen,as no connect,ortiethis pinalongwiththeotherADC_CHs togethertoa singleresistortoground. ADC_CH4 D7 AI ADC VDDA18_ADC Analog-to-Digitalconverterchannel4 Note:IftheADC isnotused,itisrecommended to eitherleavethispinopen,as no connect,ortiethis pinalongwiththeotherADC_CHs togethertoa singleresistortoground. ADC_CH5 A6 AI ADC VDDA18_ADC Analog-to-Digitalconverterchannel5 Note:IftheADC isnotused,itisrecommended to eitherleavethispinopen,as no connect,ortiethis pinalongwiththeotherADC_CHs togethertoa singleresistortoground. VDDA18_ADC G9 PWR 1.8-V Analog-to-Digitalconverteranalogpower supply Note:IftheADC isnotused atallinan application, thispincan be directlyconnectedtothe1.8-Vsupply withoutany filteringortoground. VSSA_ADC F8 GND 1.8-V Analog-to-Digitalconverterground PWCTRIO0 J3 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal0 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRIO1 J2 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal1 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRIO2 J1 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal2 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRIO3 J5 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal3 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRIO4 J4 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal4 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 41 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State PWCTRIO5 K5 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal5 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRIO6 K4 I/O/Z PRTCS VDD18_PRTCSS Input PRTCSS: GeneralInput/OutputSignal6 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRO0 K2 O PRTCS VDD18_PRTCSS Output PRTCSS: GeneralOutputSignal0 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRO1 L5 O PRTCS VDD18_PRTCSS Output PRTCSS: GeneralOutputSignal1 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRO2 L4 I/O/Z PRTCS VDD18_PRTCSS Output PRTCSS: GeneralOutputSignal2 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWCTRO3 L3 O PRTCS VDD18_PRTCSS Output PRTCSS: GeneralOutputSignal3 S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . RTCXI G1 I PRTCS VDD12_PRTCSS Input PRTCSS: CrystalInputforPRTCSS oscillator S Note:IftheRTC calendarisnotused,thispinshould be pulleddown. Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . RTCXO H1 O PRTCS VDD12_PRTCSS Output PRTCSS: CrystalOutputforPRTCSS oscillator S Note:IftheRTC calendarisnotused,thispinshould be leftunconnected. Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWRST M3 I PRTCS VDD12_PRTCSS Input PRTCSS: ResetsignalforPRTCSS S Formore pinterminationdetails,see Section6.7, Power Management and RealTime Clock Subsystem (PRTCSS) . PWRCNTON M2 I PRTCS VDD12_PRTCSS Input PRTCSS: Resetpinforsystempower sequencing S Formore pindetails,see Section6.7. RESET H3 I VDDS33 Input Globalchipreset MXI1 L1 I CLOCK VDDMXI Input Crystalinputforsystemoscillator S Note:Ifan externaloscillatoristobe used,the externaloscillatorclocksignalshouldbe connected totheMXI1 pinwitha 1.8Vamplitude.The MXO1 shouldbe leftunconnectedand theVSS_MX1 signal shouldbe connectedtoboardground(Vss). MXO1 K1 O CLOCK VDDMXI Output Outputforsystemoscillator S Note:Ifan externaloscillatoristobe used,the externaloscillatorclocksignalshouldbe connected totheMXI1 pinwitha 1.8Vamplitude.The MXO1 shouldbe leftunconnectedand theVSS_MX1 signal shouldbe connectedtoboardground(Vss). TCK F4 I EMULA VDDS33 IPU Input JTAG testclockinput TION TDI F5 I EMULA VDDS33 IPU Input JTAG testdatainput TION TDO G4 O EMULA VDDS33 Output JTAG testdataoutput TION

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State TMS G2 I EMULA VDDS33 IPU Input JTAG testmode select TION TRST H5 I EMULA VDDS33 IPD Input JTAG testlogicreset TION RTCK F2 O EMULA VDDS33 Output JTAG testclockoutput TION EMU0 G5 I/O EMULA VDDS33 IPU Input JTAG emulation0 I/O TION EMU1 H4 I/O EMULA VDDS33 IPU Input JTAG emulation1 I/O TION EMU[1:0]= 00 -ForceDebug Scan chain(ARM and ARM ETB TAPs connected) EMU[1:0]= 11 -Normal Scan chain(ICEpickonly) RSV2 R4 I Forproperdeviceoperation,thispinmust be tiedto ground. RSV1 R1 O Forproperdeviceoperation,thispinmust be left unconnected. RSV0 A1 O Forproperdeviceoperation,thispinmust be left unconnected. CV DD G6 PWR Core power (1.2-Vor1.35-V). H12 J12 J14 K12 L13 M10 M12 M13 VDD12_PRTCSS J6 PWR Power supplyforRTC oscillator,PRTCSS, and PRTCSS I/O(1.2-Vor1.35-V).K7 VDDA18_PLL N4 PWR Analogpower forPLL (1.8V). VDDRAM D4 O Output Forproperdeviceoperation,thispinmust be connectedtoa 1.0uF(6.2V)capacitor,and theother end ofthecapacitormust be connectedtoVss. Note:thispinisan internalpower supplypinand shouldnotbe connectedtoany externalpower supply.” VDDS18 G14 PWR Power supplyfor1.8-VI/O. H11 H14 M14 VDD18_PRTCSS K6 PWR Power supplyforPRTCSS (1.8V). VDDMXI L6 PWR Power supplyforPLL oscillator(1.8V). Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 43 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State VDD18_SLDO E5 PWR Power supplyforinternalRAM. Forproperdeviceoperation,thispinmust alwaysbe connectedtoVDDS18 . VDD18_DDR N9 PWR Power supplyforDDR (1.8V). N11 P10 P12 R12 VDDS33 F10 PWR Power supplyfor3.3-VI/O. H13 L12 VDD_AEMIF1_18_33 P14 PWR Power supplyforswitchableAEMIF (3.3/1.8V). VDD_AEMIF1_18_33 :can be used as a power supplyforR14 EM_A[3:13],EM_BA0, EM_BA1, EM_CE[0], VDD_AEMIF2_18_33 K14 PWR EM_ADV, EM_CLK, EM_D[8:15]oras GPIO pins. See AEMIF pindescriptions.L14 VDD_AEMIF2_18_33: can be used as a power supplyfor EM_A[0:2],EM_CE[1],EM_WE, EM_OE, EM_WAIT, EM_D[0:7]pins,HPI,orGPIO pins.See AEMIF pin descriptions. Example 1:VDD_AEMIF2_18_33 at1.8-Vfor8-bitNAND VDD_AEMIF1_18_33 at 3.3-V for GPIO. Example 2:VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at 1.8-Vfor16-bitNAND. VDD_ISIF18_33 F12 PWR Power supplyforswitchableISIF(3.3/1.8V). F13 PWR Example 1 VDD_ISIF_18_33 power supplycan be at 1.8V forVPFE pinfunctionalityoritcan be at3.3V if otherperipheralspinfunctionalityisto be used like SPI3 orGPIO orCLKOUT0, orUSBDRVVBUS. VPP R3 PWR Forproperdeviceoperation,thispinmust alwaysbe connectedtoCV DD.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table2-5.Pin Descriptions(continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State VSS A19 GND Digitalground E14 F14 G11 G12 H10 J10 J11 J13 K10 K11 L10 L11 M11 N12 N14 P13 W19 VSS_MX1 L2 GND System oscillator-ground Note:Note:Ifan externaloscillatorisused,thispin must be connectedtoboardground(Vss). VSS_32K H2 GND PRTCSS oscillator-ground VSSA M4 GND Analogground Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 45 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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2.9 Device Support

2.9.1 Development Tools

TI offersan extensivelineof development toolsfordevicesystems,includingtoolsto evaluatethe performanceoftheprocessors,generatecode,developalgorithmimplementations,and fullyintegrateand debug softwareand hardwaremodules.The toolssupportdocumentationiselectronicallyavailablewithin theCode Composer Studio™ IntegratedDevelopmentEnvironment(IDE). The followingproductssupportdevelopmentofdevicebased applications: SoftwareDevelopment Tools: Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCode Generation,and Debug plusadditionaldevelopmenttools Hardware Development Tools: Extended Development System (XDS ™) Emulator(supportsTMS320 DM365 DMSoC multiprocessor systemdebug)EVM (EvaluationModule) For a completelistingofdevelopment-supporttoolsfortheTMS320 DM365 DMSoC platform,visitthe Texas Instrumentsweb siteon the Worldwide Web at www.ti.com. For informationon pricingand availability,contactthenearestTIfieldsalesofficeorauthorizeddistributor.

2.9.2 Device Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall DSP devicesand supporttools.Each DSP commercialfamilymember has one ofthreeprefixes:TMX, TMP, or TMS (e.g.,).Texas Instrumentsrecommends two of threepossibleprefixdesignatorsforits supporttools:TMDX and TMDS. These prefixesrepresentevolutionarystagesof productdevelopment fromengineeringprototypes(TMX/TMDX) throughfullyqualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: TMX Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. TMP Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. TMS Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." TMS devicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedevices(TMX or TMP) have a greaterfailureratethan the standard productiondevices.Texas Instrumentsrecommends thatthesedevicesnot be used inany production system because theirexpectedend-usefailurerateisundefined.Only qualifiedproductiondevicesareto be used inproduction.

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TMX = Experimental device TMS = Qualified device TMS 320 DM365 ( ) ZCE ( ) 27 ( ) DEVICE FAMILY 320 = TMS320 DSP family PACKAGE TYPE ZCE = 338-pin plastic BGA, with Pb-free soldered balls (A) DEVICE DM365 (B) A B C . BGA = Ball Grid Array. . For actual device part numbers (P/Ns) and ordering information, contact your nearest TI Sales Representative. . For more information on silicon revision, see the (literature number SPRZ294).TMS320DM365 Silicon Errata SILICON REVISION (C) SPEED GRADE 21 = 216 MHz 27 = 270 MHz 30 = 300 MHZ F = Face Detection TEMPERATURE GRADE Blank = 0 to 85C D = -40 to 85C TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type (forexample, ZCE), the temperaturerange (forexample, "Blank"is the commercial temperaturerange),and the devicespeed range in megahertz (forexample,202 is202.5 MHz). The followingfigureprovidesa legendforreadingthecompletedevicename forany TMS320 DM365 DMSoC platformmember. Figure2-6.Device Nomenclature

2.9.3 RelatedDocumentation From Texas Instruments

The followingdocuments describetheTMS320DM36x DigitalMedia System-on-Chip(DMSoC). Copiesof thesedocuments areavailableon theinternetatwww.ti.com. SPRZ294 TMS320 DM365 DMSoC SiliconErrata Describesthe known exceptionsto the functional specificationsfortheTMS320 DM365 DMSoC. SPRUFG5 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) ARM Subsystem Users Guide. This document describesthe ARM Subsystem in the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master controlof the device.In general,the ARM isresponsibleforconfiguration and controlofthedevice;includingthecomponents oftheARM Subsystem,theperipherals, and theexternalmemories. SPRUFG8 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Video Processing Front End (VPFE) Users Guide.Thisdocument describestheVideo ProcessingFrontEnd (VPFE) in theTMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFG9 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Video Processing Back End (VPBE) Users Guide.Thisdocument describestheVideo ProcessingBack End (VPBE) in theTMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFH0 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) 64-bitTimer Users Guide.This document describesthe operationof the software-programmable64-bittimersin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFH1 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) SerialPeripheralInterface(SPI) Users Guide. This document describesthe serialperipheralinterface(SPI) in the TMS320DM36x DigitalMedia System-on-Chip (DMSoC). The SPI is a high-speed synchronousserialinput/outputportthatallowsa serialbitstreamofprogrammed length(1 to16 bits)tobe shiftedintoand outofthedeviceata programmed bit-transferrate.The SPI isnormallyused forcommunicationbetween theDMSoC and externalperipherals.Typical applicationsincludean interfacetoexternalI/Oorperipheralexpansionviadevicessuch as Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 47 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com shiftregisters,displaydrivers,SPI EPROMs and analog-to-digitalconverters. SPRUFH2 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter(UART) Users Guide. This document describesthe universal asynchronousreceiver/transmitter(UART) peripheralin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). The UART peripheralperformsserial-to-parallelconversionon data receivedfrom a peripheraldevice,and parallel-to-serialconversionon data received fromtheCPU. SPRUFH3 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Inter-IntegratedCircuit(I2C) PeripheralUsers Guide. This document describesthe inter-integratedcircuit(I2C) peripheralintheTMS320DM36x DigitalMedia System-on-Chip(DMSoC). The I2C peripheral providesan interfacebetween the DMSoC and otherdevicescompliantwiththe I2C-bus specificationand connectedby way ofan I2C-bus. SPRUFH5 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) MultimediaCard (MMC)/Secure Digital(SD) Card ControllerUsers Guide.Thisdocument describesthemultimediacard (MMC)/secure digital(SD) card controllerin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFH6 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Pulse-WidthModulator (PWM) Users Guide. Thisdocument describesthepulse-widthmodulator(PWM) peripheralinthe TMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFH7 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Real-TimeOut (RTO) Controller Users Guide. This document describesthe Real Time Out (RTO) controllerin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFH8 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) General-PurposeInput/Output (GPIO) Users Guide. This document describesthe general-purposeinput/output(GPIO) peripheralin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). The GPIO peripheralprovidesdedicatedgeneral-purposepinsthatcan be configuredas eitherinputs oroutputs. SPRUFH9 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) UniversalSerialBus (USB) ControllerUsers Guide.Thisdocument describestheuniversalserialbus (USB) controller intheTMS320DM36x DigitalMedia System-on-Chip(DMSoC). The USB controllersupports datathroughputratesup to480 Mbps. Itprovidesa mechanism fordatatransferbetween USB devicesand alsosupportshostnegotiation. SPRUFI0 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) ControllerUsers Guide. Thisdocument describesthe operationof the enhanced directmemory access (EDMA3) controllerin the TMS320DM36x DigitalMedia System-on-Chip (DMSoC). The EDMA controller'sprimary purpose is to service user-programmed data transfersbetween two memory-mapped slave endpointson the DMSoC. SPRUFI1 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Asynchronous External Memory Interface(EMIF) Users Guide. This document describesthe asynchronous externalmemory interface(EMIF) in the TMS320DM36x DigitalMedia System-on-Chip (DMSoC). The EMIF supportsa gluelessinterfacetoa varietyofexternaldevices. SPRUFI2 TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Users Guide. This document describes the DDR2/mDDR memory controllerin the TMS320DM36x DigitalMedia System-on-Chip (DMSoC). The DDR2/mDDR memory controlleris used to interfacewith JESD79D-2A standardcompliantDDR2 SDRAM and mobileDDR devices. SPRUFI3 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) MultibufferedSerial Port Interface(McBSP) User's Guide. This document describesthe operationof the

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 multibufferedserialhostportinterfaceintheTMS320DM36x DigitalMedia System-on-Chip (DMSoC). The primaryaudiomodes thataresupportedby theMcBSP aretheAC97 and IIS modes. In additionto the primaryaudio modes, the McBSP supportsgeneralserialport receiveand transmitoperation. SPRUFI4 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) UniversalHost Port Interface (UHPI) User's Guide. This document describesthe operationof the universalhost port interfaceintheTMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFI5 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Ethernet Media Access Controller(EMAC) User'sGuide. Thisdocument describesthe operationof the ethernet media accesscontrollerfaceintheTMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFI7 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Analog to DigitalConverter (ADC) User's Guide. This document describesthe operationof the analog to digital conversionintheTMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFI8 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Key Scan User's Guide. This document describesthe key scan peripheralin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). SPRUFI9 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Voice Codec User'sGuide.This document describesthe voice codec peripheralin the TMS320DM36x DigitalMedia System-on-Chip(DMSoC). Thismodule can accessADC/DAC datawithinternalFIFO (Read FIFO/WriteFIFO).The CPU communicates to the voicecodec module using32-bit-wide controlregistersaccessibleviatheinternalperipheralbus. SPRUFJ0 TMS320DM36x DigitalMedia System-on-Chip (DMSoC) Power Management and Real-Time Clock Subsystem (PRTCSS) User's Guide. This document providesa functionaldescriptionof the Power Management and Real-Time Clock Subsystem (PRTCSS) in the TMS320DM36x DigitalMedia System-on-Chip(DMSoC) and PRTC interface(PRTCIF). Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOverview 49 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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3 Device Configurations

Thissectionprovidesa detailedoverviewofthedevice.

3.1 System Module Registers

The system module includesstatusand controlregistersforconfigurationofthedevice.Briefdescriptions ofthevariousregistersareshown inTable3-1.Formore informationon theSystem Module registers,see theTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ). Table3-1.System Module RegisterMemory Map HEX ADDRESS REGISTER ACRONYM DESCRIPTION (1) 0x01C4 0000 PINMUX0 PinMux 0 (VideoIn)PinMux Register 0x01C4 0004 PINMUX1 PinMux 1 (VideoOut)PinMux Register 0x01C4 0008 PINMUX2 PinMux 2 (AEMIF)PinMux Register 0x01C4 000C PINMUX3 PinMux 3 (GIO/Misc)PinMux Register 0x01C4 0010 PINMUX4 PinMux 4 (Misc)PinMux Register 0x01C4 0014 BOOTCFG BootConfiguration 0x01C4 0018 ARM_INTMUX MultiplexingControlforInterrupts 0x01C4 001C EDMA_EVTMUX MultiplexingControlforEDMA Events 0x01C4 0020 DDR_SLEW DDR Slew Rate 0x01C4 0024 UHPICTL UHPI Control 0x01C4 0028 DEVICE_ID DeviceID 0x01C4 002C VDAC_CONFIG VideoDAC Configuration 0x01C4 0030 TIMER64_CTL Timer64InputControl 0x01C4 0034 USB_PHY_CTL USB PHY Control 0x01C4 0038 MISC MiscellaneousControl 0x01C4 003C MSTPRI0 MasterPrioritiesRegister0 0x01C4 0040 MSTPRI1 MasterPrioritiesRegister1 0x01C4 0044 VPSS_CLK_CTL VPSS ClockMux Control 0x01C4 0048 PERI_CLKCTL PeripheralClockControl 0x01C4 004C DEEPSLEEP DEEPSLEEP Control 0x01C4 0050 - Reserved 0x01C4 0054 DEBOUNCE0 Debounce forGIO0 Input 0x01C4 0058 DEBOUNCE1 Debounce forGIO1 Input 0x01C4 005C DEBOUNCE2 Debounce forGIO2 Input 0x01C4 0060 DEBOUNCE3 Debounce forGIO3 Input 0x01C4 0064 DEBOUNCE4 Debounce forGIO4 Input 0x01C4 0068 DEBOUNCE5 Debounce forGIO5 Input 0x01C4 006C DEBOUNCE6 Debounce forGIO6 Input 0x01C4 0070 DEBOUNCE7 Debounce forGIO7 Input 0x01C4 0074 VTPIOCR VTP IO Control 0x01C4 0078 PUPDCTL0 IO cellpullup/downon/offcontrol#0 0x01C4 007C PUPDCTL1 IO cellpullup/downon/offcontrol#1 0x01C4 0080 HDVICPBT HDVICP BootRegister 0x01C4 0084 PLL1_CONFIG PLL1 ConfigurationRegister 0x01C4 0088 PLL2_CONFIG PLL2 ConfigurationRegister (1) Formore detailson thesystemmodule registers,see theTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

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3.2 Boot Modes

The ARM can bootfrom eitherAsynchronousEMIF (OneNand/NOR) or from ARM ROM, as determined by thesettingofthedeviceconfigurationpinsBTSEL[2:0].The bootselectionpins(BTSEL[2:0])determine theARM bootprocess.Afterreset(POR, warm reset,or max reset),ARM program executionbeginsin ARM ROM at 0x0000:8000, exceptwhen BTSEL[2:0]= 001, indicatingAEMIF (OneNand/NOR) flash boot.

3.2.1 Boot Modes Overview

The ARM ROM bootloader(RBL) executeswhen theBTSEL[2:0]pinsindicatea conditionotherthanthe normalARM EMIF boot.

• IfBTSEL[2:0]= 001 - AsynchronousEMIF bootmode (NOR or OneNAND). Thismode ishandledby hardwarecontroland does notinvolvetheROM. Inthecase ofOneNAND, theuserisresponsiblefor puttingany necessarybootcode intheOneNAND's bootpage.Thiscode shallconfiguretheAEMIF module forthe OneNAND device.Afterthe AEMIF module is configured,bootingwillcontinue immediatelyaftertheOneNAND ’s bootpage withtheAEMIF module managing pages thereafter.
• The RBL supports7 distinctbootmodes: – BTSEL[2:0]= 000 -NAND Bootmode – BTSEL[2:0]= 010 -MMC0/SD0 Bootmode – BTSEL[2:0]= 011 -UART0 Bootmode – BTSEL[2:0]= 100 -USB Bootmode – BTSEL[2:0]= 101 -SPI0 Bootmode – BTSEL[2:0]= 110 -EMAC Bootmode – BTSEL[2:0]= 111 -HPI Bootmode
• IfNAND bootfails,thenMMC/SD mode istried.
• IfMMC/SD bootfails,thenMMC/SD bootistriedagain.
• IfUART bootfails,thenUART bootistriedagain.
• IfUSB bootfails,thenUSB bootistriedagain.
• IfSPI bootfails,thenSPI bootistriedagain.
• IfEMAC bootfails,thenEMAC bootistriedagain.
• IfHPI bootfails,thenHPI bootistriedagain.
• RBL shallupdatebootstatus(PASS/FAIL)inMISC registerbits8 and 9 inSystem controlmodule.
• ARM ROM Boot-NAND Mode – No supportfora fullfirmwareboot.Instead,copiesa second stageuser boot loader(UBL) from NAND flashtoARM internalRAM (AIM)and transferscontroltotheuser-definedUBL. – SupportforNAND withpage sizesup to4096 bytes. – Supportformagic number errordetectionand retry(upto24 times)when loadingUBL – Supportforup to30KB UBL (32KB IRAM -~2KB forRBL stack) – Optional,user-selectable,supportforuse of DMA and I-cacheduringRBL execution(i.e.,while loadingUBL) – Supportsbootingfrom8-bitNAND devices(16-bitNAND devicesarenotsupported) – Uses/Requires4-bitHW ECC (NAND deviceswithECC requirements≤ 4 bitsper 512 bytesare supported) – SupportsNAND flashthatrequireschipselecttostaylowduringthetR readtime Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 51 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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• ARM ROM Boot-MMC/SD Mode – No supportfora fullfirmwareboot.Instead,copiesa second stageUser Boot Loader (UBL) from MMC/SD toARM InternalRAM (AIM)and transferscontroltotheusersoftware. – SupportforMMC/SD Nativeprotocol(MMC/SD SPI protocolisnotsupported) – Supportfordescriptorerrordetectionand retry(upto24 times)when loadingUBL – Supportforup to30KB UBL (32KB -~2KB forRBL stack) – SDHC bootsupportedby RBL
• ARM ROM Boot-UART mode – Ifthe stateof BTSEL[2:0]pinsat resetis011, then the UART boot mode executes.Thismode enablesa smallprogram,referredtohere as a userbootloader(UBL),tobe downloaded tothe on-chipARM internalRAM viatheon-chipserialUART and executed.A hostprogram,(referredto as serialhostutilityprogram),manages theinteractionwithRBL and providesa means foroperator feedbackand input.The UART boot mode executionassumes the followingUART settings:24 MHz referenceclock,Time-Out500 ms, one-shotSerialRS-232 port115.2Kbps, 8-bit,no parity, one stopbitCommand, data,and checksum formatEverythingsentfrom the hostto the device UART RBL must be inASCIIformat – No supportfora fullfirmwareboot.Instead,loadsa second stageuserbootloader(UBL) viaUART toARM internalRAM (AIM)and transferscontroltotheusersoftware. – Supportforup to30KB UBL (32KB -~2KB forRBL stack)
• ARM ROM Boot– USB Mode – No supportfora fullfirmwareboot.Instead,loadsa second stageUser Boot Loader(UBL) viaUSB toARM InternalRAM (AIM)and transferscontroltotheuserssoftware.
• ARM ROM Boot– SPI Mode – The devicewillcopy UBL toARM InternalRAM (AIM)viaSPI interfacefrom a SPI peripherallike SPI EEPROM. RBL willthentransfercontroltotheUBL.
• ARM ROM Boot– EMAC Mode – The devicewillsend a bootrequestpacketand thehost/serverwillrespondwiththebootpackets. RBL willwaitforallbootpacketstoarriveand thentransfercontroltotheUBL whichisreceivedvia boot packets.In EMAC boot mode an I2C EEPROM or SPI EEPROM is necessary for programmingEMAC descriptor(includingEMAC addressforthedevice) Note:Ifa magic number isnotfoundintheEEPROM, thentheEMAC bootmode willuse a default MAC address.Inthiscase,therewillbe no magic number support.
• ARM ROM Boot– HPI Mode – The Host willcopy UBL to ARM InternalRAM (AIM) via HPI interfaceand notifythe ROM bootloaderaftercopy isfinished.RBL willthentransfercontroltotheUBL. The generalboot sequence isshown inFigure3-1. For more information,referto the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure3-1.Boot Mode FunctionalBlock Diagram Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 53 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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3.3 Device Clocking

3.3.1 Overview

The devicerequiresone primaryreferenceclock.The referenceclockfrequencymay be generatedeither by crystalinputorby externaloscillator.The referenceclockistheclockatthepinsnamed MXI1/MXO1, and whichdrivestwo separatePLL controllers(PLLC1 and PLLC2).PLLC1 generatestheclocksrequired by theARM, EDMA, VPSS and therestoftheperipherals.PLL2 generatestheclockrequiredby theDDR PHY interfaceand isalsocapableofprovidingclockstotheARM, USB, Video,orVoiceCodec modules as wellas a flexibleclockingoption.Figure3-2 representsthe clockingarchitectureforthe ARM subsystem.For more informationon deviceclockingand the system PLL controllerplease see the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

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Oscillator□(MXI1/MXO1) 19.2/24/27/36□Mhz SPI4 I2C UART0 TIMER0-3/ WDT PWM0-3 ADC RTO MMC/SD0 McBSP MMC/SD1 UART1 AEMIF SPI0-3 GPIO AINTC EMAC EDMA HPI USB□PHY USB CLKOUT0 CLKOUT1 DIV1 CLKOUT2 DDR PHY DDR2 EMIF EXTCLK PCLK VPBE VPFE ARMSSHDVICP MJCP VPSS Voice CodecDIV2 DIV3 KeyScan PRTCSS 32□Khz Oscillator PLLC1 PLLC2 VPSS_MUXSEL VENC_CLK_SRC PHYCLKSRC PRTCCLKS KEYSCLKS DDRCLKS VCLK MCLK SYSCLK1SYSCLK2SYSCLK3SYSCLK4SYSCLK5OBSCLKSYSCLK3SYSCLK2SYSCLK1SYSCLK6SYSCLK5SYSCLK4SYSCLK7OBSCLKSYSCLK9SYSCLK8SYSCLKBP TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure3-2.ClockingArchitecture

3.3.2 PLL ControllerModule

Two PLL controllersprovideclocksto differentcomponents of the chip.The PLL controller1 (PLLC1) providesclockstomost ofthecomponents ofthechip.The PLL controller2 (PLLC2) providesclocksto the DDR PHY and isalsocapableof providingclocksto the ARM, USB, VPSS or the Voice Codec modules insteadas well. As a module,thePLL controllerprovidesthefollowing:

• Glitch-freetransitions(onchangingPLL settings)
• Domain clocksalignment
• Clockgating Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 55 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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• PLL bypass
• PLL power down The variousclockoutputsgivenby thePLL controllerareas follows:
• Domain clocks:SYSCLKn
• Bypass domain clock:SYSCLKBP
• Auxiliaryclockfromreferenceclock:AUXCLK Variousdividersthatcan be used areas follows:
• Pre-PLLdivider:PREDIV
• Post-PLLdivider:POSTDIV
• SYSCLK divider:PLLDIV1,…,PLLDIVn
• SYSCLKBP divider:BPDIV The Multipliervaluessupportedarehandledby:
• PLL multipliercontrol:PLLM Notes:
• PLLCxSYSCLKy isused todenotepostdivideclockoutputSYSCLKy fromPLL controllerx
• 'x',whichdenotesPLL Controllernumber,can assume values1 and 2
• 'y',whichdenotespostdivideclockoutputs,can assume values1 to9 incase ofPLLC1 and 1 to5 in case ofPLLC2 The PLL ControllersforPLL1 and PLL2 are describedindetailintheTMS320DM36x ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

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3.3.3 PLLC1

There are two PLLs on the device,and they are independentlycontrolled.PLLC1 generatesthe frequenciesneeded forthe ARM, Video ProcessingSub System (VPSS), MJCP coprocessorblock, EDMA, and peripherals. The referenceclockforbothPLLs isthesinglecrystalinput.Both PLLs willbe ofthesame type.Itshould be noted thatthe USB2.0 PHY containsa thirdPLL embedded withinit.Table 3-2, and Figure3-3 describethecustomizationofPLLC1.

• Providesprimarysystemclock
• Softwareconfigurable
• Acceptsclockinputorinternaloscillatorinput
• PLL pre-dividervalueisprogrammable
• PLL multipliervalueisprogrammable
• PLL post-dividervalueisprogrammable.See thedatamanual forallsupportedconfigurations.
• OnlySYSCLK [9:1]areused Table3-2.PLLC1 Output Clocks PLLC1SYSCLKy Used By PLLDIV Divider PLLC1SYSCLK1 USB referenceclock(1) Programmable PLLC1SYSCLK2 ARM926EJ-S, HDVICP blockclock(1) Programmable PLLC1SYSCLK3 MJCP and HDVICP bus interfaceclock Programmable PLLC1SYSCLK4 Configurationbus clock,peripheralsysteminterfaces, Programmable EDMA PLLC1SYSCLK5 VPSS clock Programmable PLLC1SYSCLK6 VENC clock(1) Programmable PLLC1SYSCLK7 DDR 2x clock(1) Programmable PLLC1SYSCLK8 MMC/SD0 clock Programmable PLLC1SYSCLK9 CLKOUT2 Programmable PLLC1OBSCLK CLKOUT0 Programmable PLLC1SYSCLKBP USB referenceclock(1) Programmable (1) These clockoutputsaremultiplexedwithotherclocks. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 57 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

(Programmable) PLL 1 PLLEN PLLM (Programmable) Post-DIV (Programmable)OSCIN PLLDIV1* SYSCLK1 (USB□Reference□Clock) PLLDIV2* SYSCLK2□(ARM926EJ-S,□HDVICP Block□Clock) PLLDIV3* SYSCLK3□(MJCP and□HDVICP Coprocessors□Bus□Interface□Clock) PLLDIV4* SYSCLK4□(Config□Bus,□Peripheral□System Interfaces,□EDMA) PLLDIV5* SYSCLK5□(VPSS) PLLDIV6* SYSCLK6□(VENC□Clock) PLLDIV7* SYSCLK7□(DDR□2x□Clock) PLLDIV8* SYSCLK8□(MMC/SD0□Clock) PLLDIV9* SYSCLK9□(CLKOUT□2) OSCDIV1* BPDIV* OBSCLK□(CLKOUT0) SYSCLKBP ( * – Programmable USB□Reference□Clock) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure3-3.PLLC1 Configuration

3.3.4 PLLC2

PLLC2 providesthe USB referenceclock,ARM926EJ-S, DDR 2x clock,Voice Codec clockand VENC 27MHz, 74.25MHz clock.The PLLC2 functionalitycan be programmed viathe PLLC2 registers.The followinglist,Table3-3,and Figure3-4describethecustomizationofPLLC2. The PLLC2 customizationincludesthefollowingfeatures:

• PLLC2 providesDDR PHY, USB referenceclock,ARM926EJ-S clock,VENC 27MHz, 74.25Hz clock and Voicecodec clock
• Softwareconfigurable
• Acceptsclockinputorinternaloscillatorinput(thesame inputas PLLC1)
• PLL pre-dividervalueisprogrammable
• PLL multipliervalueisprogrammable
• PLL post-dividervalueisprogrammable
• OnlySYSCLK [5:1]areused Table3-3.PLLC2 Output Clocks PLLC2SYSCLKy Used by PLLDIV Divider PLLC2SYSCLK1 USB referenceclock(1) Programmable PLLC2SYSCLK2 ARM926EJ-S, HDVICP blockclock(1) Programmable PLLC2SYSCLK3 DDR 2x clock(1) Programmable PLLC2SYSCLK4 VoiceCodec clock Programmable PLLC2SYSCLK5 VENC clock(1) Programmable PLLC2OBSCLK CLKOUT1 Programmable (1) These clockoutputsaremultiplexedwithotherclocks.

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(Programmable) PLL 1 PLLEN PLLM (Programmable) Post-DIV*OSCIN PLLDIV1* SYSCLK1 (USB□Reference□Clock) PLLDIV2* SYSCLK2□(ARM926EJ-S, HDVICP Block□Clock) PLLDIV3* SYSCLK3□(DDR□2x□Clock) PLLDIV4* SYSCLK4 (Voice□Codec□Clock) PLLDIV5* SYSCLK5□(VENC□Clock) OSCDIV1* OBSCLK (CLKOUT1) * – Programmable TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure3-4.PLLC2 Configuration

3.3.5 Processing,Video,EDMA and DDR EMIF Subsystems Maximum Operating

Table3-4shows themaximum speeds supportedforeach ofthemajorblockssupportedon thedifferent speed gradedevices. Table3-4.Processing,Video,EDMA and DDR EMIF Subsystems Maximum OperatingFrequencies DM365 -216 DM365 -270 DM365 -300 ARM926 RISC 216 MHz 270 MHz 300 MHz Co-Processor(HDVICP) 173 MHz 216 MHz 270 MHz Co-Processor(MJCP) 173 MHz 216 MHz 270 MHz DDR2 173 MHz 216 MHz 270 MHz mDDR 168 MHz 168 MHz 168 MHz VPSS LogicBlock 173 MHz 216 MHz 270 MHz PeripheralSystem Bus 86.5MHz 108 MHz 135 MHzand EDMA VPBE-VENC 27 MHz 74.25MHz 74.25MHz VPFE (1) 86.5MHz 108 MHz 120 MHz (1) The pixelclock(PCLK) ofVPFE shouldmeet thefollowingconditions:PCLK <= 120MHz and PCLK < VPSS logicclock/2. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 59 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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3.3.6 PLL ControllerClockingConfigurationsExamples

The DM365 uses two PLLs togeneratethetwo fundamentalclocksused on thedevice.These two clocks feedtwo dividerblockswhichgenerateallofthefunctionalclocksused by theperipheralsand coresinthe DM365. There are some peripheralclockson the DM365 which are requiredto operateat a specific frequencyby functionalspecificationorconvention.These frequenciesaredetailedinTable3-5. Table3-5.SpecificPeripheralOperatingFrequencies Clock Required Frequency (MHz) Reason VENC (standarddefinition) 27 requiredtogeneratea validNTSC signal VENC (highdefinition) 74.25 requiredtogeneratea validATSC signal USB 36,24,or19.2 requiredby theUSB peripheraltogeneratea 48 MHz USB clock VoiceCodec 4.096 requiredtogeneratea precise16 kHz audiosample rate Table3-6,Table3-7,,and Table3-9show examples ofthePLL combinationsthatcan be supportedby DM365. Please see the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ) foradditionaldetailson specialperipherals,clockingconsiderations,and foradditionalPLL controllerconfigurationdetails. Note 1:A 300-MHz configurationispossibleusingdifferentPLL multiplier/dividercombinations.However, an externalclocksourceisrequiredtoprovide74.25MHz forHD display. Note 2: HD 720p and above displaymode resolutionsare not supportedon ARM 216-MHz clockrate devices. Note 3: There are example cases where the voicecodec samplingfrequencyislistedas 15.98 kHz or 16.002kHz. The differenceof0.125% or 0.0125% versus16 kHz specificationshouldbe acceptablefor the majorityof audioapplications.Ifthe DM365 voicecodec isrequiredto operateat precisely16 kHz thenthefunctionalclockcan be reducedtoachievepreciselythatsample frequencybuttheARM926 and HDVICP willhave torunata reducedrateresultinginlowervideoperformance. Table3-6.24-MHz InputCrystalExample (1)(2)(3) PLL1 PLL2 ARM DDR MJCP HDVICP Voice Codec (4) Video Encoder PLL Output (2M/(N+1)) PLL Output (2M/(N+1)) 27MHz 74.25MHz (5)(MHz) (MHz) 343.58 272/18 432 18/1 216 171.8 171.8 171.8 - 1/16 - 432 18/1 270 90/8 270 216 216 216 1/66(15.98 1/10 - kHz) 486 162/8 594 198/8 297 243 243 243 1/145(16.002 1/22 1/8 kHz) 540 360/16 594 396/16 297 270 270 270 1/145(16.002 1/20 1/8 kHz) (1) M = PLL controllermultiplier.N = PLL controllerdivider. (2) Allshaded frequenciesderivefromthePLL2 controller. (3) PLLC1SYSCLK4 (Configurationbus clock,peripheralsysteminterfaces,EDMA) shouldbe halfofthePLLC1SYSCLK3 (MJCP and HDVICP bus interfaceclock). (4) The VoiceCodec dividervalueisthecombinationofthePLL controller2 SYSCLK4 and PeripheralClockControlRegisterPLLDIV2 bit settingdivider. (5) PLL Outputiscalculatedby = OscillatorInput*(2M/(N+1)).

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table3-7.36-MHz InputCrystalExample (1)(2)(3) PLL1 PLL2 ARM DDR MJCP HDVICP Voice Codec (4) Video Encoder PLL Output (2M/(N+1)) PLL Output (2M/(N+1)) 27MHz 74.25MHz (5)(MHz) (MHz) 345 230/24 432 12/1 216 172.5 172.5 172.5 - 1/16 - 432 12/1 270 30/4 270 216 216 216 1/66(15.98kHz) 1/10 - 486 54/4 594 66/4 297 243 243 243 - 1/22 1/8 540 580/29 594 660/30 297 270 270 270 1/145(16.002 1/22 1/8 kHz) (1) M = PLL controllermultiplier.N = PLL controllerdivider. (2) Allshaded frequenciesderivefromthePLL2 controller. (3) PLLC1SYSCLK4 (Configurationbus clock,peripheralsysteminterfaces,EDMA) shouldbe halfofthePLLC1SYSCLK3 (MJCP and HDVICP bus interfaceclock). (4) The VoiceCodec dividervalueisthecombinationofthePLL controller2 SYSCLK4 and PeripheralClockControlRegisterPLLDIV2 bit settingdivider. (5) PLL Outputiscalculatedby = OscillatorInput*(2M/(N+1)). Table3-8.19.2-MHz InputCrystalExample (1)(2)(3) PLL1 PLL2 ARM DDR MJCP HDVICP Voice Codec (4) Video Encoder PLL Output(5) (2M/(N+1)) PLL Output (2M/(N+1)) 27MHz 74.25MHz (MHz) (MHz) 344.064 448/25 432 90/4 216 172.032 172.032 172.032 - 1/16 - 432 90/4 540 450/16 270 216 216 216 1/132(15.98 1/20 - KHz) 486 810/32 594 990/32 297 243 243 243 1/145 1/22 1/8 (16.002KHz) 540 450/16 594 990/32 297 270 270 270 1/145(16.002 1/22 1/8 KHz) 540 450/16 593.92 464/15 296.96 270 270 270 1/145 1/20 - (1) M = PLL controllermultiplier.N = PLL controllerdivider. (2) Allshaded frequenciesderivefromthePLL2 controller. (3) PLLC1SYSCLK4 (Configurationbus clock,peripheralsysteminterfaces,EDMA) shouldbe halfofthePLLC1SYSCLK3 (MJCP and HDVICP bus interfaceclock). (4) The VoiceCodec dividervalueisthecombinationofthePLL controller2 SYSCLK4 and PeripheralClockControlRegisterPLLDIV2 bit settingdivider. (5) PLL Outputiscalculatedby = OscillatorInput*(2M/(N+1)). Table3-9.27-MHz InputCrystalExample (1)(2)(3) PLL1 PLL2 ARM DDR MJCP HDVICP Voice Codec USB Video Encoder (4) PLL Output(5) (2M/(N+1)) PLL Output (2M/(N+1)) 27 MHz 74.25MHz (MHz) (MHz) 345.6 64/5 216 8/1 216 172.8 172.8 172.8 - 1/18(24MHz) 1/8 - 432 16/1 270 10/1 270 216 216 216 1/66(15.98 1/18(24MHz) 1/10 - kHz) 432 16/1 519.75 154/8 259.875 216 216 216 1/127 1/18(24MHz) 1/16 1/7 (15.98kHz) 492 164/9 594 22/1 297 246 246 246 1/145(16.002 1/41(12MHz) 1/22 1/8 kHz) 540 20/1 594 44/2 297 270 270 270 1/145(16.002 1/45(12MHz) 1/22 1/8 kHz) (1) M = PLL controllermultiplier.N = PLL controllerdivider. (2) Allshaded frequenciesderivefromthePLL2 controller. (3) PLLC1SYSCLK4 (Configurationbus clock,peripheralsysteminterfaces,EDMA) shouldbe halfofthePLLC1SYSCLK3 (MJCP and HDVICP bus interfaceclock). (4) The VoiceCodec dividervalueisthecombinationofthePLL controller2 SYSCLK4 and PeripheralClockControlRegisterPLLDIV2 bit settingdivider. (5) PLL Outputiscalculatedby = OscillatorInput*(2M/(N+1)). Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 61 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

arm_clock arm_mreset arm_power AINTC ARM module_power module_mreset MODxmodule_clock Always□on domain Interrupt PSC clksPLLC Emulation RESETN VDD DMSoC TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

3.3.7 PeripheralClockingConsiderations

The devicesupportsseveralperipheralswithspecialclockingconsiderations(VPBE, USB, Key Scan, ADC, Voice Codec, MJCP, HDVICP, AUXCLK, DDR2 EMIF). For more detailon these special considerations,see the PeripheralClockingConsiderationssectionof theTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

3.4 Power and Sleep Controller(PSC)

In the devicesystem,the Power and Sleep Controller(PSC) isresponsibleformanaging transitionsof system power on/off,clockon/off,and reset.A blockdiagramofthePSC isshown inFigure3-5.Many of theoperationsofthePSC are transparenttosoftware,such as power-on-resetoperations.However, the PSC providesyou withan interfacetocontrolseveralimportantclockand resetoperations. The PSC includesthefollowingfeatures:

• Manages chippower-on/off,clockon/off,and resets
• Providesa softwareinterfaceto: – Controlmodule clockON/OFF – Controlmodule resets
• SupportsIcePickemulationfeatures:power,clock,and reset Figure3-5.Power and Sleep Controller(PSC) For more informationon the PSC, see the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

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3.5 Pin Multiplexing

The devicemakes extensiveuse of pin multiplexingto accommodate the largenumber of peripheral functionsinthesmallestpossiblepackage.Inordertoaccomplishthis,pinmultiplexingiscontrolledusing a combinationofhardwareconfiguration(atdevicereset)and softwarecontrol.No attemptismade by the hardwaretoensurethattheproperpinmuxing has been selectedfortheperipheralsor interfacemode beingused,thusproperpinmuxing configurationistheresponsibilityoftheboardand softwaredesigners. An overviewofthepinmultiplexingisshown inTable3-10. Allpinmultiplexingoptionsare configurableby softwareviapinmux registersthatresideintheSystem ControlModule.The PinMux0 RegistercontrolstheVideoInmuxing,PinMux1 registercontrolsVideoOut signals,PinMux2 registercontrolsAEMIF signals,PinMux3 registerscontrolthemultiplexingoftheGIO signals,the PinMux4 registercontrolsthe SPI and MMC/SD0 signals.See the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 )forcompletedescriptionsofthepinmux registers. The deviceconfigurationpinsare multiplexedwithAEMIF pins.Note thatthe AECFG[2:0] inputsonly selectthe defaultAEMIF addresspinmuxing.The number of activeaddresspinsmay be increasedor reduced at any timeby modifyingthe appropriatebitsinthe PinMux2 controlregister.Afterthe device configurationpinsare sampled atreset,theyautomaticallychange tofunctionas AEMIF pins.For more detailson AEMIF defaultconfiguration,see Section3.7.5. Table3-10.PeripheralPin Mux Overview Peripheral Muxed With PrimaryFunction Secondary Function TertiaryFunction VPFE (videoin) GPIO and SPI3 GPIO VPFE (videoin) SPI3 VPBE (videoout) GPIO, PWM, and RTO GPIO VPBE (videoout) PWM & RTO AEMIF GPIO AEMIF GPIO McBSP GPIO GPIO McBSP MMC/SD0 MMC/SD0 MMC/SD1 GPIO and EMIF GPIO MMC/SD1 EMIF CLKOUT GPIO GPIO CLKOUT I2C GPIO GPIO I2C UART0/UART1 GPIO GPIO UART SPI0,SPI1,SPI2,SPI4GPIO GPIO SPI EMAC GPIO GPIO EXTINT EMAC HPI AEMIF AEMIF HPI Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 63 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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3.6 Device Reset

There are fivetypesofreset.The typesofresetdifferby how theyare initiatedand/orby theireffecton thechip.Each typeisbrieflydescribedinTable3-11and furtherdescribedintheTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ). Table3-11.Reset Types Type Initiator Effect POR (Power-On-Reset) RESET pinlowand TRST low Totalresetofthechip(coldreset). ActivatesthePOR signalon chip,whichisused toreset test/emulationlogic. Warm Reset RESET pinlow Resetseverythingexceptfortest/emulationlogic. ARM emulatorstaysaliveduringWarm reset. Max Reset ARM emulatororWatchdog Timer Same effectas warm reset. (WDT) System Reset ARM emulator A softreset. Softresetmaintainsmemory contents,and does notaffectorreset clocksorpower states. Module Reset ARM software Can independentlyapplyresettoeach module,viaan MMR. Intendedas a debug tool,and notnecessarilyforgeneraluse.

3.7 DefaultDevice Configurations

AfterPOR, warm reset,and max reset,thechipisinitsdefaultconfiguration.Thissectionhighlightsthe defaultconfigurationsassociatedwithPLLs,clocks,ARM bootmode, and AEMIF. Note: Defaultconfigurationisthe configurationimmediatelyafterPOR, warm reset,and max resetand justbeforethebootprocessbegins.The bootROM updatestheconfiguration.See Section3.2formore informationon thebootprocess.

3.7.1 Device ConfigurationPins

The deviceconfigurationpinsare describedinTable3-12.The deviceconfigurationpinsare latchedat resetand allowyou toconfigureallofthefollowingoptionsatreset:

• ARM BootMode
• AsynchronousEMIF pinconfiguration These pinsaredescribedfurtherinthefollowingsections. Note:The deviceconfigurationpinsare multiplexedwithAEMIF pins.Afterthedeviceconfigurationpins aresampled atreset,theyautomaticallychange tofunctionas AEMIF pins.Pinmultiplexingisdescribed inSection3.5. Table3-12.Device Configuration DefaultSetting(byinternal Sampled pull-up/ Device ConfigurationInput Function Pin pull-down) BTSEL[2:0] SelectsARM bootmode EM_A[13:11] 000 000 = BootfromROM (NAND) (BootfromROM -NAND) 001 = BootfromAEMIF 010 = BootfromROM (MMC/SD) 011 = BootfromROM (UART) 100 = BootfromROM (USB) 101 = BootfromROM (SPI) 110 = BootfromROM (EMAC) 111 = BootfromROM (HPI) AECFG[2:0] AEMIF Configuration(1) EM_A[10:8] 000 AECFG[2] = '0'for8-bitAEMIF configuration (8-bitNAND) AECFG[2] = '1'for16-bitAEMIF configuration (1) OthersupportedAECFG[2:0]combinationscan be foundinTable3-14.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table3-12.Device Configuration(continued) DefaultSetting(byinternal Sampled pull-up/ Device ConfigurationInput Function Pin pull-down) OSCCFG OscillatorConfiguration GIO81 0 OSCCFG = '0'formode #1 (Mode #1) OSCCFG = '1'formode #2

3.7.2 PLL Configuration

AfterPOR, warm reset,and max reset,thePLLs and clocksare settotheirdefaultconfigurations.The PLLs are inbypass mode and disabledby default.Thismeans thatthe inputreferenceclockat MXI1 (typically24 MHz) drivesthechipafterreset.For more informationon deviceclocking,see Section3.3. The defaultstateof the PLLs isreflectedinthe defaultstateof the registerbitsinthe PLLC registers. RefertotheTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ).

3.7.3 Power Domain and Module StateConfiguration

Only a subset of modules are enabled afterresetby default.Table 3-13 shows which modules are enabledafterreset.Table3-13shows thatthefollowingmodules areenableddependingon thesampled stateof the deviceconfigurationpins.For example,ifUART boot mode isBTSEL[2:0]= 011, then the defaultstateoftheUART module isenabled.For more informationon module configuration,refertothe TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ). Table3-13.LPSC Assignments and Module Configuration(1) LPSC/ MODULE MODULE NAME BTSEL [2:0] NUMBER 000 001 010 011 100 101 110 111 ROMROM ROM ROM ROM ROMAEMIF (MMC/SD0 ROM (HPI)(NAND) (UART0) (USB) (SPI0) (EMAC))

0 EDMA CC On On On On

1 EDMA TC0 On On On On

2 EDMA TC1

3 EDMA TC2

4 EDMA TC3

5 TIMER3

6 SPI1

7 MMC_SD1

8 McBSP

9 USB On

10 PWM3

11 SPI2

12 RTO

13 DDR EMIF

14 AEMIF On On

15 MMC/SD0 On

16 Reserved

17 TIMER4

18 I2C

19 UART0 On

20 UART1

21 UHPI On

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SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table3-13.LPSC Assignments and Module Configuration(1) (continued) LPSC/ MODULE MODULE NAME BTSEL [2:0] NUMBER

22 SPI0 On

23 PWM0

24 PWM1

25 PWM2

26 GPIO

27 TIMER0 On On On On On On On On

28 TIMER1

29 TIMER2 On On On On On On On On

30 SYSTEM On On On On On On On On

31 ARM On On On On On On On On

32 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

33 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

34 Reserved On On On On On On On On

35 EMULATION On On On On On On On On

36 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

37 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

38 SPI3

39 SPI4

40 EMAC On

41 RTC On On On On On On On On

42 KEYSCAN

43 ADC

44 VoiceCodec

45 VDAC CLKREC

46 VDAC CLK

47 VPSS MASTER

48 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

49 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

50 MJCP

51 HDVICP

3.7.4 ARM Boot Mode Configuration

The ARM can bootfrom eitherAsynchronousEMIF (OneNand/NOR) or from ARM ROM, as determined by thesettingofthedeviceconfigurationpinsBTSEL[2:0].The bootselectionpins(BTSEL[2:0])determine theARM bootprocess.Afterreset(POR, warm reset,or max reset),ARM program executionbeginsin ARM ROM at 0x0000:8000, exceptwhen BTSEL[2:0]= 001, indicatingAEMIF (OneNand/NOR) flash boot. Bootmodes arefurtherdescribedinSection3.2.

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3.7.5 AEMIF Configuration

3.7.5.1 AEMIF Pin Configuration

The inputpinsAECFG[2:0] determinetheAEMIF configurationimmediatelyafterreset.Pinsthatare not assignedtoanotherperipheraland notenabledas addresssignalsbecome GPIOs. These may be used as ALE and CLE signalsforNAND FlashcontrolifbootingfrominternalROM. IfbootingfromNOR Flash thentheappropriatenumber ofaddressoutputmust be enabledby theAECFG[2:0] inputsatreset.The enabledaddresssignalsarealwayscontiguousfromEM_BA[1] upwards;bitscannotbe skipped.EM_A[0] does notrepresentthelowestAEMIF addressbit.The devicehas 23 addresslinesand 2 chipselectswith an 8-bitor16-bitoption.The devicesupportsonly8-bitand 16-bitdatawidthsfortheAEMIF.

• 16-bitmode: EM_BA[1] representsthe LS address bit(the half-wordaddress)and EM_BA[0] representsaddressbit(A[14]).The maximum number of addresslinespinsin16-bitmode are 23, whichincludeEM_BA[1] + EM_A[0:13]+EM_BA[0] (aspinA[14]viaPINMUX2 register)+ EM_A[15:20] +EM_A[21] (viaPINMUX4 register) Note:PinsEM_A[15:21]areavailableby programmingthePinMux4 registerinsoftwareafterboot,but must be pulleddown externallyso thatvalidvoltagelevelsareprovidedon thefullsetofaddresspins duringboottime.EM_A[15:21]come outofresetas GPIO pinsperthePinMux4 register.
• 8-bitmode: EM_BA[1:0] representthe 2 LS address bits.Additionalselectionsare availableby programming the PinMux2 registerinsoftwareafterboot.The maximum number of addresslinesin 8-bitmode are 23, which includeEM_BA[0:1] + EM_A[0:13] + A[14] (viaPINMUX4 register)+ EM_A[15:20]. Note:PinsEM_A[15:20]areavailableby programmingthePinMux4 registerinsoftwareafterboot,but must be pulleddown externallyso thatvalidvoltagelevelsareprovidedon thefullsetofaddresspins duringboottime.EM_A[15:20]come outofresetas GPIO pinsperthePinMux4 register. For additionaldetailsabout the PinMux2 and PinMux4 registers,see the TMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ). The device'spin-mux controllogicallowsallof the Asynchronous EMIF address pinsto be used as GPIOs. Ifdevices(suchas NAND Flash)attachedto the AEMIF requirelessthan the 16 addresspins provided,then the unused upper-orderaddressesmay be configuredas GPIOs. These pinsmust be configuredatresetso thatpinsbeingdrivenby theAEMIF withaddresseswillnotcause bus contention withpinsbeingdrivenby thesystemas generalpurposeinputs. The AECFG[2:0] valuedoes notaffecttheoperationoftheAEMIF module itself,onlywhichofitsaddress bitsareseen on thedevicepins(resultinginthenaturalramificationsifdevicesdon’treceivealladdress signalsor ifcontentionwithgeneralpurpose inputsoccurs).As shown in Table 3-14, the number of addressbitsenabledon theAEMIF isselectablefrom0 to16 atboottime,see notesabove foradditional supportofup-to23 addresslines. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 67 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table3-14.AECFG (Async EMIF Configuration)Coding atBoot Time 000 001 010 100 101 110 GPIO[65] EM_A[14] EM_BA[0] GPIO[65] EM_A[14] EM_BA[0] GPIO[66] EM_BA[1] EM_BA[1] GPIO[66] EM_BA[1] EM_BA[1] GPIO[67] EM_A[0] EM_A[0] GPIO[67] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[68] EM_A[3] EM_A[3] GPIO[68] EM_A[3] EM_A[3] GPIO[69] EM_A[4] EM_A[4] GPIO[69] EM_A[4] EM_A[4] GPIO[70] EM_A[5] EM_A[5] GPIO[70] EM_A[5] EM_A[5] GPIO[71] EM_A[6] EM_A[6] GPIO[71] EM_A[6] EM_A[6] GPIO[72] EM_A[7] EM_A[7] GPIO[72] EM_A[7] EM_A[7] GPIO[73] EM_A[8] EM_A[8] GPIO[73] EM_A[8] EM_A[8] GPIO[74] EM_A[9] EM_A[9] GPIO[74] EM_A[9] EM_A[9] GPIO[75] EM_A[10] EM_A[10] GPIO[75] EM_A[10] EM_A[10] GPIO[76] EM_A[11] EM_A[11] GPIO[76] EM_A[11] EM_A[11] GPIO[77] EM_A[12] EM_A[12] GPIO[77] EM_A[12] EM_A[12] GPIO[78] EM_A[13] EM_A[13] GPIO[78] EM_A[13] EM_A[13] GPIO[57] GPIO[46] GPIO[46] EM_D[8] EM_D[8] EM_D[8] GPIO[58] GPIO[47] GPIO[47] EM_D[9] EM_D[9] EM_D[9] GPIO[59] GPIO[48] GPIO[48] EM_D[10] EM_D[10] EM_D[10] GPIO[60] GPIO[49] GPIO[49] EM_D[11] EM_D[11] EM_D[11] GPIO[61] GPIO[50] GPIO[50] EM_D[12] EM_D[12] EM_D[12] GPIO[62] GPIO[51] GPIO[51] EM_D[13] EM_D[13] EM_D[13] GPIO[63] GPIO[52] GPIO[52] EM_D[14] EM_D[14] EM_D[14] GPIO[64] GPIO[53] GPIO[53] EM_D[15] EM_D[15] EM_D[15]

3.7.5.2 AEMIF Timing Configuration

When AEMIF isenabled,thewaitstateregistersareresettotheslowestpossibleconfiguration,whichis 88 cyclesperaccess(16cyclesofsetup,64 cyclesofstrobe,and 8 cyclesofhold).Thus,witha 24 MHz clockatMXI/MXO, theAEMIF isconfiguredtorun at(12 MHz/ 88) which equalsapproximately136.36 kHz.

3.7.6 OscillatorFrequency Configuration

The oscillatorinputpins,MXI1, MXO, aredesignedtooperateintwo frequencyrangesdependingon the GIO81(OSCCFG) pinsampled atreset,whichshouldbe setaccordingtotherequiredinputfrequencyof operation.See Table3-15fordetails. Table3-15.OperationFrequency MODE GIO81 (OSCCFG) OSCILLATION 1 0 15 -35MHz 2 1 30 -40MHz The frequencyselectionpincannotbe changed dynamicallywhiletheoscillatorisrunning.They should onlybe setonce beforeoscillatorstartup. The GIO81(OSCCFG) stateislatchedduringreset,and itspecifiesthe oscillationfrequencymode as shown inTable3-15.

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3.8 Debugging Considerations

3.8.1 Pullup/PulldownResistors

Properboard designshouldensurethatinputpinstotheDMSoC devicealwaysbe ata validlogiclevel and notfloating.Thismay be achievedviapullup/pulldownresistors.The DMSoC featuresinternalpullup (IPU)and internalpulldown(IPD)resistorson most pinstoeliminatetheneed,unlessotherwisenoted,for externalpullup/pulldownresistors. An externalpullup/pulldownresistorneeds tobe used inthefollowingsituations:

• Boot and ConfigurationPins: Ifthe pin is both routedout and 3-stated(notdriven),an external pullup/pulldownresistoris strongly recommended , even ifthe IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state,use an external pullup/pulldownresistortopullthesignaltotheoppositerail. For thebootand configurationpins,iftheyare bothroutedoutand 3-stated(notdriven),itisstrongly recommended that an external pullup/pulldownresistorbe implemented. Although, internal pullup/pulldownresistorsexiston these pins and they may match the desiredconfigurationvalue, providingexternalconnectivitycan helpensurethatvalidlogiclevelsarelatchedon thesedevicebootand configurationpins.In addition,applyingexternalpullup/pulldownresistorson the boot and configuration pinsadds conveniencetotheuserindebuggingand flexibilityinswitchingoperatingmodes. Tipsforchoosingan externalpullup/pulldownresistor:
• Considerthetotalamount ofcurrentthatmay pass throughthepulluporpulldownresistor.Make sure toincludetheleakagecurrentsofallthedevicesconnectedtothenet,as wellas any internalpullupor pulldownresistors.
• Decidea targetvalueforthenet.For a pulldownresistor,thisshouldbe below thelowestVIL levelof allinputsconnectedtothenet.For a pullupresistor,thisshouldbe above thehighestVIH levelofall inputson thenet.A reasonablechoicewould be totargettheVOL orVOH levelsforthelogicfamilyof thelimitingdevice;which,by definition,have margintotheVIL and VIH levels.
• Selecta pullup/pulldownresistorwiththelargestpossiblevalue;but,whichcan stillensurethatthenet willreachthetargetpulledvaluewhen maximum currentfromalldeviceson thenetisflowingthrough the resistor.The currentto be consideredincludesleakage currentplus,any otherinternaland externalpullup/pulldownresistorson thenet.
• For bidirectionalnets,thereisan additionalconsiderationwhich setsa lowerlimiton the resistance valueoftheexternalresistor.Verifythattheresistanceissmallenough thattheweakestoutputbuffer can drivethenettotheoppositelogiclevel(includingmargin).
• Remember toincludetoleranceswhen selectingtheresistorvalue.
• Forpullupresistors,alsoremember toincludetoleranceson theDV DD rail. For most systems,a 1-kΩ resistorcan be used tooppose theIPU/IPDwhilemeetingtheabove criteria. Usersshouldconfirmthisresistorvalueiscorrectfortheirspecificapplication. For most systems,a 20-kΩ resistorcan be used tocomplimenttheIPU/IPDon thebootand configuration pinswhilemeetingtheabove criteria.Users shouldconfirmthisresistorvalueiscorrectfortheirspecific application. For more detailedinformationon inputcurrent(II),and thelow-/high-levelinputvoltages(VIL and VIH)for thedevice,see Section5.2,Recommended OperatingConditions. For the internalpullup/pulldownresistorsforalldevicepins,see the peripheral/system-specificterminal functionstable. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceConfigurations 69 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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4 System Interconnect

The deviceuses a 64-bitcrossbararchitecturetocontrolaccessbetween deviceprocessors,subsystems and peripherals.There are eleventransfermasters (TCs have separateread and writeconnections) connectedtothecrossbar;ARM, theVideoProcessingSubsystem (VPSS),themasterperipherals(USB, EMAC, HPI),and fourEDMA transfercontrollers.These can be connectedtoseven separateslaveports; ARM, the DDR EMIF, CFG bus peripherals,MJCP, and HDVICP. Not allmastersmay connectto all slaves.Connectionpathsareindicatedby √ atintersectionpointsshown inTable4-1. Table4-1.System Connection Matrix SLAVE MODULE DMA ARM Internal MPEG/JPEG HD VideoImage ConfigBus Registers DDR EMIF Master Memory Coprocessor Coprocessor and Memory Memory Memory Memory VPSS √ √ DMA MasterPeripherals √ √ (USB, EMAC, HPI)

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5 Device OperatingConditions

5.1 AbsoluteMaximum RatingsOver OperatingCase Temperature Range

(UnlessOtherwiseNoted) (1)(2) All1.2-V/1.35-Vsupplies -0.3V to1.6V Supplyvoltageranges All1.8V supplies -0.3V to2.45V All3.3V supplies -0.3V to3.8V All1.8V I/Os -0.5V to2.6V Inputvoltageranges All3.3V I/Os -0.5V to3.8V USB_VBUS 0 V to5.5V CommercialTemperatureTc 0°C to85 °C Operatingcase temperatureranges ExtendedTemperature[D versiondevices]Tc -40°C to85 °C Storagetemperatureranges Tstg -55°C to150°C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings" may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions" isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttoVSS. Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOperatingConditions 71 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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5.2 Recommended OperatingConditions

NAME DESCRIPTION MIN NOM MAX UNIT C VDD Core SupplyVoltage 216,270-MHz devices 1.14 1.2 1.26 V 300-MHz devices 1.28 1.35 1.42 PRTCSS OscillatorandVDD12_PRTCSS 216,270-MHz devices 1.14 1.2 1.26PRTCSS Core SupplyVoltage V 300-MHz devices 1.28 1.35 1.42 VDDA12_DAC 1.2-VDAC SupplyVoltage 216,270-MHz devices 1.14 1.2 1.26 V 300-MHz devices 1.28 1.35 1.42 VPP (1) VPP SupplyVoltage 216,270-MHz devices 1.14 1.2 1.26 V 300-MHz devices 1.28 1.35 1.42 VDDS18 1.8-VSupplyVoltage VDD18_PRTCSS 1.8-VPWR CTRL SupplyVoltage VDDMXI 1.8-VSystem OscillatorSupplyVoltage VDD18_DDR 1.8-VDDR2 SupplyVoltage VDDA18_PLL 1.8-VPLL SupplyVoltage 1.71 1.8 1.89 V VDDA18_USB 1.8-VUSB SupplyVoltage VDDA18_VC 1.8-VVoiceCODEC SupplyVoltage VDDA18_USB 1.8-VUSB SupplyVoltageSupply Voltage VDDA18_ADC 1.8-VADC SupplyVoltage VDDA18_DAC 1.8-VDAC SupplyVoltage VDD_AEMIF1_18_33 1.8/3.3-VswitchableEMIF1 SupplyVoltage VDD_ISIF18_33 1.8/3.3-VswitchableISIFSupplyVoltage VDDS33 3.3-VSupplyVoltage VDDA33_USB 3.3-VUSB SupplyVoltage 3.14 3.3 3.46 V VDDA33_VC 3.3-VVoiceCODEC SupplyVoltage VSS Core,USB Digitalground VSS_MX1 OSC (MX1) ground(2) VSS_32K OSC (32K)ground(2) VSSA PLL ground(3) VSSA18_USB USB ground Supply VSSA33_USB 3.3-VUSB ground 0 0 0 VGround VSSA33_VC 3.3-VVoiceCODEC ground VSSA18_VC 1.8-VVoiceCODEC ground VSSA_ADC ADC ground VSSA18_DAC 1.8-VDAC ground VSSA12_DAC 1.2-VDAC ground High-levelinputvoltage(4),excludesswitchableI/O 2 V(3.3VI/O)VoltageInput VIHHigh High-levelinputvoltage,non-DDR2 I/O,excludesswitchableI/O 0.7VDDS18 V(1.8VI/O) (1) Forproperdeviceoperation,thispinmust alwaysbe connectedtoC VDD . (2) Oscillatorgroundmust be keptseparatefromothergroundsand connecteddirectlytothecrystalloadcapacitorground(see Section6.6.1). (3) Forproperdeviceoperation,keep thispinseparatefromdigitalground. (4) These I/Ospecificationsapplytoregular3.3V I/Osand do notapplytoDDR2/mDDR, USB I/Os.DDR2/mDDR I/Osare1.8V I/Osand adheretoJESD79-2A standard,USB I/OsadheretoUSB2.0 spec.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 NAME DESCRIPTION MIN NOM MAX UNIT 0.75*VDD1High-levelinputvoltageI/O(1.2-Vor1.35-V)VIH12RTC 2_PRTCS V(PWRCNT/PWRST/RTCXI/RTCXO) S HIgh-levelswitchableinput 3.3VI/Omode 2 voltage(4) (VDD_AEMIF1_18_33,VIH1833 VVDD_AEMIF2_18_33, 1.8VI/Omode 0.7VDDS18 VDD_ISIF_18_33 powered I/Os)(5)(6)(7)(8) Low-levelinputvoltage(4),excludesswitchableI/O 0.8 V(3.3VI/O) VIL Low-levelinputvoltage(4),non-DDR2 I/O,excludesswitchableI/O 0.3*VDDS V(1.8VI/O) 18 0.25*VDD1RTC Low-levelinputvoltage(4) VIL12RTC 2_PRTCS VVoltageInput (1.2VI/O) SLow Low-levelswitchableinput 3.3VI/Omode 0.8 voltage(4) (VDD_AEMIF1_18_33,VIL1833 V0.3*VDDSVDD_AEMIF2_18_33, 1.8VI/Omode 18VDD_ISIF_18_33 powered I/Os) VREF DAC referencevoltage 475 500 525 mV R BIAS DAC full-scalecurrentadjustresistor 2376 2400 2424 Ω HD 3CH DAC (9) R LOAD_X Outputresistor 74.25 75 75.75 Ω C BG Bypass capacitor 0.1 uF R OUT Outputresistor(ROUT), between TVOUT and VFB pins 2128.5 2150 2171.5 Ω R FB Feedback resistor,between VFB and IDACOUT pins. 2079 2100 2121 VideoBuffer(9) R BIAS Full-scalecurrentadjustresistor 2400 Ω C BG Bypass capacitor 0.1 uF USB_VBUS USB externalchargepump input 0 5.25 V USB VDDA12LDO_USB InternalLDO output(10) 0.22 µF fs Samplingfrequency 8 16 kHz VoiceCodec - System clock 256fs kHz ADC FSCLK SCLK frequency 2 MHz DefaultTemperature 0 85 °C Operatingcase temperatureTemperature Tc ExtendedTemperature[D versionrange -40 85 °Cdevices] (5) VDD_AEMIF1_18_33 :can be used as a power supplyforEM_A[3:13],EM_BA0, EM_BA1, EM_CE[0],EM_ADV, EM_CLK, EM_D[8:15 ]pins,Keyscan,orGPIO pins. (6) VDD_AEMIF2_18_33: can be used as a power supplyforEM_A[0:2],EM_CE[1],EM_WE, EM_OE, EM_WAIT, EM_D[0:7]pins,HPI, Keyscan,orGPIO pins. (7) Example 1:VDD_AEMIF2_18_33 at1.8-Vfor8-bitNAND VDD_AEMIF1_18_33 at3.3-VforGPIO. Example 2:VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at1.8-Vfor16-bitNAND. (8) VDD_ISIF_18_33:can be used as a power supplyforVPFE pins(CIN[7:0],YIN[7:0],C_WE_FIELD, PCLK), orSPI3 (SPI3_SCLK,SPI3_SIMO,SPI3_SCS[0],SPI3_SCS[1])orUSBDRVVBUS orGPIO pins. (10)Forproperdeviceoperation,thispinmust be connectedtoa 0.22μF capacitortoVDDA12LDO_USB . Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOperatingConditions 73 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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5.3 ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltage

and OperatingCase Temperature (UnlessOtherwiseNoted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT High-leveloutputvoltage VDDS33 = MIN, IOH = -2mA 2.4(3.3VI/O) High-leveloutputvoltageVOH VDDS33 = MIN, IOH = -100μA 2.94 V(3.3VI/O) High-leveloutputvoltage VDDS18 -VDDS18 = MIN, IOH = -2mA(1.8VI/O) 0.45Voltage Output(2) Low-leveloutputvoltage VDDS33 = MIN, IOL = 2mA 0.4(3.3VI/O) Low-leveloutputvoltageVOL VDDS33 = MIN, IOL = 100μA 0.2 V(3.3VI/O) Low-leveloutputvoltage VDDS18 = MIN, IOH = 2mA 0.45(1.8VI/O) InputcurrentforI/OwithoutII VI= VSS toV DD ±10internalpull-up/pull-down InputcurrentforI/OwithII(pullup) VI= VSS toVDD 100internalpull-up(3)(4) InputcurrentforI/OwithCurrent II(pulldown) VI= VSS toVDD -100 μAinternalpull-down(3)(4) Input/Output IOH High-leveloutputcurrent Allperipherals -4000 IOL Low-leveloutputcurrent Allperipherals 4000 VO = VDD orVSSIOZ (5) I/Ooff-stateoutputcurrent ±20(internalpulldisabled) C I Inputcapacitance 4 Capacitance pF C O Outputcapacitance 4 Resolution Resolution 10 Bits R LOAD = 75 ΩINL Integralnon-linearity,bestfit -1.5 1.5 LSB(videobufferdisabled) R LOAD = 75 ΩDNL Differentialnon-linearity -1 1 LSB(videobufferdisabled)HD 3CH DAC VOUT Outputcompliancerange IFS = 6.67mA, R LOAD = 75 Ω 0 VREF V ZSET ZeroScaleOffsetError 0.5 % G_ERR Gain Error -5 5 % Ch_match Channelmatching +/-2 % OutputhighvoltageVOH(VIDBUF) 1.35(topof75% NTSC orPAL colorbar) V OutputlowvoltageVOL(VIDBUF) 0.35VideoBuffer (bottomofsynctip) RES Resolution 10 bits VOUT OutputVoltage R LOAD = 75 Ω 0.35 1.35 V (1) Fortestconditionsshown as MIN, MAX, orNOM, use theappropriatevaluespecifiedintherecommended operatingconditionstable. (2) These I/Ospecificationsapplytoregular3.3V and 1.8VI/Osand do notapplytoDDR2/mDDR, USB I/Os.DDR2/mDDR I/Osare1.8V I/Osand adheretoJESD79-2A standard,USB I/OsadheretoUSB2.0 spec. (3) Thisspecificationappliesonlytopinswithan internalpullup(PU)orpulldown(PD).See orSection2.8forpindescriptions. (4) To pullup a signaltotheoppositesupplyrail,a 1 kΩ resistorisrecommended. (5) IOZ appliestooutputonlypins,indicatingoff-state(Hi-Z)outputleakagecurrent.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT MIC intoADC (gain= 20 dB) Vmic Fullscaleinput 0.063 Vrms GeAD Gain error 0 dB Vcom Common voltage 0.9 V THD + N -1db,1kHz -62 dB DNR A-weighted 70 dB SNR A-weighted 67 dB Inputresistance 10 kΩ Inputcapacitance 10 pF DAC-to-LineOutput Fullscaleoutput 0.8 Vrms Gain error 0 dB Common voltage 1.5 V THD + N -60 dB DNR A-weighted 70 dB SNR A-weighted 70 dB Load resistance 10 kΩVoice Codec Load capacitance 20 pF DAC-to-Speaker Output Outputpower R L = 8Ω,THD = 10% 240 mW Outputnoise A-weighted 120 μVrms Load resistance 8 Ω Load capacitance 50 pF DecimationfilterinADC Pass band 0.375fs kHz Pass band ripple +/-0.2 dB Stopband 0.562fs kHz Stopband attenuation 40 dB HPF cutofffrequency 1.25mfs Hz InterpolationfilterinDAC Pass band 0.437fs kHz Pass band ripple +/-0.2 dB Stopband 0.562fs kHz Stopband attenuation 40 dB DNL Staticdifferentialnon-linearityerror FSCLK = 2MHz -1 2.5 LSB INL Staticintegralnon-linearityerror FSCLK = 2MHz -3 3 LSB ADC ZSET Zeroscaleoffseterror -6 6 LSB FSET Fullscaleoffseterror -6 6 LSB Copyright© 2009–2011,Texas InstrumentsIncorporated DeviceOperatingConditions 75 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Transmission□Line 4.0□pF 1.85□pF Z0□=□50 Ω (see□note) Tester Pin□Electronics Data Sheet□Timing□Reference□Point Output Under Test 42 Ω 3.5□nH Device□Pin (see□note) Vref Vref =□VIL MAX□(or□VOL MAX) Vref =□VIH MIN□(or□VOH MIN) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

6 PeripheralInformationand ElectricalSpecifications

6.1 Parameter InformationDevice-SpecificInformation

A. The data sheet providestimingat the devicepin.For outputtiminganalysis,the testerpin electronicsand its transmissionlineeffectsmust be takenintoaccount.A model ofthetesterpinelectronicsisshown inFigure6-1.A transmissionlinewitha delayof 2 ns or longercan be used to produce the desiredtransmissionlineeffect.The transmissionlineisintendedas a loadonly.Itisnotnecessarytoadd orsubtractthetransmissionlinedelay(2ns or longer)fromthedatasheettimings. Inputrequirementsinthisdatasheetaretestedwithan inputslewrateof< 4 Voltspernanosecond (4V/ns)atthe devicepinand theinputsignalsaredrivenbetween 0V and theappropriateI/Osupplyforthesignal. Figure6-1.TestLoad CircuitforAC Timing Measurements The loadcapacitancevaluestatedisonlyforcharacterizationand measurement ofAC timingsignals.This loadcapacitancevaluedoes notindicatethemaximum loadthedeviceiscapableofdriving.

6.1.1 SignalTransitionLevels

Allinputand outputtimingparametersarereferencedtoVrefforboth"0"and "1"logiclevels.For3.3V I/O, Figure6-2.Inputand Output VoltageReferenceLevelsforAC Timing Measurements Allriseand falltransitiontimingparametersare referencedto VIL MAX and VIH MIN forinputclocks, VOL MAX and VOH MIN foroutputclocks. Figure6-3.Rise and FallTransitionTime VoltageReferenceLevels

6.1.2 Timing Parameters and Board Routing Analysis

The timingparametervaluesspecifiedinthisdata sheetdo not includedelaysby board routings.As a good board designpractice,such delaysmust always be taken intoaccount.Timing valuesmay be adjustedby increasing/decreasingsuch delays.TI recommends utilizingthe availableI/O buffer informationspecification(IBIS)models toanalyzethetimingcharacteristicscorrectly.To properlyuse IBIS models to attainaccuratetiminganalysisfora givensystem,see the Using IBIS Models forTiming AnalysisApplicationReport (literaturenumber SPRA839 ).Ifneeded, externallogichardware such as buffersmay be used tocompensate any timingdifferences.

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6.2 Recommended Clock and ControlSignalTransitionBehavior

Allclocksand controlsignalsshould transitionbetween VIH and VIL (orbetween VIL and VIH) in a monotonicmanner.

6.3 Power Supplies

The power suppliesaresummarized inTable6-1. Table6-1.Power Supplies CUSTOMER TOLERANCE PACKAGE DEVICE PLANE DESCRIPTION BOARD SUPPLY PLANE 1.2Vor1.35V ±5% 1.2Vor1.35V CV DD Core power supply VDD12_PRTCSS RTC oscillatorpower supply PWR CTRL power supply PWR CTRL 1.2-Vor1.35-VI/Opower supply VDDA12_DAC DAC 1.2-Vor1.35-Vanalogpower supply VPP VPP power supply 1.8V ±5% 1.8V VDD18_PRTCSS PWR CTRL 1.8-Vpower supply VDDMXI MXI1 (oscillator)1.8-Vpower supply VDD18_SLDO Power supplyforinternalRAM Forproperdeviceoperation,thispinmust be connectedtoVDDS18 . VDD18_DDR 1.8-VDDR2 SupplyVoltage VDDA18_PLL 1.8-VPLL AnalogSupplyVoltage VDDA18_USB 1.8-VUSB AnalogSupplyVoltage VDDA18_VC 1.8-VVoiceCodec Module AnalogSupplyVoltage VDDA18_DAC 1.8-VDAC AnalogSupplyVoltage VDDS18 1.8-VSupplyVoltage VDDA18_ADC 1.8-VADC SupplyVoltage 3.3V ±5% 3.3V VDDS33 3.3-VI/OSupplyVoltage VDDA33_USB 3.3-VUSB AnalogSupplyVoltage VDDA33_VC 3.3-VVoiceCodec Module AnalogSupplyVoltage Note:Power supplyisswitchableforAEMIF and itsmultiplexed peripherals(3.3/1.8V) (2). VDD_AEMIF2_18_33 Switchable3.3/1.8-VEMIF2 SupplyVoltage(3) Note:Power supplyisswitchableforAEMIF and itsmultiplexed peripherals(3.3/1.8V) (2). VDD_ISIF18_33 Switchable3.3/1.8-VISIFSupplyVoltage(4) Note:Power supplyisswitchableforISIFand itsmultiplexed peripherals(3.3V/1.8V)(5)

0 V 0 V VSS_MX1 Oscillator(MXI1)ground

Note:Forproperdeviceoperation,connecttoexternalcrystal capacitorgroundand must be keptseparatefromothergrounds.

0 V 0 V VSS_32K Oscillator(32K)ground

Note:Forproperdeviceoperation,connecttoexternalcrystal capacitorgroundand must be keptseparatefromothergrounds.

0 V 0 V VSS Ground

(1) VDD_AEMIF1_18_33 :can be used as a power supplyforEM_A[3:13],EM_BA0, EM_BA1, EM_CE[0],EM_ADV, EM_CLK, EM_D[8:15 ]pins,Keyscan,orGPIO pins. (2) Example 1:VDD_AEMIF2_18_33 at1.8-Vfor8-bitNAND VDD_AEMIF1_18_33 at3.3-VforGPIO. Example 2:VDD_AEMIF1_18_33 and VDD_AEMIF2_18_33 at1.8-Vfor16-bitNAND. (3) VDD_AEMIF2_18_33: can be used as a power supplyforEM_A[0:2],EM_CE[1],EM_WE, EM_OE, EM_WAIT, EM_D[0:7]pins,HPI, Keyscan,orGPIO pins. (4) VDD_ISIF_18_33:can be used as a power supplyforVPFE pins(CIN[7:0],YIN[7:0],C_WE_FIELD, PCLK), orSPI3 (SPI3_SCLK,SPI3_SIMO,SPI3_SCS[0],SPI3_SCS[1])orUSBDRVVBUS orGPIO pins. (5) Example 1 VDD_ISIF_18_33 power supplycan be at1.8VforVPFE pinfunctionalityoritcan be at3.3Vifotherperipheralspinfunctionality istobe used likeSPI3 orGPIO orCLKOUT0, orUSBDRVVBUS. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 77 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-1.Power Supplies(continued) CUSTOMER TOLERANCE PACKAGE DEVICE PLANE DESCRIPTION BOARD SUPPLY PLANE

0 V 0 V VSSA PLL ground

Note:Forproperdeviceoperation,keep separatefromdigital groundVSS .

0 V 0 V VSSA18_USB USB ground

0 V 0 V VSSA33_USB 3.3-VUSB ground 0 V 0 V VSSA33_VC 3.3-VVoiceCodec Module ground 0 V 0 V VSSA18_VC 1.8-VVoiceCodec Module ground

0 V 0 V VSSA_ADC Analog-to-digitalconverter(ADC) ground

0 V 0 V VSSA18_DAC 1.8-VDAC ground 0 V 0 V VSSA12_DAC 1.2-VDAC ground VDD18_DDR *0.5 VDD18_DDR *0.5 DDR_VREF DRR referencevoltage (VDDS dividedby 2,throughboardresistors) 0.5V ±5% VREF DAC referencevoltage 5.25V USB_VBUS VBUS

6.4 Power-Supply Sequencing

In order to ensure device reliability,the device requiresthe followingpower supply power-on and power-offsequences.See Section5.2, Recommended OperatingConditions, fora descriptionof the power supplies.

• The followingpower sequencesarerecommended topreventdamage tothedevice.
• The PRTCSS coremust alwaysbe powered-onand powered-offregardlessofwhetherthePRTCSS featureisused.
• IfthePRTCSS sequenceristobe used inany PRTCSS modes, pleaserefertotheTMS320DM36x PRTCSS User'sGuide (literaturenumber SPRUFJ0 ) formore detailson thedifferencestothepower sequence.

6.4.1 Simple Power-On and Power-OffMethod

The followingstepsmust be followedinsequentialorderforthesimplepower-onmethod: 1. Power on thePRTCSS/ Main core(1.2-Vor1.35-V). 2. Power on thePRTCSS/Main I/O(1.8-V). 3. Power on theMain/AnalogI/O(3.3-V). Note forsimplepower-on:RESET must be lowuntilallsuppliesareramped up. The followingstepsshouldbe followedforthesimplepower-offmethod: 1. Power offtheMain/AnalogI/O(3.3-V). 2. Power offthePRTCSS/Main I/O(1.8-V). 3. Power offthePRTCSS/Main core(1.2-Vor1.35-V). Notes forsimplepower-off: – IfRESET islow,steps2 and 3 may be performedsimultaneously. – IfRESET isnot low,thesestepsmust be followedsequentially.

6.4.2 RestrictedPower-On and Power-OffMethod

The followingstepsshouldbe followedfortherestrictedpower-onmethod: 1. Power on thePRTCSS/ Main core(1.2-Vor1.35-V). 2. Power on thePRTCSS/Main I/O(1.8-V). 3. Power on theMain/AnalogI/O(3.3-V). Notes forrestrictedpower-on:

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 – RESET must be lowuntilallsuppliesareramped up. – Steps1,2,and 3 may be performedsimultaneouslyiftheMain corefinishesrampingup beforethe I/Osand themaximum deltavoltagedifferencebetween the1.8-Vand 3.3-VI/Osis2.0-Vuntilthe 1.8-VI/Oreachesthefullvoltage. The followingstepsshouldbe followedfortherestrictedpower-offmethod: 1. Power offMain/AnalogI/O(3.3-V). 2. Power offPRTCSS/Main I/O(1.8-V). 3. Power offPRTCSS/Main core(1.2-Vor1.35-V). Notes forrestrictedpower-off: – The 3.3-/1.8-VI/Osmay be powered offsimultaneouslyifthemaximum deltavoltagedifference between them is2.0Vuntilthe1.8-VI/Oiscompletelypowered off,and thePRTCSS/Main core must be powered down last. When bootingtheDM365 fromOneNAND, you must ensurethattheOneNAND deviceisreadywithvalid program instructionsbeforetheDM365 attemptstoreadprogram instructionsfromit.Inparticular,before you releasethedevice'sreset,you must allowtimeforOneNAND devicepower tostabilizeand forthe OneNAND deviceto completeitsinternalcopy routine.Duringthe internalcopy routine,the OneNAND devicecopiesbootcode from itsinternalnon-volatilememory toitsinternalbootmemory section.Board designerstypicallyachievethisrequirementby designofthesystem power and resetsupervisorcircuit. Refer to your OneNAND devicedatasheetforOneNAND power ramp and stabilizationtimesand for OneNAND bootcopy times.

6.4.3 Power-Supply Design Considerations

Core and I/Osupplyvoltageregulatorsshouldbe locatedclosetothedevicetominimizeinductanceand resistancein the power deliverypath.Additionally,when designingforhigh-performanceapplications utilizingthe device,the PC board shouldincludeseparatepower planesforcore,I/O,and ground,all bypassedwithhigh-qualitylow-ESL/ESR capacitors.

6.4.4 Power-Supply Decoupling

Inordertoproperlydecouplethesupplyplanesfrom system noise,placeas many capacitors(caps)as possiblecloseto the device.These caps need to be closeto the power pins,no more than 1.25 cm maximum distanceto be effective.Physicallysmallercaps,such as 0402, are betterbecause of their lowerparasiticinductance.Propercapacitancevaluesare alsoimportant.Smallbypass caps (near560 pF) shouldbe closesttothepower pins.Medium bypass caps (220nF oras largeas can be obtainedina smallpackage)shouldbe nextclosest.TI recommends no lessthan 8 smalland 8 medium caps per supplybe placedimmediatelynext to the BGA vias,usingthe "interior"BGA space and at leastthe cornersofthe"exterior". Largercaps foreach supplycan be placedfurtheraway forbulkdecoupling.Largebulkcaps (ontheorder of100 uF) shouldbe furthestaway, butstillas closeas possible.Large caps foreach supplyshouldbe placedoutsideoftheBGA footprint. Any cap selectionneeds tobe evaluatedfroma yield/manufacturingpoint-of-view.As withtheselectionof any component, verificationof capacitoravailabilityover the product’s productionlifetimeshould be considered.See also Section 6.6.1 for additionalrecommendations on power suppliesfor the oscillator/PLLsupplies. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 79 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Boot□Configuration□Pins (BTSEL[2:0],□AECFG[2:0]) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

6.5 Reset

6.5.1 Reset ElectricalData/Timing

Table6-2.Timing Requirements forReset (1)(2)(3)(seeFigure6-4) DEVICE NO. UNIT MIN MAX 1 tw(RESET) ActivelowwidthoftheRESET pulse 12C ns 2 tsu(BOOT) Setuptime,bootconfigurationpinsvalidbeforeRESET risingedge 2E ns 3 th(BOOT) Holdtime,bootconfigurationpinsvalidafterRESET risingedge 0 ns (1) BTSEL[2:0]and AECFG[2:0]arethebootconfigurationpinsduringdevicereset. (2) C = MXI1/CLKIN cycletimeinns.Forexample,when MXI1/CLKIN frequencyis24 MHz use C = 41.6 ns. (3) E = 1/PLLC1SYSCLK4 cycletimeinns. Figure6-4.Reset Timing

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MXI1/CLKIN MXO1 V SS_MX1 0.1 Fµ VDDA_PLL1 VSSA_PLL1 Crystal 19.2□MHz 24□MHz□or 36□MHz 0.1 Fµ CL C1C2 (C1 C2) TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011

6.6 Oscillatorsand Clocks

The devicehas one oscillatorinput/outputpair(MXI1/MXO1) usablewithexternalcrystalsor ceramic resonatorsto provideclockinputs.The optimalfrequenciesforthe crystalsare 19.2 MHz, 24 MHz, 27 MHz, and 36 MHz. Optionally,theoscillatorinputsareconfigurableforuse withexternalclockoscillators. Ifexternalclockoscillatorsareused,tominimizetheclockjitter,a singlecleanpower supplyshouldpower both the deviceand the externaloscillatorcircuitand the minimum CLKIN riseand falltimesmust be observed.The electricalrequirementsand characteristicsaredescribedinthissection. The timingparametersforCLKOUT[3:1] are alsodescribedinthissection.The devicehas threeoutput clockpins(CLKOUT[3:1]).See Section3.3formore informationon CLKOUT[3:1]. Note:Pleaseensurethattheappropriateoscillatorinputpin(GIO81/OSCCFG) frequencyrangesettingis setcorrectly.Formore detailson thispinsetting,see Section3.7.6.

6.6.1 MXI1 Oscillator

The MXI1 (typically24 MHz, can alsobe 19.2MHz, 27 MHz, or 36 MHz) oscillatorprovidestheprimary referenceclockforthe device.The on-chiposcillatorrequiresan externalcrystalconnectedacrossthe MXI1 and MXO1 pins,alongwithtwo loadcapacitors,as shown inFigure6-5.The externalcrystalload capacitorsmust be connectedonlytotheoscillatorgroundpin(VSS_MX1 ).Do not connecttoboardground (VSS ).Also,the PLL power pin(VDDA_PLL1 ) shouldbe connectedto the power supplythrougha ferrite bead,L1 intheexample circuitshown inFigure6-5. Note:Ifan externaloscillatoristobe used,theexternaloscillatorclocksignalshouldbe connectedtothe MXI1 pinwitha 1.8V amplitude.The MXO1 shouldbe leftunconnectedand theVSS_MX1 signalshould be connectedtoboardground(Vss). Figure6-5.MXI1 Oscillator The loadcapacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesare C1 = C2 = 10 pF).CL in the equationisthe load specifiedby the crystalmanufacturer.Alldiscrete components used to implement the oscillatorcircuitshould be placed as close as possibleto the associatedoscillatorpins(MXI1 and MXO1) and totheVSS_MX1 pin. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 81 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-3.SwitchingCharacteristicsOver Recommended OperatingConditionsforSystem Oscillator PARAMETER MIN TYP MAX UNIT Start-uptime(frompower up untiloscillatingatstablefrequency) 2 ms Oscillationfrequency 19.2/24/2 MHz CrystalESR 19 -30 MHz 60 Ω 30 -36 MHz 40 Ω Frequencystability +/-50 ppm

6.6.2 Clock PLL ElectricalData/Timing(Inputand Output Clocks)

Table6-4.Timing Requirements forMXI1/CLKIN1 (1)(2)(3)(seeFigure6-6) DEVICENO UNIT. MIN TYP MAX 1 tc(MXI1) Cycletime,MXI1/CLKIN1 27.7 52.083 ns 2 tw(MXI1H) Pulseduration,MXI1/CLKIN1 high 0.45C 0.55C ns 3 tw(MXI1L) Pulseduration,MXI1/CLKIN1 low 0.45C 0.55C ns 4 tt(MXI1) Transitiontime,MXI1/CLKIN1 .05C ns 5 tJ(MXI1) Periodjitter,MXI1/CLKIN1 .02C ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (2) C = MXI1/CLKIN1 cycletimeinns.Forexample,when MXI1/CLKIN1 frequencyis24 MHz use C = 41.6 ns. (3) tc(MXI1)= 52.083 ns,tc(MXI1)= 41.6 ns,tc(MXI1)= 37.037 ns,and tc(MXI1)= 27.7 ns aretheonlysupportedcycletimesfor MXI1/CLKIN1. Figure6-6.MXI1/CLKIN1 Timing

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-5.SwitchingCharacteristicsOver Recommended OperatingConditionsforCLKOUT0/CLKOUT1 (1) (2)(seeFigure6-7) DEVICE NO. PARAMETER UNIT MIN TYP MAX 1 tC(CLKOUT0/CLKOUT1) Cycletime,CLKOUT0/CLKOUT1 27.7 ns 2 tw(CLKOUT0H/CLKOUT1H) Pulseduration,CLKOUT0/CLKOUT1 high .45P .55P ns 3 tw(CLKOUT0L/CLKOUT1L) Pulseduration,CLKOUT0/CLKOUT1 low .45P .55P ns 4 tt(CLKOUT0/CLKOUT1) Transitiontime,CLKOUT0/CLKOUT1 3 ns Delaytime,MXI1/CLKIN1 hightoCLKOUT0/CLKOUT15 td(MXI1H-CLKOUT0H/CLKOUT1H) 1 8 nshigh Delaytime,MXI1/CLKIN1IlowtoCLKOUT0/CLKOUT16 td(MXI1L-CLKOUT0L/CLKOUT1L) 1 8 nslow (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) P = 1/CLKOUT0/1 clockfrequencyinnanoseconds(ns).Forexample,when CLKOUT1 frequencyis24 MHz use P = 41.6 ns. Figure6-7.CLKOUT1 Timing Table6-6.SwitchingCharacteristicsOver Recommended OperatingConditionsforCLKOUT2 (1)(2)(see Figure6-8) DEVICE NO. PARAMETER UNIT MIN TYP MAX 1 tC(CLKOUT2) Cycletime,CLKOUT2 20 ns 2 tw(CLKOUT2H) Pulseduration,CLKOUT2 high .45P .55P ns 3 tw(CLKOUT2L) Pulseduration,CLKOUT2 low .45P .55P ns 4 tt(CLKOUT2) Transitiontime,CLKOUT2 3 ns td(MXI1H-5 Delaytime,MXI1/CLKIN1 hightoCLKOUT2 high 1 8 ns CLKOUT2H) td(MXI1L-6 Delaytime,MXI1/CLKIN1 lowtoCLKOUT2 low 1 8 ns CLKOUT2L) (1) The referencepointsfortheriseand falltransitionsaremeasured atVOL MAX and VOH MIN. (2) P = 1/CLKOUT2 clockfrequencyinnanoseconds(ns).Forexample,when CLKOUT2 frequencyis8 MHz use P = 125 ns. Figure6-8.CLKOUT2 Timing Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

RTCXI RTCXO V SS_32k Crystal 32.768□kHz CL C1C2 (C1 C2) RTCXI TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

6.6.3 PRTCSS Oscillator

The devicehas an PRTCSS oscillatorinput/outputpair(RTCXI/RTCXO) usablewithexternalcrystalsor ceramicresonatorsto provideclockinputs.The optimalfrequencyforthe crystalis32.768 kHz. The electricalrequirementsand characteristicsare describedinthissection.Figure6-9 shows an example circuit. Figure6-9.RTCXI1 Oscillator The loadcapacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesare C1 = C2 = 2 fF).C L intheequationbelow istheloadspecifiedby thecrystalmanufacturer.Alldiscrete components used to implement the oscillatorcircuitshould be placed as close as possibleto the associatedoscillatorpins(RTCXI and RTCXO) and totheVSS_32K pin. (1)

6.6.4 PRTCSS ElectricalData/Timing

Table6-7.Timing Requirements forRTCXI (1)(2)(seeFigure6-6) DEVICE UNIT NO. MIN TYP MAX 1 tc(RTCXI) Cycletime,RTCXI 30.5175 µs 2 tw(RTCXIH) Pulseduration,RTCXI high .45C .55C ns 3 tw(RTCXIL) Pulseduration,RTCXI low .45C .55C ns (1) The referencepointsfortheriseand falltransitionsaremeasured atVILMAX and VIH MIN. (2) C = MXI1/CLKIN1 cycletimeinns.Forexample,when MXI1/CLKIN1 frequencyis24 MHz use C = 41.6 ns. Figure6-10.RTCXI Timing

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-8.SwitchingCharacteristicsOver Recommended OperatingConditionsforRTC Oscillator PARAMETER MIN TYP MAX UNIT Start-uptime(frompower up untiloscillatingatstablefrequency) 0.85 2 s Oscillationfrequency 32.768 kHz CrystalESR 70 kΩ Frequencystability +/-50 ppm The loadcapacitors,C1 and C2, shouldbe chosen such thattheequationissatisfied(typicalvaluesare C1 = C2 = 2 fF).CL in the equationis the load specifiedby the crystalmanufacturer.Alldiscrete components used to implement the oscillatorcircuitshould be placed as close as possibleto the associatedoscillatorpins(RTCXI and RTCXO) and totheVSS_MX1 pin.

6.7 Power Management and Real Time Clock Subsystem (PRTCSS)

The Power Management and Real Time ClockSubsystem (PRTCSS) isused forcalendarapplications. The PRTCSS has an independentpower supplyand can remainON whiletherestofthepower supplyis turnedOFF. The PRTCSS supportsthefollowingfeatures:

• RealTime Clock(RTC) – Simpleday counter(Up to89-years) – To generatetheAlarmeventtochecktheRTC count – 16-bitsimpletimer – Watch-dogtimertogeneratetheeventforRTC-Sequencer
• GeneralPurposeI/OwithAnti-chattering – 3-outputpins(PWRCTRO[2:0]) – 7-In/Outputpins(PWRCTRIO[6:0])
• Interrupt – 2 RTCSS interrupts(ARMSS and Timer) – 7 GPIO interrupts(PWRCTRIO[6:0]

6.7.1 PRTCSS PeripheralRegisterDescription(s)

The followingtableliststhe PRTCSS Interfaceregisters(PRTCIF) and Table 6-10 liststhe PRTCSS registerswhichcan onlybe accessedviathePRTCIF registers,theircorrespondingacronyms,and device memory locations(offsets).For more details,see the TMS320DM36x PRTCSS User'sGuide (literature number SPRUFJ0 ). Table6-9.PRTC Interface(PRTCIF)Registers Offset Acronym RegisterDescription 0x0 PID PRTCIF peripheralID register 0x4 PRTCIF_CTRL PRTCIF controlregister 0x8 PRTCIF_LDATA PRTCIF accesslowerdataregister 0xC PRTCIF_UDATA PRTCIF accessupperdataregister 0x10 PRTCIF_INTEN PRTCIF interruptenableregister 0x14 PRTCIF_INTFLG PRTCIF interruptflagregister Table6-10.Power Management and Real Time Clock Subsystem (PRTCSS) Registers Offset Acronym RegisterDescription 0x0 GO_OUT Globaloutputpinoutputdataregister 0x1 GIO_OUT Globalinput/outputpinoutputdataregister 0x2 GIO_DIR Globalinput/outputpindirectionregister 0x3 GIO_IN Globalinput/outputpininputdataregister Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-10.Power Management and Real Time Clock Subsystem (PRTCSS) Registers(continued) Offset Acronym RegisterDescription 0x4 GIO_FUNC Globalinput/outputpinfunctionregister 0x5 GIO_RISE_INT_EN GIO riseinterruptenableregister 0x6 GIO_FALL_INT_EN GIO fallinterruptenableregister 0x7 GIO_RISE_INT_FLG GIO riseinterruptflagregister 0x8 GIO_FALL_INT_FLG GIO fallinterruptflagregister 0x9 -0xA Reserved Reserved 0xB INTC_EXTENA0 EXT interruptenable0 register 0xC INTC_EXTENA1 EXT interruptenable1 register 0xD INTC_FLG0 Eventinterruptflag0 register 0xE INTC_FLG1 Eventinterruptflag1 register 0x10 RTC_CTRL RTC controlregister 0x11 RTC_WDT Watchdog timercounterregister 0x12 RTC_TMR0 Timercounter0 register 0x13 RTC_TMR1 Timercounter1 register 0x14 RTC_CCTRL Calendercontrolregister 0x15 RTC_SEC Seconds register 0x16 RTC_MIN Minutesregister 0x17 RTC_HOUR Hours register 0x18 RTC_DAY0 Days[[7:0]register 0x19 RTC_DAY1 Days[14:8]register 0x1A RTC_AMIN MinutesAlarmregister 0x1B RTC_AHOUR Hour Alarmregister 0x1C RTC_ADAY0 Days[7:0]Alarmregister 0x1D RTC_ADAY1 Days[14:8]Alarmregister 0x20 CLKC_CNT Clockcontrolregister

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6.8 General-PurposeInput/Output(GPIO)

The GPIO peripheralprovidesgeneral-purposepinsthatcan be configuredas eitherinputsor outputs. When configuredas an output,a writetoan internalregistercan controlthestatedrivenon theoutputpin. When configuredas an input,the stateof the inputisdetectableby readingthe stateof an internal register.In addition,the GPIO peripheralcan produce CPU interruptsand EDMA events in different interrupt/eventgenerationmodes. The GPIO peripheralprovidesgenericconnectionstoexternaldevices. The GPIO pinsare grouped intobanks of16 pinsper bank (i.e.,bank 0 consistsofGPIO [0:15]).There are a totalof7 GPIO banks inthedevice,because thedevicehas 104 GPIOs. For additionaldetailson GPIO pinsvoltageleveland theassociatedpower supplypleasesee Table6-11. Table6-11.GPIO Pin VoltageLeveland Power Supply Reference VoltageLevel 1.8V or 3.3V 3.3V 1.8V Power Supply Name VDD_AEMIF1_18_33 VDD_AEMIF2_18_33 VDD_ISIF18_33 VDDS33 VDD18_PRTCSS GIO[78:68] GIO[67] GIO[103:93] GIO[92:79] GIO[110:104] Pin Name GIO[66:56] GIO[55:52] GIO[49:0] GIO[51:50] The GPIO peripheralsupportsthefollowing:

• Up to104 GPIO pins,GPIO[103:0]
• Up to 7 GPIO pinsdedicatedto the PRTC Subsystem.These pinsare labeledas PWRCTRIO[6:0]. OnlyPWRCTRIO[2:0] areconnectedtotheGPIO module,labeledas GPIO[106:104].ForthePRTCSS module thePWRCTRIO[6:0] pinssupportinputand outputfunctionalitybutfortheGPIO module the GPIO[106:104]pinssupportinputfunctionalityonly.Formore detailspleaserefertoSection6.7.
• Interrupts: – Up to15 uniqueGPIO[15:0]interruptsfromBank 0. – Up to 3 unique GPIO[106:104]interruptsfrom Bank 6, dedicatedto the PRTC Subsystem. For more detailspleaserefertoSection6.7. – Interruptscan be triggeredby risingand/orfallingedge,specifiedforeach interruptcapableGPIO signal
• DMA events: – Up to15 uniqueGPIO DMA eventsfromBank 0
• Set/clearfunctionality:Firmware writes1 to correspondingbitposition(s)to set or to clearGPIO signal(s).ThisallowsmultiplefirmwareprocessestotoggleGPIO outputsignalswithoutcriticalsection protection(disableinterrupts,program GPIO, re-enableinterrupts,to preventcontextswitchingto antherprocessduringGPIO programming).
• SeparateInput/Outputregisters
• Outputregisterinadditiontoset/clearso that,ifpreferredby firmware,some GPIO outputsignalscan be toggledby directwritetotheoutputregister(s).
• Outputregister,when read,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflecting pinstatus,allowswiredlogicbe implemented. For more detailedinformationon GPIOs, see theDocumentationSupportsectionfortheGeneral-Purpose Input/Output(GPIO)ReferenceGuide. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.8.1 GPIO PeripheralRegisterDescription(s)

Table6-12liststheGPIO registers,theircorrespondingacronyms,and devicememory locations(offsets). Table6-12.General-PurposeInput/Output(GPIO)Registers OFFSET ACRONYM REGISTER DESCRIPTION 0h PID PeripheralIdentificationRegister 8h BINTEN GPIO InterruptPer-BankEnableRegister GPIO Banks 0 and 1 10h DIR01 GPIO Banks 0 and 1 DirectionRegister 14h OUT_DATA01 GPIO Banks 0 and 1 OutputData Register 18h SET_DATA01 GPIO Banks 0 and 1 SetData Register 1Ch CLR_DATA01 GPIO Banks 0 and 1 ClearData Register 20h IN_DATA01 GPIO Banks 0 and 1 InputData Register 24h SET_RIS_TRIG GPIO SetRisingEdge InterruptRegister 28h CLR_RIS_TRIG GPIO ClearRisingEdge InterruptRegister 2Ch SET_FAL_TRIG GPIO SetFallingEdge InterruptRegister 30h CLR_FAL_TRIG GPIO ClearFallingEdge InterruptRegister 34h INTSTAT GPIO InterruptStatusRegister GPIO Banks 2 and 3 38h DIR23 GPIO Banks 2 and 3 DirectionRegister 3Ch OUT_DATA23 GPIO Banks 2 and 3 OutputData Register 40h SET_DATA23 GPIO Banks 2 and 3 SetData Register 44h CLR_DATA23 GPIO Banks 2 and 3 ClearData Register 48h IN_DATA23 GPIO Banks 2 and 3 InputData Register GPIO Bank 4 and 5 60h DIR45 GPIO Bank 4 and 5 DirectionRegister 64h OUT_DATA45 GPIO Bank 4 and 5 OutputData Register 68h SET_DATA45 GPIO Bank 4 and 5 SetData Register 6Ch CLR_DATA45 GPIO Bank 4 and 5 ClearData Register 70h IN_DATA45 GPIO Bank 4 and 5 InputData Register GPIO Bank 6 88h DIR6 GPIO Bank 6 DirectionRegister 8Ch OUT_DATA6 GPIO Bank 6 OutputData Register 90h SET_DATA6 GPIO Bank 6 SetData Register 94h CLR_DATA6 GPIO Bank 6 ClearData Register 98h IN_DATA6 GPIO Bank 6 InputData Register

6.8.2 GPIO PeripheralInput/OutputElectricalData/Timing

Table6-13.Timing Requirements forGPIO Inputs(seeFigure6-11) DEVICE NO. UNIT MIN MAX 1 tw(GPIH) Pulseduration,GPIx high 12P (1) ns 2 tw(GPIL) Pulseduration,GPIx low 12P (1) ns (1) P = PLLC1.SYSCLK4 period,where SYSCLK4 isan outputclockofPLLC1. Formore details,see Section3.3,DeviceClocking.

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EXT_INTx TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-14.SwitchingCharacteristicsOver Recommended OperatingConditionsforGPIO Outputs (seeFigure6-11) DEVICE NO. PARAMETER UNIT MIN MAX 36P (1)-3 tw(GPOH) Pulseduration,GPOx high ns8 36P (1)-4 tw(GPOL) Pulseduration,GPOx low ns8 (1) P = PLLC1.SYSCLK4 period,where SYSCLK4 isan outputclockofPLLC1. Formore details,see Section3.3,DeviceClocking. Figure6-11.GPIO PortTiming

6.8.3 GPIO PeripheralExternalInterruptsElectricalData/Timing

Table6-15.Timing Requirements forExternalInterrupts/EDMAEvents(1)(seeFigure6-12) DEVICE NO. UNIT MIN MAX 1 tw(ILOW) Widthoftheexternalinterruptpulselow 2P (2) ns 2 tw(IHIGH) Widthoftheexternalinterruptpulsehigh 2P (2) ns (1) The pulsewidthgivenissufficienttogeneratean interruptoran EDMA event.However,ifa userwantsthedevicetorecognizethe GPIO changes throughsoftwarepollingoftheGPIO register,theGPIO durationmust be extendedtoallowthedeviceenough timeto accesstheGPIO registerthroughtheinternalbus. (2) P = PLLC1.SYSCLK4 period,where SYSCLK4 isan outputclockofPLLC1. Formore details,see Section3.3,DeviceClocking. Figure6-12.GPIO ExternalInterruptTiming

6.9 EDMA Controller

The EDMA controllerhandlesalldatatransfersbetween memories and thedeviceslaveperipheralson thedevice.These aresummarized as follows:

• Transferto/fromon-chipmemories – ARM program/dataRAM – HDVICP Coprocessormemory – MPEG/JPEG Coprocessormemory
• Transferto/fromexternalstorage – DDR2 /mDDR SDRAM – AsynchronousEMIF – OneNAND flash – NAND flash,NOR flash – Smart Media,SD, MMC, xD media storage Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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• Transferto/fromperipherals – McBSP – SPI – I2C – PWM – RTO – GPIO – Timer/WDT – UART – MMC/SD The EDMA Controllerconsistsof two major blocks:the TransferController(TC) and the Channel Controller(CC).The CC isa highlyflexibleChannel Controllerthatservesas theuserinterfaceand event interfaceforthe EDMA system.The CC supports64-eventchannelsand 8 QDMA channels.The CC consistsof a scalableParameter RAM (PaRAM) thatsupportsflexibleping-pong,circularbuffering, channel-chaining,auto-reloading,and memory protection. The EDMA ChannelControllerhas thefollowingfeatures:
• Fullyorthogonaltransferdescription – Threetransferdimensions – A-synchronizedtransfers:one dimensionservicedperevent – AB- synchronizedtransfers:two dimensionsservicedperevent – Independentindexeson sourceand destination – Chainingfeatureallows3-D transferbased on singleevent
• Flexibletransferdefinition – Incrementand constantaddressingmodes – Linkingmechanism allowsautomaticPaRAM setupdate – Chainingallowsmultipletransferstoexecutewithone event
• Interruptgenerationfor: – DMA completion – Errorconditions
• Debug visibility – Queue watermarking/threshold – Errorand statusrecordingtofacilitatedebug
• 64 DMA channels – Eventsynchronization – Manual synchronization(CPU(s)writetoeventsetregister) – Chainsynchronization(completionofone transferchainstonext)
• 8 QDMA channels – QDMA channelsaretriggeredautomaticallyupon writingtoa PaRAM setentry – SupportforprogrammableQDMA channeltoPaRAM mapping
• 256 PaRAM sets – Each PaRAM setcan be used fora DMA channel,QDMA channel,orlinkset(remaining)
• Fourtransfercontrollers/eventqueues.The system-levelpriorityofthesequeues isuserprogrammable
• 16 evententriespereventqueue
• Externalevents(forexample,McBSP TX Evtand RX Evt) The EDMA TransferControllerhas thefollowingfeatures:
• Fourtransfercontrollers
• 64-bitwidereadand writeportsperchannel

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• Up tofourin-flighttransferrequests(TR)
• Programmable prioritylevel
• Supports two dimensionaltransferswith independentindexes on source and destination(EDMA ChannelControllermanages the3rddimension)
• Supportforincrementand constantaddressingmodes
• Interruptand errorsupport Parameter RAM: Each EDMA is specifiedby an eightword (32-byte)parametertablecontainedin ParameterRAM (PaRAM) withintheCC. The deviceprovides256 PaRAM entries,one foreach ofthe64 DMA channelsand for8 QDMA /LinkedDMA entries. DMA Channels:Can be triggeredby: " Externalevents(forexample,McBSP TX Evt and RX Evt)," Softwarewritinga '1'tothegivenbitlocation,orchannel,oftheEventSet register,or,"Chainingtoother DMAs. QDMA: The Quick DMA (QDMA) functioniscontainedwithinthe CC. The deviceimplements8 QDMA channels.Each QDMA channelhas a selectablePaRAM entryused to specifythe transfer.A QDMA transferissubmittedimmediatelyupon writingofthe"trigger"parameter(asopposed totheoccurrenceof an eventas withEDMA). The QDMA parameterRAM may be writtenby any Configbus masterthrough theConfigBus and by DMAs throughtheConfigBus bridge. QDMA Channels:Triggeredby a configurationbus writeto a designated'QDMA triggerword'.QDMAs allowa minimum number of linearwrites(optimizedforGEM IDMA feature)to be issuedto the CC to forcea seriesoftransferstotakeplace.

6.9.1 EDMA Channel SynchronizationEvents

The EDMA supportsup to 64 EDMA channelswhich serviceperipheraldevicesand externalmemory. Table6-16 liststhesourceofEDMA synchronizationeventsassociatedwitheach oftheprogrammable EDMA channels.For the device,the associationof an eventto a channelisfixed;each of the EDMA channelshas one specificeventassociatedwithit.These specificeventsarecapturedintheEDMA event registers(ER, ERH) even iftheeventsare disabledby theEDMA eventenableregisters(EER, EERH). For more detailedinformationon the EDMA module and how EDMA events are enabled,captured, processed,linked,chained,and cleared,etc.,see theDocument SupportsectionfortheEnhanced Direct Memory Access (EDMA) ControllerReferenceGuide. Table6-16.EDMA Channel SynchronizationEvents(1)(2) EDMA EVENT NAME EVENT DESCRIPTIONCHANNEL

0 TIMER3: TEVT6 Timer3 Interrupt(TEVT6) Event

1 TIMER3 TEVT7 Timer3 Interrupt(TEVT7) Event

McBSP: XEVT or2 McBSP TransmitEventorVoiceCodec TransmitEventVoiceCodec:VCREVT McBSP :REVT or3 McBSP ReceiveEventorVoiceCodec ReceiveEventVoiceCodec:VCREVT

4 VPSS: EVT1 VPSS Event1

5 VPSS: EVT2 VPSS Event2

6 VPSS: EVT3 VPSS Event3

7 VPSS: EVT4 VPSS Event4

8 TIMER2: TEVT4 Timer2 interrupt(TEVT4) Event

(1) Inadditiontotheeventsshown inthistable,each ofthe64 channelscan alsobe synchronizedwiththetransfercompletionor intermediatetransfercompletionevents.Formore detailedinformationon EDMA event-transferchaining,see theDocument Support sectionfortheEnhanced DirectMemory Access (EDMA) ControllerReferenceGuide. (2) The totalnumber ofEDMA eventsexceeds64,whichisthemaximum valueoftheEDMA module.Therefore,severaleventsare multiplexedand you must use theregisterEDMA_EVTMUX intheSystem ControlModule toselecttheeventsourceformultiplexed events.RefertotheTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 )formore informationon theSystem ControlModule registerEDMA_EVTMUX. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-16.EDMA Channel SynchronizationEvents(1)(2) (continued) EDMA EVENT NAME EVENT DESCRIPTIONCHANNEL

9 TIMER2: TEVT5 Timer2 interrupt(TEVT5) Event

10 SPI2:SPI2XEVT SPI2 TransmitEvent

11 SPI2:SPI2REVT SPI2 ReceiveEvent

MJCP :IMX0INT or MPEG/JPEG CoprocessorIMX0INT EventorHighDefinitionVideoImage Coprocessor12 HDVICP : HDVICP_ARMINT EventHDVICP_ARMINT

13 MJCP :SEQINT MPEG/JPEG CoprocessorSEQINT Event

14 SPI1:SPI1XEVT SPI1 TransmitEvent

15 SPI1:SPI1REVT SPI1 ReceiveEvent

16 SPI0:SPI0XEVT SP0I TransmitEvent

17 SPI0:SPI0REVT SPI0 ReceiveEvent

UART0: URXEVT0 orSPI3:18 UART 0 ReceiveEventSPI3XEVT UART0: UTXEVT0 orSPI3:19 UART 0 TransmitEventSPI3REVT

20 UART1: URXEVT1 UART 1 ReceiveEvent

21 UART1: UTXEVT1 UART 1 TransmitEvent

22 TIMER4 :TEVT8 Timer4 (TEVT8) Event

23 TIMER4 :TEVT9 Timer4 (TEVT9) Event

24 RTOEVT RealTime Out Module Event

25 GPIO: GPINT9 GPIO 9 Event

26 MMC0RXEVT MMC/SD0 ReceiveEvent

27 MMC0TXEVT MMC/SD0 TransmitEvent

28 I2C :ICREVT I2C ReceiveEvent

29 I2C :ICXEVT I2C TransmitEvent

30 MMC1RXEVT MMC/SD1 ReceiveEvent

31 MMC1TXEVT MMC/SD1 TransmitEvent

32 GPIO :GPINT0 GPIO 0 Event

33 GPIO: GPINT1 GPIO 1 Event

34 GPIO :GPINT2 GPIO 2 Event

35 GPIO :GPINT3 GPIO 3 Event

36 GPIO :GPINT4 GPIO 4 Event

37 GPIO :GPINT5 GPIO 5 Event

38 GPIO :GPINT6 GPIO 6 Event

39 GPIO :GPINT7 GPIO 7 Event

GPIO :GPINT10 or40 GPIO 10 EventorEMAC EMACRXTHREESHEMACRXTHREESH GPIO :GPINT11 or41 GPIO 11 EventorEMAC EMACRXPULSEEMACRXPULSE GPIO :GPINT12 or42 GPIO 12 EventorEMAC EMACTXPULSEEMACTXPULSE GPIO :GPINT13 or43 GPIO 13 EventorEMAC EMACMISCPULSEEMACMISCPULSE

44 GPIO :GPINT14 GPIO 14 Event

45 GPIO :GPINT15 GPIO 15 Event

46 ADC :ADINT AnalogtoDigitalConverterInterruptEvent

47 GPIO :GPINT8 GPIO 8 Event

48 TIMER0 :TEVT0 Timer0 (TEVT0) Event

49 TIMER0: TEVT1 Timer1 (TEVT1) Event

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-16.EDMA Channel SynchronizationEvents(1)(2) (continued) EDMA EVENT NAME EVENT DESCRIPTIONCHANNEL

50 TIMER1: TEVT2 Timer2(TEVT2) Event

51 TIMER1: TEVT3 Timer3(TEVT3) Event

52 PWM0 PWM 0 Event

53 PWM1 orMJCP :IMX1INT PWM 1 EventorMJCP IMX1INT interrupt

54 PWM2 orMJCP :NSFINT PWM 2 EventorMJCP NSFINT interrupt

PWM3 orHDVICP(6) : MPEG/JPEG CoprocessorPWM 3 EventorHighDefinitionVideoImage Coprocessor55 CP_UNDEF CP_UNDEF Event MJCP :VLCDINT or MPEG/JPEG CoprocessorVLCDINT EventorHighDefinitionVideoImage Coprocessor56 HDVICP(5) :CP_ECDCMP CP_ECDCMP Event MJCP :BIMINT or MPEG/JPEG CoprocessorBIMINT EventorHighDefinitionVideoImage Coprocessor57 HDVICP(8) :CP_ME CP_ME Event MJCP :DCTINT or MPEG/JPEG CoprocessorDCTINT EventorHighDefinitionVideoImage Coprocessor58 HDVICP(1) :CP_CALC CP_CALC Event MJCP :QIQINT or MPEG/JPEG CoprocessorQIQINT EventorHighDefinitionVideoImage Coprocessor59 HDVICP(7) :CP_IPE CP_IPE Event MJCP :BPSINT or MPEG/JPEG CoprocessorBPSINT EventorHighDefinitionVideoImage Coprocessor60 HDVICP(2) :CP_BS CP_BS Event MJCP :VLCDERRINT or MPEG/JPEG CoprocessorVLCDERRINT EventorHighDefinitionVideoImage Coprocessor61 HDVICP(0) :CP_LPF CP_LPF Event MJCP :RCNTINT or MPEG/JPEG CoprocessorRCNTINT EventorHighDefinitionVideoImage Coprocessor62 HDVICP(3) :CP_MC CP_MC Event MJCP :COPCINT or MPEG/JPEG CoprocessorCOPCINT EventorHighDefinitionVideoImage Coprocessor63 HDVICP(4) :CP_ECDEND CP_ECDEND Event

6.9.2 EDMA PeripheralRegisterDescription(s)

Table 6-17 liststhe EDMA registers,theircorrespondingacronyms, and device memory locations (offsets). Table6-17.EDMA Registers Offset Acronym RegisterDescription 00h PID PeripheralIdentificationRegister 04h CCCFG EDMA3CC ConfigurationRegister GlobalRegisters 0200h QCHMAP0 QDMA Channel0 Mapping Register 0204h QCHMAP1 QDMA Channel1 Mapping Register 0208h QCHMAP2 QDMA Channel2 Mapping Register 020Ch QCHMAP3 QDMA Channel3 Mapping Register 0210h QCHMAP4 QDMA Channel4 Mapping Register 0214h QCHMAP5 QDMA Channel5 Mapping Register 0218h QCHMAP6 QDMA Channel6 Mapping Register 021Ch QCHMAP7 QDMA Channel7 Mapping Register 0240h DMAQNUM0 DMA Queue Number Register0 0244h DMAQNUM1 DMA Queue Number Register1 0248h DMAQNUM2 DMA Queue Number Register2 024Ch DMAQNUM3 DMA Queue Number Register3 0250h DMAQNUM4 DMA Queue Number Register4 0254h DMAQNUM5 DMA Queue Number Register5 0258h DMAQNUM6 DMA Queue Number Register6 025Ch DMAQNUM7 DMA Queue Number Register7 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-17.EDMA Registers(continued) Offset Acronym RegisterDescription 0260h QDMAQNUM QDMA Queue Number Register 0284h QUEPRI Queue PriorityRegister 0300h EMR EventMissedRegister 0304h EMRH EventMissedRegisterHigh 0308h EMCR EventMissedClearRegister 030Ch EMCRH EventMissedClearRegisterHigh 0310h QEMR QDMA EventMissedRegister 0314h QEMCR QDMA EventMissedClearRegister 0318h CCERR EDMA3CC ErrorRegister 031Ch CCERRCLR EDMA3CC ErrorClearRegister 0320h EEVAL ErrorEvaluateRegister 0340h DRAE0 DMA RegionAccess EnableRegisterforRegion0 0344h DRAEH0 DMA RegionAccess EnableRegisterHighforRegion0 ... 0350h DRAE2 DMA RegionAccess EnableRegisterforRegion2 0354h DRAEH2 DMA RegionAccess EnableRegisterHighforRegion2 0360h DRAE4 DMA RegionAccess EnableRegisterforRegion4 0364h DRAEH4 DMA RegionAccess EnableRegisterHighforRegion4 0368h DRAE5 DMA RegionAccess EnableRegisterforRegion5 036Ch DRAEH5 DMA RegionAccess EnableRegisterHighforRegion5 0380h QRAE0 QDMA RegionAccess EnableRegisterforRegion0 0388h QRAE2 QDMA RegionAccess EnableRegisterforRegion2 0390h QRAE4 0394h QRAE5 0400h-047Ch Q0E0-Q1E15 EventQueue EntryRegistersQ0E0-Q1E15 0600h QSTAT0 Queue 0 StatusRegister 0604h QSTAT1 Queue 1 StatusRegister 0608h QSTAT2 Queue 2 StatusRegister 060Ch QSTAT3 Queue 3 StatusRegister 0620h QWMTHRA Queue Watermark ThresholdA Register 0640h CCSTAT EDMA3CC StatusRegister GlobalChannel Registers 1000h ER EventRegister 1004h ERH EventRegisterHigh 1008h ECR EventClearRegister 100Ch ECRH EventClearRegisterHigh 1010h ESR EventSetRegister 1014h ESRH EventSetRegisterHigh 1018h CER ChainedEventRegister 101Ch CERH ChainedEventRegisterHigh 1020h EER EventEnableRegister 1024h EERH EventEnableRegisterHigh 1028h EECR EventEnableClearRegister 102Ch EECRH EventEnableClearRegisterHigh 1030h EESR EventEnableSetRegister 1034h EESRH EventEnableSetRegisterHigh 1038h SER SecondaryEventRegister

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-17.EDMA Registers(continued) Offset Acronym RegisterDescription 103Ch SERH SecondaryEventRegisterHigh 1040h SECR SecondaryEventClearRegister 1044h SECRH SecondaryEventClearRegisterHigh 1050h IER InterruptEnableRegister 1054h IERH InterruptEnableRegisterHigh 1058h IECR InterruptEnableClearRegister 105Ch IECRH InterruptEnableClearRegisterHigh 1060h IESR InterruptEnableSetRegister 1064h IESRH InterruptEnableSetRegisterHigh 1068h IPR InterruptPendingRegister 106Ch IPRH InterruptPendingRegisterHigh 1070h ICR InterruptClearRegister 1074h ICRH InterruptClearRegisterHigh 1078h IEVAL InterruptEvaluateRegister 1080h QER QDMA EventRegister 1084h QEER QDMA EventEnableRegister 1088h QEECR QDMA EventEnableClearRegister 108Ch QEESR QDMA EventEnableSetRegister 1090h QSER QDMA SecondaryEventRegister 1094h QSECR QDMA SecondaryEventClearRegister Shadow Region 0 Channel Registers 2000h ER EventRegister 2004h ERH EventRegisterHigh 2008h ECR EventClearRegister 200Ch ECRH EventClearRegisterHigh 2010h ESR EventSetRegister 2014h ESRH EventSetRegisterHigh 2018h CER ChainedEventRegister 201Ch CERH ChainedEventRegisterHigh 2020h EER EventEnableRegister 2024h EERH EventEnableRegisterHigh 2028h EECR EventEnableClearRegister 202Ch EECRH EventEnableClearRegisterHigh 2030h EESR EventEnableSetRegister 2034h EESRH EventEnableSetRegisterHigh 2038h SER SecondaryEventRegister 203Ch SERH SecondaryEventRegisterHigh 2040h SECR SecondaryEventClearRegister 2044h SECRH SecondaryEventClearRegisterHigh 2050h IER InterruptEnableRegister 2054h IERH InterruptEnableRegisterHigh 2058h IECR InterruptEnableClearRegister 205Ch IECRH InterruptEnableClearRegisterHigh 2060h IESR InterruptEnableSetRegister 2064h IESRH InterruptEnableSetRegisterHigh 2068h IPR InterruptPendingRegister 206Ch IPRH InterruptPendingRegisterHigh Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 95 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-17.EDMA Registers(continued) Offset Acronym RegisterDescription 2070h ICR InterruptClearRegister 2074h ICRH InterruptClearRegisterHigh 2078h IEVAL InterruptEvaluateRegister 2080h QER QDMA EventRegister 2084h QEER QDMA EventEnableRegister 2088h QEECR QDMA EventEnableClearRegister 208Ch QEESR QDMA EventEnableSetRegister 2090h QSER QDMA SecondaryEventRegister 2094h QSECR QDMA SecondaryEventClearRegister Shadow Region 1 Channel Registers 2200h ER EventRegister 2204h ERH EventRegisterHigh 2208h ECR EventClearRegister 220Ch ECRH EventClearRegisterHigh 2210h ESR EventSetRegister 2214h ESRH EventSetRegisterHigh 2218h CER ChainedEventRegister 221Ch CERH ChainedEventRegisterHigh 2220h EER EventEnableRegister 2224h EERH EventEnableRegisterHigh 2228h EECR EventEnableClearRegister 222Ch EECRH EventEnableClearRegisterHigh 2230h EESR EventEnableSetRegister 2234h EESRH EventEnableSetRegisterHigh 2238h SER SecondaryEventRegister 223Ch SERH SecondaryEventRegisterHigh 2240h SECR SecondaryEventClearRegister 2244h SECRH SecondaryEventClearRegisterHigh 2250h IER InterruptEnableRegister 2254h IERH InterruptEnableRegisterHigh 2258h IECR InterruptEnableClearRegister 225Ch IECRH InterruptEnableClearRegisterHigh 2260h IESR InterruptEnableSetRegister 2264h IESRH InterruptEnableSetRegisterHigh 2268h IPR InterruptPendingRegister 226Ch IPRH InterruptPendingRegisterHigh 2270h ICR InterruptClearRegister 2274h ICRH InterruptClearRegisterHigh 2278h IEVAL InterruptEvaluateRegister 2280h QER QDMA EventRegister 2284h QEER QDMA EventEnableRegister 2288h QEECR QDMA EventEnableClearRegister 228Ch QEESR QDMA EventEnableSetRegister 2290h QSER QDMA SecondaryEventRegister 2294h QSECR QDMA SecondaryEventClearRegister 2400h-2494h — Shadow Region2 ChannelRegisters 2600h-2694h — Shadow Region3 ChannelRegisters

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-17.EDMA Registers(continued) Offset Acronym RegisterDescription 2800h-2894h Shadow Region4 ChannelRegisters 2A00h-2A94h Shadow Region5 ChannelRegisters 2C00h-2C94h Shadow Region6 ChannelRegisters 2E00h-2E94h Shadow Region7 ChannelRegisters 4000h-4FFFh — ParameterRAM (PaRAM) Table6-18shows an abbreviationofthesetofregisterswhichmake up theparametersetforeach of512 EDMA events.Each oftheparameterregistersetsconsistof8 32-bitword entries.Table6-19shows the parametersetentryregisterswithrelativememory addresslocationswithineach oftheparametersets. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 97 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-18.EDMA Parameter Set RAM HEX ADDRESS RANGE DESCRIPTION 0x01C0 4000 -0x01C0 401F ParametersSet0 (832-bitwords) 0x01C0 4020 -0x01C0 403F ParametersSet1 (832-bitwords) 0x01C0 4040 -0x01C0 405F ParametersSet2 (832-bitwords) 0x01C0 4060 -0x01C0 407F ParametersSet3 (832-bitwords) 0x01C0 4080 -0x01C0 409F ParametersSet4 (832-bitwords) 0x01C0 40A0 -0x01C0 40BF ParametersSet5 (832-bitwords) 0x01C0 7FC0 -0x01C0 7FDF ParametersSet510 (832-bitwords) 0x01C0 7FE0 -0x01C0 7FFF ParametersSet511 (832-bitwords) Table6-19.Parameter Set Entries HEX OFFSET ADDRESS ACRONYM PARAMETER ENTRYWITHIN THE PARAMETER SET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT A Count,B Count 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceB Index,DestinationB Index 0x0014 LINK_BCNTRLD LinkAddress,B Count Reload 0x0018 SRC_DST_CIDX SourceC Index,DestinationC Index 0x001C CCNT C Count

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6.10 ExternalMemory Interface(EMIF)

The devicesupportsseveralmemory and externaldeviceinterfaces,including:

• AsynchronousEMIF (AEMIF)forinterfacingtoSRAM. – OneNAND flashmemories – NAND flashmemories – NOR flashmemories
• DDR2/mDDR Memory ControllerforinterfacingtoSDRAM.

6.10.1 Asynchronous EMIF (AEMIF)

The EMIF supportsthefollowingfeatures:

• SRAM, NOR flash,etc.on up to2 asynchronouschipselectsaddressableup to16MB each
• Supports8-bitor16-bitdatabus widths
• Programmable asynchronouscycletimings
• Supportsextendedwaitmode
• SupportsSelectStrobemode 6.10.1.1NAND (NAND, SmartMedia,xD) The NAND featuresoftheEMIF areas follows:
• NAND flashon up to2 asynchronouschipselects
• 8 and 16-bitdatabus widths
• Programmable cycletimings
• Performs1-bitand 4-bitECC calculation
• NAND Mode alsosupportsSmartMedia/SSFDC (SolidStateFloppyDiskController)and xD memory cards 6.10.1.2OneNAND The OneNAND featuressupportedareas follows.
• NAND flashon up to2 asynchronouschipselects
• Only16-bitdatabus widths
• Supportsasynchronouswritesand reads
• Supportssynchronousreadswithcontinuouslinearburstmode (Does notsupportsynchronousreads withwrap burstmodes)
• Programmable cycletimingsforeach chipselectinasynchronousmode 6.10.1.3EMIF PeripheralRegisterDescriptions Table 6-20 liststhe EDMA registers,theircorrespondingacronyms, and device memory locations (offsets). Table6-20.ExternalMemory Interface(EMIF)Registers OFFSET ACRONYM REGISTER DESCRIPTION 04h AWCCR AsynchronousWaitCycleConfiguration Register 10h A1CR Asynchronous1 ConfigurationRegister(CE0 space) 14h A2CR Asynchronous2 ConfigurationRegister(CE1 space) 40h EIRR EMIF InterruptRaw Register 44h EIMR EMIF InterruptMask Register Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-20.ExternalMemory Interface(EMIF)Registers(continued) OFFSET ACRONYM REGISTER DESCRIPTION 48h EIMSR EMIF InterruptMask SetRegister 4Ch EIMCR EMIF InterruptMask ClearRegister 5Ch ONENANDCTL OneNAND FlashControlRegister 60h NANDFCR NAND FlashControlRegister 64h NANDFSR NAND FlashStatusRegister 70h NANDF1ECC NAND Flash1-BitECC Register1 (CE0 Space) 74h NANDF2ECC NAND Flash1-BitECC Register2 (CE1 Space) BCh NAND4BITECCLOAD NANDFlash 4-BitECC Load Register C0h NAND4BITECC1 NAND Flash4-BitECC Register1 C4h NAND4BITECC2 NAND Flash4-BitECC Register2 C8h NAND4BITECC3 NAND Flash4-BitECC Register3 CCh NAND3BITECC4 NAND Flash4-BitECC Register4 D0h NANDERRADD1 NAND Flash4-BitECC ErrorAddress Register1 D4h NANDERRADD2 NAND Flash4-BitECC ErrorAddress Register2 D8h NANDERRVAL1 NAND Flash4-BitECC ErrorValueRegister DCh NANDERRVAL2 NAND Flash4-BitECC ErrorValueRegister

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6.10.1.4 AEMIF ElectricalData/Timing

Table6-21.Timing Requirements forAsynchronous Memory Cycles forAEMIF Module (1)(seeFigure6-13 and Figure6-14) DEVICENO UNIT. MIN NOM MAX READS and WRITES Pulseduration,EM_WAIT assertionand2 tw(EM_WAIT) 2E nsdeassertion READS 12 tsu(EMDV-EMOEH) Setuptime,EM_D[15:0]validbeforeEM_OE high 4 ns 13 th(EMOEH-EMDIV) Holdtime,EM_D[15:0]validafterEM_OE high 3 ns tsu SetuptimeEM_WAIT assertedbeforeEM_OE14 4E + 3 ns (EMOEL-EMWAIT) high(2) READS (OneNAND Synchronous BurstRead) Setuptime,EM_D[15:0]validbeforeEM_CLK30 tsu(EMDV-EMCLKH) 4 nshigh 31 th(EMCLKH-EMDIV) Holdtime,EM_D[15:0]validafterEM_CLK high 3 ns WRITES tsu SetuptimeEM_WAIT assertedbeforeEM_WE28 4E + 3 ns (EMWEL-EMWAIT) high(2) (1) E=2*PLL1C SYSCLK4 periodinns.See Section3.3formore information. (2) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEM_WAIT must be assertedtoadd extended waitstates.Figure6-15and Figure6-16describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringtheSTROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestartofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles. Table6-22.SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Memory Cycles forAEMIF Module (1)(2)(3)(seeFigure6-13and Figure6-14) DEVICE UNINO. PARAMETER TMIN TYP MAX READS and WRITES 1 td(TURNAROUND) Turnaroundtime (TA)*E ns READS EMIF readcycletime(EW = 0) (RS+RST+RH + 3)*E ns 3 tc(EMRCYCLE) EMIF readcycletime(EW = 1) (RS+RST+RH+3)*E ns Outputsetuptime,EM_CE[1:0]lowto (RS + 1)*E+ 3 nsEM_OE low(SS = 0) 4 tsu(EMCEL-EMOEL) Outputsetuptime,EM_CE[1:0]lowto (RS + 1)*E nsEM_OE low(SS = 1) Outputholdtime,EM_OE highto (RH + 1)*E nsEM_CE[1:0]high(SS = 0) 5 th(EMOEH-EMCEH) Outputholdtime,EM_OE highto (RH + 1)*E nsEM_CE[1:0]high(SS = 1) Outputsetuptime,EM_BA[1:0]validto6 tsu(EMBAV-EMOEL) (RS + 1)*E nsEM_OE low Outputholdtime,EM_OE highto7 th(EMOEH-EMBAIV) (RH + 1)*E nsEM_BA[1:0]invalid (1) TA = Turnaround,RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold, MEWC = Maximum externalwaitcycles.These parametersareprogrammed viatheAsynchronousBank and AsynchronousWaitCycle ConfigurationRegisters.These supportthefollowingrangeofvalues:TA[4-1],RS[16-1],RST[64-1],RH[8-1],WS[16-1],WST[64-1], WH[8-1],and MEW[1-256].See theTMS320DM36x DMSoC AsynchronousExternalMemory InterfaceUser's Guide (SPRUFI1 )for more information. (2) E=2*PLL1C SYSCLK4 periodinns.See Section3.3formore information. (3) EWC = externalwaitcyclesdeterminedby EM_WAIT inputsignal.EWC supportsthefollowingrangeofvaluesEWC[256-1].Note that themaximum waittimebeforetimeoutisspecifiedby bitfieldMEWC intheAsynchronousWaitCycleConfigurationRegister.See the TMS320DM36x DMSoC AsynchronousExternalMemory InterfaceUser's Guide (SPRUFI1 )formore information. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 101 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-22.SwitchingCharacteristicsOver Recommended OperatingConditionsforAsynchronous Memory Cycles forAEMIF Module (1)(2)(3)(seeFigure6-13and Figure6-14)(continued) DEVICE UNINO. PARAMETER TMIN TYP MAX Outputsetuptime,EM_A[21:0]validto8 tsu(EMBAV-EMOEL) (RS + 1)*E nsEM_OE low Outputholdtime,EM_OE highto9 th(EMOEH-EMAIV) (RH + 1)*E nsEM_A[21:0]invalid EM_OE activelowwidth(EW = 0) (RST)*E ns 10 tw(EMOEL) EM_OE activelowwidth(EW = 1) (RST+(EWC*16))*E ns td(EMWAITH- DelaytimefromEM_WAIT deassertedto11 4E ns EMOEH) EM_OE high READS (OneNAND Synchronous BurstRead) MH32 fc(EM_CLK) Frequency,EM_CLK 66 z 33 tc(EM_CLK) Cycletime,EM_CLK 15.15 ns tsu(EM_ADVV- Outputsetuptime,EM_ADV validbefore34 2E -2.5 ns EM_CLKH) EM_CLK high th(EM_CLKH- Outputholdtime,EM_CLK hightoEM_ADV35 2E + 3 ns EM_ADVIV) invalid tsu(EM_AV- Outputsetuptime,EM_A[21:0]/EM_BA[1]36 2E -2.5 ns EM_CLKH) validbeforeEM_CLK high th(EM_CLKH- Outputholdtime,EM_CLK highto37 2E + 3 ns EM_AIV) EM_A[21:0]/EM_BA[1]invalid 38 tw(EM_CLKH) Pulseduration,EM_CLK high 5.05 ns 39 tw(EM_CLKL) Pulseduration,EM_CLK low 5.05 ns WRITES (WS + WST + (WS + WST + EMIF writecycletime(EW = 0) WH + TA + 4)*E WH + TA + 4)*E ns -3 + 3 15 tc(EMWCYCLE) (WS + WST + (WS + WST + EMIF writecycletime(EW = 1) WH + TA + 4)*E WH + TA + 4)*E ns -3 + 3 Outputsetuptime,EM_CE[1:0]lowto (WS+1) *E -3 nsEM_WE low(SS = 0) 16 tsu(EMCEL-EMWEL) Outputsetuptime,EM_CE[1:0]lowto (WS+1) *E -3 nsEM_WE low(SS = 1) Outputholdtime,EM_WE highto (WH+1) *E -3 nsEM_CE[1:0]high(SS = 0) 17 th(EMWEH-EMCEH) Outputholdtime,EM_WE highto (WH+1) *E -3 nsEM_CE[1:0]high(SS = 1) Outputsetuptime,EM_BA[1:0]validto20 tsu(EMBAV-EMWEL) (WS+1) *E -3 nsEM_WE low Outputholdtime,EM_WE highto21 th(EMWEH-EMBAIV) (WH+1) *E -3 nsEM_BA[1:0]invalid Outputsetuptime,EM_A[21:0]validto22 tsu(EMAV-EMWEL) (WS+1) *E -3 nsEM_WE low Outputholdtime,EM_WE highto23 th(EMWEH-EMAIV) (WH+1) *E -3 nsEM_A[21:0]invalid EM_WE activelowwidth(EW = 0) (WST+1) *E -3 ns 24 tw(EMWEL) EM_WE activelowwidth(EW = 1) (WST+1) *E -3 ns td(EMWAITH- DelaytimefromEM_WAIT deassertedto25 4E + 3 ns EMWEH) EM_WE high Outputsetuptime,EM_D[15:0]validto26 tsu(EMDV-EMWEL) (WS+1) *E -3 nsEM_WE low Outputholdtime,EM_WE highto27 th(EMWEH-EMDIV) (WH+1) *E -3 nsEM_D[15:0]invalid

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EM_CE[1:0] EM_BA[1:0] EM_A[21:0] EM_OE EM_D[15:0] EM_WE EM_CE[1:0] EM_BA[1:0] EM_A[21:0] EM_WE EM_D[15:0] EM_OE TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure6-13.Asynchronous Memory Read Timing forEMIF Figure6-14.Asynchronous Memory WriteTiming forEMIF Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 103 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

EM_CE[1:0] 1 1 Asser ted Deasser ted 2214 EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_OE EM_W AIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_CE[1:0] Asser ted Deasser ted EM_BA[1:0] EM_A[21:0] EM_D[15:0] EM_WE EM_W AIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-15.EM_WAIT Read Timing Requirements Figure6-16.EM_WAIT WriteTiming Requirements

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Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+n Da+n+1 EM_CLK EM_CE[1:0] EM_ADV EM_BA0, EM_A[21:0], EM_BA1 EM_D[15:0] EM_OE EM_WAIT TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure6-17.Synchronous OneNAND FlashRead Timing Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 105 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

6.10.2 DDR2/mDDR Memory Controller

The DDR2 / mDDR Memory Controllerisa dedicatedinterfaceto DDR2 / mDDR SDRAM. Itsupports JESD79D-2A standardcompliantDDR2 SDRAM devicesand compliantMobileDDR SDRAM devices. DDR2 /mDDR SDRAM playsa key roleina device-basedsystem.Such a system isexpectedtorequire a significantamount ofhigh-speedexternalmemory forallofthefollowingfunctions:

• Bufferingofinputimage datafromsensorsorvideosources
• Intermediatebufferingforprocessing/resizingofimage dataintheVPFE
• Numerous OSD displaybuffers
• Intermediatebufferingforlargeraw Bayer data image fileswhileperformingimage processing functions
• Bufferingforintermediatedatawhileperformingvideoencode and decode functions
• Storageofexecutablecode fortheARM The DDR2 /mDDR Memory Controllersupportsthefollowingfeatures:
• JESD79D-2A standardcompliantDDR2 SDRAM
• MobileDDR SDRAM
• 256 MByte memory space
• Data bus width16 bits
• CAS latencies: – DDR2: 2,3,4,and 5 – mDDR: 2 and 3
• Internalbanks: – DDR2: 1,2,4,and 8 – mDDR: 1,2,and 4
• Burstlength:8
• Bursttype:sequential
• 1 CS signal
• Page sizes:256,512,1024,and 2048
• SDRAM autoinitialization
• Self-refreshmode
• Partialarrayself-refresh(formDDR)
• Power down mode
• Prioritizedrefresh
• Programmable refreshrateand backlogcounter
• Programmable timingparameters
• Littleendian For detailson the DDR2 Memory Controller,see the TMS320DM36x DMSoC DDR2/mDDR Memory ControllerUser'sGuide (literaturenumber SPRUFI2 ).

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DDR_CLK TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011

6.10.3 DDR2 Memory ControllerElectricalData/Timing

Table6-23.SwitchingCharacteristicsOver Recommended OperatingConditionsforDDR2 Memory Controller(1)(2)(see) NO. PARAMETER MIN MAX UNIT 1 tf(DDR_CLK) Frequency,DDR_CLK 173-DDR2 (supportedfor216-MHz device) 125 173 216-DDR2 (supportedfor270-MHz device) 125 216 MHz 270-DDR2 (supportedfor300-MHz device) 125 270 mDDR (supportedforalldevices) 90 168 (1) DDR_CLK = PLLC1.SYSCLK7/2 orPLLC2.SYSCLK3/2. (2) The PLL2 Controllermust be programmed such thattheresultingDDR_CLK clockfrequencyiswithinthespecifiedrange. Figure6-18.DDR2 Memory ControllerClock Timing 6.10.3.1DDR2/mDDR Interface This sectionprovidesthe timingspecificationforthe DDR2/mDDR interfaceas a PCB design and manufacturingspecification.The design rulesconstrainPCB tracelength,PCB traceskew, signal integrity,cross-talk,and signaltiming.These rules,when followed,resultin a reliableDDR2/mDDR memory system withouttheneed fora complex timingclosureprocess.For more informationregarding guidelinesforusingthisDDR2 specification,UnderstandingTI'sPCB RoutingRule-BasedDDR2 Timing Specification(SPRAAV0 ). 6.10.3.1.1DDR2/mDDR InterfaceSchematic Figure6-19 shows theDDR2/mDDR interfaceschematicfora single-memoryDDR2/mDDR system.The dual-memory system shown inFigure6-20. Pin numbers forthe devicecan be obtainedfrom the pin descriptionsection. 6.10.3.1.2Compatible JEDEC DDR2/mDDR Devices Table 6-24 shows the parametersof the JEDEC DDR2/mDDR devicesthatare compatiblewiththis interface.Generally,theDDR2/mDDR interfaceiscompatiblewithx16 DDR2/mDDR devices. The devicealsosupportsJEDEC DDR2/mDDR x8 devicesinthedualchipconfiguration.Inthiscase,one chipsuppliesthe upper byteand the second chipsuppliesthe lowerbyte.Addresses and most control signalsaresharedjustlikeregulardualchipmemory configurations. Table6-24.Compatible JEDEC DDR2/mDDR Devices No. Parameter Min Max Unit Notes

1 JEDEC DDR2/mDDR DeviceSpeed Grade DDR2-400 See Notes (1),

(for173MHz DDR2) (2) mDDR-400 See Notes (1), (for168MHz mDDR) (3) DDR2-533 See Notes (1), (for216MHz DDR2) (2) DDR2-667 See Notes (1), (for270MHz DDR2) (2)

2 JEDEC DDR2/mDDR DeviceBitWidth x8 x16 Bits

3 JEDEC DDR2/mDDR DeviceCount 1 2 Devices See Note (4)

(1) HigherDDR2/mDDR speed gradesaresupporteddue toinherentJEDEC DDR2/mDDR backwardscompatibility. (2) Used forDDR2. (3) Used formobileDDR. (4) Supportedconfigurationsareone 16-bitDDR2/mDDR memory ortwo 8-bitDDR2/mDDR memories. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 107 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com 6.10.3.1.3PCB Stack Up The minimum stackup requiredforroutingthe deviceisa sixlayerstackas shown in Table 6-25. Additionallayersmay be added tothePCB stackup toaccommodate othercircuitryortoreducethesize ofthePCB footprint. Table6-25.Minimum PCB Stack Up Layer Type Description

1 Signal Top RoutingMostlyHorizontal

2 Plane Ground

3 Plane Power

4 Signal InternalRouting

5 Plane Ground

6 Signal BottomRoutingMostlyVertical

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DDR_DQ00 DDR_DQ07 DDR2/mDDR DDR_DQM0 DDR_DQS0 ODT DQ0 DQ7 DDR_DQ08 DDR_DQ15 DQ8 DQ15 LDM LDQS LDQS DDR_DQM1 DDR_DQS1 UDM UDQS UDQS DDR_BA0 DDR_BA2 BA0 BA2 DDR_A00 DDR_A13 A13(C) DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE DDR_CLK DDR_CLK CK CK DDR_DQGATE0 DDR_DQGATE1 T T T T T T T T T T T T T T T T T T T T DDR_PADREF VREF(D)DDR_VREF(D) 0.1 μF (B) 0.1 μF (B) 0.1 μF (B) 50 .5 Ω % T Terminator, if desired. See terminator comments. DDR_DQSN0 DMSoC DDR_DQ00 DDR_DQ07 DDR2/mDDR DDR_DQM0 DDR_DQS0 ODT DQ0 DQ7 DDR_DQ08 DDR_DQ15 DQ8 DQ15 LDM LDQS LDQS DDR_DQM1 DDR_DQS1 UDM UDQS UDQS DDR_BA0 DDR_BA2 BA0 BA2 DDR_A00 DDR_A13 A13(C) DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE DDR_CLK DDR_CLK CK CK DDR_DQGATE0 DDR_DQGATE1 T T T T T T T T T T T T T T T T T T T T VREF(D)DDR_VREF(D) 0.1 μF (B) 0.1 μF (B) 0.1 μF (B) 50 .5 Ω % T Terminator, if desired. See terminator comments. DMSoC DDR_DQ00 DDR_DQ07 DDR2/mDDR DDR_DQM0 DDR_DQS0 ODT DQ0 DQ7 DDR_DQ08 DDR_DQ15 DQ8 DQ15 LDM LDQS LDQS DDR_DQM1 DDR_DQS1 UDM UDQS UDQS DDR_BA0 DDR_BA2 BA0 BA2 DDR_A00 DDR_A13 A13(C) DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE DDR_CLK DDR_CLK CK CK DDR_DQGATE0 DDR_DQGATE1 T T T T T T T T T T T T T T T T T T T T VREF(D)DDR_VREF(D)

1 K Ω 1%

Vio 1.8(A) VREF(D) 1 K Ω 1%0.1 μF 0.1 μF Vio 1.8(A) VREF(D) 1 K Ω 1%0.1 μF 0.1 μF VREF(D) 0.1 μF 0.1 μF 0.1 μF (B) 0.1 μF (B) 0.1 μF (B) 50 .5 Ω % T Terminator, if desired. See terminator comments. T DDR_DQSN1 T TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Completestackup specificationsareprovidedbelow. A. Vio1.8isthepower supplyfortheDDR2/mDDR memories and theDM36x DDR2/mDDR interface. B. One ofthesecapacitorscan be eliminatedifthedividerand itscapacitorsareplacedneara deviceVREF pin.Inthe Case ofmobileDDR, thesecapacitorscan be eliminatedcompletely. C. When present,A13 signalsshouldbe connected. D. VREF appliesinthecase ofDDR2 memories.For mDDR theDMSoC DDR_VREF pinstillneeds tobe connectedto thedividercircuit. Figure6-19.DDR2/mDDR Single-Memory High LevelSchematic Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 109 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

DDR_DQ00-07 Lower ByteDDR2/mDDR DDR_DQM0 DDR_DQS0 ODT DQ0 - DQ7 BA0-BA2CK CK DM DQS DQS CS CAS RAS DDR_BA0-BA2 CKE BA0-BA2 DDR_A00-A13 DDR_CLK A0-A13(C) DDR_CLK DDR_CS CK CS DDR_CAS DDR_RAS CAS RAS DDR_WE WE DDR_DQ08-15 DQS DQ0 - DQ7 DDR_DQGATE0 DDR_DQGATE1 T T T T T T T T T T T T T DDR_PADREF VREF(D) DDR_VREF(D) Vio 1.8(A) VREF(D) 1 K Ω 1%0.1 μF 0.1 μF 0.1 μF (B) 0.1 μF (B) 0.1 μF (B) 50 .5 Ω % T Terminator, if desired. See terminator comments. ODT A0-A13(C) WE VREF(D) Upper ByteDDR2/mDDR CK DDR_CKE CKET DDR_DQM1 DMT DDR_DQS1 DQST DDR_DQSN0 T DDR_DQSN1 T TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com A. Vio1.8isthepower supplyfortheDDR2/mDDR memories and theDM36x DDR2/mDDR interface. B. One ofthesecapacitorscan be eliminatedifthedividerand itscapacitorsareplacedneara deviceVREF pin.Inthe Case ofmobileDDR, thesecapacitorscan be eliminatedcompletely. C. When present,A13 signalsshouldbe connected. D. VREF appliesinthecase ofDDR2 memories.For mDDR theDMSoC DDR_VREF pinstillneeds tobe connectedto thedividercircuit. Figure6-20.DDR2/mDDR Dual-Memory High LevelSchematic

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X Y OFFSET Recommended DDR2/mDDR Device Orientation Y Y OFFSET DDR2/mDDR Device DDR2/mDDRControllerDMSoC TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-26.PCB Stack Up Specifications(1) No. Parameter Min Typ Max Unit Notes

1 PCB Routing/PlaneLayers 6

2 SignalRoutingLayers 3

3 FullgroundlayersunderDDR2/mDDR routingRegion 2

4 Number ofgroundplanecutsallowedwithinDDR routingregion 0

5 Number ofgroundreferenceplanesrequiredforeach DDR2/mDDR 1

6 Number oflayersbetween DDR2/mDDR routinglayerand reference 0

7 PCB RoutingFeatureSize 4 Mils

8 PCB TraceWidthw 4 Mils

9 DMSoC DeviceBGA pad size 0.3 mm

10 DDR2/mDDR DeviceBGA pad size See Note (2)

11 SingleEnded Impedance,Zo 50 75 Ω

12 Impedance Control Z-5 Z Z+5 Ω See Note (3)

(1) ConsultthePCB fabricatortodeterminetheirpreferenceforescape viasize. (2) PleaserefertotheDDR2/mDDR devicemanufacturerdocumentationfortheDDR2/mDDR deviceBGA pad size. (3) Z isthenominalsingledended impedance selectedforthePCB specifiedby item12. 6.10.3.1.4Placement Figure6-21 shows the requiredplacementforthe deviceas wellas the DDR2/mDDR devices.The dimensionsforFigure6-21aredefinedinTable6-27.The placementdoes notrestrictthesideofthePCB thatthe devicesare mounted on. The ultimatepurpose of the placementisto limitthe maximum trace lengthsand allowforproper routingspace. For single-memoryDDR2/mDDR systems,the second DDR2/mDDR deviceisomittedfromtheplacement. Figure6-21.DM365 and DDR2/mDDR Device Placement Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 111 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Region□should□encompass□all□DDR2/mDDR□circuitry□and□varies depending□on□placement.□Non-DDR2/mDDR□signals□should□not□be routed□on□the□DDR□signal□layers□within□the□DDR2/mDDR□keep□out region.□Non-DDR2/mDDR□signals□may□be□routed□in□the□region provided□they□are□routed□on□layers□separated□from□DDR2/mDDR signal□layers□by□a□ground□layer.□No□breaks□should□be□allowed□in□the reference□ground□layers□in□this□region.□In□addition,□the□1.8□V□power plane□should□cover□the□entire□keep□out□region. TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-27.Placement Specifications No. Parameter Min Max Unit Notes

1 X 1750 Mils See Notes (1),(2)

2 Y 1280 Mils See Notes (1),(2)

3 Y Offset 650 Mils See Notes (1).(2), (3)

4 DDR2/mDDR KeepoutRegion See Note (4)

5 Clearancefromnon-DDR2/mDDR signaltoDDR2/mDDR KeepoutRegion 4 w See Note (5)

(1) See Figure6-19fordimensiondefinitions. (2) Measurements fromcenterofDMSoC devicetocenterofDDR2/mDDR device. (3) Forsinglememory systemsitisrecommended thatY Offsetbe as smallas possible. (4) DDR2/mDDR Keepoutregiontoencompass entireDDR2/mDDR routingarea (5) Non-DDR2/mDDR signalsallowedwithinDDR2/mDDR keepoutregionprovidedtheyareseparatedfromDDR2/mDDR routinglayersby a groundplane. 6.10.3.1.5DDR2/mDDR Keep Out Region The regionof the PCB used forthe DDR2/mDDR circuitrymust be isolatedfrom othersignals.The DDR2/mDDR keep out regionisdefinedforthispurpose and isshown inFigure6-22. The sizeof this regionvarieswiththeplacementand DDR routing.Additionalclearancesrequiredforthekeep outregion areshown inTable6-27. Figure6-22.DDR2/mDDR Keepout Region

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 6.10.3.1.6Bulk Bypass Capacitors Bulk bypass capacitorsare requiredformoderate speed bypassingof the DDR2/mDDR and other circuitry.Table 6-28 containsthe minimum numbers and capacitancerequiredforthe bulk bypass capacitors.Note thatthistableonlycoversthebypass needs oftheDMSoC and DDR2/mDDR interfaces. Additionalbulkbypasscapacitancemay be needed forothercircuitry. Table6-28.Bulk Bypass Capacitors No. Parameter Min Max Unit Notes

1 VDD18_DDR BulkBypass CapacitorCount 3 Devices See Note

(1)

2 VDD18_DDR BulkBypass TotalCapacitance 30 uF

3 DDR#1 BulkBypass CapacitorCount 1 Devices See Note

(1)

4 DDR#1 BulkBypass TotalCapacitance 22 uF

5 DDR#2 BulkBypass CapacitorCount 1 Devices See Notes

(1),(2)

6 DDR#2 BulkBypass TotalCapacitance 22 uF See Note

(2) (1) These devicesshouldbe placednearthedevicetheyarebypassing,butpreferenceshouldbe giventotheplacementofthehigh-speed (HS)bypasscaps. (2) Onlyused on dual-memorysystems Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 113 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com 6.10.3.1.7High-Speed Bypass Capacitors High-speed (HS) bypass capacitorsare criticalfor proper DDR2/mDDR interfaceoperation.It is particularlyimportant to minimize the parasiticseries inductance of the HS bypass cap, DMSoC/DDR2/mDDR power, and DMSoC/DDR2/mDDR ground connections.Table 6-29 containsthe specificationfortheHS bypasscapacitorsas wellas forthepower connectionson thePCB. 6.10.3.1.8Net Classes Table 6-30 liststhe clocknet classesforthe DDR2/mDDR interface.Table 6-31 liststhe signalnet classes,and associatedclocknetclasses,forthesignalsintheDDR2/mDDR interface.These netclasses areused fortheterminationand routingrulesthatfollow. Table6-29.High-Speed Bypass Capacitors No. Parameter Min Max Unit Notes

1 HS Bypass CapacitorPackage Size 0402 10 Mils See Note (1)

2 DistancefromHS bypasscapacitortodevicebeingbypassed 250 Mils

3 Number ofconnectionviasforeach HS bypasscapacitor 2 Vias See Note (2)

4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 1 30 Mils

5 Number ofconnectionviasforeach DDR2/mDDR devicepower orgroundballs 1 Vias

6 TracelengthfromDDR2/mDDR devicepower balltoconnectionvia 35 Mils

7 VDD18_DDR HS Bypass CapacitorCount 10 Devices See Note (3)

8 VDD18_DDR HS Bypass CapacitorTotalCapacitance 1.2 uF

9 DDR#1 HS Bypass CapacitorCount 8 Devices See Note (3)

10 DDR#1 HS Bypass CapacitorTotalCapacitance 0.4 uF

11 DDR#2 HS Bypass CapacitorCount 8 Devices See Notes

(3),(4) 12 DDR#2 HS Bypass CapacitorTotalCapacitance 0.4 uF See Note (4) (1) LxW, 10 milunits,i.e.,a 0402 isa 40x20 milsurfacemount capacitor (2) An additionalHS bypasscapacitorcan sharetheconnectionviasonlyifitismounted on theoppositesideoftheboard. (3) These devicesshouldbe placedas closeas possibletothedevicebeingbypassed. (4) Onlyused on dual-memorysystems

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-30.Clock Net Class Definitions Clock Net Class DMSoC Pin Names CK DDR_CLK/ DDR_CLK DQS0 DDR_DQS0/DDR_DQSN0 DQS1 DDR_DQS1/DDR_DQSN1 Table6-31.SignalNet Class Definitions AssociatedClock Net Clock Net Class Class DMSoC Pin Names ADDR_CTRL CK DDR_BA[2:0],DDR_A[13:0],DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE DQ0 DQS0 DDR_DQ[7:0],DDR_DQM0 DQ1 DQS1 DDR_DQ[15:8],DDR_DQM1 DQGATE CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1 6.10.3.1.9DDR2/mDDR SignalTermination No terminationsof any kindare requiredinorderto meet signalintegrityand overshootrequirements. Serialterminatorsare permitted,ifdesired,toreduceEMI risk;however,serialterminationsare theonly typepermitted.Table6-32shows thespecificationsfortheseriesterminators. Table6-32.DDR2/mDDR SignalTerminations No. Parameter Min Typ Max Unit Notes

1 CK Net Class 0 10 Ω See Note (1)

2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes (1),

(2),(3)

3 Data ByteNet Classes(DQS0-DQS1, DQ0-DQ1) 0 22 Zo Ω See Notes (1),

(2),(3),(4)

4 DQGATE Net Class(DQGATE) 0 10 Zo Ω See Notes (1),

(2),(3) (1) Onlyseriesterminationispermitted,parallelorSST specificallydisallowed. (2) Terminatorvalueslargerthantypicalonlyrecommended toaddressEMI issues. (3) Terminationvalueshouldbe uniformacrossnetclass. (4) When no terminationisused on datalines(0Ωs),theDDR2/mDDR devicesmust be programmed tooperatein60% strengthmode. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 115 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized. C B A T DDR2/mDDRController DMSoC TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com 6.10.3.1.10VREF Routing VREF isused as a referenceby theinputbuffersoftheDDR2/mDDR memories as wellas thedevice. VREF isintendedtobe theDDR2/mDDR power supplyvoltageand shouldbe createdusinga resistive divideras shown inFigure6-19. Other methods of creatingVREF are not recommended. Figure6-23 shows thelayoutguidelinesforVREF. Figure6-23.VREF Routing and Topology 6.10.3.1.11DDR2/mDDR CK and ADDR_CTRL Routing Figure6-24 shows thetopologyoftheroutingfortheCK and ADDR_CTRL netclasses.The routeisa balancedT as itisintendedthatthelengthofsegments B and C be equal.Inaddition,thelengthofA shouldbe maximized. Figure6-24.CK and ADDR_CTRL Routing and Topology

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T T DMSoC T DDR2/mDDRController T TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-33.CK and ADDR_CTRL Routing Specification(1) No Parameter Min Typ Max Unit Notes

1 CentertocenterDQS-DQSN spacing 2w

2 CK A toB/A toC Skew LengthMismatch 25 Mils See Note (1)

3 CK B toC Skew LengthMismatch 25 Mils

4 CentertocenterCK tootherDDR2/mDDR tracespacing 4w See Note (2)

5 CK/ADDR_CTRL nominaltracelength CACLM-50 CACLM CACLM+50 Mils See Note (3)

6 ADDR_CTRL toCK Skew LengthMismatch 100 Mils

7 ADDR_CTRL toADDR_CTRL Skew LengthMismatch 100 Mils

8 CentertocenterADDR_CTRL tootherDDR2/mDDR 4w See Note (2)

9 CentertocenterADDR_CTRL tootherADDR_CTRL 3w See Note (2)

10 ADDR_CTRL A toB/A toC Skew LengthMismatch 100 Mils See Note (1)

11 ADDR_CTRL B toC Skew LengthMismatch 100 Mils

(1) Seriesterminator,ifused,shouldbe locatedclosesttoDMSoC. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) CACLM isthelongestManhattandistanceoftheCK and ADDR_CTRL netclasses. Figure6-25shows thetopologyand routingfortheDQS and DQ netclasses;theroutesarepointtopoint. Skew matchingacrossbytesisnotneeded norrecommended. Figure6-25.DQS and DQ Routing and Topology Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 117 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

T T FL FH DDR2/mDDRController DMSoC TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-34.DQS and DQ Routing Specification No. Parameter Min Typ Max Unit Notes

2 DQS E Skew LengthMismatch 25 Mils

3 CentertocenterDQS tootherDDR2/mDDR tracespacing 4w See Note (1)

4 DQS/DQ nominaltracelength DQLM-50 DQLM DQLM+50 Mils See Notes (2),(3)

5 DQ toDQS Skew LengthMismatch 100 Mils See Note (3)

6 DQ toDQ Skew LengthMismatch 100 Mils See Note (3)

7 CentertocenterDQ tootherDDR2/mDDR tracespacing 4w See Notes (1),(4)

8 CentertoCenterDQ tootherDQ tracespacing 3w See Notes (5),(1)

9 DQ/DQS E Skew LengthMismatch 100 Mils See Note (3)

(1) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (2) Seriesterminator,ifused,shouldbe locatedclosesttoDDR. (3) Thereisno need and itisnotrecommended toskew match acrossdatabytes,i.e.,fromDQS0 and databyte0 toDQS1 and databyte (4) DQ 's fromotherDQS domains areconsideredotherDDR2/mDDR trace. (5) DQLM isthelongestManhattandistanceofeach oftheDQS and DQ netclasses. Figure6-26shows theroutingfortheDQGATE netclasses.Table6-35containstheroutingspecification. Figure6-26.DQGATE Routing

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-35.DQGATE Routing Specification No. Parameter Min Typ Max Unit Notes

1 DQGATE LengthF CKB0B1 See Note (1)

3 CentertocenterDQGATE toany othertracespacing 4w

4 DQS/DQ nominaltracelength DQLM-50 DQLM DQLM+50 Mils

5 DQGATE Skew 100 Mils See Note (2)

(1) CKB0B1 isthesum ofthelengthoftheCK netplustheaveragelengthoftheDQS0 and DQS1 nets. (2) Skew fromCKB0B1 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 119 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.11 MMC/SD

The deviceincludesMMC/SD Controllerswhich are compliantwithMMC V3.31,Secure DigitalPart1 PhysicalLayerSpecificationV1.1and SecureDigitalInputOutput(SDIO)V2.0specifications. The deviceMMC/SD Controllerhas followingfeatures:

• MultiMediaCard(MMC)
• SecureDigital(SD)Memory Card
• MMC/SD protocolsupport
• SDIO protocolsupport
• Programmable clockfrequency
• 512 bitRead/WriteFIFO tolowersystemoverhead
• SlaveEDMA transfercapability
• SD HighCapacitysupport The deviceMMC/SD Controllerdoes notsupportSPI mode.

6.11.1 MMC/SD PeripheralRegisterDescription(s)

Table 6-36 liststhe MMC/SD registers,theircorrespondingacronyms, and devicememory locations (offsets). Table6-36.MultimediaCard/SecureDigital(MMC/SD) Card ControllerRegisters OFFSET ACRONYM REGISTER DESCRIPTION 00h MMCCTL MMC ControlRegister 04h MMCCLK MMC Memory ClockControlRegister 08h MMCST0 MMC StatusRegister0 0Ch MMCST1 MMC StatusRegister1 10h MMCIM MMC InterruptMask Register 14h MMCTOR MMC Response Time-OutRegister 18h MMCTOD MMC Data Read Time-OutRegister 1Ch MMCBLEN MMC BlockLengthRegister 20h MMCNBLK MMC Number ofBlocksRegister 24h MMCNBLC MMC Number ofBlocksCounterRegister 28h MMCDRR MMC Data ReceiveRegister 2Ch MMCDXR MMC Data TransmitRegister 30h MMCCMD MMC Command Register 34h MMCARGHL MMC Argument Register 38h MMCRSP01 MMC Response Register0 and 1 3Ch MMCRSP23 MMC Response Register2 and 3 40h MMCRSP45 MMC Response Register4 and 5 44h MMCRSP67 MMC Response Register6 and 7 48h MMCDRSP MMC Data Response Register 50h MMCCIDX MMC Command IndexRegister 64h SDIOCTL SDIO ControlRegister 68h SDIOST0 SDIO StatusRegister0 6Ch SDIOIEN SDIO InterruptEnableRegister 70h SDIOIST SDIO InterruptStatusRegister 74h MMCFIFOCTL MMC FIFO ControlRegister

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ST ART XMIT V alid Valid Valid END SD_CLK SD_CMD 13 13 13 ST ART XMIT V alid Valid Valid END SD_CLK SD_CMD 1097 ST ART D0 D1 Dx END SD_CLK SD_DA Tx 1414 14 14 TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011

6.11.2 MMC/SD ElectricalData/Timing

Table6-37.Timing Requirements forMMC/SD Module (seeFigure6-28and Figure6-30) DEVICE NO. FAST MODE STANDARD MODE UNIT MIN MAX MIN MAX 1 tsu(CMDV-CLKH) Setuptime,SD_CMD validbeforeSD_CLK high 2.7 2.7 ns 2 th(CLKH-CMDV) Holdtime,SD_CMD validafterSD_CLK high 2.5 2.5 ns 3 tsu(DATV-CLKH) Setuptime,SD_DATx validbeforeSD_CLK high 2.7 2.7 ns 4 th(CLKH-DATV) Holdtime,SD_DATx validafterSD_CLK high 2.5 2.5 ns Table6-38.SwitchingCharacteristicsOver Recommended OperatingConditionsforMMC/SD Module (seeFigure6-27through Figure6-30) DEVICE STANDARDNO. PARAMETER FAST MODE UNITMODE MIN MAX MIN MAX 7 f(CLK) Operatingfrequency,SD_CLK 0 50 0 25 MHz 8 f(CLK_ID) Identificationmode frequency,SD_CLK 0 400 0 400 KHz 9 tW(CLKL) Pulsewidth,SD_CLK low 6.5 6.5 ns 10 tW(CLKH) Pulsewidth,SD_CLK high 6.5 6.5 ns 11 tr(CLK) Risetime,SD_CLK 3 3 ns 12 tf(CLK) Falltime,SD_CLK 3 3 ns 13 td(CLKL-CMD) Delaytime,SD_CLK lowtoSD_CMD transition -4.1 1.5 -4.1 1.5 ns 14 td(CLKL-DAT) Delaytime,SD_CLK lowtoSD_DATx transition -4.1 1.5 -4.1 1.5 ns Figure6-27.MMC/SD Host Command Timing Figure6-28.MMC/SD Card Response Timing Figure6-29.MMC/SD Host WriteTiming Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 121 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SD_CLK SD_DA Tx 3 3 TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-30.MMC/SD Host Read and Card CRC StatusTiming

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6.12 Video ProcessingSubsystem (VPSS) Overview

The devicecontainsa Video ProcessingSubsystem (VPSS) thatprovidesan inputinterface(Video ProcessingFrontEnd orVPFE) forexternalimagingperipheralssuch as image sensors,videodecoders, etc.;and an outputinterface(VideoProcessingBack End or VPBE) fordisplaydevices,such as analog SDTV/HDTV displays,digitalLCD panels,etc. In additionto theseperipherals,thereisa setof common buffermemory and DMA controlto ensure efficientuse oftheDDR2/mDDR burstbandwidth.The sharedbufferlogic/memoryisa uniqueblockthat istailoredforseamlesslyintegratingthe VPSS intoan image/videoprocessingsystem.Itactsas the primarysourceorsinktoalltheVPFE and VPBE modules thatareeitherrequestingortransferringdata from/toDDR2/mDDR .InordertoefficientlyutilizetheexternalDDR2/mDDR bandwidth,thesharedbuffer logic/memoryinterfaceswiththeDMA system viaa highbandwidthbus (64-bitwide).The sharedbuffer logic/memoryalsointerfaceswithallthe VPFE and VPBE modules viaa 128-bitwide bus.The shared bufferlogic/memory(dividedintotheread& writebuffersand arbitrationlogic)iscapableofperformingthe followingfunctions.ItisimperativethattheVPSS utilizeDDR2/mDDR bandwidthefficientlydue tobothits largebandwidthrequirementsand thereal-timerequirementsoftheVPSS modules.Because itispossible to configurethe VPSS modules insuch a way thatDDR2/mDDR bandwidthisexceeded,a setof user accessibleregistersisprovidedtomonitoroverflowsorfailuresindatatransfers.

6.12.1 Video ProcessingFront-End(VPFE)

The VPFE orVideoProcessingFront-EndblockiscomprisedoftheImage Sensor Interface(ISIF),Image Pipe (IPIPE),Image Pipe Interface(IPIPEIF),Hardware 3A StatisticGenerator(H3A),and a Hardware Face DetectEngine.These modules aredescribedinthesectionsthatfollow. The VPFE sub-moduleregistermemory mapping isshown inTable6-39. Table6-39.Video ProcessingFrontEnd Sub-Module RegisterMap Address:Offset Acronym RegisterDescription 0x01C7:0000 ISP ISP System Configuration 0x01C7:0200 VPBE_CLK_CTRL VPBE ClockControl 0x01C7:0400 RSZ Resizer 0x01C7:0800 IPIPE Image Pipe 0x01C7:1000 ISIF Image SensorInterface 0x01C7:1200 IPIPEIF Image PipeInterface 0x01C7:1400 H3A Hardware 3A 0x01C7:1600- Reserved Reserved 0x01C7:17FF 0x01C7:1800 FDIF Face DetectionRegisterInterface 0x01C7:1C00 OSD VPBE On-ScreenDisplay 0x01C7:1D00 - Reserved Reserved 0x01C7:1DFF 0x01C7:1E00 VENC VPBE VideoEncoder 0x01C7:2000- Reserved Reserved 0x01CF:FFFF 6.12.1.1Image Sensor Interface(ISIF) The ISIFisresponsibleforacceptingraw (unprocessed)image/videodatafroma sensor(CMOS orCCD). In addition,the ISIFcan acceptYUV videodata in numerous formats,typicallyfrom so-calledvideo decoderdevices.Incase ofraw inputs,theISIFoutputrequiresadditionalimage processingtotransform Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 123 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com theraw inputimage tothefinalprocessedimage.Thisprocessingcan be done eitheron-the-flyinIPIPE or insoftwareon theARM and MPEG/JPEG and HD Video Image coprocessorsubsystems.Inparallel, raw data inputto the ISIFcan alsoused forcomputingvariousstatistics(3A,Histogram)to eventually controltheimage/videotuningparameters.The ISIFisprogrammed viacontroland parameterregisters. The followingfeaturesaresupportedby theISIFmodule.

• SupportforconventionalBayerpattern,pixelsummation mode, and RGB stripesensorformats.
• Supportforthevariouspixelsummation mode formatsisprovidedviaa datareformatterofISIF,which transformsany specificsensorformatstotheBayer format.The maximum linewidthsupportedby the reformatteris4736 pixels.
• Image processingstepsapplicabletoRGB stripesensorsare limitedtocolor-dependentgaincontrol and blackleveloffsetcontrol."
• GeneratesHD/VD timingsignalsand fieldID toan externaltiminggenerator,orcan synchronizetothe externaltiminggenerator.
• Supportforprogressiveand interlacedsensors(hardwaresupportforup to 2 fieldsand firmware supportforhighernumber offields,typically3-,4-,and 5-fieldsensors.
• Supportforup to32K pixels(imagesize)inboththehorizontaland verticaldirection.
• Supportforup to120 MHz sensorclock.
• SupportforITU-R BT.656/1120standardformat.
• SupportforYCbCr 422 format,either8-or16-bitwithdiscreteHSYNC and VSYNC signals.
• Supportforup to16-bitinput.
• Supportforcolorspace conversion.
• Digitalclamp withHorizontal/Verticaloffsetdriftcompensation.
• VerticalLinedefectcorrectionbased on a lookuptablethatcontainsdefectposition.
• Supportforcolor-dependentgaincontroland blackleveloffsetcontrol.
• AbilitytocontroloutputtotheDDR2/mDDR viaan externalwriteenablesignal.
• Supportfordown samplingviaprogrammablecullingpatterns.
• Supportfor12-bitto8-bitDPCM compression.
• Supportfor10-bitto8-bitA-lawcompression.
• Supportforgeneratingoutputto range 16-bits,12-bits,and 8-bitswide (8-bitswide allowsfor50% savinginstoragearea).
• OTF DPC
• NoiseFilter
• 2D edge enhancement The ISIFregistermemory mapping (offsets)isshown inTable6-40. Table6-40.Image Sensor Interface(ISIF)Registers Offset Acronym RegisterDescription 0h SYNCEN SynchronizationEnable 4h MODESET Mode Setup 8h HDW HD pulsewidth Ch VDW VD pulsewidth 10h PPLN Pixelsperline 14h LPFR Linesperframe 18h SPH Startpixelhorizontal 1Ch LNH Number ofpixelsinline 20h SLV0 Startlinevertical-field0 24h SLV1 Startlinevertical-field1 28h LNV Number oflinesvertical

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-40.Image Sensor Interface(ISIF)Registers (continued) Offset Acronym RegisterDescription 2Ch CULH Culling-horizontal 30h CULV Culling-vertical 34h HSIZE Horizontalsize 38h SDOFST SDRAM LineOffset 3Ch CADU SDRAM Address-high 40h CADL SDRAM Address-low 44h -48h Reserved Reserved 4Ch CCOLP CCD ColorPattern 50h CRGAIN CCD Gain Adjustment-R/Ye 54h CGRGAIN CCD Gain Adjustment-Gr/Cy 58h CGBGAIN CCD Gain Adjustment-Gb/G 5Ch CBGAIN CCD Gain Adjustment-B/Mg 60h COFSTA CCD OffsetAdjustment 64h FLSHCFG0 FLSHCFG0 68h FLSHCFG1 FLSHCFG1 6Ch FLSHCFG2 FLSHCFG2 70h VDINT0 VD Interrupt#0 74h VDINT1 VD Interrupt#1 78h VDINT2 VD Interrupt#2 7Ch Reserved Reserved 80h CGAMMAWD Gamma Correctionsettings 84h REC656IF CCIR 656 Control 88h CCDCFG CCD Configuration 8Ch DFCCTL DefectCorrection-Control 90h VDFSATLV DefectCorrection-VerticalSaturationLevel 94h DFCMEMCTL DefectCorrection-Memory Control 98h DFCMEM0 DefectCorrection-SetV Position 9Ch DFCMEM1 DefectCorrection-SetH Position A0h DFCMEM2 DefectCorrection-SetSUB1 A4h DFCMEM3 DefectCorrection-SetSUB2 A8h DFCMEM4 DefectCorrection-SetSUB3 ACh CLAMPCFG BlackClamp configuration B0h CLDCOFST DC offsetforBlackClamp B4h CLSV BlackClamp Startposition B8h CLHWIN0 HorizontalBlackClamp configuration BCh CLHWIN1 HorizontalBlackClamp configuration C0h CLHWIN2 HorizontalBlackClamp configuration C4h CLVRV VerticalBlackClamp configuration C8h CLVWIN0 VerticalBlackClamp configuration CCh CLVWIN1 VerticalBlackClamp configuration D0h CLVWIN2 VerticalBlackClamp configuration D4h CLVWIN3 VerticalBlackClamp configuration D8h -1A2h Reserved Reserved 1A4h CSCCTL ColorSpace ConverterEnable 1A8h CSCM0 ColorSpace Converter-Coefficients#0 1ACh CSCM1 ColorSpace Converter-Coefficients#1 1B0h CSCM2 ColorSpace Converter-Coefficients#2 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 125 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-40.Image Sensor Interface(ISIF)Registers (continued) Offset Acronym RegisterDescription 1B4h CSCM3 ColorSpace Converter-Coefficients#3 1B8h CSCM4 ColorSpace Converter-Coefficients#4 1BCh CSCM5 ColorSpace Converter-Coefficients#5 1C0h CSCM6 ColorSpace Converter-Coefficients#6 1C4h CSCM7 ColorSpace Converter-Coefficients#7 6.12.1.2The Image Pipe Interface(IPIPEIF) The IPIPEIFisdataand sync signalsinterfacemodule forISIFand IPIPE.Data sourceofthismodule is sensorparallelport,ISIForSDRAM and theselecteddataisoutputtoISIFand IPIPE.Thismodule also outputsblackframe subtraction(two-way)data which isgeneratedby subtractingSDRAM data from sensor parallelportor ISIFdata and viceversa.Depending on the functionsperformed,itmay also readjusttheHD, VD, and PCLK timingtotheIPIPEand/orISIFinput. The IPIPEIFmodule supportsthefollowingfeatures:

• Up to16-bitsensordatainput
• Dark-framesubtractofraw image storedinSDRAM from image coming from sensorparallelportor ISIF
• 8-10,8-12DPCM decompressionof10-8,12-8compressed datainSDRAM
• InverseALAW decompressionofRAW datafromSDRAM
• (1,2,1)averagefilteringbeforehorizontaldecimation
• Horizontaldecimation(downsizing)ofinputlinesto<= 2160 maximum requiredby theIPIPE
• Gain multiplyforoutputdatatoIPIPE
• Simpledefectcorrectiontopreventa subtractionofdefectpixel
• 8-bit,12-bitunpackingof8-bit,12-bitpacked SDRAM data The IPIPEregistermemory mapping (offsets)isshown inTable6-41. Table6-41.Image Pipe InputInterface(IPIPEIF)Registers Address Acronym RegisterDescription 0h ENABLE IPIPEI/FEnable 4h CFG1 IPIPEI/FConfiguration 8h PPLN IPIPEI/FIntervalofHD /StartpixelinHD Ch LPFR IPIPEI/FIntervalofVD /StartlineinVD 10h HNUM IPIPEI/FNumber ofvalidpixelsperline 14h VNUM IPIPEI/FNumber ofvalidlinesperframe 18h ADDRU IPIPEI/FMemory Address(Upper) 1Ch ADDRL IPIPEI/FMemory Address(Lower) 20h ADOFS IPIPEI/FAddressoffsetofeach line 24h RSZ IPIPEI/FHorizontalResizingParameter 28h GAIN IPIPEI/FGain Parameter 2Ch DPCM IPIPEI/FDPCM Configuration 30h CFG2 IPIPEI/FConfiguration2 34h INIRSZ IPIPEI/FInitialpositionofresize 38h OCLIP IPIPEI/FOutputclippingvalue 3Ch DTUDF IPIPEI/FData underflowerrorstatus 40h CLKDIV IPIPEI/FClockrateconfiguration 44h DPC1 IPIPEI/FDefectpixelcorrection 48h DPC2 IPIPEI/FDefectpixelcorrection

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-41.Image Pipe InputInterface(IPIPEIF)Registers(continued) Address Acronym RegisterDescription 54h RSZ3A IPIPEI/FHorizontalResizingParameterforH3A 58h INIRSZ3A IPIPEI/FInitialpositionofresizeforH3A 6.12.1.3Image Pipe – Hardware Image SignalProcessor (IPIPE) The Image Pipe (IPIPE)isa programmable hardware image processingmodule thatgeneratesimage data inYCbCr-4:2:2or YCbCr-4:2:0formatsfrom raw CCD/CMOS data.An image resizerisalsofully integratedwithinthismodule.The IPIPE can alsobe configuredtooperateina resize-onlymode, which allowsYCbCr-4:2:2orYCbCr-4:2:0tobe resizedwithoutprocessingeverymodule intheIPIPE. The followingfeaturesaresupportedby theIPIPE:

• 12-bitRAW dataimage processingor16-bitYCbCr resizing
• RGB Bayer patternforinputcolorfilterarray;does not supportcomplementarycolorpattern,stripe pattern,orFoveon™ sensors.
• Requiresat leasteightpixelsforhorizontalblankingand fourlinesforverticalblanking.In one shot mode, 16 blankinglinesafterprocessingareaarerequired.
• Maximum horizontaland verticaloffsetofIPIPEprocessingareafromsynchronoussignalis65534
• Maximum inputand outputwidthsup to2176 pixelswide(1088forRSZ[2]).
• Raw pass-throughmode forimages widerthan2176 pixels(upto8190 pixels)
• Automaticmirroringofpixels/lineswhen edge processingisperformedso thatthewidthand heightis consistentthroughout.
• Defectpixelcorrectionusing – Lookup tablemethod thatcontainsrow and column positionofthepixeltobe corrected – On-the-flyadaptivemethod
• Offsetand gaincontrolforwhitebalancingateach colorcomponent (WB).
• CFA interpolationforgood qualityCFA interpolation
• Programmable RGB toRGB blendingmatrix(9coefficientsforthe3x3 matrix).(RGB2RGB module)
• Separatelookuptablesforgamma correctionon each ofR, G and B components fordisplaythrough piece-wiselinearinterpolationapproach
• 4:4:4data to 4:2:2data conversionby chroma low-passfilteringand down samplingto Cb and Cr. (4:4:4to4:2:2module)
• Programmable look-uptableforluminanceedge enhancement.Adjustablebrightnessand contrastfor Y component (Edge Enhancermodule)
• Programmable down or up-samplingfilterforboth horizontaland verticaldirectionswithrange from 1/16xto16x,inwhichthefilteroutputstwo images withdifferentmagnificationsimultaneously(Resizer module)
• 4:2:2to4:2:0conversionthatcan be done intheresizingblock
• Differentdataformats[YCbCr (4:2:2or4:2:0),RGB (32bit/16bit),Raw data]areavailablewhilestoring dataintheSDRAM fromIPIPE
• Flippingimage horizontallyand/orvertically
• Programmable histogramengine(4windows,256 bins)
• Boxcarcalculation(1/8or1/16size). The IPIPEregistermemory mapping (offsets)isshown inTable6-42. Table6-42.IPIPERegisters Offset Acronym RegisterDescription 0h SRC_EN IPIPEEnable Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 127 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-42.IPIPERegisters(continued) Offset Acronym RegisterDescription 04h SRC_MODE One ShotMode 08h SRC_FMT Input/OutputData Paths Ch SRC_COL ColorPattern 10h SRC_VPS VerticalStartPosition 14h SRC_VSZ VerticalProcessingSize 18h SRC_HPS HorizontalStartPosition 1Ch SRC_HSZ HorizontalProcessingSize 24h DMA_STA StatusFlags(Reserved) 48h GCK_MMR MMR Gated ClockControl 2Ch GCK_PIX PCLK Gated ClockControl 30h Reserved Reserved 34h DPC_LUT_EN LUTDPC (=LUT DefectPixelCorrection):Enable 38h DPC_LUT_SEL LUTDPC: ProcessingMode Selection 3Ch DPC_LUT_ADR LUTDPC: StartAddressinLUT 40h DPC_LUT_SIZ LUTDPC: Number ofavailableentriesinLUT 1D0h WB2_OFT_R WB2 (=WhiteBalance):Offset 1D4h WB2_OFT_GR WB2: Offset 1D8h WB2_OFT_GB WB2: Offset 1DCh WB2_OFT_B WB2: Offset 1E0h WB2_WGN_R WB2: Gain 1E4h WB2_WGN_GR WB2: Gain 1E8h WB2_WGN_GB WB2: Gain 1ECh WB2_WGN_B WB2: Gain 1F0h-228h Reserved Reserved 22Ch RGB1_MUL_RR RGB1 (=1stRGB2RGB conv):MatrixCoefficient 230h RGB1_MUL_GR RGB1: MatrixCoefficient 234h RGB1_MUL_BR RGB1: MatrixCoefficient 238h RGB1_MUL_RG RGB1: MatrixCoefficient 23Ch RGB1_MUL_GG RGB1: MatrixCoefficient 240h RGB1_MUL_BG RGB1: MatrixCoefficient 244h RGB1_MUL_RB RGB1: MatrixCoefficient 248h RGB1_MUL_GB RGB1: MatrixCoefficient 24Ch RGB1_MUL_BB RGB1: MatrixCoefficient 250h RGB1_OFT_OR RGB1: Offset 254h RGB1_OFT_OG RGB1: Offset 258h RGB1_OFT_OB RGB1: Offset 25Ch GMM_CFG Gamma CorrectionConfiguration 294h YUV_ADJ YUV (RGB2YCbCr conv):Luminance Adjustment(contrast& brightness) 298h YUV_MUL_RY YUV: MatrixCoefficient 29Ch YUV_MUL_GY YUV: MatrixCoefficient 2A0h YUV_MUL_BY YUV: MatrixCoefficient 2A4h YUV_MUL_RCB YUV: MatrixCoefficient 2A8h YUV_MUL_GCB YUV: MatrixCoefficient 2ACh YUV_MUL_BCB YUV: MatrixCoefficient 2B0h YUV_MUL_RCR YUV: MatrixCoefficient 2B4h YUV_MUL_GCR YUV: MatrixCoefficient 2B8h YUV_MUL_BCR YUV: MatrixCoefficient

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-42.IPIPERegisters(continued) Offset Acronym RegisterDescription 2BCh YUV_OFT_Y YUV: Offset 2C0h YUV_OFT_CB YUV: Offset 2C4h YUV_OFT_CR YUV: Offset 2C8h YUV_PHS ChrominancePosition(for422 down sampler) 2D4h YEE_EN YEE (=Edge Enhancer):Enable 2D8h YEE_TYP YEE: Method Selection 2DCh YEE_SHF YEE: HPF ShiftLength 2E0h YEE_MUL_00 YEE: HPF Coefficient 2E4h YEE_MUL_01 YEE: HPF Coefficient 2E8h YEE_MUL_02 YEE: HPF Coefficient 2ECh YEE_MUL_10 YEE: HPF Coefficient 2F0h YEE_MUL_11 YEE: HPF Coefficient 2F4h YEE_MUL_12 YEE: HPF Coefficient 2F8h YEE_MUL_20 YEE: HPF Coefficient 2FCh YEE_MUL_21 YEE: HPF Coefficient 300h YEE_MUL_22 YEE: HPF Coefficient 304h YEE_THR YEE: Lower ThresholdbeforereferringtoLUT 308h YEE_E_GAN YEE: Edge SharpenerGain 30Ch YEE_E_THR_1 YEE: Edge SharpenerHP ValueLower Threshold 310h YEE_E_THR_2 YEE: Edge SharpenerHP ValueUpper Limit 314h YEE_G_GAN YEE: Edge SharpenerGain on Gradient 318h YEE_G_OFT YEE: Edge SharpenerOffseton Gradient 380h BOX_EN BOX (=Boxcar)Enable 384h BOX_MODE BOX: One ShotMode 388h BOX_TYP BOX: BlockSize(16x16or8x8) 38Ch BOX_SHF BOX: Down shiftvalueofinput 390h BOX_SDR_SAD_H BOX: SDRAM AddressMSB 394h BOX_SDR_SAD_L BOX: SDRAM AddressLSB 398h Reserved Reserved 39Ch HST_EN HST (=Histogram):Enable 3A0h HST_MODE HST: One ShotMode 3A4h HST_SEL HST: SourceSelect 3A8h HST_PARA HST: ParametersSelect 3ACh HST_0_VPS HST: VerticalStartPosition 3B0h HST_0_VSZ HST: VerticalSize 3B4h HST_0_HPS HST: HorizontalStartPosition 3B8h HST_0_HSZ HST: HorizontalSize 3BCh HST_1_VPS HST: VerticalStartPosition 3C0h HST_1_VSZ HST: VerticalSize 3C4h HST_1_HPS HST: HorizontalStartPosition 3C8h HST_1_HSZ HST: HorizontalSize 3CCh HST_2_VPS HST: VerticalStartPosition 3D0h HST_2_VSZ HST: VerticalSize 3D4h HST_2_HPS HST: HorizontalStartPosition 3D8h HST_2_HSZ HST: HorizontalSize 3DCh HST_3_VPS HST: VerticalStartPosition 3E0h HST_3_VSZ HST: VerticalSize Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 129 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-42.IPIPERegisters(continued) Offset Acronym RegisterDescription 3E4h HST_3_HPS HST: HorizontalStartPosition 3E8h HST_3_HSZ HST: HorizontalSize 3ECh HST_TBL HST: TableSelect 3F0h HST_MUL_R HST: MatrixCoefficient 3F4h HST_MUL_GR HST: MatrixCoefficient 3F8h HST_MUL_GB HST: MatrixCoefficient 3FCh HST_MUL_B HST: MatrixCoefficient 6.12.1.4Hardware 3A (H3A) The H3A module isdesignedtosupportthecontrolloopsforAuto Focus,Auto White Balanceand Auto Exposure by collectingmetricsabout the imaging/videodata.The metricsare to adjustthe various parametersforprocessingtheimaging/videodata.Thereare2 main blocksintheH3A module:

• AutoFocus (AF)engine
• AutoExposure(AE)AutoWhiteBalance(AWB) engine The AF engineextractsand filtersthe red,green,and bluedata from the inputimage/videodata and provideseitherthe accumulationor peaks of the data ina specifiedregion.The specifiedregionisa two-dimensionalblockofdataand isreferredtoas a "paxel"forthecase ofAF. The AE/AWB Engine accumulatesthevaluesand checks forsaturatedvaluesina sub samplingofthe videodata.Inthecase oftheAE/AWB, thetwo-dimensionalblockofdataisreferredtoas a "window". Thus,otherthanreferringthem by differentnames, a paxeland a window areessentiallythesame thing. However, thenumber, dimensions,and startingpositionoftheAF paxelsand theAE/AWB windows are separatelyprogrammable. The followingfeaturesaresupportedby theAF engine:
• SupportforinputfromDDR2 /mDDR SDRAM (inadditiontotheISIFport)
• Supportfora Peak Mode ina Paxel(aPaxelisdefinedas a two dimensionalblockofpixels).
• Accumulatethemaximum Focus Valueofeach lineina Paxel
• Supportforan Accumulation/SumMode (insteadofPeak mode).
• AccumulateFocus Valueina Paxel.
• Supportforup to36 Paxelsinthehorizontaldirectionand up to128 Paxelsintheverticaldirection. The number ofhorizontalpaxelsislimitedby thememory size(andcost),whiletheverticalnumber of paxelsisnot.Therefore,the number of paxelsinhorizontaldirectionissmallerthan the number of paxelsinverticaldirection.
• Programmable widthand heightforthePaxel.Allpaxelsintheframewillbe ofsame size.
• Programmable red,green,and bluepositionwithina 2x2 matrix.
• Separatehorizontalstartforpaxeland filtering.
• Programmable verticallineincrementswithina paxel.
• ParallelIIRfiltersconfiguredina dual-biquadconfigurationwithindividualcoefficients(2filterswith11 coefficientseach).The filtersareintendedtocompute thesharpness/peaksintheframetofocuson. The followingfeaturesaresupportedby theAE/AWB engine:
• SupportforinputfromDDR2 /mDDR SDRAM (inadditiontotheISIFport)
• Accumulateclippedpixelsalongwithallnon-saturatedpixels
• Supportforup to36 horizontalwindows.
• Supportforup to128 verticalwindows.
• Programmable widthand heightforthewindows.Allwindows intheframewillbe ofsame size.
• Separate verticalstartco-ordinateand heightfora blackrow of paxelsthatis differentthan the remainingcolorpaxels.

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• Programmable HorizontalSamplingPointsina window
• Programmable VerticalSamplingPointsina window The Hardware 3A (H3A)registermemory mapping (offsets)isshown inTable6-43. Table6-43.Hardware 3A StatisticsGeneration(AE,AF, AWB) (H3A) Registers Offset Acronym RegisterDescription 0h PID PeripheralRevisionand ClassInformation 4h PCR PeripheralControlRegister 8h AFPAX1 SetupfortheAF EnginePaxelConfiguration Ch AFPAX2 SetupfortheAF EnginePaxelConfiguration 10h AFPAXSTART StartPositionforAF EnginePaxels 18h AFBUFST SDRAM/DDRAM StartaddressforAF Engine 4Ch AEWWIN1 ConfigurationforAE/AWB Windows 50h AEWINSTART StartpositionforAE/AWB Windows 54h AEWINBLK Startpositionand heightforblacklineofAE/AWB Windows 58h AEWSUBWIN ConfigurationforsubsampledatainAE/AWB window 5Ch AEWBUFST SDRAM/DDRAM StartaddressforAE/AWB EngineOutputData 60h RSDR_ADDR AE/AWB EngineConfiguration 64h LINE_START LinestartpositionforISIFinterface 68h VFV_CFG1 AF VerticalFocus Configuration1 Register 6Ch VFV_CFG2 AF VerticalFocus Configuration2 Register 70h VFV_CFG3 AF VerticalFocus Configuration3 Register 74h VFV_CFG4 AF VerticalFocus Configuration4 Register 78h HFV_THR ConfigurestheHorizontalThresholdsfortheAF IIRfilters 6.12.1.5Face DetectionModule The followingfeaturesaresupportedon theFace Detectionmodule:
• Highdetectionrateofcloseto100% undermost conditions
• Allowsdetectionindifferentdirections-up,left,and right
• Allowsdetectionwithrotationinplane(RIP)-±45°,@ 0°/+90°/-90°
• Allowsdetectionforrotationoutofplane(ROP) – Horizontal(left/right)pan:±60° – Vertical(up/down)tilt:±30°
• Configurableminimum facesizeof20 -40 pixels
• Configurableregionofinterestintheinputframe
• Configurablestartpositionintheinputframe
• Supportsup to35 facedetectionsina singleframe
• Interruptgenerationto ARM using the Video ProcessingSubsystem (VPSS) multiplexedinterrupt mechanism
• Robust performanceinlow lightconditions,nightvision,monochromatic,and falsecolorsensingas skintonenotused forfacedetection
• Supportedinputsizeis(256X192)
• Inputformatis8-bitgrayscaledata The Face DetectionModule registermemory mapping (offsets)isshown inTable6-44. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 131 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-44.Face DetectionModule Registers Offset Acronym RegisterDescription 0x000 FDIF_PID FDIF PID 0x008 FDIF_INTEN FDIF Interruptenable 0x00C FDIF_PICADDR FDIF PictureData address 0x010 FDIF_WKADDR FDIF Work Area address 0x020 FD_CTRL FD Core ControlRegister 0x024 FD_DNUM Detectnumber 0x028 FD_DCOND DetectConditionsetregister 0x02C FD_STARTX X Startaddress 0x030 FD_STARTY Y Startaddress 0x034 FD_SIZEX X Sizefordetection 0x038 FD_SIZEY Y Sizefordetection 0x03C FD_LHIT Detectprocessthreshold 0x100 FD_CENTERX1 DetectResultCenterX Address 0x104 FD_CENTERY1 DetectResultCenterY Address 0x108 FD_CONFSIZE1 DetectResultConfidence/Size 0x10C FD_ANGLE1 DetectAngle 0x110 FD_CENTERX2 DetectResultCenterX Address 0x114 FD_CENTERY2 DetectResultCenterY Address 0x118 FD_CONFSIZE2 DetectResultConfidence/Size 0x11C FD_ANGLE2 DetectAngle 0x120 FD_CENTERX3 DetectResultCenterX Address 0x124 FD_CENTERY3 DetectResultCenterY Address 0x128 FD_CONFSIZE3 DetectResultConfidence/Size 0x12C FD_ANGLE3 DetectAngle 0x130 FD_CENTERX4 DetectResultCenterX Address 0x134 FD_CENTERY4 DetectResultCenterY Address 0x138 FD_CONFSIZE4 DetectResultConfidence/Size 0x13C FD_ANGLE4 DetectAngle 0x140 FD_CENTERX5 DetectResultCenterX Address 0x144 FD_CENTERY5 DetectResultCenterY Address 0x148 FD_CONFSIZE5 DetectResultConfidence/Size 0x14C FD_ANGLE5 DetectAngle 0x150 FD_CENTERX6 DetectResultCenterX Address 0x154 FD_CENTERY6 DetectResultCenterY Address 0x158 FD_CONFSIZE6 DetectResultConfidence/Size 0x15C FD_ANGLE6 DetectAngle 0x160 FD_CENTERX7 DetectResultCenterX Address 0x164 FD_CENTERY7 DetectResultCenterY Address 0x168 FD_CONFSIZE7 DetectResultConfidence/Size 0x16C FD_ANGLE7 DetectAngle 0x170 FD_CENTERX8 DetectResultCenterX Address 0x174 FD_CENTERY8 DetectResultCenterY Address 0x178 FD_CONFSIZE8 DetectResultConfidence/Size 0x17C FD_ANGLE8 DetectAngle 0x180 FD_CENTERX9 DetectResultCenterX Address 0x184 FD_CENTERY9 DetectResultCenterY Address 0x188 FD_CONFSIZE9 DetectResultConfidence/Size

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-44.Face DetectionModule Registers(continued) Offset Acronym RegisterDescription 0x18C FD_ANGLE9 DetectAngle 0x190 FD_CENTERX10 DetectResultCenterX Address 0x194 FD_CENTERY10 DetectResultCenterY Address 0x198 FD_CONFSIZE10 DetectResultConfidence/Size 0x19C FD_ANGLE10 DetectAngle 0x1A0 FD_CENTERX11 DetectResultCenterX Address 0x1A4 FD_CENTERY11 DetectResultCenterY Address 0x1A8 FD_CONFSIZE11 DetectResultConfidence/Size 0x1AC FD_ANGLE11 DetectAngle 0x1B0 FD_CENTERX12 DetectResultCenterX Address 0x1B4 FD_CENTERY12 DetectResultCenterY Address 0x1B8 FD_CONFSIZE12 DetectResultConfidence/Size 0x1BC FD_ANGLE12 DetectAngle 0x1C0 FD_CENTERX13 DetectResultCenterX Address 0x1C4 FD_CENTERY13 DetectResultCenterY Address 0x1C8 FD_CONFSIZE13 DetectResultConfidence/Size 0x1CC FD_ANGLE13 DetectAngle 0x1D0 FD_CENTERX14 DetectResultCenterX Address 0x1D4 FD_CENTERY14 DetectResultCenterY Address 0x1D8 FD_CONFSIZE14 DetectResultConfidence/Size 0x1DC FD_ANGLE14 DetectAngle 0x1E0 FD_CENTERX15 DetectResultCenterX Address 0x1E4 FD_CENTERY15 DetectResultCenterY Address 0x1E8 FD_CONFSIZE15 DetectResultConfidence/Size 0x1EC FD_ANGLE15 DetectAngle 0x1F0 FD_CENTERX16 DetectResultCenterX Address 0x1F4 FD_CENTERY16 DetectResultCenterY Address 0x1F8 FD_CONFSIZE16 DetectResultConfidence/Size 0x1FC FD_ANGLE16 DetectAngle 0x200 FD_CENTERX17 DetectResultCenterX Address 0x204 FD_CENTERY17 DetectResultCenterY Address 0x208 FD_CONFSIZE17 DetectResultConfidence/Size 0x20C FD_ANGLE17 DetectAngle 0x210 FD_CENTERX18 DetectResultCenterX Address 0x214 FD_CENTERY18 DetectResultCenterY Address 0x218 FD_CONFSIZE18 DetectResultConfidence/Size 0x21C FD_ANGLE18 DetectAngle 0x220 FD_CENTERX19 DetectResultCenterX Address 0x224 FD_CENTERY19 DetectResultCenterY Address 0x228 FD_CONFSIZE19 DetectResultConfidence/Size 0x22C FD_ANGLE19 DetectAngle 0x230 FD_CENTERX20 DetectResultCenterX Address 0x234 FD_CENTERY20 DetectResultCenterY Address 0x238 FD_CONFSIZE20 DetectResultConfidence/Size 0x23C FD_ANGLE20 DetectAngle 0x240 FD_CENTERX21 DetectResultCenterX Address 0x244 FD_CENTERY21 DetectResultCenterY Address Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 133 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-44.Face DetectionModule Registers(continued) Offset Acronym RegisterDescription 0x248 FD_CONFSIZE21 DetectResultConfidence/Size 0x24C FD_ANGLE21 DetectAngle 0x250 FD_CENTERX22 DetectResultCenterX Address 0x254 FD_CENTERY22 DetectResultCenterY Address 0x258 FD_CONFSIZE22 DetectResultConfidence/Size 0x25C FD_ANGLE22 DetectAngle 0x260 FD_CENTERX23 DetectResultCenterX Address 0x264 FD_CENTERY23 DetectResultCenterY Address 0x268 FD_CONFSIZE23 DetectResultConfidence/Size 0x26C FD_ANGLE23 DetectAngle 0x270 FD_CENTERX24 DetectResultCenterX Address 0x274 FD_CENTERY24 DetectResultCenterY Address 0x278 FD_CONFSIZE24 DetectResultConfidence/Size 0x27C FD_ANGLE24 DetectAngle 0x280 FD_CENTERX25 DetectResultCenterX Address 0x284 FD_CENTERY25 DetectResultCenterY Address 0x288 FD_CONFSIZE25 DetectResultConfidence/Size 0x28C FD_ANGLE25 DetectAngle 0x290 FD_CENTERX26 DetectResultCenterX Address 0x294 FD_CENTERY26 DetectResultCenterY Address 0x298 FD_CONFSIZE26 DetectResultConfidence/Size 0x29C FD_ANGLE26 DetectAngle 0x2A0 FD_CENTERX27 DetectResultCenterX Address 0x2A4 FD_CENTERY27 DetectResultCenterY Address 0x2A8 FD_CONFSIZE27 DetectResultConfidence/Size 0x2AC FD_ANGLE27 DetectAngle 0x2B0 FD_CENTERX28 DetectResultCenterX Address 0x2B4 FD_CENTERY28 DetectResultCenterY Address 0x2B8 FD_CONFSIZE28 DetectResultConfidence/Size 0x2BC FD_ANGLE28 DetectAngle 0x2C0 FD_CENTERX29 DetectResultCenterX Address 0x2C4 FD_CENTERY29 DetectResultCenterY Address 0x2C8 FD_CONFSIZE29 DetectResultConfidence/Size 0x2CC FD_ANGLE29 DetectAngle 0x2D0 FD_CENTERX30 DetectResultCenterX Address 0x2D4 FD_CENTERY30 DetectResultCenterY Address 0x2D8 FD_CONFSIZE30 DetectResultConfidence/Size 0x2DC FD_ANGLE30 DetectAngle 0x2E0 FD_CENTERX31 DetectResultCenterX Address 0x2E4 FD_CENTERY31 DetectResultCenterY Address 0x2E8 FD_CONFSIZE31 DetectResultConfidence/Size 0x2EC FD_ANGLE31 DetectAngle 0x2F0 FD_CENTERX32 DetectResultCenterX Address 0x2F4 FD_CENTERY32 DetectResultCenterY Address 0x2F8 FD_CONFSIZE32 DetectResultConfidence/Size 0x2FC FD_ANGLE32 DetectAngle 0x300 FD_CENTERX33 DetectResultCenterX Address

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-44.Face DetectionModule Registers(continued) Offset Acronym RegisterDescription 0x304 FD_CENTERY33 DetectResultCenterY Address 0x308 FD_CONFSIZE33 DetectResultConfidence/Size 0x30C FD_ANGLE33 DetectAngle 0x310 FD_CENTERX34 DetectResultCenterX Address 0x314 FD_CENTERY34 DetectResultCenterY Address 0x318 FD_CONFSIZE34 DetectResultConfidence/Size 0x31C FD_ANGLE34 DetectAngle 0x320 FD_CENTERX35 DetectResultCenterX Address 0x324 FD_CENTERY35 DetectResultCenterY Address 0x328 FD_CONFSIZE35 DetectResultConfidence/Size 0x32C FD_ANGLE35 DetectAngle Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 135 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com 6.12.1.6VPFE ElectricalData/Timing Table6-45.Timing Requirements forVPFE PCLK Master/SlaveMode (1)(seeFigure6-31) NO. MIN MAX UNIT SlaveMode 8.33 120 ns 1 tc(PCLK) Cycletime,PCLK MasterMode 13.33 120 ns 2 tw(PCLKH) Pulseduration,PCLK high tc(PCLK)*0.35 tc(PCLK)*0.65 ns 3 tw(PCLKL) Pulseduration,PCLK low tc(PCLK)*0.35 tc(PCLK)*0.65 ns 4 tt(PCLK) Transitiontime,PCLK 2 ns (1) P = 1/SYSCLK4 innanoseconds(ns).Forexample,iftheSYSCLK4 frequencyis135 MHz, use P = 7.41ns.See Section3.3,Device Clocking,formore informationon thesupportedclockconfigurationsofthedevice. Figure6-31.VPFE PCLK Timing Table6-46.Timing Requirements forVPFE (ISIF)SlaveMode (seeFigure6-32) DEVICE UNINO. TMIN MAX PositiveEdge 2.5tsu(DATAV-5 Setuptime,ISIFDATA validbeforePCLK edge ns PCLK) NegativeEdge 1.5 PositiveEdge 1.5 6 th(PCLK-DATAV) Holdtime,ISIFDATA validafterPCLK edge ns NegativeEdge 2.5 PositiveEdge 2.5 7 tsu(HDV-PCLK) Setuptime,HD validbeforePCLK edge ns NegativeEdge 1.5 PositiveEdge 1.5 8 th(PCLK-HDV) Holdtime,HD validafterPCLK edge ns NegativeEdge 2.5 PositiveEdge 2.5 9 tsu(VDV-PCLK) Setuptime,VD validbeforePCLK edge ns NegativeEdge 1.5 PositiveEdge 1.5 10 th(PCLK-VDV) Holdtime,VD validafterPCLK edge ns NegativeEdge 2.5 PositiveEdge 2.5tsu(C_WEV-11 Setuptime,C_WE validbeforePCLK edge ns PCLK) NegativeEdge 1.5 PositiveEdge 1.5 12 th(PCLK-C_WEV) Holdtime,C_WE validafterPCLK edge ns NegativeEdge 2.5 PositiveEdge 2.5tsu(C_FIELDV-13 Setuptime,C_FIELD validbeforePCLK edge ns PCLK) NegativeEdge 1.5 PositiveEdge 1.5th(PCLK-14 Holdtime,C_FIELD validafterPCLK edge ns C_FIELDV) NegativeEdge 2.5

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(Positive Edge Clocking) PCLK (Negative Edge Clocking) 7, 9 HD/VD CIN[7:0]/YIN[7:0]/ CCD[15:0] 8, 10 11, 13 12, 14 C_WE/C_FIELD PCLK (Positive Edge Clocking) 15 16 23 24 CIN[7:0]/YIN[7:0]/ CCD[15:0] C_WE/C_FIELD PCLK (Positive Edge Clocking) TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure6-32.VPFE (ISIF)SlaveMode InputData Timing Table6-47.Timing Requirements forVPFE (ISIF)Master Mode (1)(seeFigure6-33) DEVICE UNINO. TMIN MAX PositiveEdge 2.5tsu(DATAV-15 Setuptime,ISIFDATA validbeforePCLK edge ns PCLK) NegativeEdge 1.5 PositiveEdge 1.5 16 th(PCLK-DATAV) Holdtime,ISIFDATA validafterPCLK edge ns NegativeEdge 2.5 PositiveEdge 2.5 23 tsu(CWEV-PCLK) Setuptime,C_WE validbeforePCLK edge ns NegativeEdge 1.5 PositiveEdge 1.5 24 th(PCLK-CWEV) Holdtime,C_WE validafterPCLK edge ns NegativeEdge 2.5 (1) The VPFE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode the risingedge ofPCLK isreferenced.When innegativeedge clockingmode thefallingedge ofPCLK isreferenced. Figure6-33.VPFE (ISIF)Master Mode InputData Timing Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 137 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

(Positive□Edge□Clocking) HD VD PCLK (Negative□Edge□Clocking) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-48.SwitchingCharacteristicsOver Recommended OperatingConditionsforVPFE (ISIF)Master Mode (seeFigure6-34) DEVICE NO. PARAMETER UNIT MIN MAX 18 td(PCLKL-HDIV) Delaytime,PCLK edge toHD valid 1.5 11 ns 20 td(PCLKL-VDIV) Delaytime,PCLK edge toVD valid 1.5 11 ns Figure6-34.VPFE (ISIF)Master Mode ControlOutput Data Timing

6.12.2 Video ProcessingBack-End (VPBE)

The Video ProcessingBack-End ofVPBE module iscomprisedoftheOn Screen Display(OSD) module and theVideoEncoder/DigitalLCD Controller(VENC/DLCD). Table6-49liststheVideoProcessingBack-End (VPBE) module registers,theircorrespondingacronyms, and thedevicememory locations(offsets). Note:HD displaymode resolutionsarenotsupportedon ARM 216MHz clockratedevices. Table6-49.VPBE Module RegisterMap Address Peripheral Description 0x01C7:0200 VPBE_CLK_CTRL VPBE ClockControl 0x01C7:1C00 OSD VPBE On-ScreenDisplay 0x01C7:1E00 VENC VPBE VideoEncoder 6.12.2.1On-Screen Display(OSD) The primaryfunctionoftheOSD module istogatherand blendvideodataand display/bitmapdataand then pass itto the Video Encoder (VENC) inYCbCr format.The videoand displaydata isread from externalDDR2/mDDR memory. The OSD is programmed via controland parameter registers.The followingaretheprimaryfeaturesthataresupportedby theOSD.

• Supportfortwo videowindows and two OSD bitmappedwindows thatcan be displayedsimultaneously (VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1).
• Video windows supportYCbCr datain422 and 420 formatsfrom externalmemory, withtheabilityto interchangetheorderoftheCbCr component inthe32-bitword
• OSD bitmapwindows support= 4/8bitwidthindexdataofcolorpalette
• Inadditionone OSD bitmapwindow ata timecan be configuredtoone ofthefollowing: – YUV422 (same as videodata) – RGB formatdatain16-bitmode (R=5bit,G=6bit,B=5bit) – 24-bitmode (eachR/G/B=8bit)withpixellevelblendingwithvideowindows
• Programmable colorpalettewiththeabilitytoselectbetween a RAM/ROM tablewithsupportfor256 colors.
• Supportfor2 ROM tables,one ofwhichcan be selectedata giventime
• Separateenable/disablecontrolforeach window

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• Programmable width,height,and base startingcoordinatesforeach window
• Externalmemory addressand offsetregistersforeach window
• Supportforx2 and x4 zoom inboththehorizontaland verticaldirection
• Pixel-levelblending/transparency/blinkingattributescan be definedforOSDWIN0 when OSDWIN1 is configuredas an attributewindow forOSDWIN0.
• Supportforblinkingintervalstotheattributewindow
• Abilitytoselecteitherfield/framemode forthewindows (interlaced/progressive)
• An eightstepblendingprocessbetween thebitmapand videowindows
• Transparencysupportforthe bitmapand videodata (when a bitmappixeliszero,therewillbe no blendingforthatcorrespondingvideopixel)
• AbilitytoresizefromVGA toNTSC/PAL (640x480to720x576)forboththeOSD and videowindows
• Horizontalrescalingx1.5issupported
• Supportfora rectangularcursorwindow and a programmablebackgroundcolorselection.
• The width,height,and colorofthecursorisselectable
• The displaypriorityis:Rectangular-Cursor> OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 > backgroundcolor
• SupportforattenuationoftheYCbCr valuesfortheREC601 standard. The followingrestrictionsexistintheOSD module.
• Iftheverticalresizefilterisenabledforeitherofthevideowindows,themaximum horizontalwindow dimensioncannotbe greaterthan 1024 currently.Thisisdue to the limitationinthe sizeof the line memory.
• Itisnotpossibletouse bothoftheCLUT ROMs atthesame time.However,a window can use RAM whileanotheruses ROM. Table 6-50 liststhe On-Screen Display(OSD) registers,theircorrespondingacronyms,and the device memory locations(offsets). Table6-50.On-Screen Display(OSD) Registers Offset Acronym RegisterDescription 0h MODE OSD Mode Setup 4h VIDWINMD VideoWindow Mode Setup 8h OSDWIN0MD BitmapWindow 0 Mode Setup Ch OSDWIN1MD OSD Window 1 Mode Setup (when used as a second OSD window) Ch OSDATRMD OSD AttributeWindow Mode Setup (when used as an attributewindow) 10h RECTCUR RectangularCursorSetup 14h RSV0 Reserved 18h VIDWIN0OFST VideoWindow 0 Offset 1Ch VIDWIN1OFST VideoWindow 1 Offset 20h OSDWIN0OFST BitmapWindow 0 Offset 24h OSDWIN1OFST BitmapWindow 1/AttributeWindow Offset 28h VIDWINADH VideoWindow 0/1Address-High 2Ch VIDWIN0ADL VideoWindow 0 Address-Low 30h VIDWIN1ADL VideoWindow 1 Address-Low 34h OSDWINADH BMP Window 0/1Address-High 38h OSDWIN0ADL BMP Window 0 Address-Low 3Ch OSDWIN1ADL BitmapWindow 1/AttributeAddress-Low 40h BASEPX Base PixelX Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 139 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-50.On-Screen Display(OSD) Registers(continued) Offset Acronym RegisterDescription 44h BASEPY Base PixelY 48h VIDWIN0XP VideoWindow 0 X-Position 4Ch VIDWIN0YP VideoWindow 0 Y-Position 50h VIDWIN0XL VideoWindow 0 X-Size 54h VIDWIN0YL VideoWindow 0 Y-Size 58h VIDWIN1XP VideoWindow 1 X-Position 5Ch VIDWIN1YP VideoWindow 1 Y-Position 60h VIDWIN1XL VideoWindow 1 X-Size 64h VIDWIN1YL VideoWindow 1 Y-Size 68h OSDWIN0XP BitmapWindow 0 X-Position 6Ch OSDWIN0YP BitmapWindow 0 Y-Position 70h OSDWIN0XL BitmapWindow 0 X-Size 74h OSDWIN0YL BitmapWindow 0 Y-Size 78h OSDWIN1XP BitmapWindow 1 X-Position 7Ch OSDWIN1YP BitmapWindow 1 Y-Position 80h OSDWIN1XL BitmapWindow 1 X-Size 84h OSDWIN1YL BitmapWindow 1 Y-Size 88h CURXP RectangularCursorWindow X-Position 8Ch CURYP RectangularCursorWindow Y-Position 90h CURXL RectangularCursorWindow X-Size 94h CURYL RectangularCursorWindow Y-Size 98h RSV1 Reserved 9Ch RSV2 Reserved A0h W0BMP01 Window 0 BitmapValuetoPaletteMap 0/1 A4h W0BMP23 Window 0 BitmapValuetoPaletteMap 2/3 A8h W0BMP45 Window 0 BitmapValuetoPaletteMap 4/5 ACh W0BMP67 Window 0 BitmapValuetoPaletteMap 6/7 B0h W0BMP89 Window 0 BitmapValuetoPaletteMap 8/9 B4h W0BMPAB Window 0 BitmapValuetoPaletteMap A/B B8h W0BMPCD Window 0 BitmapValuetoPaletteMap C/D BCh W0BMPEF Window 0 BitmapValuetoPaletteMap E/F C0h W1BMP01 Window 1 BitmapValuetoPaletteMap 0/1 C4h W1BMP23 Window 1 BitmapValuetoPaletteMap 2/3 C8h W1BMP45 Window 1 BitmapValuetoPaletteMap 4/5 CCh W1BMP67 Window 1 BitmapValuetoPaletteMap 6/7 D0h W1BMP89 Window 1 BitmapValuetoPaletteMap 8/9 D4h W1BMPAB Window 1 BitmapValuetoPaletteMap A/B D8h W1BMPCD Window 1 BitmapValuetoPaletteMap C/D DCh W1BMPEF Window 1 BitmapValuetoPaletteMap E/F E0h VBNDRY TestMode E4h EXTMODE ExtendedMode E8h MISCCTL MiscellaneousControl ECh CLUTRAMYCB CLUT RAM Y/Cb Setup F0h CLUTRAMCR CLUT RAM Cr/MappingSetup F4h TRANSPVALL TransparentColorCode -Lower F8h TRANSPVALU TransparentColorCode -Upper FCh TRANSPBMPIDX TransparentIndexCode forBitmaps

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 6.12.2.2Video Encoder /DigitalLCD Controller(VENC/DLCD) The VENC/DLCD consistsofthreemajorblocks:

• Videoencodertogenerateanalogvideooutput
• DigitalLCD controllertogeneratedigitalRGB/YCbCr dataoutputand timingsignals
• Timinggenerator The videoencoderforanalogvideosupportsthefollowingfeatures:
• MasterClockInput-27 MHz or74.25MHz
• SDTV Support – CompositeNTSC-M, PAL-B/D/G/H/I – S-Video(Y/C) – Component YPbPr – RGB – CGMS/WSS – ClosedCaption
• HDTV Support – 525p/625p/720p/1080i – Component YPbPr – RGB – CGMS/WSS
• Master/SlaveOperation
• Three10-bitD/A Converters The digitalLCD controllersupportsthefollowingfeatures:
• Programmable TimingGenerator
• VariousOutputFormats – YCbCr 4:2:216-bit – YCbCr 4:2:28-bit – ParallelRGB 16/18/24-bit – SerialRGB 8-bit
• EAV/SAV insertion
• Master/SlaveOperation Table6-51 liststheVideo Encoder /DigitalLCD Controller(VENC/DLCD) registers,theircorresponding acronyms,and thedevicememory locations(offsets). Table6-51.Video Encoder (VENC) Registers Offset Acronym RegisterDescription 0h VMOD VideoMode 4h VIOCTL VideoInterfaceI/OControl 8h VDPRO VideoData Processing Ch SYNCCTL Sync Control 10h HSPLS HorizontalSync PulseWidth 14h VSPLS VerticalSync PulseWidth 18h HINTVL HorizontalInterval 1Ch HSTART HorizontalValidData StartPosition 20h HVALID HorizontalData ValidRange 24h VINTVL VerticalInterval 28h VSTART VerticalValidData StartPosition Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 141 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-51.Video Encoder (VENC) Registers(continued) Offset Acronym RegisterDescription 2Ch VVALID VerticalData ValidRange 30h HSDLY HorizontalSync Delay 34h VSDLY VerticalSync Delay 38h YCCCTL YCbCr Control 3Ch RGBCTL RGB Control 40h RGBCLP RGB LevelClipping 44h LINECTL LineID Control 48h CULLLINE CullingLineControl 4Ch LCDOUT LCD OutputSignalControl 50h BRT0 BrightnessStartPositionSignalControl 54h BRT1 BrightnessWidthSignalControl 58h ACCTL LCD_AC SignalControl 5Ch PWM0 PWM OutputPeriod 60h PWM1 PWM OutputPulseWidth 64h DCLKCTL DCLK Control 68h DCLKPTN0 DCLK Pattern0 6Ch DCLKPTN1 DCLK Pattern1 70h DCLKPTN2 DCLK Pattern2 74h DCLKPTN3 DCLK Pattern3 78h DCLKPTN0A DCLK AuxiliaryPattern0 7Ch DCLKPTN1A DCLK AuxiliaryPattern1 80h DCLKPTN2A DCLK AuxiliaryPattern2 84h DCLKPTN3A DCLK AuxiliaryPattern3 88h DCLKHSTT HorizontalDCLK Mask StartPosition 8Ch DCLKHSTTA HorizontalAuxiliaryDCLK Mask StartPosition 90h DCLKHVLD HorizontalDCLK Mask Range 94h DCLKVSTT VerticalDCLK Mask StartPosition 98h DCLKVVLD VerticalDCLK Mask Range 9Ch CAPCTL ClosedCaptionControl A0h CAPDO ClosedCaptionOdd FieldData A4h CAPDE ClosedCaptionEven FieldData A8h ATR0 VideoAttributeData 0 ACh ATR1 VideoAttributeData 1 B0h ATR2 VideoAttributeData 2 B4h RSV0 Reserved0 B8h VSTAT VideoStatus BCh RAMADR GCP/FRC TableRAM Address C0h RAMPORT GCP/FRC TableRAM Data Port C4h DACTST DAC Test C8h YCOLVL YOUT and COUT Levels CCh SCPROG Sub-CarrierProgramming D0h RSV1 Reserved1 D4h RSV2 Reserved2 D8h RSV3 Reserved3 DCh CVBS CompositeMode E0h CMPNT Component Mode E4h ETMG0 CVBS TimingControl0

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-51.Video Encoder (VENC) Registers(continued) Offset Acronym RegisterDescription E8h ETMG1 CVBS TimingControl1 ECh ETMG2 CVBS TimingControl2 F0h ETMG3 CVBS TimingControl3 F4h DACSEL DAC OutputSelect 100h ARGBX0 AnalogRGB Matrix0 104h ARGBX1 AnalogRGB Matrix1 108h ARGBX2 AnalogRGB Matrix2 10Ch ARGBX3 AnalogRGB Matrix3 110h ARGBX4 AnalogRGB Matrix4 114h DRGBX0 DigitalRGB Matrix0 118h DRGBX1 DigitalRGB Matrix1 11Ch DRGBX2 DigitalRGB Matrix2 120h DRGBX3 DigitalRGB Matrix3 124h DRGBX4 DigitalRGB Matrix4 128h VSTARTA VerticalData ValidStartPositionForEven Field 12Ch OSDCLK0 OSD ClockControl0 130h OSDCLK1 OSD ClockControl1 134h HVLDCL0 HorizontalValidCullingControl0 138h HVLDCL1 HorizontalValidCullingControl1 13Ch OSDHADV OSD HorizontalSync Advance 140h CLKCTL ClockControl 144h GAMCTL EnableGamma Correction 148h VVALIDA VerticalData ValidArea ForEven Field 14Ch BATR0 VideoAttribute0 ForType B Packet 150h BATR1 VideoAttribute1 ForType B Packet 154h BATR2 VideoAttribute2 ForType B Packet 158h BATR3 VideoAttribute3 ForType B Packet 15Ch BATR4 VideoAttribute4 ForType B Packet 160h BATR5 VideoAttribute5 ForType B Packet 164h BATR6 VideoAttribute6 ForType B Packet 168h BATR7 VideoAttribute7 ForType B Packet 16Ch BATR8 VideoAttribute8 ForType B Packet 170h DACAMP Gain and Offset 6.12.2.3VPBE ElectricalData/Timing Table6-52.Timing Requirements forVPBE CLK Inputs(seeFigure6-35) DEVICE NO. UNIT MIN MAX 1 tc(PCLK) Cycletime,PCLK (1) 13.33 160 ns 2 tw(PCLKH) Pulseduration,PCLK high 5.7 ns 3 tw(PCLKL) Pulseduration,PCLK low 5.7 ns 4 tt(PCLK) Transitiontime,PCLK 3 ns 5 tc(EXTCLK) Cycletime,EXTCLK 13.33 160 ns 6 tw(EXTCLKH) Pulseduration,EXTCLK high 5.7 ns 7 tw(EXTCLKL) Pulseduration,EXTCLK low 5.7 ns (1) FortimingspecificationsrelatingtoPCLK see Table6-45,TimingRequirementsforVPFE PCLK Master/SlaveMode . Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

VCLKIN(A) (Positive Edge Clocking) VCLKIN(A) (Negative Edge Clocking) VCTL(B) A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. B. VCTL = HSYNC, VSYNC, and FIELD TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-52.Timing Requirements forVPBE CLK Inputs(seeFigure6-35)(continued) DEVICE NO. UNIT MIN MAX 8 tt(EXTCLK) Transitiontime,EXTCLK 3 ns Figure6-35.VPBE PCLK and EXTCLK Timing Table6-53.Timing Requirements forVPBE ControlInputWith Respect toPCLK and EXTCLK (1)(2)(3)(see Figure6-36) DEVICE UNINO. TMIN MAX PositiveEdge 4tsu(VCTLV- Setuptime,VCTL validbeforeVCLKIN9 ns VCLKIN) edge NegativeEdge 3 PositiveEdge 1th(VCLKIN-10 Holdtime,VCTL validafterVCLKIN edge ns VCTLV) NegativeEdge 2 (1) The VPBE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode, the risingedge ofVCLKIN isreferenced.When innegativeedge clockingmode, thefallingedge ofVCLKIN isreferenced. (2) VCTL = HSYNC, VSYNC, and FIELD (3) VCLKIN = PCLK orEXTCLK. Positiveand NegativeEdge applytoPCLK only;EXTCLK does notsupportNegativeEdge clocking. Figure6-36.VPBE InputTiming With Respect toPCLK and EXTCLK

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VCLKIN(A) (Positive Edge Clocking) VCLKIN(A) (Negative Edge Clocking) VCTL(B) A. VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] VDATA(C) TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-54.SwitchingCharacteristicsOver Recommended OperatingConditionsforVPBE Controland Data Output With Respect toPCLK and EXTCLK (1)(2)(3)(seeFigure6-37) DEVICE NO. PARAMETER UNIT MIN MAX PositiveEdge 15td(VCLKIN-11 Delaytime,VCLKIN edge toVCTL valid ns VCTLV) NegativeEdge 16 td(VCLKIN-12 Delaytime,VCLKIN edge toVCTL invalid 2 ns VCTLIV) VCLKIN = EXTCLK 15td(VCLKIN-13 Delaytime,VCLKIN edge toVDATA valid ns VDATAV) VCLKIN = PCLK 17.5 td(VCLKIN-14 Delaytime,VCLKIN edge toVDATA invalid 2 ns VDATAIV) (1) The VPBE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode, the risingedge ofVCLKIN isreferenced.When innegativeedge clockingmode, thefallingedge ofVCLKIN isreferenced. (2) VCLKIN = PCLK orEXTCLK. Positiveand NegativeEdge applytoPCLK only;EXTCLK does notsupportNegativeEdge clocking. (3) VCTL = HSYNC, VSYNC, FIELD,and LCD_OE. Figure6-37.VPBE Controland Data Output With Respect toPCLK and EXTCLK Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

(Positive Edge Clocking) VCLK (Negative Edge Clocking) VCTL(B) VDATA(C) 1822 23 24 25 26 VCLKIN(A) B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE C. VDATA = COUT[7:0], YOUT[7:0], R[7:0], G[7:0], and B[7:0] 2020 VCLKIN = PCLK or EXTCLK. Note Positive and Negative edge apply for PCLK only, EXTCLK does not support negative edge clocking. TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-55.SwitchingCharacteristicsOver Recommended OperatingConditionsforVPBE Controland Data Output With Respect toVCLK (1)(2)(3)(seeFigure6-38) DEVICE NO. PARAMETER UNIT MIN MAX 17 tc(VCLK) Cycletime,VCLK 13.33 160 ns 18 tw(VCLKH) Pulseduration,VCLK high 5.7 ns 19 tw(VCLKL) Pulseduration,VCLK low 5.7 ns 20 tt(VCLK) Transitiontime,VCLK 3 ns 21 td(VCLKINH-VCLKH) Delaytime,VCLKIN hightoVCLK high 3 16 ns 22 td(VCLKINL-VCLKL) Delaytime,VCLKIN lowtoVCLK low 3 16 ns 23 td(VCLK-VCTLV) Delaytime,VCLK edge toVCTL valid 1.5 ns 24 td(VCLK-VCTLIV) Delaytime,VCLK edge toVCTL invalid -1.5 ns 25 td(VCLK-VDATAV) Delaytime,VCLK edge toVDATA valid 1.5 ns 26 td(VCLK-VDATAIV) Delaytime,VCLK edge toVDATA invalid -1.5 ns (1) The VPBE may be configuredtooperateineitherpositiveornegativeedge clockingmode. When inpositiveedge clockingmode, the risingedge ofVCLK isreferenced.When innegativeedge clockingmode, thefallingedge ofVCLK isreferenced. (2) VCLKIN = PCLK orEXTCLK. Positiveand Negativeedge applyforPCLK only,EXTCLK does notsupportnegativeedge clocking.For timingspecificationsrelatingtoPCLK, see Table6-45,TimingRequirementsforVPFE PCLK Master/SlaveMode . (3) VCTL= HSYNC, VSYNC, FIELD and LCD_OE. Figure6-38.VPBE Controland Data Output Timing With Respect toVCLK 6.12.2.4High-Definition(HD) DACs and Video BufferElectricalData/Timing ThreeDACs and a videobufferareavailableon thedevice. 6.12.2.4.1HD DACs-Only Option IntheHD DACs-only configuration,theinternalvideobufferisnotused and an externalvideobufferis attachedto the DACs. Anothersolutionisto use a Video Amplifier,such as the Texas Instruments' THS7303 whichprovidesa completesolutiontothetypicaloutputcircuitshown inFigure6-39. Note:HD displaymode resolutionsarenotsupportedon ARM 216MHz clockratedevices.

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75 Ω Low-Pass Filter ~R = 75 ΩLOAD Amplifier Gain = 5.6 V/V 75 Ω 75 Ω DAC CH-A 75 Ω 75 Ω 75 Ω Low-Pass Filter ~R = 75 ΩLOAD Low-Pass Filter ~R = 75 ΩLOAD Amplifier Gain = 5.6 V/V Amplifier Gain = 5.6 V/V CBG 0.1 µF DC = 0.5 V DAC CH-B DAC CH-C TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 A. RBIAS = 2400Ω. B. VREF = 0.5V(fromexternalsupply). C. IDACOUT must be connectedtoVss orleftopen forproperdeviceconfiguration. D. VFB must be connectedtoVss orleftopen forproperdeviceconfiguration. E. TVOUT must be connectedtoVss orleftopen forproperdeviceconfiguration. Figure6-39.HD Video DAC ApplicationExample 6.12.2.4.2DAC With Video BufferOption Ina DAC plusvideobufferconfiguration,one oftheDACs may be used alongwiththevideobufferfor standarddefinitionTVOUT mode. IntheDAC plusvideobufferconfiguration,theDAC and internalvideo bufferarebothused,and a TV cablemay be attacheddirectlytotheoutputofthevideobuffer.Figure6-40 shows an example oftheDAC PlusVideoBufferOptioncircuitconfiguration. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

0.1 µF DC = 0.5 V DAC CHC Video Buffer TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-40.SD Video BufferApplicationExample

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 6.13 USB 2.0 The USB2.0 peripheralsupportsthefollowingfeatures:

• USB 2.0peripheralatspeeds highspeed (HS:480 Mb/s)and fullspeed (FS:12 Mb/s)
• USB 2.0hostatspeeds HS, FS, and lowspeed (LS:1.5Mb/s)
• Alltransfermodes (control,bulk,interrupt,and isochronous)
• FourTransmit(TX)and fourReceive(RX)endpointsinadditiontoendpoint0
• FIFO RAM – 4K bytessharedby allendpoints. – Programmable FIFO size
• Includesa DMA sub-modulethatsupportsfourTX and fourRX channelsofCPPI 3.0DMAs
• RNDIS mode foracceleratingRNDIS typeprotocolsusingshortpacketterminationoverUSB
• USB OTG extensions,i.e.sessionrequestprotocol(SRP) and hostnegotiationprotocol(HNP) The USB2.0 peripheraldoes notsupportthefollowingfeatures:
• On-chipchargepump
• HighbandwidthISO mode isnotsupported(triplebuffering)
• RNDIS mode accelerationforUSB sizesthatarenotmultiplesof64 bytes
• Endpointmax USB packetsizesthatdo notconformtotheUSB 2.0spec (forFS/LS:8,16,32,64, and 1023 aredefined;forHS: 64,128,512,and 1024 aredefined)

6.13.1 USB PeripheralRegisterDescription(s)

Table 6-56 liststhe USB registers,theircorrespondingacronyms, and the devicememory locations (offsets). Table6-56.UniversalSerialBus (USB) Registers Offset Acronym RegisterDescription 4h CTRLR ControlRegister 8h STATR StatusRegister 10h RNDISR RNDIS Register 14h AUTOREQ AutorequestRegister 20h INTSRCR USB InterruptSourceRegister 24h INTSETR USB InterruptSourceSetRegister 28h INTCLRR USB InterruptSourceClearRegister 2Ch INTMSKR USB InterruptMask Register 30h INTMSKSETR USB InterruptMask SetRegister 34h INTMSKCLRR USB InterruptMask ClearRegister 38h INTMASKEDR USB InterruptSourceMasked Register 3Ch EOIR USB End ofInterruptRegister 40h INTVECTR USB InterruptVectorRegister 80h TCPPICR TransmitCPPI ControlRegister 84h TCPPITDR TransmitCPPI Teardown Register 88h TCPPIEOIR TransmitCPPI DMA ControllerEnd ofInterruptRegister 8Ch Reserved - 90h TCPPIMSKSR TransmitCPPI Masked StatusRegister 94h TCPPIRAWSR TransmitCPPI Raw StatusRegister 98h TCPPIIENSETR TransmitCPPI InterruptEnableSetRegister 9Ch TCPPIIENCLRR TransmitCPPI InterruptEnableClearRegister C0h RCPPICR ReceiveCPPI ControlRegister D0h RCPPIMSKSR ReceiveCPPI Masked StatusRegister Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-56.UniversalSerialBus (USB) Registers(continued) Offset Acronym RegisterDescription D4h RCPPIRAWSR ReceiveCPPI Raw StatusRegister D8h RCPPIENSETR ReceiveCPPI InterruptEnableSetRegister DCh RCPPIIENCLRR ReceiveCPPI InterruptEnableClearRegister E0h RBUFCNT0 ReceiveBufferCount 0 Register E4h RBUFCNT1 ReceiveBufferCount 1 Register E8h RBUFCNT2 ReceiveBufferCount 2 Register ECh RBUFCNT3 ReceiveBufferCount 3 Register Transmit/ReceiveCPPI Channel 0 StateBlock 100h TCPPIDMASTATEW0 TransmitCPPI DMA StateWord 0 104h TCPPIDMASTATEW1 TransmitCPPI DMA StateWord 1 108h TCPPIDMASTATEW2 TransmitCPPI DMA StateWord 2 10Ch TCPPIDMASTATEW3 TransmitCPPI DMA StateWord 3 110h TCPPIDMASTATEW4 TransmitCPPI DMA StateWord 4 114h TCPPIDMASTATEW5 TransmitCPPI DMA StateWord 5 11Ch TCPPICOMPPTR TransmitCPPI CompletionPointer 120h RCPPIDMASTATEW0 ReceiveCPPI DMA StateWord 0 124h RCPPIDMASTATEW1 ReceiveCPPI DMA StateWord 1 128h RCPPIDMASTATEW2 ReceiveCPPI DMA StateWord 2 12Ch RCPPIDMASTATEW3 ReceiveCPPI DMA StateWord 3 130h RCPPIDMASTATEW4 ReceiveCPPI DMA StateWord 4 134h RCPPIDMASTATEW5 ReceiveCPPI DMA StateWord 5 138h RCPPIDMASTATEW6 ReceiveCPPI DMA StateWord 6 13Ch RCPPICOMPPTR ReceiveCPPI CompletionPointer Transmit/ReceiveCPPI Channel 1 StateBlock 140h TCPPIDMASTATEW0 TransmitCPPI DMA StateWord 0 144h TCPPIDMASTATEW1 TransmitCPPI DMA StateWord 1 148h TCPPIDMASTATEW2 TransmitCPPI DMA StateWord 2 14Ch TCPPIDMASTATEW3 TransmitCPPI DMA StateWord 3 150h TCPPIDMASTATEW4 TransmitCPPI DMA StateWord 4 154h TCPPIDMASTATEW5 TransmitCPPI DMA StateWord 5 15Ch TCPPICOMPPTR TransmitCPPI CompletionPointer 160h RCPPIDMASTATEW0 ReceiveCPPI DMA StateWord 0 164h RCPPIDMASTATEW1 ReceiveCPPI DMA StateWord 1 168h RCPPIDMASTATEW2 ReceiveCPPI DMA StateWord 2 16Ch RCPPIDMASTATEW3 ReceiveCPPI DMA StateWord 3 170h RCPPIDMASTATEW4 ReceiveCPPI DMA StateWord 4 174h RCPPIDMASTATEW5 ReceiveCPPI DMA StateWord 5 178h RCPPIDMASTATEW6 ReceiveCPPI DMA StateWord 6 17Ch RCPPICOMPPTR ReceiveCPPI CompletionPointer Transmit/ReceiveCPPI Channel 2 StateBlock 180h TCPPIDMASTATEW0 TransmitCPPI DMA StateWord 0 184h TCPPIDMASTATEW1 TransmitCPPI DMA StateWord 1 188h TCPPIDMASTATEW2 TransmitCPPI DMA StateWord 2 18Ch TCPPIDMASTATEW3 TransmitCPPI DMA StateWord 3 190h TCPPIDMASTATEW4 TransmitCPPI DMA StateWord 4 194h TCPPIDMASTATEW5 TransmitCPPI DMA StateWord 5 19Ch TCPPICOMPPTR TransmitCPPI CompletionPointer

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-56.UniversalSerialBus (USB) Registers(continued) Offset Acronym RegisterDescription 1A0h RCPPIDMASTATEW0 ReceiveCPPI DMA StateWord 0 1A4h RCPPIDMASTATEW1 ReceiveCPPI DMA StateWord 1 1A8h RCPPIDMASTATEW2 ReceiveCPPI DMA StateWord 2 1ACh RCPPIDMASTATEW3 ReceiveCPPI DMA StateWord 3 1B0h RCPPIDMASTATEW4 ReceiveCPPI DMA StateWord 4 1B4h RCPPIDMASTATEW5 ReceiveCPPI DMA StateWord 5 1B8h RCPPIDMASTATEW6 ReceiveCPPI DMA StateWord 6 1BCh RCPPICOMPPTR ReceiveCPPI CompletionPointer Transmit/ReceiveCPPI Channel 3 StateBlock 1C0h TCPPIDMASTATEW0 TransmitCPPI DMA StateWord 0 1C4h TCPPIDMASTATEW1 TransmitCPPI DMA StateWord 1 1C8h TCPPIDMASTATEW2 TransmitCPPI DMA StateWord 2 1CCh TCPPIDMASTATEW3 TransmitCPPI DMA StateWord 3 1D0h TCPPIDMASTATEW4 TransmitCPPI DMA StateWord 4 1D4h TCPPIDMASTATEW5 TransmitCPPI DMA StateWord 5 1DCh TCPPICOMPPTR TransmitCPPI CompletionPointer 1E0h RCPPIDMASTATEW0 ReceiveCPPI DMA StateWord 0 1E4h RCPPIDMASTATEW1 ReceiveCPPI DMA StateWord 1 1E8h RCPPIDMASTATEW2 ReceiveCPPI DMA StateWord 2 1ECh RCPPIDMASTATEW3 ReceiveCPPI DMA StateWord 3 1F0h RCPPIDMASTATEW4 ReceiveCPPI DMA StateWord 4 1F4h RCPPIDMASTATEW5 ReceiveCPPI DMA StateWord 5 1F8h RCPPIDMASTATEW6 ReceiveCPPI DMA StateWord 6 1FCh RCPPICOMPPTR ReceiveCPPI CompletionPointer Common USB Registers 400h FADDR FunctionAddressRegister 401h POWER Power Management Register 402h INTRTX InterruptRegisterforEndpoint0 plusTransmitEndpoints1 to4 404h INTRRX InterruptRegisterforReceiveEndpoints1 to4 406h INTRTXE InterruptenableregisterforINTRTX 408h INTRRXE InterruptEnableRegisterforINTRRX 40Ah INTRUSB InterruptRegisterforCommon USB Interrupts 40Bh INTRUSBE InterruptEnableRegisterforINTRUSB 40Ch FRAME Frame Number Register 40Eh INDEX IndexRegisterforSelectingtheEndpointStatusand ControlRegisters 40Fh TESTMODE RegistertoEnabletheUSB 2.0TestModes Indexed Registers These registersoperateon theendpointselectedby theINDEX register 410h TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint. (IndexregistersettoselectEndpoints1-4) 412h PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralMode. (IndexregistersettoselectEndpoint0) HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostMode. (IndexregistersettoselectEndpoint0) PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint. (IndexregistersettoselectEndpoints1-4) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint. (IndexregistersettoselectEndpoints1-4) Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-56.UniversalSerialBus (USB) Registers(continued) Offset Acronym RegisterDescription 414h RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint. (IndexregistersettoselectEndpoints1-4) 416h PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint. (IndexregistersettoselectEndpoints1-4) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint. (IndexregistersettoselectEndpoints1-4) 418h COUNT0 Number ofReceivedBytesinEndpoint0 FIFO. (IndexregistersettoselectEndpoint0) RXCOUNT Number ofBytesinHostReceiveEndpointFIFO. (IndexregistersettoselectEndpoints1-4) 41Ah HOST_TYPE0 Definesthespeed ofEndpoint0 HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. (IndexregistersettoselectEndpoints1-4) 41Bh HOST_NAKLIMIT0 SetstheNAK responsetimeouton Endpoint0. (IndexregistersettoselectEndpoint0) HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint.(Indexregistersetto selectEndpoints1-4) 41Ch HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. (IndexregistersettoselectEndpoints1-4) 41Dh HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint.(Indexregistersettoselect Endpoints1-4) 41Fh CONFIGDATA Returnsdetailsofcoreconfiguration.(IndexregistersettoselectEndpoint0) FIFOn 420h FIFO0 Transmitand ReceiveFIFO RegisterforEndpoint0 424h FIFO1 Transmitand ReceiveFIFO RegisterforEndpoint1 428h FIFO2 Transmitand ReceiveFIFO RegisterforEndpoint2 42Ch FIFO3 Transmitand ReceiveFIFO RegisterforEndpoint3 430h FIFO4 Transmitand ReceiveFIFO RegisterforEndpoint4 OTG Device Control 460h DEVCTL OTG DeviceControlRegister Dynamic FIFO Control 462h TXFIFOSZ TransmitEndpointFIFO Size (IndexregistersettoselectEndpoints1-4) 463h RXFIFOSZ ReceiveEndpointFIFO Size (IndexregistersettoselectEndpoints1-4) 464h TXFIFOADDR TransmitEndpointFIFO Address (IndexregistersettoselectEndpoints1-4) 466h RXFIFOADDR ReceiveEndpointFIFO Address (IndexregistersettoselectEndpoints1-4) TargetEndpoint 0 ControlRegisters,ValidOnly inHost Mode 480h TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 482h TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 483h TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 484h RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-56.UniversalSerialBus (USB) Registers(continued) Offset Acronym RegisterDescription 486h RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 487h RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 1 ControlRegisters,ValidOnly inHost Mode 488h TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 48Ah TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 48Bh TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 48Ch RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 48Eh RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 48Fh RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 2 ControlRegisters,ValidOnly inHost Mode 490h TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 492h TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 493h TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 494h RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 496h RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 497h RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 3 ControlRegisters,ValidOnly inHost Mode 498h TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 49Ah TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 49Bh TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 49Ch RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 49Eh RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 49Fh RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 4 ControlRegisters,ValidOnly inHost Mode Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-56.UniversalSerialBus (USB) Registers(continued) Offset Acronym RegisterDescription 4A0h TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 4A2h TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 4A3h TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 4A4h RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 4A6h RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 4A7h RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. Controland StatusRegisterforEndpoint 0 502h PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralMode HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostMode 508h COUNT0 Number ofReceivedBytesinEndpoint0 FIFO 50Ah HOST_TYPE0 DefinestheSpeed ofEndpoint0 50Bh HOST_NAKLIMIT0 SetstheNAK Response Timeouton Endpoint0 50Fh CONFIGDATA Returnsdetailsofcoreconfiguration. Controland StatusRegisterforEndpoint 1 510h TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 512h PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint (peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint (hostmode) 514h RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 516h PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint (peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint (hostmode) 518h RXCOUNT Number ofBytesinHostReceiveendpointFIFO 51Ah HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 51Bh HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 51Ch HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 51Dh HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Controland StatusRegisterforEndpoint 2 520h TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 522h PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint (peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint (hostmode) 524h RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 526h PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint (peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint (hostmode)

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-56.UniversalSerialBus (USB) Registers(continued) Offset Acronym RegisterDescription 528h RXCOUNT Number ofBytesinHostReceiveendpointFIFO 52Ah HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 52Bh HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 52Ch HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 52Dh HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Controland StatusRegisterforEndpoint 3 530h TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 532h PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint (peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint (hostmode) 534h RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 536h PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint (peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint (hostmode) 538h RXCOUNT Number ofBytesinHostReceiveendpointFIFO 53Ah HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 53Bh HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 53Ch HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 53Dh HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Controland StatusRegisterforEndpoint 4 540h TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 542h PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint (peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint (hostmode) 544h RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 546h PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint (peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint (hostmode) 548h RXCOUNT Number ofBytesinHostReceiveendpointFIFO 54Ah HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 54Bh HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 54Ch HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 54Dh HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

90%□VOH 10%□VOL USB_DM USB_DP tper − tjr TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com 6.13.2 USB2.0 ElectricalData/Timing Table6-57.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB2.0 (see Figure6-41) DEVICE LOW SPEED FULL SPEED HIGH SPEED (1) NO. PARAMETER UNIT1.5Mbps 12 Mbps 480 Mbps MIN MAX MIN MAX MIN MAX 1 tr(D) Risetime,USB_DP and USB_DM signals(2) 75 300 4 20 0.5 20 ns 2 tf(D) Falltime,USB_DP and USB_DM signals(2) 75 300 4 20 0.5 20 ns 3 tfrfm Rise/Falltime,matching(3) 80 125 90 111.11 - - % 4 VCRS Outputsignalcross-overvoltage(2) 1.3 2 1.3 2 - - V 5 tjr(source)NT Source(Host)Driverjitter,nexttransition 2 2 ns tjr(FUNC)NT FunctionDriverjitter,nexttransition 25 2 ns 6 tjr(source)PT Source(Host)Driverjitter,pairedtransition(4) 1 1 ns tjr(FUNC)PT FunctionDriverjitter,pairedtransition 10 1 ns 7 tw(EOPT) Pulseduration,EOP transmitter 1250 1500 160 175 - - ns 8 tw(EOPR) Pulseduration,EOP receiver 670 82 - ns 9 t(DRATE) Data Rate 1.5 12 480 Mb/s 10 ZDRV DriverOutputResistance - - 28 49.5 40.5 49.5 Ω (1) Formore detailedspecificationinformation,see theUniversalSerialBus SpecificationRevision2.0,Chapter7. (2) Low Speed:C L = 200 pF,FullSpeed:C L = 50 pF,HighSpeed:C L = 50 pF (3) tfrfm= (tr/tf)x 100.[ExcludingthefirsttransactionfromtheIdlestate.] (4) tjr= tpx(1)-tpx(0) Figure6-41.USB2.0 IntegratedTransceiverInterfaceTiming

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6.14 UniversalAsynchronous Receiver/Transmitter(UART)

The UART module performsserial-to-parallelconversionon data receivedfrom a peripheraldeviceor modem, and parallel-to-serialconversionon data receivedfrom the CPU. Each UART alsoincludesa programmablebaud rategeneratorcapableofdividingthemodule'sreferenceclockby divisorsfrom1 to 65,535 to produce a 16 x clockdrivingthe internallogic.The UART modules supportthe following features:

• Frequencypre-scalevaluesfrom1 to65,535togenerateappropriatebaud rates
• 16-bytestoragespace forboththetransmitterand receiverFIFOs
• Uniqueinterrupts,one foreach UART
• UniqueEDMA events,bothreceivedand transmitteddataforeach UART
• 1,4,8,or14 byteselectablereceiverFIFO triggerlevelforautoflowcontroland DMA
• Programmable auto-rtsand auto-ctsforautoflowcontrol(supportedon UART1)
• Programmable serialdataformats – 5,6,7,or8-bitcharacters – Even,odd,orno paritybitgenerationand detection – 1,1.5,or2 stopbitgeneration
• Falsestartbitdetection
• Linebreakgenerationand detection
• Internaldiagnosticcapabilities – Loopback controlsforcommunicationslinkfaultisolation – Break,parity,overrun,and framingerrorsimulation
• Modem controlfunctions:CTS, RTS (supportedon UART1)

6.14.1 UART PeripheralRegisterDescription(s)

Table 6-58 liststhe UART registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-58.UART Registers OFFSET ACRONYM REGISTER DESCRIPTION 0h RBR ReceiverBufferRegister(readonly) 0h THR TransmitterHoldingRegister(writeonly) 4h IER InterruptEnableRegister 8h IIR InterruptIdentificationRegister(readonly) 8h FCR FIFO ControlRegister(writeonly) Ch LCR LineControlRegister 10h MCR Modem ControlRegister 14h LSR LineStatusRegister 20h DLL DivisorLSB Latch 24h DLH DivisorMSB Latch 28h PID PeripheralIdentificationRegister 30h PWREMU_MGMT Power and EmulationManagement Register 34h MDR Mode DefinitionRegister

6.14.2 UART ElectricalData/Timing

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Data□Bits UART_TXDn UART_RXDn Data□Bits Bit Start TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-59.Timing Requirements forUARTx Receive (seeFigure6-42)(1) DEVICE NO. UNIT MIN MAX 4 tw(URXDB) Pulseduration,receivedatabit(RXDn) .96U 1.05U ns 5 tw(URXSB) Pulseduration,receivestartbit .96U 1.05U ns (1) U = UART baud time= 1/programmedbaud rate. Table6-60.SwitchingCharacteristicsOver Recommended OperatingConditionsforUARTx Transmit (seeFigure6-42)(1) DEVICE NO. PARAMETER UNIT MIN MAX UART0 Maximum programmablebaud rate 5 1 f(baud) MHz UART1 Maximum programmablebaud rate 5 2 tw(UTXDB) Pulseduration,transmitdatabit(TXDn) U -2 U + 2 ns 3 tw(UTXSB) Pulseduration,transmitstartbit U -2 U + 2 ns (1) U = UART baud time= 1/programmedbaud rate. Figure6-42.UART Transmit/ReceiveTiming

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6.15 SerialPortInterface(SPI)

The SPI module providesa programmable lengthshiftregisterwhich allowsserialcommunicationwith otherSPI devicesthrougha 3 or 4 wireinterface(Clock,Data In,Data Out,and Chip-select).The SPI supportsthefollowingfeatures:

• Masterand Slavemode operationissupportedon allSPI ports(mastermode means thatthedevice providestheserialclock)
• 2 chipselectsforinterfacingtomultipleslaveSPI devices.
• 3 or4 wireinterface(Clock,Data In,Data Out,and Enable)
• Uniqueinterruptforeach SPI port(exceptSPI4)
• SeparateEDMA eventsforSPI Receiveand Transmitforeach SPI port(exceptSPI4)
• 16-bitshiftregister
• Receivebufferregister
• Programmable characterlength(2to16 bits)
• Programmable SPI clockfrequencyrange
• 8-bitclockprescaler
• Programmable clockphase (delayorno delay)
• Programmable clockpolarity Note:SPI4 slavemode does notsupportChip-selectinput,onlysupports3-wireinterface. The SPI modules do notsupportthefollowingfeatures:
• GPIO mode. GPIO functionalityis supportedby the GIO modules forthose SPI pins thatare multiplexedwithGPIO signals.

6.15.1 SPI PeripheralRegisterDescription(s)

Table 6-61 liststhe SPI registers,theircorrespondingacronyms, and the devicememory locations (offsets).These offsetsapplytoalldeviceSPI modules. Table6-61.SPI Registers OFFSET ACRONYM REGISTER DESCRIPTION 00h SPIGCR0 SPI globalcontrolregister0 04h SPIGCR1 SPI globalcontrolregister1 08h SPIINT SPI interruptregister 0Ch SPILVL SPI interruptlevelregister 10h SPIFLG SPI flagregister 14h SPIPC0 SPI pincontrolregister 18h - Reserved 1Ch SPIPC2 SPI pincontrolregister2 20h -38h - Reserved 3Ch SPIDAT1 SPI shiftregister 40h SPIBUF SPI bufferregister 44h SPIEMU SPI emulationregister 48h SPIDELAY SPI delayregister 4Ch SPIDEF SPI defaultchipselectregister 50h-5Ch SPIFMT0 SPI dataformatregister0 60h INTVECT0 SPI interruptvectorregister0 64h INTVECT1 SPI interruptvectorregister1 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.15.2 SPI ElectricalData/Timing

Master Mode — General Table6-62.GeneralSwitchingCharacteristicsinMaster Mode (1) NO. PARAMETER MIN MAX UNIT greaterof2P1 tc(CLK) Cycletime,SPI_SCLK 256P nsor25 .5(tc(CLK))-2 tw(CLKH) Pulsewidth,SPI_SCLK high ns1.25 .5(tc(CLK))-3 tw(CLKL) Pulsewidth,SPI_SCLK low ns1.25 Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_SCLK risingedge,3-/4-pinmode, 6.5 polarity= 0,phase = 0 Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_SCLK risingedge,3-/4-pinmode, .5tc(CLK) + 6.5 polarity= 0,phase = 1 4 tosu(SIMO-CLK) ns Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_SCLK fallingedge,3-/4-pinmode, 6.5 polarity= 1,phase = 0 Outputsetuptime,SPI_SIMO valid(1stbit)beforeinitialSPI_SCLK fallingedge,3-/4-pinmode, .5tc(CLK) + 6.5 polarity= 1,phase = 1 Delaytime,SPI_SCLK transmitrisingedge toSPI_SIMO output -3 6valid(subsequentbitdriven),3-/4-pinmode, polarity= 0,phase = 0 Delaytime,SPI_SCLK transmitfallingedge toSPI_SIMO output -3 6valid(subsequentbitdriven),3-/4-pinmode, polarity= 0,phase = 1 5 td(CLK-SIMO) ns Delaytime,SPI_SCLK transmitfallingedge toSPI_SIMO output -3 6valid(subsequentbitdriven),3-/4-pinmode, polarity= 1,phase = 0 Delaytime,SPI_SCLK transmitrisingedge toSPI_SIMO output -3 6valid(subsequentbitdriven),3-/4-pinmode, polarity= 1,phase = 1 Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive fallingedge ofSPI_SCLK, 9.5 3-/4-pinmode, polarity= 0,phase = 0 Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive risingedge ofSPI_SCLK, 9.5 3-/4-pinmode, polarity= 0,phase = 1 6 toh(CLK-SIMO) ns Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive risingedge ofSPI_SCLK, 9.5 3-/4-pinmode, polarity= 1,phase = 0 Outputholdtime,SPI_SIMO valid(exceptfinalbit)afterreceive fallingedge ofSPI_SCLK, 9.5 3-/4-pinmode, polarity= 1,phase = 1 (1) T = periodofSPI_SCLK; ForSPI0,SPI1,SPI2,and SPI3,P = periodofSPI coreclock(PLL1SYSCLK4). ForSPI4,P = periodofSPI coreclock(OSCIN).

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-63.GeneralInputTiming Requirements inMaster Mode NO. MIN MAX UNIT Setuptime,SPI_SOMI validbeforereceivefallingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 0,phase = 0 Setuptime,SPI_SOMI validbeforereceiverisingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 0,phase = 1 7 tsu(SOMI-CLK) ns Setuptime,SPI_SOMI validbeforereceiverisingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 1,phase = 0 Setuptime,SPI_SOMI validbeforereceivefallingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 1,phase = 1 Holdtime,SPI_SOMI validafterreceivefallingedge ofSPI_SCLK, 43-/4-pinmode, polarity= 0,phase = 0 Holdtime,SPI_SOMI validafterreceiverisingedge ofSPI_SCLK, 43-/4-pinmode, polarity= 0,phase = 1 8 th(CLK-SOMI) ns Holdtime,SPI_SOMI validafterreceiverisingedge ofSPI_SCLK, 43-/4-pinmode, polarity= 1,phase = 0 Holdtime,SPI_SOMI validafterreceivefallingedge ofSPI_SCLK, 43-/4-pinmode, polarity= 1,phase = 1 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com SlaveMode — General Table6-64.GeneralSwitchingCharacteristicsinSlaveMode (For3-/4-PinModes) (1) NO. PARAMETER MIN MAX UNIT Delaytime,transmitrisingedge ofSPI_SCLK toSPI_SOMI output 2 16.5valid,3-/4-pinmode, polarity= 0,phase = 0 Delaytime,transmitfallingedge ofSPI_SCLK toSPI_SOMI output 2 16.5valid,3-/4-pinmode, polarity= 0,phase = 1 13 td(CLK-SOMI) ns Delaytime,transmitfallingedge ofSPI_SCLK toSPI_SOMI output 2 16.5valid,3-/4-pinmode, polarity= 1,phase = 0 Delaytime,transmitrisingedge ofSPI_SCLK toSPI_SOMI output 2 16.5valid,3-/4-pinmode, polarity= 1,phase = 1 Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 4fallingedge ofSPI_SCLK, 3-/4-pinmode, polarity= 0,phase = 0 Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 4risingedge ofSPI_SCLK, 3-/4-pinmode, polarity= 0,phase = 1 14 toh(CLK-SOMI) ns Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 4risingedge ofSPI_SCLK, 3-/4-pinmode, polarity= 1,phase = 0 Outputholdtime,SPI_SOMI valid(exceptfinalbit)afterreceive 4fallingedge ofSPI_SCLK, 3-/4-pinmode, polarity= 1,phase = 1 (1) T = periodofSPI_SCLK

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-65.GeneralInputTiming Requirements inSlaveMode (1) NO. MIN MAX UNIT greaterof2P9 tc(CLK) Cycletime,SPI_SCLK 256P nsor25 .5(tc(CLK))-10 tw(CLKH) Pulsewidth,SPI_SCLK high ns1.25 .5(tc(CLK))-11 tw(CLKL) Pulsewidth,SPI_SCLK low ns1.25 Setuptime,SPI_SIMO datavalidbeforereceivefallingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 0,phase = 0 Setuptime,SPI_SIMO datavalidbeforereceiverisingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 0,phase = 1 15 tsu(SIMO-CLK) ns Setuptime,SPI_SIMO datavalidbeforereceiverisingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 1,phase = 0 Setuptime,SPI_SIMO datavalidbeforereceivefallingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 1,phase = 1 Holdtime,SPI_SIMO datavalidafterreceivefallingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 0,phase = 0 Holdtime,SPI_SIMO datavalidafterreceiverisingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 0,phase = 1 16 th(CLK-SIMO) ns Holdtime,SPI_SIMO datavalidafterreceiverisingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 1,phase = 0 Holdtime,SPI_SIMO datavalidafterreceivefallingedge of SPI_SCLK, 3-/4-pinmode, 4 polarity= 1,phase = 1 (1) T = periodofSPI_SCLK; ForSPI0,SPI1,SPI2,and SPI3,P = periodofSPI coreclock(PLL1SYSCLK4). ForSPI4,P = periodofSPI coreclock(OSCIN). Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Master Mode — Additional Table6-66.AdditionalOutput SwitchingCharacteristicsof4-PinChip-SelectOption inMaster Mode NO. PARAMETER MIN MAX UNIT Outputsetuptime,SPI_SCS[n]activebeforefirst (C2TDELAY+2)*P+6SPI_SCLK risingedge,polarity= 0,phase = 0, .5SPIDELAY.C2TDELAY = 0 Outputsetuptime,SPI_SCS[n]activebeforefirst (C2TDELAY+2)*PSPI_SCLK risingedge,polarity= 0,phase = 1, + .5tc+ 6.5SPIDELAY.C2TDELAY = 0 19 tosu(CS-CLK) (1) ns Outputsetuptime,SPI_SCS[n]activebeforefirst (C2TDELAY+2)*P +SPI_SCLK fallingedge,polarity= 1,phase = 0, 6.5SPIDELAY.C2TDELAY = 0 Outputsetuptime,SPI_SCS[n]activebeforefirst (C2TDELAY+2)*PSPI_SCLK fallingedge,polarity= 1,phase = 1, + .5tc+ 6.5SPIDELAY.C2TDELAY = 0 Delaytime,finalSPI_SCLK fallingedge tomaster deassertingSPI_SCS[n],polarity= 0,phase = 0, (T2CDELAY+1)*P - SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD 3 notenabled Delaytime,finalSPI_SCLK fallingedge tomaster deassertingSPI_SCS[n],polarity= 0,phase = 1, (T2CDELAY+1)*P - SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD 3 notenabled 20 td(CLK-CS) ns Delaytime,finalSPI_SCLK risingedge tomaster deassertingSPI_SCS[n],polarity= 1,phase = 0, (T2CDELAY+1)*P - SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD 3 notenabled Delaytime,finalSPI_SCLK risingedge tomaster deassertingSPI_SCS[n],polarity= 1,phase = 1, (T2CDELAY+1)*P - SPIDELAY.T2CDELAY = 0,SPIDAT1.CSHOLD 3 notenabled (1) The MasterSPI isreadywithnew databeforeSPI_SCS[n]assertion. SlaveMode — Additional Table6-67.AdditionalOutput SwitchingCharacteristicsof4-PinChip-SelectOption inSlaveMode (1) NO. PARAMETER MIN MAX UNIT Delaytime,masterassertingSPI_SCS[n]toslavedriving27 td(CSL-SOMI) 2P + 16.5 nsSPI_SOMI datavalid Disabletime,masterdeassertingSPI_SCS[n]toslavedriving28 tdis(CSH-SOMI) 2P + 16.5 nsSPI_SOMI highimpedance (1) T = periodofSPI_SCLK; ForSPI0,SPI1,SPI2,and SPI3,P = periodofSPI coreclock(PLL1SYSCLK4). ForSPI4,P = periodofSPI coreclock(OSCIN).

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-68.AdditionalInputTiming Requirements of4-PinChip-SelectOption inSlaveMode (1) NO. MIN MAX UNIT Setuptime,SPI_SCS[n]assertedatslavetofirstSPI_SCLK edge25 tsu(CSL-CLK) 2P + 25 ns(risingorfalling)atslave Delaytime,finalfallingedge SPI_SCLK toSPI_SCS[n] .5(tc(CLK))+ 2P -4deasserted,polarity= 0,phase = 0 Delaytime,finalfallingedge SPI_SCLK toSPI_SCS[n] 2P -4deasserted,polarity= 0,phase = 1 26 td(CLK-CSH) ns Delaytime,finalrisingedge SPI_SCLK toSPI_SCS[n]deasserted, .5(tc(CLK))+ 2P -4polarity= 1,phase = 0 Delaytime,finalrisingedge SPI_SCLK toSPI_SCS[n]deasserted, 2P -4polarity= 1,phase = 1 (1) T = periodofSPI_SCLK; ForSPI0,SPI1,SPI2,and SPI3,P = periodofSPI coreclock(PLL1SYSCLK4). ForSPI4,P = periodofSPI coreclock(OSCIN). Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 165 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI MO(0) MO(1) MO(n-1) MO(n) MI(0) MI(1) MI(n-1) MI(n) MO(n) MI(n-1) MO(1) 4 5 5 6 MASTER MODE POLARITY = 0 PHASE = 0 MASTER MODE POLARITY = 0 PHASE = 1 MASTER MODE POLARITY = 1 PHASE = 0 MASTER MODE POLARITY = 1 PHASE = 1 MO(0) MO(1) MO(n-1) MI(n)MI(n-1)MI(1)MI(0) MO(0) MO(1) MO(n-1) MO(n) MI(n)MI(1)MI(0) MO(0) MO(n-1) MO(n) MI(n)MI(n-1)MI(1)MI(0) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-43.SPI Timings—Master Mode

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SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SPI_CLK SPI_SIMO SPI_SOMI SI(1) SI(n-1) SI(n) SO(0) SO(1) SO(n-1) SO(n) SI(0) SI(1) SI(n) SO(0) SO(1) SLAVE MODE POLARITY = 0 PHASE = 0 SLAVE MODE POLARITY = 0 PHASE = 1 SLAVE MODE POLARITY = 1 PHASE = 0 SLAVE MODE POLARITY = 1 PHASE = 1 SI(1)SI(0) SI(n-1) SO(n-1) SO(n) SO(n-1) SI(n)SI(n-1)SI(1)SI(0) SO(n)SO(1)SO(0) SI(n)SI(n-1) SO(n-1) SO(n)SO(1)SO(0) SI(0) TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 A. The firstbitoftransmitdatabecomes validon theSPI_SOMI pinwhen softwarewritestotheSPIDAT1 register.For more details,see theTMS320DM36x DMSoC SerialPeripheralInterfaceUser's Guide (literaturenumber SPRUFH1). Figure6-44.SPI Timings—SlaveMode Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 167 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

MASTER MODE 4 PIN WITH CHIP SELECT SPI_CLK SPI_SIMO SPI_SOMI SPI_SCS[n] 19 20 MO(0) MO(1) MO(n-1) MO(n) MI(n)MI(n-1)MI(1)MI(0) SPI_CLK SPI_SOMI SPI_SIMO SPI_SCS[n] SO(0) SI(1) SLAVE MODE 4 PIN WITH CHIP SELECT SO(n)SO(n-1) SI(0) SI(n-1) SI(n) SO(1) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-45.SPI Timings—Master Mode (4-Pin) Figure6-46.SPI Timings—SlaveMode (4-Pin)

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6.16 Inter-IntegratedCircuit(I2C)

The inter-integratedcircuit(I2C)module providesan interfacebetween the DM365 and otherdevices compliantwithPhilipsSemiconductorsInter-ICbus (I2C-bus)specificationversion2.1and connectedby way ofan I2C-bus.Externalcomponents attachedtothis2-wireserialbus can transmit/receiveup to8-bit datato/fromthedevicethroughtheI2C module. The I2C portsupports:

• CompatiblewithPhilipsI2C SpecificationRevision2.1(January2000)
• FastMode up to400 Kbps (nofail-safeI/Obuffers)
• NoiseFiltertoRemove Noise50 ns orless
• Seven-and Ten-BitDeviceAddressingModes
• Master(Transmit/Receive)and Slave(Transmit/Receive)Functionality
• Events:DMA, Interrupt,orPolling Formore detailedinformationon theI2C peripheral,see theDocumentationSupportsectionforthedevice Inter-IntegratedCircuit(I2C)Module ReferenceGuide.

6.16.1 I2C PeripheralRegisterDescription(s)

Table 6-69 liststhe I2C registers,theircorrespondingacronyms, and the device memory locations (offsets). Table6-69.Inter-IntegratedCircuit(I2C)Registers Offset Acronym RegisterDescription 0h ICOAR I2C Own AddressRegister 4h ICIMR I2C InterruptMask Register 8h ICSTR I2C InterruptStatusRegister Ch ICCLKL I2C ClockLow-Time DividerRegister 10h ICCLKH I2C ClockHigh-TimeDividerRegister 14h ICCNT I2C Data Count Register 18h ICDRR I2C Data ReceiveRegister 1Ch ICSAR I2C SlaveAddressRegister 20h ICDXR I2C Data TransmitRegister 24h ICMDR I2C Mode Register 28h ICIVR I2C InterruptVectorRegister 2Ch ICEMDR I2C ExtendedMode Register 30h ICPSC I2C PrescalerRegister 34h REVID1 I2C RevisionID Register1 38h REVID2 I2C RevisionID Register2 48h ICPFUNC I2C PinFunctionRegister 4ch ICPDIR I2C PinDirectionRegister 50h ICPDIN I2C PinData InRegister 54h ICPDOUT I2C PinData Out Register 58h ICPDSET I2C PinData SetRegister 5ch ICPDCLR I2C PinData Clearregister Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 169 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.16.2 I2C ElectricalData/Timing

6.16.2.1 Inter-IntegratedCircuits(I2C)Timing

Table6-70.Timing Requirements forI2C Timings(1)(seeFigure6-47) DEVICE STANDARD FASTNO. UNITMODE MODE MIN MAX MIN MAX 1 tc(SCL) Cycletime,SCL 10 2.5 μs 2 tsu(SCLH-SDAL) Setuptime,SCL highbeforeSDA low(fora repeatedSTART condition) 4.7 0.6 μs Holdtime,SCL lowafterSDA low(fora START and a repeatedSTART3 th(SCLL-SDAL) 4 0.6 μscondition) 4 tw(SCLL) Pulseduration,SCL low 4.7 1.3 μs 5 tw(SCLH) Pulseduration,SCL high 4 0.6 μs 6 tsu(SDAV-SCLH) Setuptime,SDA validbeforeSCL high 250 100 ns 7 th(SDA-SCLL) Holdtime,SDA validafterSCL low(ForI2C bus™ devices) 0 3.45 0 0.9 μs 8 tw(SDAH) Pulseduration,SDA highbetween STOP and START conditions 4.7 1.3 μs 20 + 9 tr(SDA) Risetime,SDA 1000 0.1C 300 ns b (1) 20 + 10 tr(SCL) Risetime,SCL 1000 0.1C 300 ns b (1) 20 + 11 tf(SDA) Falltime,SDA 300 0.1C 300 ns b (1) 20 + 12 tf(SCL) Falltime,SCL 300 0.1C 300 ns b (1) 13 tsu(SCLH-SDAH) Setuptime,SCL highbeforeSDA high(forSTOP condition) 4 0.6 μs 14 tw(SP) Pulseduration,spike(mustbe suppressed) 50 ns

15 C b

(2) Capacitiveloadforeach bus line 400 400 pF (1) The I2C pinsSDA and SCL do notfeaturefail-safeI/Obuffers.These pinscouldpotentiallydraw currentwhen thedeviceispowered down. (2) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. Figure6-47.I2C Receive Timings

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-71.SwitchingCharacteristicsforI2C Timings(1)(seeFigure6-48) DEVICE STANDARDNO. PARAMETER FAST MODE UNITMODE MIN MAX MIN MAX 16 tc(SCL) Cycletime,SCL 10 2.5 μs 17 td(SCLH-SDAL) Delaytime,SCL hightoSDA low(fora repeatedSTART condition) 4.7 0.6 μs Delaytime,SDA lowtoSCL low(fora START and a repeated18 td(SDAL-SCLL) 4 0.6 μsSTART condition) 19 tw(SCLL) Pulseduration,SCL low 4.7 1.3 μs 20 tw(SCLH) Pulseduration,SCL high 4 0.6 μs 21 td(SDAV-SCLH) Delaytime,SDA validtoSCL high 250 100 ns 22 tv(SCLL-SDAV) Validtime,SDA validafterSCL low(ForI2C devices) 0 0 0.9 μs 23 tw(SDAH) Pulseduration,SDA highbetween STOP and START conditions 4.7 1.3 μs 28 td(SCLH-SDAH) Delaytime,SCL hightoSDA high(forSTOP condition) 4 0.6 μs

29 C p Capacitanceforeach I2C pin 10 10 pF

(1) C b = totalcapacitanceofone bus lineinpF.Ifmixed withHS-mode devices,fasterfall-timesareallowed. CAUTION The I2C pinsuse a standard±4-mA LVCMOS buffer,nottheslowI/OPbufferdefinedin theI2C specification.Seriesresistorsmay be necessarytoreducenoiseatthesystem level. Figure6-48.I2C TransmitTimings Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 171 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.17 Multi-ChannelBufferedSerialPort(McBSP)

The primaryuse fortheMulti-ChannelBufferedSerialPort(McBSP) isforaudiointerfacepurposes.The primaryaudiomodes thatare supportedby theMcBSP are theAC97 and IISmodes. Inadditiontothe primaryaudiomodes, theMcBSP supportsgeneralserialportreceiveand transmitoperation,butisnot intendedtobe used as a high-speedinterface.The McBSP supportsthefollowingfeatures:

• Full-duplexcommunication
• Double-buffereddataregisters,whichallowa continuousdatastream
• Independentframingand clockingforreceiveand transmit
• Externalshiftclockgenerationoran internalprogrammablefrequencyshiftclock
• Double-buffereddataregisters,whichallowa continuousdatastream
• Independentframingand clockingforreceiveand transmit
• Directinterfaceto industry-standardcodecs, analog interfacechips (AICs),and other serially connectedanalog-to-digital(A/D)and digital-to-analog(D/A)devices
• DirectinterfacetoAC97 compliantdevices(thenecessarymultiphaseframesynchronizationcapability isprovided)
• DirectinterfacetoIIScompliantdevices
• DirectinterfacetoSPI protocolinmastermode only
• A wideselectionofdatasizes,including8,12,16,20,24,and 32 bits
• μ-Law and A-Law companding
• 8-bitdatatransferswiththeoptionofLSB orMSB first
• Programmable polarityforbothframesynchronizationand dataclocks
• Highlyprogrammableinternalclockand framegeneration
• DirectinterfacetoT1/E1 Framers
• Multi-channeltransmitand receiveofup to128 channels For more detailedinformationon theMcBSP peripheral,see theDocumentationSupportsectionforthe Multi-ChannelBufferedSerialPort(McBSP) ReferenceGuide.

6.17.1 McBSP PeripheralRegisterDescription(s)

Table 6-72 liststhe McBSP registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-72.McBSP Registers Offset Acronym RegisterName - RBR (1) Receivebufferregister - RSR (1) Receiveshiftregister - XSR (1) Transmitshiftregister 00h DRR (2)(3) Data receiveregister 04h DXR (3) Data transmitregister 08h SPCR Serialportcontrolregister 0Ch RCR Receivecontrolregister 10h XCR Transmitcontrolregister 14h SRGR Sample rategeneratorregister 18h MCR MultichannelControlRegister Enhanced ReceiveChannelEnableRegister1Ch RCERE0 0 PartitionA/B (1) The RBR, RSR, and XSR arenotdirectlyaccessibleviatheCPUs ortheEDMA controller. (2) The CPUs and EDMA controllercan onlyreadthisregister;theycannotwritetoit. (3) The DRR and DXR areaccessibleviatheCPUs ortheEDMA controller.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-72.McBSP Registers(continued) Offset Acronym RegisterName Enhanced TransmitChannelEnableRegister20h XCERE0 0 PartitionA/B 24h PCR Pincontrolregister Enhanced ReceiveChannelEnableRegister28h RCERE1 1 PartitionC/D Enhanced TransmitChannelEnableRegister2Ch XCERE1 1 PartitionC/D Enhanced ReceiveChannelEnableRegister30h RCERE2 2 PartitionE/F Enhanced TransmitChannelEnableRegister34h XCERE2 2 PartitionE/F Enhanced ReceiveChannelEnableRegister38h RCERE3 3 PartitionG/H Enhanced TransmitChannelEnableRegister3Ch XCERE3 3 PartitionG/H Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 173 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.17.2 McBSP ElectricalData/Timing

6.17.2.1 Multi-ChannelBufferedSerialPort(McBSP) Timing

Table6-73.Timing Requirements forMcBSP (1)(2)(seeFigure6-49) DEVICE NO. UNIT MIN MAX 15(3) tc(CLKS) Cycletime,CLKS CLKS ext 38.5or2P ns 16(4) tw (CLKS) Pulseduration,CLKR/X highorCLKR/X low CLKS ext 19.25orP ns CLKR int 21 5 tsu(FRH-CKRL) Setuptime,externalFSR highbeforeCLKR low ns CLKR ext 6 CLKR int 0 6 th(CKRL-FRH) Holdtime,externalFSR highafterCLKR low ns CLKR ext 6 CLKR int 21 7 tsu(DRV-CKRL) Setuptime,DR validbeforeCLKR low ns CLKR ext 6 CLKR int 0 8 th(CKRL-DRV) Holdtime,DR validafterCLKR low ns CLKR ext 6 CLKX int 21 10 tsu(FXH-CKXL) Setuptime,externalFSX highbeforeCLKX low ns CLKX ext 6 CLKX int 0 11 th(CKXL-FXH) Holdtime,externalFSX highafterCLKX low ns CLKX ext 10 (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) P = (1/SYSCLK4),where SYSCLK4 isan outputclockofPLLC1 (seeSection3.3). (3) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source.The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (4) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-74.SwitchingCharacteristicsOver Recommended OperatingConditionsforMcBSP (1)(2)(3) (seeFigure6-49) DEVICE NO. PARAMETER UNIT MIN MAX CLKR/X int 2(4)(5) tc(CKRX) Cycletime,CLKR/X 38.5or2P ns CLKR/X ext 17 td(CLKS-CLKRX) Delaytime,CLKS hightointernalCLKR/X CLKR/X int 1 24 CLKR/X int 19.25-1 orP -1 3(6) tw(CKRX) Pulseduration,CLKR/X highorCLKR/X low ns CLKR/X ext 19.25orP CLKR int -4 8 4 td(CKRH-FRV) Delaytime,CLKR hightointernalFSR valid ns CLKR ext 3 25 CLKX int -4 8 9 td(CKXH-FXV) Delaytime,CLKX hightointernalFSX valid ns CLKX ext 3 25 CLKX int 12 nstdis(CKXH- Disabletime,DX highimpedance followinglastdata12 DXHZ) bitfromCLKX high CLKX ext 25 ns CLKX int -5+ D1 (7) 12 + D2 (7) ns 13 td(CKXH-DXV) Delaytime,CLKX hightoDX valid CLKX ext 3 + D1 (7) 25 + D2 (7) ns Delaytime,FSX hightoDX valid FSX int 0 + D1 (8) 14 + D2 (8) 14 td(FXH-DXV) ONLY applieswhen indata ns FSX ext 0 + D1 (8) 25 + D2 (8) delay0 (XDATDLY = 00b)mode (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimum delaytimesalsorepresentminimum outputholdtimes. (3) P = (1/SYSCLK4),where SYSCLK4 isan outputclockofPLLC1 (seeSection3.3). (4) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source. (5) The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitations and AC timingrequirements.Use whichevervalueisgreater. (6) C = H orL S = sample rategeneratorinputclock= P ifCLKSM = 1 (P = SYSCLK3 period) S = sample rategeneratorinputclock= P_clksifCLKSM = 0 (P_clks= CLKS period) H = CLKX highpulsewidth= (CLKGDV/2 + 1)*S ifCLKGDV iseven H = (CLKGDV + 1)/2*S ifCLKGDV isodd L = CLKX lowpulsewidth= (CLKGDV/2) *S ifCLKGDV iseven L = (CLKGDV + 1)/2*S ifCLKGDV isodd CLKGDV shouldbe setappropriatelytoensuretheMcBSP bitratedoes notexceed themaximum limit. (7) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. IfDXENA = 0,thenD1 = D2 = 0 IfDXENA = 1,thenD1 = 6P,D2 = 12P (8) ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. IfDXENA = 0,thenD1 = D2 = 0 IfDXENA = 1,thenD1 = 6P,D2 = 12P Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 175 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Bit(n-1) (n-2) (n-3) Bit□0 Bit(n-1) (n-2) (n-3) 13(A) 13(A) A. Parameter□No.□13□applies□to□the□first□data□bit only when□XDA TDLY≠ 0. CLKR FSR□(int) FSR□(ext) DR CLKX FSX□(int) FSX□(ext) FSX (XDATDLY=00b) DX CLKS TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-49.McBSP Timing Table6-75.McBSP as SPI Timing Requirements CLKSTP = 10b,CLKXP = 0 (seeFigure6-50) MASTER NO. UNIT MIN MAX M30 tsu(DRV-CKXL) Setuptime,DR validbeforeCLKX low 16 ns M31 th(CKXL-DRV) Holdtime,DR validafterCLKX low 0 ns Table6-76.McBSP as SPI SwitchingCharacteristics(1)(2) CLKSTP = 10b,CLKXP = 0 (seeFigure6-50) MASTER NO. PARAMETER UNIT MIN MAX 38.5orM33 tc(CKX) Cycletime,CLKX ns2P CLKXP - CLKXP +M24 td(CKXL-FXH) Delaytime,CLKX lowtoFSX high(2) ns2 4 CLKXL - CLKXL +M25 td(FXL-CKXH) Delaytime,FSX lowtoCLKX high(3) ns2 2 M26 td(CKXH-DXV) Delaytime,CLKX hightoDX valid -2 6 ns CLKXL - CLKXL +M27 tdis(CKXL-DXHZ) Disabletime,DX highimpedance followinglastdatabitfromCLKX low ns3 8 (1) P = (1/SYSCLK4),where SYSCLK4 isan outputclockofPLLC1 (seeSection3.3). (2) T = CLKX period= (1+ CLKGDV) × 2P L1 = CLKX lowpulsewidth= T/2when CLKGDV isodd orzeroand = (CLKGDV/2) × 2P when CLKGDV iseven. (3) FSX shouldbe lowbeforetherisingedge ofclocktoenableslavedevicesand thenbegina SPI transferattherisingedge ofthemaster clock(CLKX).

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Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M31M30 M26M27 M25M24 CLKX FSX DX DR M33 TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure6-50.McBSP as SPI:CLKSTP = 10b,CLKXP = 0 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 177 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M39 M36M38M37 M35M34 CLKX FSX DX DR M40 M42 TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-77.McBSP as SPI Timing Requirements CLKSTP = 11b,CLKXP = 0 MASTER NO. UNIT MIN MAX M39 tsu(DRV-CKXH) Setuptime,DR validbeforeCLKX high 16 ns M40 th(CKXH-DRV) Holdtime,DR validafterCLKX high 1 ns Table6-78.McBSP as SPI SwitchingCharacteristics(1)(2) CLKSTP = 11b,CLKXP = 0 (seeFigure6-51) MASTER NO. PARAMETER UNIT MIN MAX M42 tc(CKX) Cycletime,CLKX 38.5or2P ns M34 td(CKXL-FXH) Delaytime,CLKX lowtoFSX high(3) CLKXP -2 CLKXP + 4 ns M35 td(FXL-CKXH) Delaytime,FSX lowtoCLKX high(4) CLKXP -2 CLKXP + 2 ns M36 td(CKXL-DXV) Delaytime,CLKX lowtoDX valid -2 6 ns Disabletime,DX highimpedance followinglastdatabitfromM37 tdis(CKXL-DXHZ) -3 8 nsCLKX low M38 td(FXL-DXV) Delaytime,FSX lowtoDX valid CLKXH -2 CLKXH + 10 ns (1) P = (1/SYSCLK4),where SYSCLK4 isan outputclockofPLLC1 (seeSection3.3). (2) T = CLKX period= (1+ CLKGDV) × 2P L1 = CLKX lowpulsewidth= T/2when CLKGDV isodd orzeroand = (CLKGDV/2) × 2P when CLKGDV iseven H 1 = CLKX highpulsewidth= T/2when CLKGDV isodd orzeroand = (CLKGDV/2 + 1)× 2P when CLKGDV iseven (3) FSRP = FSXP = 1.As a SPI master,FSX isinvertedtoprovideactive-lowslave-enableoutput. CLKXM = FSXM = 1,CLKRM = FSRM = 0 formasterMcBSP (4) FSX shouldbe lowbeforetherisingedge ofclocktoenableslavedevicesand thenbegina SPI transferattherisingedge ofthemaster clock(CLKX). Figure6-51.McBSP as SPI:CLKSTP = 11b,CLKXP = 0

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Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M50M49 M45M46 M44M43 CLKX FSX DX DR M52 TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-79.McBSP as SPI Timing Requirements CLKSTP = 10b,CLKXP = 1 (seeFigure6-52) MASTER NO. UNIT MIN MAX M49 tsu(DRV-CKXH) Setuptime,DR validbeforeCLKX high 16 ns M50 th(CKXH-DRV) Holdtime,DR validafterCLKX high 0 ns Table6-80.McBSP as SPI SwitchingCharacteristics(1)(2) CLKSTP = 10b,CLKXP = 1 (seeFigure6-52) MASTER NO. PARAMETER UNIT MIN MAX M52 tc(CKX) Cycletime,CLKX 38.5or2P ns M43 td(CKXH-FXH) Delaytime,CLKX hightoFSX high(3) CLKXP -2 CLKXP + 4 ns M44 td(FXL-CKXL) Delaytime,FSX lowtoCLKX low(4) CLKXH -2 CLKXH + 2 ns M45 td(CKXL-DXV) Delaytime,CLKX lowtoDX valid -2 6 ns Disabletime,DX highimpedance followinglastdatabitfromM46 tdis(CKXH-DXHZ) CLKXH -3 CLKXL + 8 nsCLKX high (1) P = (1/SYSCLK4),where SYSCLK4 isan outputclockofPLLC1 (seeSection3.3). (2) T = CLKX period= (1+ CLKGDV) × 2P H 1 = CLKX highpulsewidth= T/2when CLKGDV isodd orzeroand = (CLKGDV/2 + 1)× 2P when CLKGDV iseven (3) FSRP = FSXP = 1.As a SPI master,FSX isinvertedtoprovideactive-lowslave-enableoutput. CLKXM = FSXM = 1,CLKRM = FSRM = 0 formasterMcBSP (4) FSX shouldbe lowbeforetherisingedge ofclocktoenableslavedevicesand thenbegina SPI transferattherisingedge ofthemaster clock(CLKX). Figure6-52.McBSP as SPI:CLKSTP = 10b,CLKXP = 1 Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 179 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M59M58 M55M57M56 M54M53 CLKX FSX DX DR M62 TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-81.McBSP as SPI Timing Requirements CLKSTP = 11b,CLKXP = 1 (seeFigure6-53) MASTER NO. UNIT MIN MAX M58 tsu(DRV-CKXL) Setuptime,DR validbeforeCLKX low 16 ns M59 th(CKXL-DRV) Holdtime,DR validafterCLKX low 0 ns Table6-82.McBSP as SPI SwitchingCharacteristics(1)(2) CLKSTP = 11b,CLKXP = 1 (seeFigure6-53) MASTER NO. PARAMETER UNIT MIN MAX M62 tc(CKX) Cycletime,CLKX 38.5or2P ns M53 td(CKXH-FXH) Delaytime,CLKX hightoFSX high(3) CLKXP -2 CLKXP + 4 ns M54 td(FXL-CKXL) Delaytime,FSX lowtoCLKX low(4) CLKXP -2 CLKXP + 2 ns M55 td(CKXL-DXV) Delaytime,CLKX hightoDX valid -2 6 ns Disabletime,DX highimpedance followinglastdatabitfromM56 tdis(CKXH-DXHZ) -3 8 nsCLKX high M57 td(FXL-DXV) Delaytime,FSX lowtoDX valid CLKXL -1 CLKXL + 10 ns (1) P = (1/SYSCLK4),where SYSCLK4 isan outputclockofPLLC1 (seeSection3.3). (2) T = CLKX period= (1+ CLKGDV) × 2P L1 = CLKX lowpulsewidth= T/2when CLKGDV isodd orzeroand = (CLKGDV/2) × 2P when CLKGDV iseven H 1 = CLKX highpulsewidth= T/2when CLKGDV isodd orzeroand = (CLKGDV/2 + 1)× 2P when CLKGDV iseven (3) FSRP = FSXP = 1.As a SPI master,FSX isinvertedtoprovideactive-lowslave-enableoutput. CLKXM = FSXM = 1,CLKRM = FSRM = 0 formasterMcBSP (4) FSX shouldbe lowbeforetherisingedge ofclocktoenableslavedevicesand thenbegina SPI transferattherisingedge ofthemaster clock(CLKX). Figure6-53.McBSP as SPI:CLKSTP = 11b,CLKXP = 1

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6.18 Timer

The device containsfoursoftware-programmabletimers.Timer 0, Timer 1, Timer 3, and Timer 4 (general-purposetimers)can be programmed in64-bitmode, dual32-bitunchainedmode, or dual32-bit chainedmode. Timer 3 supportsadditionalfeaturesover the othertimers:externalclock/eventinput, periodreload,outputeventtiedtoRealTime Out (RTO) module,externaleventcapture,and timercounter registerreadreset.Timer2 isused onlyas a watchdogtimer.Timer2 istiedtodevicereset.

• 64-bitcount-upcounter
• Timermodes: – 64-bitgeneral-purposetimermode (Timer0,1,3,4) – Dual32-bitgeneral-purposetimermode (Timer0,1,3,4) – Watchdog timermode (Timer2)
• Two possibleclocksources: – Internalclock – Externalclock/eventinputviatimerinputpins(Timer3)
• Threepossibleoperationmodes: – One-timeoperation(timerrunsforone periodthenstops) – Continuousoperation(timerautomaticallyresetsaftereach period) – Continuousoperationwithperiodreload(Timer3)
• GeneratesinterruptstotheARM CPU
• GeneratessynceventtoEDMA
• Generatesoutputeventtodevicereset(Timer2)
• GeneratesoutputeventtoRealTimerOut (RTO) module (Timer3)
• Externaleventcaptureviatimerinputpins(Timer3) For more detailedinformation,see the TMS320DM36x DMSoC Timer/WatchdogTimer User'sGuide (SPRUFH0 ).

6.18.1 Timer PeripheralRegisterDescription(s)

Table 6-83 liststhe Timer registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-83.Timer GlobalRegisters Offset Acronym RegisterDescription 00h PID12 PeripheralIdentificationRegister12 04h EMUMGT EmulationManagement Register 10h TIM12 TimerCounterRegister12 14h TIM34 TimerCounterRegister34 18h PRD12 TimerPeriodRegister12 1Ch PRD34 TimerPeriodRegister34 20h TCR TimerControlRegister 24h TGCR TimerGlobalControlRegister 28h WDTCR Watchdog TimerControlRegister 34h REL12 TimerReloadRegister12 38h REL34 TimerReloadRegister34 3Ch CAP12 TimerCaptureRegister12 40h CAP34 TimerCaptureRegister34 44h INTCTL_STAT TimerInterruptControland StatusRegister Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 181 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

TIM_IN TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

6.18.2 Timer ElectricalData/Timing

Table6-84.Timing Requirements forTimer Input(1)(2)(seeFigure6-54) DEVICE NO. UNIT MIN MAX 1 tc(TIN) Cycletime,TIM_IN 4P ns 2 tw(TINPH) Pulseduration,TIM_IN high 0.45C 0.55C ns 3 tw(TINPL) Pulseduration,TIM_IN low 0.45C 0.55C ns 4 tt(TIN) Transitiontime,TIM_IN 5 ns (1) GPIO001, GPIO002, GPIO003, and GPIO004 can be used as externalclockinputsforTimer3.See theTMS320DM36x DMSoC Timer/WatchdogTimerUser's Guide formore information(SPRUFH0 ). (2) P = MXI1/CLKIN cycletimeinns.Forexample,when MXI1/CLKIN frequencyis24 MHz use P = 41.6 ns. Figure6-54.Timer InputTiming

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6.19 Pulse Width Modulator(PWM)

The pulsewidthmodulator(PWM) featureisverycommon inembedded systems.Itprovidesa way to generatea pulseperiodicwaveform formotorcontrolorcan actas a digital-to-analogconverterwithsome externalcomponents.ThisPWM peripheralisbasicallya timerwitha periodcounterand a first-phase durationcomparator,where bitwidthoftheperiodand first-phasedurationare bothprogrammable.The PulseWidthModulator(PWM) modules supportthefollowingfeatures:

• 32-bitperiodcounter
• 32-bitfirst-phasedurationcounter
• 8-bitrepeatcount forone-shotoperation.One-shot operationwillproduce N + 1 periodsof the waveform,where N istherepeatcountervalue.
• Configurabletooperateineitherone-shotorcontinuousmode
• Bufferedperiodand first-phasedurationregisters
• One-shotoperationtriggerableby hardwareeventswithprogrammableedge transitions.(low-to-highor high-to-low).
• One-shotoperationtriggerableby theISIFVSYNC outputofthevideoprocessingsubsystem(VPSS), whichallowsany ofthePWM instantiationstobe used as a ISIFtimer.Thisallowsthedevicemodule tosupportthefunctionsprovidedby theISIFtimerfeature(generatingstrobeand shuttersignals).
• One-shotoperationgeneratesN+1 periodsofwaveform,N beingtherepeatcountregistervalue
• ConfigurablePWM outputpininactivestate
• Interruptand EDMA synchronizationevents

6.19.1 PWM PeripheralRegisterDescription(s)

Table 6-85 liststhe PWM registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-85.Pulse Width Modulator(PWM) Registers Offset Acronym RegisterDescription 00h PID PWM PeripheralIdentificationRegister 04h PCR PWM PeripheralControlRegister 08h CFG PWM ConfigurationRegister 0Ch START PWM StartRegister 10h RPT PWM Repeat Count Register 14h PER PWM PeriodRegister 18h PH1D PWM First-PhaseDurationRegister

6.19.2 PWM0/1/2/3 Electrical/TimingData

Table6-86.SwitchingCharacteristicsOver Recommended OperatingConditionsforPWM0/1/2/3 Outputs(1)(seeFigure6-55and Figure6-56) DEVICE NO. PARAMETER UNIT MIN MAX 1 tw(PWMH) Pulseduration,PWMx high 37 ns 2 tw(PWML) Pulseduration,PWMx low 37 ns 3 tt(PWM) Transitiontime,PWMx 5 ns 4 td(ISIF-PWMV) Delaytime,ISIF(VD)triggereventtoPWMx valid 0 10 ns (1) P = MXI1/CLKIN cycletimeinns.Forexample,when MXI1/CLKIN frequencyis24 MHz use P = 41.6 ns. Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 183 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

VD(CCDC) INV ALID INV ALID INV ALID VALID V ALID VALID PWM0 PWM1 PWM2 INV ALID VALIDPWM3 TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-55.PWM Output Timing Figure6-56.PWM Output Delay Timing

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6.20 Real Time Out (RTO)

The deviceuses the Real Time Out (RTO) peripheralto provideappropriateinputcontrolsignalsto externaldevicessuch as motorcontrollers.Thisperipheralsupportsthefollowingfeatures:

• Fourseparateoutputs
• Triggeron Timer3event

6.20.1 Real Time Out (RTO) PeripheralRegisterDescription(s)

Table 6-87 liststhe RTO registers,theircorrespondingacronyms, and the devicememory locations (offsets). Table6-87.Real Time Out (RTO) Registers Offset Acronym RegisterDescription 0h REVID RTO ControllerRevisionID Register 04h CTRL_STATUS RTO ControllerControland StatusRegister

6.20.2 RTO Electrical/TimingData

Table6-88.SwitchingCharacteristicsOver Recommended OperatingConditionsforRTO Outputs (see Figure6-57and Figure6-58)(1) DEVICE NO. PARAMETER UNIT MIN MAX 52.081 tw(RTOH) Pulseduration,RTOx high 27.7 ns3 2 tw(RTOL) Pulseduration,RTOx low .45C .55C ns 3 tt(RTO) Transitiontime,RTOx .45C .55C ns 4 td(TIMER3-RTOV) Delaytime,Timer3 (TINT12orTINT34)triggereventtoRTOx valid 10 ns (1) C = MXI1/CLKIN1 cycletimeinns.Forexample,when MXI1/CLKIN1 frequencyis24 MHz use C = 41.6 ns. Figure6-57.RTO Output Timing Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 185 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

(Timer3) INV ALID INV ALID INV ALID V ALID VALID V ALID RTO0 INV ALID V ALID RTO1 RTO2 RTO3 TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-58.RTO Output Delay Timing

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6.21 EthernetMedia Access Controller(EMAC)

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween thedeviceand the network.The EMAC supportsboth10Base-T (10 Mbits/second[Mbps])and 100Base-TX (100 Mbps) in eitherhalf-or full-duplexmode. The EMAC module alsosupportshardware flowcontroland qualityof service(QOS) support. The frequenciessupportedfortransmitand receiveclocksarefixedby theIEEE 802.3standardas:

• 2.5MHz for10Mbps
• 25 MHz for100Mbps The EMAC controlstheflowofpacketdatafromthedevicetothePHY. The MDIO module controlsPHY configurationand statusmonitoring. The EMAC module conformsto the IEEE 802.3-2002standard,describingthe “CarrierSense Multiple Access withCollisionDetection(CSMA/CD) Access Method and PhysicalLayer” specifications.The IEEE 802.3standardhas alsobeen adoptedby ISO/IECand re-designatedas ISO/IEC8802-3:2000(E). Deviationfrom thisstandard,theEMAC module does notuse theTransmitCoding ErrorsignalMTXER. Insteadofdrivingtheerrorpinwhen an underflowconditionoccurson a transmittedframe,theEMAC will intentionallygeneratean incorrectchecksum by invertingthe frame CRC, so thatthe transmittedframe willbe detectedas an errorby thenetwork Both the EMAC and the MDIO modules interfaceto the devicethrougha custom interfacethatallows efficientdata transmissionand reception.This custom interfaceis referredto as the EMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts. For more informationon the TMS320DM36x DMSoC EthernetMedia Access ControllerUser'sGuide (literaturenumber SPRUFI5 ).

6.21.1 EMAC PeripheralRegisterDescription(s)

Table 6-89 liststhe EMAC registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-89.EthernetMedia Access Controller(EMAC) ControlModule Registers SlaveVBUS Acronym RegisterDescription Address Offset 0h CMIDVER Identificationand VersionRegister 04h CMSOFTRESET SoftwareResetRegister 08h CMEMCONTROL EmulationControlRegister Ch CMINTCTRL InterruptControlRegister 10h CMRXTHRESHINTEN ReceiveThresholdInterruptEnableRegister 14h CMRXINTEN ReceiveInterruptEnableRegister 18h CMTXINTEN TransmitInterruptEnableRegister 1Ch CMMISCINTEN MiscellaneousInterruptEnableRegister 40h CMRXTHRESHINTSTAT ReceiveThresholdInterruptStatusRegister 44h CMRXINTSTAT ReceiveInterruptStatusRegister 48h CMTXINTSTAT TransmitInterruptStatusRegister 4Ch CMMISCINTSTAT MiscellaneousInterruptStatusRegister 70Ch CMRXINTMAX ReceiveInterruptsPer MillisecondRegister 74h CMTXINTMAX TransmitInterruptsPer MillisecondRegister Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 187 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-90.EthernetMedia Access Controller(EMAC) Registers Offset Acronym RegisterDescription 0h TXIDVER TransmitIdentificationand VersionRegister 4h TXCONTROL TransmitControlRegister 8h TXTEARDOWN TransmitTeardown Register 10h RXIDVER ReceiveIdentificationand VersionRegister 14h RXCONTROL ReceiveControlRegister 18h RXTEARDOWN ReceiveTeardown Register 80h TXINTSTATRAW TransmitInterruptStatus(Unmasked) Register 84h TXINTSTATMASKED TransmitInterruptStatus(Masked)Register 88h TXINTMASKSET TransmitInterruptMask SetRegister 8Ch TXINTMASKCLEAR TransmitInterruptClearRegister 90h MACINVECTOR MAC InputVectorRegister 94h MACEOIVECTOR MAC End ofInterruptVectorRegister A0h RXINTSTATRAW ReceiveInterruptStatus(Unmasked) Register A4h RXINTSTATMASKED ReceiveInterruptStatus(Masked)Register A8h RXINTMASKSET ReceiveInterruptMask SetRegister ACh RXINTMASKCLEAR ReceiveInterruptMask ClearRegister B0h MACINTSTATRAW MAC InterruptStatus(Unmasked) Register B4h MACINTSTATMASKED MAC InterruptStatus(Masked)Register B8h MACINTMASKSET MAC InterruptMask SetRegister BCh MACINTMASKCLEAR MAC InterruptMask ClearRegister 100h RXMBPENABLE ReceiveMulticast/Broadcast/PromiscuousChannelEnableRegister 104h RXUNICASTSET ReceiveUnicastEnableSetRegister 108h RXUNICASTCLEAR ReceiveUnicastClearRegister 10Ch RXMAXLEN ReceiveMaximum LengthRegister 110h RXBUFFEROFFSET ReceiveBufferOffsetRegister 114h RXFILTERLOWTHRESH ReceiveFilterLow PriorityFrame ThresholdRegister 120h RX0FLOWTHRESH ReceiveChannel0 Flow ControlThresholdRegister 124h RX1FLOWTHRESH ReceiveChannel1 Flow ControlThresholdRegister 128h RX2FLOWTHRESH ReceiveChannel2 Flow ControlThresholdRegister 12Ch RX3FLOWTHRESH ReceiveChannel3 Flow ControlThresholdRegister 130h RX4FLOWTHRESH ReceiveChannel4 Flow ControlThresholdRegister 134h RX5FLOWTHRESH ReceiveChannel5 Flow ControlThresholdRegister 138h RX6FLOWTHRESH ReceiveChannel6 Flow ControlThresholdRegister 13Ch RX7FLOWTHRESH ReceiveChannel7 Flow ControlThresholdRegister 140h RX0FREEBUFFER ReceiveChannel0 FreeBufferCount Register 144h RX1FREEBUFFER ReceiveChannel1 FreeBufferCount Register 148h RX2FREEBUFFER ReceiveChannel2 FreeBufferCount Register 14Ch RX3FREEBUFFER ReceiveChannel3 FreeBufferCount Register 150h RX4FREEBUFFER ReceiveChannel4 FreeBufferCount Register 154h RX5FREEBUFFER ReceiveChannel5 FreeBufferCount Register 158h RX6FREEBUFFER ReceiveChannel6 FreeBufferCount Register 15Ch RX7FREEBUFFER ReceiveChannel7 FreeBufferCount Register 160h MACCONTROL MAC ControlRegister 164h MACSTATUS MAC StatusRegister 168h EMCONTROL EmulationControlRegister 16Ch FIFOCONTROL FIFO ControlRegister 170h MACCONFIG MAC ConfigurationRegister

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-90.EthernetMedia Access Controller(EMAC) Registers(continued) Offset Acronym RegisterDescription 174h SOFTRESET SoftResetRegister 1D0h MACSRCADDRLO MAC SourceAddressLow BytesRegister 1D4h MACSRCADDRHI MAC SourceAddressHighBytesRegister 1D8h MACHASH1 MAC Hash AddressRegister1 1DCh MACHASH2 MAC Hash AddressRegister2 1E0h BOFFTEST Back OffTestRegister 1E4h TPACETEST TransmitPacingAlgorithmTestRegister 1E8h RXPAUSE ReceivePause TimerRegister 1ECh TXPAUSE TransmitPause TimerRegister 500h MACADDRLO MAC AddressLow BytesRegister,Used inReceiveAddressMatching 504h MACADDRHI MAC AddressHighBytesRegister,Used inReceiveAddressMatching 508h MACINDEX MAC IndexRegister 600h TX0HDP TransmitChannel0 DMA Head DescriptorPointerRegister 604h TX1HDP TransmitChannel1 DMA Head DescriptorPointerRegister 608h TX2HDP TransmitChannel2 DMA Head DescriptorPointerRegister 60Ch TX3HDP TransmitChannel3 DMA Head DescriptorPointerRegister 610h TX4HDP TransmitChannel4 DMA Head DescriptorPointerRegister 614h TX5HDP TransmitChannel5 DMA Head DescriptorPointerRegister 618h TX6HDP TransmitChannel6 DMA Head DescriptorPointerRegister 61Ch TX7HDP TransmitChannel7 DMA Head DescriptorPointerRegister 620h RX0HDP ReceiveChannel0 DMA Head DescriptorPointerRegister 624h RX1HDP ReceiveChannel1 DMA Head DescriptorPointerRegister 628h RX2HDP ReceiveChannel2 DMA Head DescriptorPointerRegister 62Ch RX3HDP ReceiveChannel3 DMA Head DescriptorPointerRegister 630h RX4HDP ReceiveChannel4 DMA Head DescriptorPointerRegister 634h RX5HDP ReceiveChannel5 DMA Head DescriptorPointerRegister 638h RX6HDP ReceiveChannel6 DMA Head DescriptorPointerRegister 63Ch RX7HDP ReceiveChannel7 DMA Head DescriptorPointerRegister 640h TX0CP TransmitChannel0 CompletionPointerRegister 644h TX1CP TransmitChannel1 CompletionPointerRegister 648h TX2CP TransmitChannel2 CompletionPointerRegister 64Ch TX3CP TransmitChannel3 CompletionPointerRegister 650h TX4CP TransmitChannel4 CompletionPointerRegister 654h TX5CP TransmitChannel5 CompletionPointerRegister 658h TX6CP TransmitChannel6 CompletionPointerRegister 65Ch TX7CP TransmitChannel7 CompletionPointerRegister 660h RX0CP ReceiveChannel0 CompletionPointerRegister 664h RX1CP ReceiveChannel1 CompletionPointerRegister 668h RX2CP ReceiveChannel2 CompletionPointerRegister 66Ch RX3CP ReceiveChannel3 CompletionPointerRegister 670h RX4CP ReceiveChannel4 CompletionPointerRegister 674h RX5CP ReceiveChannel5 CompletionPointerRegister 678h RX6CP ReceiveChannel6 CompletionPointerRegister 67Ch RX7CP ReceiveChannel7 CompletionPointerRegister Network StatisticsRegisters 200h RXGOODFRAMES Good ReceiveFrames Register 204h RXBCASTFRAMES BroadcastReceiveFrames Register Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 189 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-90.EthernetMedia Access Controller(EMAC) Registers(continued) Offset Acronym RegisterDescription 208h RXMCASTFRAMES MulticastReceiveFrames Register 20Ch RXPAUSEFRAMES Pause ReceiveFrames Register 210h RXCRCERRORS ReceiveCRC ErrorsRegister 214h RXALIGNCODEERRORS ReceiveAlignment/CodeErrorsRegister 218h RXOVERSIZED ReceiveOversizedFrames Register 21Ch RXJABBER ReceiveJabberFrames Register 220h RXUNDERSIZED ReceiveUndersizedFrames Register 224h RXFRAGMENTS ReceiveFrame FragmentsRegister 228h RXFILTERED FilteredReceiveFrames Register 22Ch RXQOSFILTERED ReceiveQOS FilteredFrames Register 230h RXOCTETS ReceiveOctetFrames Register 234h TXGOODFRAMES Good TransmitFrames Register 238h TXBCASTFRAMES BroadcastTransmitFrames Register 23Ch TXMCASTFRAMES MulticastTransmitFrames Register 240h TXPAUSEFRAMES Pause TransmitFrames Register 244h TXDEFERRED DeferredTransmitFrames Register 248h TXCOLLISION TransmitCollisionFrames Register 24Ch TXSINGLECOLL TransmitSingleCollisionFrames Register 250h TXMULTICOLL TransmitMultipleCollisionFrames Register 254h TXEXCESSIVECOLL TransmitExcessiveCollisionFrames Register 258h TXLATECOLL TransmitLateCollisionFrames Register 25Ch TXUNDERRUN TransmitUnderrunErrorRegister 260h TXCARRIERSENSE TransmitCarrierSense ErrorsRegister 264h TXOCTETS TransmitOctetFrames Register 268h FRAME64 Transmitand Receive64 OctetFrames Register 26Ch FRAME65T127 Transmitand Receive65 to127 OctetFrames Register 270h FRAME128T255 Transmitand Receive128 to255 OctetFrames Register 274h FRAME256T511 Transmitand Receive256 to511 OctetFrames Register 278h FRAME512T1023 Transmitand Receive512 to1023 OctetFrames Register 27Ch FRAME1024TUP Transmitand Receive1024 toRXMAXLEN OctetFrames Register 280h NETOCTETS NetworkOctetFrames Register 284h RXSOFOVERRUNS ReceiveFIFO orDMA StartofFrame OverrunsRegister 288h RXMOFOVERRUNS ReceiveFIFO orDMA MiddleofFrame OverrunsRegister 28Ch RXDMAOVERRUNS ReceiveDMA OverrunsRegister Table6-91.EMAC DescriptorMemory HEX ADDRESS RANGE ACRONYM DESCRIPTION 0x01D0 8000 -0x01D0 9FFF – EMAC ControlModule DescriptorMemory

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MRCLK (Input) MRXD3−MRXD0, MRXDV , MRXER (Inputs) TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011

6.21.2 EthernetMedia Access Controller(EMAC) ElectricalData/Timing

Table6-92.Timing Requirements forMRCLK (seeFigure6-59) 10 Mbps 100 MbpsNO. UNIT MIN MAX MIN MAX 1 tc(MRCLK) Cycletime,MRCLK 400 40 ns 2 tw(MRCLKH) Pulseduration,MRCLK high 140 14 ns 3 tw(MRCLKL) Pulseduration,MRCLK low 140 14 ns Figure6-59.MRCLK Timing (EMAC -Receive) Table6-93.Timing Requirements forMTCLK (seeFigure6-59) 10 Mbps 100 MbpsNO. UNIT MIN MAX MIN MAX 1 tc(MTCLK) Cycletime,MTCLK 400 40 ns 2 tw(MTCLKH) Pulseduration,MTCLK high 140 14 ns 3 tw(MTCLKL) Pulseduration,MTCLK low 140 14 ns Figure6-60.MTCLK Timing (EMAC -Transmit) Table6-94.Timing Requirements forEMAC MIIReceive 10/100Mbit/s(1)(seeFigure6-61) NO. UNITMIN MAX 1 tsu(MRXD-MRCLKH) Setuptime,receiveselectedsignalsvalidbeforeMRCLK high 8 ns 2 th(MRCLKH-MRXD) Holdtime,receiveselectedsignalsvalidafterMRCLK high 8 ns (1) Receiveselectedsignalsinclude:MRXD3-MRXD0, MRXDV, and MRXER. Figure6-61.EMAC Receive InterfaceTiming Table6-95.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC MIITransmit Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 191 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Table6-95.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC MIITransmit 10/100Mbit/s(1)(seeFigure6-62)(continued) 10/100Mbit/s(1)(seeFigure6-62) NO. UNITMIN MAX 1 td(MTCLKH-MTXD) Delaytime,MTCLK hightotransmitselectedsignalsvalid 5 25 ns (1) Transmitselectedsignalsinclude:MTXD3-MTXD0, and MTXEN. Figure6-62.EMAC TransmitInterfaceTiming

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6.22 Management Data Input/Output(MDIO)

The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerateallPHY devicesinthesystem. The Management Data Input/Output(MDIO) module implementsthe802.3serialmanagement interfaceto interrogateand controlEthernetPHY(s) usinga shared two-wirebus. Host softwareuses the MDIO module to configurethe auto-negotiationparametersof each PHY attachedto the EMAC, retrievethe negotiationresults,and configurerequiredparametersinthe EMAC module forcorrectoperation.The module is designed to allow almost transparentoperationof the MDIO interface,with very little maintenancefromthecoreprocessor.Onlyone PHY may be connectedatany giventime. For more detailedinformationon theMDIO peripheral,see theTMS320DM36x DMSoC EthernetMedia Access ControllerUser'sGuide (literaturenumber SPRUFI5 ).

6.22.1 MDIO PeripheralRegisterDescription(s)

Table 6-96 liststhe MDIO registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-96.Management Data Input/Output(MDIO) Registers Offset Acronym RegisterDescription 0h VERSION Identificationand VersionRegister 04h CONTROL MDIO ControlRegister 08h ALIVE PHY AliveStatusregister Ch LINK PHY LinkStatusRegister 10h LINKINTRAW MDIO LinkStatusChange Interrupt (Unmasked) Register 14h LINKINTMASKED MDIO LinkStatusChange Interrupt(Masked) Register 20h USERINTRAW MDIO User Command CompleteInterrupt (Unmasked) Register 24h USERINTMASKED MDIO User Command CompleteInterrupt (Masked)Register 28h USERINTMASKSET MDIO User Command CompleteInterrupt Mask SetRegister 2Ch USERINTMASKCLEAR MDIO User Command CompleteInterrupt Mask ClearRegister 80h USERACCESS0 MDIO User Access Register0 84h USERPHYSEL0 MDIO User PHY SelectRegister0 88h USERACCESS1 MDIO User Access Register1 8Ch USERPHYSEL1 MDIO User PHY SelectRegister1

6.22.2 Management Data Input/Output(MDIO) ElectricalData/Timing

Table6-97.Timing Requirements forMDIO Input(seeFigure6-63and Figure6-64) DEVICE NO. UNIT MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 ns 2 tw(MDCLK) Pulseduration,MDCLK high/low 180 ns 3 tt(MDCLK) Transitiontime,MDCLK 5 ns 4 tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMDCLK high 10 ns 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK high 0 ns Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 193 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

(input) 3 3 MDCLK MDIO (output) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-63.MDIO InputTiming Table6-98.SwitchingCharacteristicsOver Recommended OperatingConditionsforMDIO Output (seeFigure6-64) DEVICE NO. UNIT MIN MAX 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutputvalid 100 ns Figure6-64.MDIO Output Timing

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6.23 Host-PortInterface(HPI)Peripheral

Note:HPI ispinmultiplexedwithAsynchronousEMIF attheoutputpin.HPI isavailableonlywhen boot mode selectedisHPI bootmode. Inthisconfiguration,thedevicewillalwaysactas a slave.

6.23.1 HPI Device-SpecificInformation

The deviceincludesa user-configurable16-bitHost-portinterface(HPI16).

• Multiplexed(address/data)operation
• Configurablesinglefull-wordcycleand dualhalf-wordcycleaccessmodes
• Burstingavailableutilizing8-wordreadand writeFIFOs
• HPIA registersupportsauto-incrementing
• HPID register/FIFOsprovidingdata-pathbetween externalhostinterfaceand systembus
• Multiplestrobesand controlsignalstoallowflexiblehostconnection
• SoftwarecontrolofdataprefetchingtotheHPID/FIFOs
• DMSoC-to-Hostinterruptoutputsignalcontrolledby HPIC accesses
• Host-to-DMSoCinterruptcontrolledby HPIC accesses NOTE: The deviceHPI does not supporttheHAS feature.For properHPI operationiftheHAS pinis routedout,theHAS pinmust be pulledup viaan externalresistor. The deviceHPICTL register(0x01C4 0024)ispartoftheSystem Module Registers.The HPICTL register controlswriteaccess totheHPI peripheralcontroland addressregistersas wellas determinesthehost time-outvalue.

6.23.2 HPI Bus Master

The HPI peripheralincludesa bus masterinterfacethatallowsexternaldeviceinitiatedtransferstoaccess theDM365 system bus.See theMasterPeripheralMem Map column inTable2-3,thedeviceMemory Map.

6.23.3 HPI PeripheralRegisterDescription(s)

Table 6-99 liststhe HPI registers,theircorrespondingacronyms, and the devicememory locations (offsets). Table6-99.HPI Registers Offset Acronym RegisterDescription 0h PID PeripheralIdentificationRegister 4h PWREMU_MGMT Power and EmulationManagement Register 30h HPIC HostPortInterfaceControlRegister 34h HPIAW HostPortInterfaceWriteAddressRegister 38h HPIAR HostPortInterfaceRead AddressRegister Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 195 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.23.4 HPI ElectricalData/Timing

Table6-100.Timing Requirements forHost-PortInterfaceCycles(1)(2)(seeFigure6-65and Figure6-66) DEVICE NO. UNIT MIN MAX 1 tsu(SELV-HSTBL) Setuptime,selectsignals(3)validbeforeHSTROBE low 6 ns 2 th(HSTBL-SELV) Holdtime,selectsignals(3)validafterHSTROBE low 2 ns 3 tw(HSTBL) Pulseduration,HSTROBE activelow 15 ns 4 tw(HSTBH) Pulseduration,HSTROBE inactivehighbetween consecutiveaccesses 2P ns 11 tsu(HDV-HSTBH) Setuptime,hostdatavalidbeforeHSTROBE high 5 ns 12 th(HSTBH-HDV) Holdtime,hostdatavalidafterHSTROBE high 2 ns Holdtime,HSTROBE highafterHRDY low.HSTROBE shouldnotbe 13 th(HRDYL-HSTBL) inactivateduntilHRDY isactive(low);otherwise,HPI writeswillnot 2 ns completeproperly. (1) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (2) P = PLLC1.SYSCLK4 period,where SYSCLK4 isan outputclockofPLLC1. Formore details,see Section3.3,DeviceClocking (3) Selectsignalsinclude:HCNTLA, HCNTLB, HR/W and HHWIL.

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-101.SwitchingCharacteristicsforHost-PortInterfaceCycles(1)(2)(3) (seeFigure6-65and Figure6-66) DEVICE NO. PARAMETER UNIT MIN MAX ForHPI Write,HRDY can go high(not ready)fortheseHPI Writeconditions; otherwise,HRDY stayslow(ready): Case 1:Back-to-backHPIA writes(can be eitherfirstorsecond half-word) Case 2:HPIA writefollowinga PREFETCH command (canbe either firstorsecond half-word) Case 3:HPID writewhen FIFO isfull orflushing(canbe eitherfirstor second half-word) Case 4:HPIA writeand WriteFIFO not empty ForHPI Read, HRDY can go high(not ready)fortheseHPI Read conditions: Case 1:HPID read(withDelaytime,HSTROBE lowto5 td(HSTBL-HRDYV) 17 nsauto-increment)and datanotinReadHRDY valid FIFO (canonlyhappen tofirst half-wordofHPID access) Case 2:Firsthalf-wordaccessofHPID Read withoutauto-increment ForHPI Read, HRDY stayslow(ready) fortheseHPI Read conditions: Case 1:HPID readwithauto-increment and dataisalreadyinRead FIFO (appliestoeitherhalf-wordofHPID access) Case 2:HPID readwithout auto-incrementand dataisalreadyin Read FIFO (alwaysappliestosecond half-wordofHPID access) Case 3:HPIC orHPIA read(appliesto eitherhalf-wordaccess) 6 ten(HSTBL-HDLZ) Enabletime,HD drivenfromHSTROBE low 2 ns 7 td(HRDYL-HDV) Delaytime,HRDY lowtoHD valid 0 ns 8 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 1.5 ns 14 tdis(HSTBH-HDV) Disabletime,HD high-impedancefromHSTROBE high 15 ns ForHPI Read. Appliestoconditions where dataisalreadyresidingin HPID/FIFO: Case 1:HPIC orHPIA readDelaytime,HSTROBE lowto15 td(HSTBL-HDV) Case 2:Firsthalf-wordofHPID read 18 nsHD valid withauto-incrementand datais alreadyinRead FIFO Case 3:Second half-wordofHPID readwithorwithoutauto-increment (1) P = PLLC1.SYSCLK4 period,where SYSCLK4 isan outputclockofPLLC1. Formore details,see Section3.3,DeviceClocking. (2) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (3) By design,whenever HCS isdriveninactive(high),HPI willdriveHRDY active(low). Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 197 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

A. refers to the following logical operation on , , and : [NOT( XOR )] or .HSTROBE HCS HDS1 HDS2 HDS1 HDS2 HCS B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on may or may not occur.HRDY C. reflects typical behavior when assertion is caused by or . timing requirements are reflected by parameters for . HCS HCS HSTROBE HDS1 HDS2 HCS HSTROBE D. For proper HPI operation, must be pulled up via an external resistor.HAS HCNTL[B:A] 2nd Half-Word 1st Half-Word 1 1 HAS (D) HR/W HHWIL HSTROBE (A)(C) HD[15:0] (output) HRDY (B) HCS 3 3 TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com Figure6-65.HPI16 Read Timing (HAS Not Used, TiedHigh)

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A. refers to the following logical operation on , , and : [NOT( XOR )] OR .HSTROBE HCS HDS1 HDS2 HDS1 HDS2 HCS B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on may or may not occur.HRDY C. reflects typical behavior when assertion is caused by or . timing requirements are reflected by parameters for . HCS HCS HSTROBE HDS1 HDS2 HCS HSTROBE D. For proper HPI operation, must be pulled up via an external resistor.HAS HCNTL[B:A] 135 HAS (D) HR/W HHWIL HSTROBE (A)(C) HD[15:0] (input) HRDY (B) HCS 3 3 11 12 1st Half-Word 2nd Half-Word TMS320DM365 www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Figure6-66.HPI16 WriteTiming (HAS Not Used, TiedHigh)

6.24 Key Scan

The devicecontainsKey Scan module thatsupportstwo typesof Key Matrices- 4x4 and 5x3.Italso supportsthefollowingfeatures:

• Supportsthefollowingtwo scan modes – ChannelIntervalmode – Scan Intervalmode
• Programmable key scan time – Strobetime – Intervaltime
• Two inputdetectionmodes – Directmode – 3-Datacheckmode
• Supportsone interrupttodetectthefollowing: – Key inputchanges – Periodictimeintervalsaftera key ispressed Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 199 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

KEY_ IN[4:0] KEY_OUT[3:0] (Active□Low) Hi -ZHi -Z KEY_OUT[3:0] (Always□Out) TMS320DM365 SPRS457E –MARCH 2009–REVISED JUNE 2011 www.ti.com

6.24.1 Key Scan PeripheralRegisterDescription(s)

Table6-102liststheKey Scan registers,theircorrespondingacronyms,and thedevicememory locations (offsets). Table6-102.Key Scan Registers Offset Register Description 0x0 KEYCTRL Module Controlregister 0x4 INTCENA InterruptEnablecontrol 0x8 INTFLG InterruptFlagcontrol 0xC INTCLR InterruptClearcontrol 0x10 STRBWIDTH Strobewidth 0x14 INTERVALTIME IntervalTime 0x18 CONTITIME Continuoustimer 0x1C CURRENTST Keyscan currentstatus 0x20 PREVIOUSST Keyscan previousstatus 0x24 EMUCTRL Emulationcontrol

6.24.2 Key Scan ElectricalData/Timing

Table6-103.Timing Requirements forKeyscan (seeFigure6-63and Figure6-64) DEVICENO UNIT. MIN MAX (STWIDTH + 1)*CLK_P-1(1) 1 tw(KEYOUTV) Pulseduration,Keyscan out(activelowmode) ns(2) (STWIDTH + 1)*CLK_P-1(1) 2 tw(KEYOUTL) Pulseduration,Keyscan out(alwaysoutmode) ns(2) Setuptime,Keyscan input(alwaysoutmode) 3 tsu(KEYOUT-KEYIN) 20 ns Setuptime,Keyscan input(activelowmode) Holdtime,Keyscan input(alwaysoutmode) 4 th(KEYOUT-KEYIN) 0 ns Holdtime,Keyscan input(activelowmode) (1) STWIDTH = thevalueprogrammed intotheSTRBWIDTH register. (2) CLK_P = 1/(PLLC1.AUXCLK/(DIV3+1))or1/(RTCXI),where RTCXI isthePRTCSS oscillatorinputpinfrequencyof32.768kHz. Figure6-67.Key Scan Timing

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6.25 Analog-to-DigitalConverter(ADC)

The devicehas a 6-channel10-bitAnalog-to-DigitalConverter(ADC) interface.The analog-to-digital converter(ADC) featureisverycommon inembedded systems.The followingfeaturesare supportedon theAnalog-to-DigitalConverter(ADC):

• Sixconfigurableanaloginputselects
• SuccessiveApproximationtype10 bitA-D converter
• Programmable Sampling/ConversionTime (baseclockisAUXCLK)
• Channelselectby AutoScan conversion
• Mode selectby One-shotmode orFree-runmode
• Programmable setup(idle)periodtosecureA/D samplingstarttime
• SupportstheclockstopsignalstoconnectthePSC ForAnalog-to-DigitalConvertercharacteristics,see Section5.2and Section5.3.

6.25.1 Analog-to-DigitalConverter(ADC) PeripheralRegisterDescription(s)

Table 6-104 liststhe ADC registers,theircorrespondingacronyms,and the devicememory locations (offsets). Table6-104.Analog-to-DigitalConverter(ADC) InterfaceRegisters Offset Register Description 0x0 ADCTL Controlregister 0x4 CMPTGT Comparatortargetchannel 0x8 CMPLDAT ComparisonA/D Lower data 0xC CMPUDAT ComparisonA/D Upper data 0x10 SETDIV SETUP dividevalueforstartA/D conversion 0x14 CHSEL AnalogInputchannelselect 0x18 AD0DAT A/D conversiondata0 0x1C AD1DAT A/D conversiondata1 0x20 AD2DAT A/D conversiondata2 0x24 AD3DAT A/D conversiondata3 0x28 AD4DAT A/D conversiondata4 0x2C AD5DAT A/D conversiondata5 0x30 EMUCTRL EmulationControl

6.26 Voice Codec

The devicehas VoiceCodec withFIFO (Read FIFO/WriteFIFO).The followingfeaturesaresupportedon theVoiceCodec module.

• 16bitx 16 word FIFO forRecording/Playbackdatatransfer
• FulldifferentialMicrophoneAmplifier
• Monauralsingleended Lineoutput
• MonauralSpeakerAmplifier(BTL)
• Dynamic Range: 70dB(DAC)
• Dynamic Range: 70dB(ADC)
• 200-300mW SpeakeroutputatR L = 8Ω
• Samplingfrequency:8 KHz or16 KHz
• AutomaticLevelControlforRecording Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 201 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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• Programmable Functionby RegisterControl – DigitalAttenuatorofDAC: 0 dB to-62dB – DigitalgaincontrolforRecording(0/+6/+12/+18dB) – Power Up/Down Controlforeach module – 20 dB/26dB BoostSelectableforMicrophoneInput – Two StageNotchfilter ForVoiceCodec characteristics,see Section5.2and Section5.3.

6.26.1 Voice Codec RegisterDescription(s)

Table 6-105 liststhe Voice Codec registers,theircorrespondingacronyms, and the devicememory locations(offsets). Table6-105.Voice Codec Registers Offset Register Description 0x00 VC_PID VCIF PID 0x04 VC_CTRL VCIF ControlRegister 0x08 VC_INTEN VCIF Interruptenable 0x0C VC_INTSTATUS VCIF Interruptstatus 0x10 VC_INTCLR VCIF Interruptstatusclear 0x14 VC_EMUL_CTRL VCIF emulatorControl 0x20 RFIFO VCIF Read FIFO accessregister 0x24 WFIFO VCIF WriteFIFO accessregister 0x28 FIFOSTAT FIFO Status 0x80 VC_REG00 Notchfilterparameter1 0x84 VC_REG01 Notchfilterparameter1 0x88 VC_REG02 Notchfilterparameter2 0x8C VC_REG03 Notchfilterparameter2 0x90 VC_REG04 Recordingsidemode control 0x94 VC_REG05 PGM & MIC gain 0x98 VC_REG06 ALC 0xA4 VC_REG09 Digitalsoftmute/attention 0xA8 VC_REG10 Digitalsoftmute/attention 0xB0 VC_REG12 Power up/down control

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 6.27 IEEE 1149.1JTAG The JTAG (1)interfaceisused forBSDL testingand emulationofthedevice. The devicerequiresthatboth TRST and RESET be assertedupon power up to be properlyinitialized. WhileRESET initializesthedevice,TRST initializesthedevice'semulationlogic.Both resetsarerequired forproperoperation. WhilebothTRST and RESET need tobe assertedupon power up,onlyRESET needs tobe releasedfor thedevicetobootproperly.TRST may be assertedindefinitelyfornormaloperation,keepingtheJTAG portinterfaceand device'semulationlogicintheresetstate. TRST onlyneeds tobe releasedwhen itisnecessarytouse a JTAG controllertodebug thedeviceor exercisethedevice'sboundaryscan functionality.Note:TRST issynchronousand must be clockedby TCK; otherwise,theboundaryscan logicmay notrespondas expectedafterTRST isasserted. RESET must be releasedonlyin orderforboundary-scanJTAG to read the variantfieldof IDCODE correctly.Otherboundary-scaninstructionswork correctlyindependentofcurrentstateofRESET. For maximum reliability,the deviceincludesan internalpulldown(PD) on the TRST pinto ensure that TRST willalways be assertedupon power up and the device'sinternalemulationlogicwillalways be properlyinitialized. JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay notdriveTRST highbutexpecttheuse ofa pullupresistoron TRST. When usingthistypeofJTAG controller,assertTRST toinitializethedeviceafterpower up and externally driveTRST highbeforeattemptingany emulationor boundaryscan operations.Followingthereleaseof RESET, the low-to-hightransitionofTRST must be "seen"to latchthe stateof EMU1 and EMU0. The EMU[1:0]pinsconfigurethedeviceforeitherBoundary Scan mode orEmulationmode. For more detailed information,see theterminalfunctionssectionofthisdatasheet.

6.27.1 JTAG RegisterDescription(s)

Table 6-105 shows the DEVICE ID register(which includesthe JTAG ID relatedinformation),its correspondingacronym,and thedevicememory location.For more detailson theDEVICE ID registerbit fields,see theTMS320DM36x DMSoC ARM Subsystem ReferenceGuide (literaturenumber SPRUFG5 ). Table6-106.DEVICE ID Register HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS Read-only.Provides32-bit0x01C4 0028 DEVICEID JTAG IdentificationRegister JTAG ID ofthedevice. (1) IEEE Standard1149.1-1990Standard-Test-AccessPortand BoundaryScan Architecture. The DEVICE ID registerisa read-onlyregisterthatidentifiestothecustomertheJTAG/DeviceID.For the device,theDEVICE ID registerresidesataddresslocation0x01C4 0028.The registerhex valueforthe deviceis:0xXB70 002F where 'X'denotesthesiliconrevisionofthedevice.Formore detailson thesilicon revision,see theTMS320 DM365 DMSoC SiliconErrata(literaturenumber SPRZ294 ). Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 203 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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6.27.2 JTAG Test-PortElectricalData/Timing

Table6-107.Timing Requirements forJTAG TestPort(seeFigure6-68) DEVICE NO. UNIT MIN MAX 1 tc(TCK) Cycletime,TCK 50 ns 2 tw(TCKH) Pulseduration,TCK high 20 ns 3 tw(TCKL) Pulseduration,TCK low 20 ns 4 tsu(TDIV-RTCKH) Setuptime,TDI validbeforeRTCK high 5 ns 5 th(RTCKH-TDIIV) Holdtime,TDI validafterRTCK high 10 ns 6 tsu(TMSV-RTCKH) Setuptime,TMS validbeforeRTCK high 5 ns 7 th(RTCKH-TMSV) Holdtime,TMS validafterRTCK high 10 ns Figure6-68.JTAG InputTiming

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www.ti.com SPRS457E –MARCH 2009–REVISED JUNE 2011 Table6-108.SwitchingCharacteristicsOver Recommended OperatingConditionsforJTAG TestPort (seeFigure6-68) DEVICE NO. PARAMETER UNIT MIN MAX 8 tc(RTCK) Cycletime,RTCK 50 ns 9 tw(RTCKH) Pulseduration,RTCK high 20 ns 10 tw(RTCKL) Pulseduration,RTCK low 20 ns 11 tr(allJTAG outputs) Risetime,allJTAG outputs 5 ns 12 tf(allJTAG outputs) Falltime,allJTAG outputs 5 ns 13 td(RTCKL-TDOV) Delaytime,TCK lowtoTDO valid 0 23 ns Figure6-69.JTAG Output Timing Copyright© 2009–2011,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 205 SubmitDocumentationFeedback ProductFolderLink(s):TMS320DM365

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7 MechanicalData

The followingtable(s)show the thermalresistancecharacteristicsforthe PBGA − ZCE mechanical package.

7.1 Thermal Data forZCE

The followingtableshows the thermalresistancecharacteristicsforthe PBGA − ZCE mechanical package. Table7-1.Thermal ResistanceCharacteristics(PBGA Package) [ZCE] NO. °C/W (1) 1 R ΘJC Junction-to-case 7.2 2 R ΘJB Junction-to-board 11.4 3 R ΘJA Junction-to-freeair 27.0 4 PsiJT Junction-to-packagetop 0.1 5 PsiJB Junction-to-board 11.3 (1) The junction-to-casemeasurement was conductedina JEDEC defined2S2P systemand willchange based on environmentas wellas application.Formore information,see thesethreeEIA/JEDEC standards:

• EIA/JESD51-2,IntegratedCircuitsThermalTestMethod EnvironmentConditions-NaturalConvection(StillAir)
• EIA/JESD51-3,Low EffectiveThermalConductivityTestBoard forLeaded SurfaceMount Packages
• JESD51-7,HighEffectiveThermalConductivityTestBoard forLeaded SurfaceMount Packages

7.2 Packaging Information

The followingpackaginginformationreflectsthemost currentdataavailableforthedesignateddevice(s). Thisdataissubjecttochange withoutnoticeand withoutrevisionofthisdocument.

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www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DM365ZCES ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 DM365ZCEW ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 DM365ZCEZ ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30F 570 TMS320DM365ZCE21 ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE21 570 TMS320DM365ZCE27 ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE27 570 TMS320DM365ZCE30 ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 TMS320DM365ZCED30 ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 85 DM365ZCED30 570 TMS320DM365ZCEF ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30F 570 TMS320DM365ZCEZ ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30F 570 VCBU65WMCE30 ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 VS3673UNION ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE30 570 VVLOG365ZCE ACTIVE NFBGA ZCE 338 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 85 DM365ZCE27 570 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.

www.ti.com 15-Apr-2017 Addendum-Page 2 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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