DM355SZCE216

Texas Instruments

Digital Media System-on-Chip (DMSoC)

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(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 8-/16-bit YCC and Up to 18-Bit RGB666 High-Performance Digital Media Digital Output System-on-Chip BT.601/BT.656 Digital YCbCr 4:2:2 135-, 216- and 270-MHz ARM926EJ-S Clock (8-/16-Bit) Interface Rate Supports digital HDTV (720p/1080i) Fully Software-Compatible With ARM9 output for connection to external Extended temperature support for 135- and encoder 216-MHz devices External Memory Interfaces (EMIFs) ARM926EJ-S Core DDR2 and mDDR SDRAM 16-bit wide EMIF Support for 32-Bit and 16-Bit (Thumb Mode) With 256 MByte Address Space (1.8-V I/O) Instruction Sets Asynchronous16-/8-bit Wide EMIF (AEMIF) DSP Instruction Extensions and Single Flash Memory Interfaces Cycle MAC NAND (8-/16-bit Wide Data) ARM Jazelle Technology OneNAND(16-bit Wide Data) EmbeddedICE-RT Logic for Real-Time Debug Flash Card Interfaces Two Multimedia Card (MMC) Secure ARM9 Memory Architecture Digital (SD/SDIO) 16K-Byte Instruction Cache SmartMedia 8K-Byte Data Cache Enhanced Direct-Memory-Access (EDMA) 32K-Byte RAM Controller (64 Independent Channels) 8K-Byte ROM USB Port with Integrated 2.0 High-Speed PHY Little Endian that Supports MPEG4/ JPEG Coprocessor USB 2.0 Full and High-Speed Device Fixed Function Coprocessor Supports: USB 2.0 Low, Full, and High-Speed Host MPEG4 SP Codec at HD (720p), D1, Three 64-Bit General-Purpose Timers (each VGA, SIF configurable as two 32-bit timers) JPEG Codec up to 50M Pixels per One 64-Bit Watch Dog Timer Second Three UARTs (One fast UART with RTS and Video Processing Subsystem CTS Flow Control) Front End Provides: Three Serial Port Interfaces (SPI) each with Hardware IPIPE for Real-Time Image two Chip-Selects Processing One Master/Slave Inter-Integrated Circuit Up to 14-bit CCD/CMOS Digital Interface Bus 16-/8-bit Generic YcBcR-4:2 Interface Two Audio Serial Port (ASP) (BT.601) I2S and TDM I2S 10-/8-bit CCIR6565/BT655 Interface AC97 Audio Codec Interface Up to 75-MHz Pixel Clock S/PDIF via Software Histogram Module Standard Voice Codec Interface (AIC12) Resize Engine SPI Protocol (Master Mode Only) Resize Images From 1/16x to Four Pulse Width Modulator (PWM) Outputs Separate Horizontal/Vertical Control Four RTO (Real Time Out) Outputs Two Simultaneous Output Paths Up to 104 General-Purpose I/O (GPIO) Pins Back End Provides: (Multiplexed with Other Device Functions) Hardware On-Screen Display (OSD) On-Chip ARM ROM Bootloader (RBL) to Boot Composite NTSC/PAL video encoder From NAND Flash, MMC/SD, or UART output Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

document. Windows is a trademark of Microsoft. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2007 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Configurable Power-Saving Modes ETB™ (Embedded Trace Buffer™) with 4K-Bytes Trace Buffer memory Crystal or External Clock Input (typically Device Revision ID Readable by ARM MHz or MHz) 337-Pin Ball Grid Array (BGA) Package Flexible PLL Clock Generators (ZCE Suffix), 0.65-mm Ball Pitch Debug Interface Support 90nm Process Technology IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 3.3-V and 1.8-V I/O, 1.3-V Internal TMS320DM355 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback

1.2

Description

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc. The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates: A coprocessor (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second. The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: A Video Processing Front-End (VPFE) A Video Processing Back-End (VPBE) The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output. The DM355 peripheral set includes: An inter-integrated circuit (I2C) Bus interface Two audio serial ports (ASP) Three 64-bit general-purpose timers each configurable as two independent 32-bit timers A 64-bit watchdog timer Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals Three UARTs with hardware handshaking support on one UART Three serial port Interfaces (SPI) Four pulse width modulator (PWM) peripherals Four real time out (RTO) outputs Two Multi-Media Card Secure Digital (MMC/SD/SDIO) interfaces Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO A USB 2.0 full and high-speed device and host interface Two external memory interfaces: An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND, A high speed synchronous memory interface for DDR2/mDDR. Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC)

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com For software development support the DM355 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320DM355 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback

1.3 Functional Block Diagram Peripherals64bit□DMA/Data□Bus JTAG 24□MHz or□36□MHz 27□MHz (optional) CCD/ CMOS Module DDR2/mDDR□16 CLOCK PLL CLOCK□ctrl PLLs JTAJTAG I/F Clocks ARM z ) ARM926EJ-S_Z8 I-cach e16 K B l-cache 16KB B RA M32 K B RAM 32KB B D-cach e8K D-cache 8KB RO M8 K ROM 8KB CCD C 3AH3A DMA /Data□and□configuration□bus DMA/Data□and□configuration□bus DDR MH z ) DDR controller DLDLL/ PHY 16□bit 32bit□Configuration□Bus CCDC IPIPE VPBE Vide oEncod er Video Encoder 10b DAC OS D OSD er c ARMARM□INTC Enhanced channels3PCC /TC (100 MHz Enhanced□DMA 64□channels Composite□video Digital□RGB/YUV Nand /Nand/SM/ Async/One□Nand (AEMIF) USB 2.0USB2.0□PHY Speaker microphone ASP (2x) Buffer□Lo gic VPSS MMC/SD□(x2) SPI□I/F□(x3) UART (x3) I2C Timer/ WDT (x4□-□64) GIO PWM□(x4) RTO VPFE Enhanced channels3PCC /TC (100 MHz MPEG4/JPEG Coprocessor TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 1-1 shows the functional block diagram of the DM355 device. Figure 1-1. Functional Block Diagram Submit Documentation Feedback TMS320DM355 Digital Media System-on-Chip (DMSoC)

2.1 Device Characteristics TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-1 provides an overview of the DMSoC. The table shows significant device, including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin count, etc. Table 2-1. Characteristics of the Processor HARDWARE (16-bit bus width) Asynchronous (8/16-bit bus width) Asynchronous EMIF (AEMIF) RAM, Flash (NAND, OneNAND) Two MMC/SD Flash Card Interfaces One SmartMedia/xD independent DMA channels EDMA Eight EDMA channels Three 64-Bit General Purpose (each configurable as two separate 32-bit Timers timers) Peripherals One 64-Bit Watch Dog Not all peripherals pins are Three (one with RTS and CTS flow available at the same time UART control) (For more detail, see the Device Configuration Three (each supports two slave SPI section). devices) I C One (Master/Slave) Audio Serial Port [ASP] Two ASP General-Purpose Input/Output Port Up to 104 Pulse width modulator (PWM) Four outputs One Input (VPFE) Configurable Video Ports One Output (VPBE) High, Full Speed Device USB 2.0 High, Full, Low Speed Host ARM On-Chip CPU Memory Organization 16-KB I-cache, 8-KB D-cache, 32-KB RAM, 8-KB ROM JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) 0x0B73B01F CPU Frequency (Maximum) MHz ARM 135, 216 (1) and 270 MHz Core (V) 1.3 V Voltage I/O (V) 3.3 1.8 V Reference frequency options MHz (typical), MHz PLL Options Configurable PLL controller PLL bypass, programmable PLL BGA Package x mm 337-Pin BGA (ZCE) Process Technology nm Product Preview (PP), Product Status (2) Advance Information (AI), PD or Production Data (PD) (1) Extended temperature supported for A216 and A135 devices. (2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Submit Documentation Feedback Device Overview

2.2 Memory Map Summary TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. The bus masters are the ARM, EDMA, USB, and VPSS. Table 2-2. DM355 Memory Map Start Address End Address Size (Bytes) ARM EDMA USB VPSS Mem Map Mem Map Mem Map Mem Map 0x0000 0000 0x0000 3FFF 16K ARM RAM0 (Instruction) 0x0000 4000 0x0000 7FFF 16K ARM RAM1 Reserved Reserved (Instruction) 0x0000 8000 0x0000 FFFF 32K ARM ROM (Instruction) only used 0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1 0x0001 8000 0x0001 FFFF 32K ARM ROM (Data) ARM ROM ARM ROM only used 0x0002 0000 0x000F FFFF 896K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF ARM ETB Mem 0x01BC 1000 0x01BC 17FF ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x01C0 0000 0x01FF FFFF CFG Bus CFG Bus Reserved Peripherals Peripherals 0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data) 0x0A00 0000 0x11EF FFFF 127M 16K 0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved 0x11F2 0000 0x1FFF FFFF 141M-64K 0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control Regs Regs 0x2000 8000 0x41FF FFFF 544M-32K Reserved 0x4200 0000 0x49FF FFFF 128M Reserved Reserved 0x4A00 0000 0x7FFF FFFF 864M Reserved 0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved Table 2-3. DM355 ARM Configuration Bus Access to Peripherals Address Accessibility Region Start End Size ARM EDMA EDMA CC 0x01C0 0000 0x01C0 FFFF 64K EDMA TC0 0x01C1 0000 0x01C1 03FF EDMA TC1 0x01C1 0400 0x01C1 07FF Reserved 0x01C1 0800 0x01C1 9FFF 38K Reserved 0x01C1 A000 0x01C1 FFFF 24K UART0 0x01C2 0000 0x01C2 03FF Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) Address Accessibility UART1 0x01C2 0400 0x01C2 07FF Timer4/5 0x01C2 0800 0x01C2 0BFF Real-time out 0x01C2 0C00 0x01C2 0FFF I2C 0x01C2 1000 0x01C2 13FF Timer0/1 0x01C2 1400 0x01C2 17FF Timer2/3 0x01C2 1800 0x01C2 1BFF WatchDog Timer 0x01C2 1C00 0x01C2 1FFF PWM0 0x01C2 2000 0x01C2 23FF PWM1 0x01C2 2400 0x01C2 27FF PWM2 0x01C2 2800 0x01C2 2BFF PWM3 0x01C2 2C00 0x01C2 2FFF System Module 0x01C4 0000 0x01C4 07FF PLL Controller 0x01C4 0800 0x01C4 0BFF PLL Controller 0x01C4 0C00 0x01C4 0FFF Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF Reserved 0x01C4 2000 0x01C4 7FFF 24K ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF Reserved 0x01C4 8400 0x01C6 3FFF 111K USB OTG 2.0 Regs RAM 0x01C6 4000 0x01C6 5FFF SPI0 0x01C6 6000 0x01C6 67FF SPI1 0x01C6 6800 0x01C6 6FFF GPIO 0x01C6 7000 0x01C6 77FF SPI2 0x01C6 7800 0x01C6 FFFF VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K VPSS Clock Control 0x01C7 0000 0x01C7 007F 128 Hardware 0x01C7 0080 0x01C7 00FF 128 Image Pipe (IPIPE) Interface 0x01C7 0100 0x01C7 01FF 256 On Screen Display 0x01C7 0200 0x01C7 02FF 256 Reserved 0x01C7 0300 0x01C7 03FF 256 Video Encoder 0x01C7 0400 0x01C7 05FF 512 CCD Controller 0x01C7 0600 0x01C7 07FF 256 VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256 Reserved 0x01C7 0900 0x01C7 09FF 256 Image Pipe (IPIPE) 0x01C7 1000 0x01C7 3FFF 12K Reserved 0x01C7 4000 0x01CD FFFF 432K Multimedia SD 0x01E0 0000 0x01E0 1FFF ASP0 0x01E0 2000 0x01E0 3FFF ASP1 0x01E0 4000 0x01E0 5FFF UART2 0x01E0 6000 0x01E0 63FF Reserved 0x01E0 6400 0x01E0 FFFF 39K ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF Multimedia SD 0x01E1 1000 0x01E1 FFFF 60K Reserved 0x01E2 0000 0x01FF FFFF 1792K ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M Reserved 0x0600 0000 0x09FF FFFF 64M Reserved 0x0A00 0000 0x0BFF FFFF 32M Submit Documentation Feedback Device Overview

2.3 Pin Assignments 2.3.1 Pin Map (Bottom View) J VSSA_PLL2 VDDA33_USB 65431 H G VDDA13_USB VSS F E D CIN2 C B A VREFCIN3CIN0 VDDA_PLL2VSSLCD_OEFIELDVCLKVSS VSSCVDDVSYNCEXTCLKVFB VDD_VOUTVDD_VOUTVDD_VOUTHSYNCCOUT0COUT1TVOUT TDOEMU0EMU1VSS_USBUSB_VBUSCOUT2COUT3IOUT TDITMSVSS_USBUSB_IDCOUT4VSS TRSTVSS_USB_REFUSB_R1VDDD13_USBUSB_DRV VBUSCVDDYOUT7COUT5 MXO1VSS VSS_USBVDDA33_USB_ PLL VSSYOUT5YOUT4YOUT0 MXI1VSSUSB_DPUSB_DMVSSYOUT6YOUT2CVDD VSS VSS VSS IBIAS VSS COUT6 COUT7 YOUT3 YOUT1 RSV01 VDD VDD NC TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued) Address Accessibility Reserved 0x0C00 0000 0x0FFF FFFF 64M Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. Figure 2-1 through Figure 2-4 show the pin assignments in four quadrants (A, and D). Note that micro-vias are not required. Contact your TI representative for routing recommendations. Figure 2-1. Pin Map [Quadrant Device Overview Submit Documentation Feedback

W DDR_CLK DDR_CLK 7654 DDR_A05 DDR_A02 V DDR_A07DDR_A04DDR_A00 U VSS T PCLK R P N M L K DDR_A1 1DDR_A09DDR_A08VSS DDR_CASDDR_BA[2]DDR_A12DDR_A10DDR_A01VSS DDR_BA[0]DDR_BA[1]DDR_A13DDR_A06 DDR_A03 VSSVSSVSSVSS DDR_ZNDDR_CSDDR_RASVSSVSSMXO2 VDD_DDRCVDDCVDDVSSCAM_WEN_ FIELD CAM_VDYIN3VSSMXI2 VDD_DDRVDD_VINYIN0YIN2YIN4YIN1VSS_MX2 VSSVSSCVDDCAM_HDCIN7RSV05VSS VDD_DDRVSSVSSVSSYIN5YIN6CIN5RSV06RSV04 VSSVSS_DACVDDA18V_DACVDDYIN7CIN4CIN1VSSRSV03 VSSVDDCVDDCIN6VSSRSV07RSV02 VDD_VINVDD_VIN TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 2-2. Pin Map [Quadrant Submit Documentation Feedback Device Overview

W DDR_ DQGA TE0 DDR_DQ15 DDR_DQ13 DDR_DQ1 1 DDR_DQ10 DDR_DQ07 DDR_DQ05 1 1 DDR_DQ01 DDR_WE EM_A13 VVSS DDR_ DQGA TE1DDR_DQ14DDR_DQS[1]DDR_DQ09DDR_DQ06DDR_DQS[0]DDR_DQ00DDR_CKE EM_A12 UUART0_RXDVSSDDR_DQ12DDR_DQM[1]VSSDDR_DQ08DDR_DQ04DDR_DQ02DDR_VREF EM_A08 TUART0_TXDCVDDVSSVDD_DDRDDR_DQM[0]DDR_DQ03 EM_A05 REM_A10UART1_TXDEM_A1 1UART1_RXDI2C_SCLI2C_SDAVDD_DDRVSSA_DLLVDDA33_DDRDLL EM_BA1 PEM_A06EM_A09EM_A07EM_A04VDD_DDR EM_BA0 NEM_A03EM_A01EM_A02VSSVDDVDD EM_D14 MEM_D15VSSEM_A00EM_D13VSSVDD EM_D10 LEM_D12EM_D1 1EM_D08EM_D04CVDDVSS EM_D07 KEM_D09EM_D06 VDD_DDR VDD_DDR VDD_DDR VDD_DDR VDDVDDVDD CVDD VDD VSS CVDD CVDD VSS VSS VDD TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 2-3. Pin Map [Quadrant Device Overview Submit Documentation Feedback

EM_D05 J EM_D02 H EM_CE1 G F E D C VDD B A EM_D03EM_D01EM_CE0EM_WEVSS EM_D00EM_ADVASP0_DXVSSA_PLL1CVDD EM_WAITASP0_FSXGIO003VDDA_PLL1 EM_OEASP0_CLKXASP0_CLKRASP0_FSRGIO002 EM_CLKASP0_DRASP1_FSRASP1_FSXGIO001SPI1_ SDENA[0]SPI1_SDORTCKTCK ASP1_CLKXASP1_CLKRASP1_CLKSGIO005MMCSD0_ DA T A1CLKOUT1RESET ASP1_DRASP1_DXGIO007GIO000MMCSD1_CLKMMCSD0_CMDSPI1_SCLKSPI0_SCLKCLKOUT3VSS_MX1 GIO006 MMCSD1_ DA T A0 MMCSD1_ DA T A3 MMCSD1_ DA T A2 GIO004 MMCSD1_ CMD MMCSD1_ DA T A1 MMCSD0_ CLK MMCSD0_ DA T A0 MMCSD0_ DA T A3 MMCSD0_ DA T A2 SPI1_SDI SPI0_ SDENA[0] SPI0_SDI SPI0_SDO CLKOUT2 VSS CVDD CVDD CVDD VSS CVDD VSS CVDD CVDD VDDVDDVDDVDDVDD VSS CVDDVSS VSSCVDD TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 2-4. Pin Map [Quadrant Submit Documentation Feedback Device Overview

2.4 Pin Functions 2.4.1 Image Data Input Video Processing Front End TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The pin functions tables Table 2-4 through Table 2-22 identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see Section For the list of all pin in chronological order see Section 2.5 The CCD Controller module in the Video Processing Front End has an external signal interface for image data input. It supports YUV (YC) inputs as well as Bayer RGB and complementary input signals (I.e., image data input). The definition of the CCD controller data input signals depend on the input mode selected. In 16-bit YCbCr mode, the Cb and Cr signals are multiplexed on the Cl signals and the order is configurable (i.e., Cb first or Cr first). In 8-bit YCbCr mode, the Cb, and Cr signals are multiplexed and not only is the order selectable, but also the half of the bus used. Table 2-4. CCD Controller Signals for Each Input Mode PIN NAME CCD 16-BIT YCbCr 8-BIT YCbCr Cl7 Cb7,Cr7 Y7,Cb7,Cr7 Cl6 Cb6,Cr6 Y6,Cb6,Cr6 Cl5 CCD13 Cb5,Cr5 Y5,Cb5,Cr5 Cl4 CCD12 Cb4,Cr4 Y4,Cb4,Cr4 Cl3 CCD11 Cb3,Cr3 Y3,Cb3,Cr3 Cl2 CCD10 Cb2,Cr2 Y2,Cb2,Cr2 Cl1 CCD9 Cb1,Cr1 Y1,Cb1,Cr1 Cl0 CCD8 Cb0,Cr0 Y0,Cb0,Cr0 Yl7 CCD7 Y7,Cb7,Cr7 Yl6 CCD6 Y6,Cb6,Cr6 Yl5 CCD5 Y5,Cb5,Cr5 Yl4 CCD4 Y4,Cb4,Cr4 Yl3 CCD3 Y3,Cb3,Cr3 Yl2 CCD2 Y2,Cb2,Cr2 Yl1 CCD1 Y1,Cb1,Cr1 Yl0 CCD0 Y0,Cb0,Cr0 Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-5. CCD Controller/Video Input Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. Standard CCD/CMOS input: NOT USED YCC 16-bit: Time multiplexed between chroma: CB/CR[07] CIN7/ PD YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO101/ I/O/Z V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[07] SPI2_SCLK SPI: SPI2 Clock GIO: GIO[101] Standard CCD/CMOS input: NOT USED YCC 16-bit: Time multiplexed between chroma: CB/CR[06] CIN6/ PD YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO100/ I/O/Z V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[06] SPI2_SDO SPI: SPI2 Data Out GIO: GIO[100] Standard CCD/CMOS input: Raw[13] CIN5/ YCC 16-bit: Time multiplexed between chroma: CB/CR[05] GIO099/ PD YCC 8-bit (which allows for two simultaneous decoder inputs), it is time I/O/Z SPI2_SDEN V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[05] A[0] SPI: SPI2 Chip Select GIO: GIO[099] Standard CCD/CMOS input: Raw[12] CIN4/ YCC 16-bit: Time multiplexed between chroma: CB/CR[04] GIO098/ PD YCC 8-bit (which allows for two simultaneous decoder inputs), it is time I/O/Z SPI2_SDEN V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[04] A[1] SPI: SPI2 Data In GIO: GIO[098] Standard CCD/CMOS input: Raw[11] YCC 16-bit: Time multiplexed between chroma: CB/CR[03] CIN3/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO097/ V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[03] GIO: GIO[097] Standard CCD/CMOS input: Raw[10] YCC 16-bit: Time multiplexed between chroma: CB/CR[02] CIN2/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO096/ V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[02] GIO: GIO[097] Standard CCD/CMOS input: Raw[09] YCC 16-bit: Time multiplexed between chroma: CB/CR[01] CIN1/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO095/ V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[01] GIO: GIO[095] Standard CCD/CMOS input: Raw[08] YCC 16-bit: Time multiplexed between chroma: CB/CR[00] CIN0/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO094/ V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[00] GIO: GIO[094] Standard CCD/CMOS input: Raw[07] YCC 16-bit: Time multiplexed between chroma: Y[07] YIN7/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO093 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[07] GIO: GIO[093] Standard CCD/CMOS input: Raw[06] YCC 16-bit: Time multiplexed between chroma: Y[06] YIN6/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO092 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[06] GIO: GIO[092] (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) PD internal pull-down, PU internal pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) (3) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. Submit Documentation Feedback Device Overview

2.4.2 Image Data Output Video Processing Back End (VPBE) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-5. CCD Controller/Video Input Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. Standard CCD/CMOS input: Raw[05] YCC 16-bit: Time multiplexed between chroma: Y[05] YIN5/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO091 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[05] GIO: GIO[091] Standard CCD/CMOS input: Raw[04] YCC 16-bit: Time multiplexed between chroma: Y[04] YIN4/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO090 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[04] GIO: GIO[090] Standard CCD/CMOS input: Raw[03] YCC 16-bit: Time multiplexed between chroma: Y[03] YIN3/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO089 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[03] GIO: GIO[089] Standard CCD/CMOS input: Raw[02] YCC 16-bit: Time multiplexed between chroma: Y[02] YIN2/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO088 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[02] GIO: GIO[088] Standard CCD/CMOS input: Raw[01] YCC 16-bit: Time multiplexed between chroma: Y[01] YIN1/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO087 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[01] GIO: GIO[087] Standard CCD/CMOS input: Raw[00] YCC 16-bit: Time multiplexed between chroma: Y[00] YIN0/ PD I/O/Z YCC 8-bit (which allows for two simultaneous decoder inputs), it is time GIO086 V DD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[00] GIO: GIO[086] Horizontal synchronization signal that can be either an input (slave mode) or an CAM_HD/ PD I/O/Z output (master mode). Tells the CCDC when a new line starts. GIO085 V DD_VIN GIO: GIO[085] Vertical synchronization signal that can be either an input (slave mode) or an output CAM_VD PD I/O/Z (master mode). Tells the CCDC when a new frame starts. GIO084 V DD_VIN GIO: GIO[084] Write enable input signal is used by external device (AFE/TG) to gate the DDR output of the CCDC module. Alternately, the field identification input signal is used CAM_WEN PD by external device (AFE/TG) to indicate which of two frames is input to the CCDC _FIELD I/O/Z V DD_VIN module for sensors with interlaced output. CCDC handles or 2-field sensors in GIO083 hardware. GIO: GIO[083] PCLK/ PD Pixel clock input (strobe for lines C17 through Y10) I/O/Z GIO082 V DD_VIN GIO: GIO[0082] The Video Encoder/Digital LCD interface module in the video processing back end has an external signal interface for digital image data output as described in Table 2-7 and Table 2-8 The digital image data output signals support multiple functions interfaces, depending on the display mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565 signals requires enabling pin multiplexing to support (i.e., for RGB666 mode). Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-6. Signals for VPBE Display Modes PIN NAME YCC16 YCC8/ PRGB SRGB REC656 HSYNC HSYNC HSYNC HSYNC HSYNC GIO073 VSYNC VSYNC VSYNC VSYNC VSYNC GIO072 LCD_OE As needed As needed As needed As needed GIO071 FIELD As needed As needed As needed As needed GIO070 PWM3C EXTCLK As needed As needed As needed As needed GIO069 PWM3D VCLK VCLK VCLK VCLK VCLK GIO068 YOUT7 Y7,Cb7,Cr7 Data7 YOUT6 Y6,Cb6,Cr6 Data6 YOUT5 Y5,Cb5,Cr5 Data5 YOUT4 Y4,Cb4,Cr4 Data4 YOUT3 Y3,Cb3,Cr3 Data3 YOUT2 Y2,Cb2,Cr2 Data2 YOUT1 Y1,Cb1,Cr1 Data1 YOUT0 Y0,Cb0,Cr0 Data0 COUT7 LCD_AC LCD_AC GIO081 PWM0 COUT6 LCD_OE LCD_OE GIO080 PWM1 COUT5 BRIGHT BRIGHT GIO079 PWM2A RTO0 COUT4 PWM PWM GIO078 PWM2B RTO1 COUT3 CSYNC CSYNC GIO077 PWM2C RTO2 COUT2 GIO076 PWM2D RTO3 COUT1 GIO075 PWM3A COUT0 GIO074 PWM3B Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-7. Digital Video Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) (4) NAME NO. YOUT7-R7 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT6-R6 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT5-R5 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT4-R4 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT3-R3 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT2-G7 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT1-G6 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function YOUT0-G5 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function COUT7- G4/GIO081 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[081] PWM0 /PWM0 COUT6-G3 /GIO080 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[080] PWM1 /PWM1 COUT5-G2 GIO079 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A RTO0 PWM2A RTO0 COUT4-B7 GIO078 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B RTO1 PWM2B RTO1 COUT3-B6 GIO077 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C RTO2 PWM2C RTO2 COUT2-B5 GIO076 I/O/Z V DD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D RTO3 PWM2D RTO3 COUT1-B4 Digital Video Out: VENC settings determine function GIO075 I/O/Z V DD_VOUT GIO: GIO[075] PWM3A PWM3A COUT0-B3 Digital Video Out: VENC settings determine function GIO074 I/O/Z V DD_VOUT GIO: GIO[074] PWM3B PWM3B HSYNC PD Video Encoder: Horizontal Sync I/O/Z GIO073 V DD_VOUT GIO: GIO[073] VSYNC PD Video Encoder: Vertical Sync I/O/Z GIO072 V DD_VOUT GIO: GIO[072] FIELD Video Encoder: Field identifier for interlaced display formats GIO070 GIO: GIO[070] I/O/Z V DD_VOUT Digital Video Out: PWM3C PWM3C Video Encoder: External clock input, used if clock rates MHz are needed, e.g. EXTCLK 74.25 MHz for HDTV digital output GIO069 PD I/O/Z GIO: GIO[069] V DD_VOUT Digital Video Out: PWM3D PWM3D VCLK Video Encoder: Video Output Clock I/O/Z V DD_VOUT GIO068 GIO: GIO[068] (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) (4) To reduce EMI and reflections, depending on the trace length, approximately Ω to Ω damping resistors are recommend on the following outputs placed near the DM355: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths should be minimized. Device Overview Submit Documentation Feedback

2.4.3 Asynchronous External Memory Interface (AEMIF) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-8. Analog Video Terminal Functions TERMINAL TYPE (1) OTHER (2) NO. Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not VREF A I/O/Z used, the VREF signal should be connected to V SS Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not IOUT A I/O/Z used, the IOUT signal should be connected to V SS Video DAC: External resistor (2550 Ohms to GND) connection for current bias IBIAS A I/O/Z configuration. When the DAC is not used, the IBIAS signal should be connected to V SS Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to VFB A I/O/Z TVOUT). When the DAC is not used, the VFB signal should be connected to V SS Video DAC: Analog Composite NTSC/PAL output (See Figure 5-31 and Figure 5-32 for TVOUT A I/O/Z V circuit connection). When the DAC is not used, the TVOUT signal should be left as a No Connect or connected to V SS Video DAC: Analog 1.8V power. When the DAC is not used, the V DDA18_DAC signal V DDA18_DAC PWR should be connected to V SS Video DAC: Analog 1.8V ground. When the DAC is not used, the V SSA_DAC signal V SSA_DAC GND should be connected to V SS (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (2) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND. Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. Async EMIF: Address bus bit[13] EM_A13/ PD GIO: GIO[67] GIO067/ V19 I/O/Z V DD System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used BTSEL[1] to drive boot status LED signal (active low) in ROM boot modes. EM_A12/ Async EMIF: Address bus bit[12] PD GIO066/ U19 I/O/Z GIO: GIO[66] V DD BTSEL[0] System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Async EMIF: Address bus bit[11] EM_A11/ PU GIO: GIO[65] GIO065/ R16 I/O/Z V DD AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets AECFG[3] default for PinMux2_EM_D15_8: AEMIF default bus width (16 or bits) Async EMIF: Address bus bit[10] EM_A10/ GIO: GIO[64] PU GIO064/ R18 I/O/Z AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1] V DD AECFG[2] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0, EM_A14, GIO[054], rsvd) Async EMIF: Address bus bit[09] EM_A09/ GIO: GIO[63] PD GIO063/ P17 I/O/Z AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1] V DD AECFG[1] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0, EM_A14, GIO[054], rsvd) Async EMIF: Address bus bit[08] GIO: GIO[62] EM_A08/ PU AECFG[0] sets default for: GIO062/ T19 I/O/Z V DD AECFG[0] PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND) PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND) EM_A07/ Async EMIF: Address bus bit[07] P16 I/O/Z V DD GIO061 GIO: GIO[61] (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. EM_A06/ Async EMIF: Address bus bit[06] P18 I/O/Z V DD GIO060 GIO: GIO[60] EM_A05/ Async EMIF: Address bus bit[05] R19 I/O/Z V DD GIO059 GIO: GIO[59] EM_A04/ Async EMIF: Address bus bit[04] P15 I/O/Z V DD GIO058 GIO: GIO[58] EM_A03/ Async EMIF: Address bus bit[03] N18 I/O/Z V DD GIO057 GIO: GIO[57] Async EMIF: Address bus bit[02] EM_A02/ N15 I/O/Z V DD NAND/SM/xD: CLE Command latch enable output Async EMIF: Address bus bit[01] EM_A01/ N17 I/O/Z V DD NAND/SM/xD: ALE Address latch enable output EM_A00/ Async EMIF: Address bus bit[00] M16 I/O/Z V DD GIO056 GIO: GIO[56] Async EMIF: Bank address signal 16-bit address: EM_BA1/ In 16-bit mode, lowest address bit. P19 I/O/Z V DD GIO055 In 8-bit mode, second lowest address bit. GIO: GIO[055] Async EMIF: Bank address signal 8-bit address: EM_BA0/ In 8-bit mode, lowest address bit. or can be used as an extra address line GIO054 N19 I/O/Z V DD (bit14) when using 16-bit memories. EM_A14 GIO: GIO[054] EM_D15/ Async EMIF: Data bus bit M18 I/O/Z V DD GIO053 GIO: GIO[053] EM_D14/ Async EMIF: Data bus bit M19 I/O/Z V DD GIO052 GIO: GIO[052] EM_D13/ Async EMIF: Data bus bit M15 I/O/Z V DD GIO051 GIO: GIO[051] EM_D12/ Async EMIF: Data bus bit L18 I/O/Z V DD GIO050 GIO: GIO[050] EM_D11/ Async EMIF: Data bus bit L17 I/O/Z V DD GIO049 GIO: GIO[049] EM_D10/ Async EMIF: Data bus bit L19 I/O/Z V DD GIO048 GIO: GIO[048] EM_D09/ Async EMIF: Data bus bit K18 I/O/Z V DD GIO047 GIO: GIO[047] EM_D08/ Async EMIF: Data bus bit L16 I/O/Z V DD GIO046 GIO: GIO[046] EM_D07/ Async EMIF: Data bus bit K19 I/O/Z V DD GIO045 GIO: GIO[045] EM_D06/ Async EMIF: Data bus bit K17 I/O/Z V DD GIO044 GIO: GIO[044] EM_D05/ Async EMIF: Data bus bit J19 I/O/Z V DD GIO043 GIO: GIO[043] EM_D04/ Async EMIF: Data bus bit L15 I/O/Z V DD GIO042 GIO: GIO[042] EM_D03/ Async EMIF: Data bus bit J18 I/O/Z V DD GIO041 GIO: GIO[041] EM_D02/ Async EMIF: Data bus bit H19 I/O/Z V DD GIO040 GIO: GIO[040] EM_D01/ Async EMIF: Data bus bit J17 I/O/Z V DD GIO039 GIO: GIO[039] EM_D00/ Async EMIF: Data bus bit H18 I/O/Z V DD GIO038 GIO: GIO[038] Device Overview Submit Documentation Feedback

2.4.4 DDR Memory Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. Async EMIF: Lowest numbered chip select. Can be programmed to be used for EM_CE0/ standard asynchronous memories (example: flash), OneNAND, or NAND J16 I/O/Z V DD GIO037 memory. Used for the default boot and ROM boot modes. GIO: GIO[037] Async EMIF: Second chip select. Can be programmed to be used for standard EM_CE1/ G19 I/O/Z V DD asynchronous memories(example: flash), OneNAND, or NAND memory. GIO036 GIO: GIO[036] Async EMIF: Write Enable EM_WE/ J15 I/O/Z V DD NAND/SM/xD: WE (Write Enable) output GIO035 GIO: GIO[035] Async EMIF: Output Enable EM_OE/ F19 I/O/Z V DD NAND/SM/xD: RE (Read Enable) output GIO034 GIO: GIO[034] Async EMIF: Async WAIT EM_WAIT/ G18 I/O/Z V DD NAND/SM/xD: RDY/ BSY input GIO033 GIO: GIO[033] EM_ADV/ OneNAND: Address valid detect for OneNAND interface H16 I/O/Z V DD GIO032 GIO: GIO[032] EM_CLK/ OneNAND: Clock for OneNAND flash interface E19 I/O/Z V DD GIO031 GIO: GIO[031] The DDR EMIF supports DDR2 and mobile DDR. Table 2-10. DDR Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. DDR_CLK I/O/Z V DD_DDR DDR Data Clock DDR_CLK I/O/Z V DD_DDR DDR Complementary Data Clock DDR_RAS I/O/Z V DD_DDR DDR Row Address Strobe DDR_CAS I/O/Z V DD_DDR DDR Column Address Strobe DDR_WE W10 I/O/Z V DD_DDR DDR Write Enable DDR_CS I/O/Z V DD_DDR DDR Chip Select DDR_CKE V10 I/O/Z V DD_DDR DDR Clock Enable DDR_DQM[1] U15 I/O/Z V DD_DDR Data mask outputs: DDR_DQM[1] For DDR_DQ[15:8] DDR_DQM[0] T12 I/O/Z V DD_DDR DDR_DQM[0] For DDR_DQ[7:0] DDR_DQS[1] V15 I/O/Z V DD_DDR Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading. DDR_DQS[0] V12 I/O/Z V DD_DDR DDR_DQS[1] For DDR_DQ[15:8] DDR_DQS[0] For DDR_DQ[7:0] DDR_BA[2] I/O/Z V DD_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[1] I/O/Z V DD_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[0] I/O/Z V DD_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_A13 I/O/Z V DD_DDR DDR Address Bus bit DDR_A12 I/O/Z V DD_DDR DDR Address Bus bit DDR_A11 I/O/Z V DD_DDR DDR Address Bus bit DDR_A10 I/O/Z V DD_DDR DDR Address Bus bit (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-10. DDR Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. DDR_A09 I/O/Z V DD_DDR DDR Address Bus bit DDR_A08 I/O/Z V DD_DDR DDR Address Bus bit DDR_A07 I/O/Z V DD_DDR DDR Address Bus bit DDR_A06 I/O/Z V DD_DDR DDR Address Bus bit DDR_A05 I/O/Z V DD_DDR DDR Address Bus bit DDR_A04 I/O/Z V DD_DDR DDR Address Bus bit DDR_A03 I/O/Z V DD_DDR DDR Address Bus bit DDR_A02 I/O/Z V DD_DDR DDR Address Bus bit DDR_A01 I/O/Z V DD_DDR DDR Address Bus bit DDR_A00 I/O/Z V DD_DDR DDR Address Bus bit DDR_DQ15 W17 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ14 V16 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ13 W16 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ12 U16 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ11 W15 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ10 W14 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ09 V14 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ08 U13 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ07 W13 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ06 V13 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ05 W12 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ04 U12 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ03 T11 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ02 U11 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ01 W11 I/O/Z V DD_DDR DDR Data Bus bit DDR_DQ00 V11 I/O/Z V DD_DDR DDR Data Bus bit DDR_ DDR: Loopback signal for external DQS gating. Route to DDR and back to W18 I/O/Z V DD_DDR DQGATE0 DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR_ DDR: Loopback signal for external DQS gating. Route to DDR and back to V17 I/O/Z V DD_DDR DQGATE1 DDR_DQGATE0 with same constraints as used for DDR clock and data. DDR: Voltage input for the SSTL_18 I/O buffers. Note even in the case of DDR_VREF U10 I/O/Z V DD_DDR mDDR an external resistor divider connected to this pin is necessary. V SSA_DLL R11 I/O/Z V SSA_DLL DDR: Ground for the DDR DLL V DDA33_DDRDL R10 I/O/Z V DDA33_DDRDLL DDR: Power (3.3 for the DDR DLL L DDR: Reference output for drive strength calibration of N and P channel DDR_ZN I/O/Z V DD_DDR outputs. Tie to ground via ohm resistor 0.5% tolerance. Device Overview Submit Documentation Feedback

2.4.5 GPIO TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are multiplexed with other functions. Table 2-11. GPIO Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. GIO:GIO[000] is sampled at reset and stored in the GIO0_RESET bit of the BOOTCFG register. GIO000 C16 I/O/Z V DD Active low during MMC/SD boot (can be used as MMC/SD power control). Can be used as external clock input for Timer GIO001 E14 I/O/Z V DD GIO: GIO[001] Can be used as external clock input for Timer GIO002 F15 I/O/Z V DD GIO: GIO[002] Can be used as external clock input for Timer GIO003 G15 I/O/Z V DD GIO: GIO[003] Can be used as external clock input for Timer GIO004 B17 I/O/Z V DD GIO: GIO[004] GIO005 D15 I/O/Z V DD GIO: GIO[005] GIO006 B18 I/O/Z V DD GIO: GIO[006] GIO007 GIO: GIO[007] SPI0_SDE C17 I/O/Z V DD SPI0: Chip Select NA[1] SPI1_SD SPI1: Data Out O E12 I/O/Z V DD GIO: GIO[008] GIO008 SPI1_SDI GIO009 A13 I/O/Z V DD SPI1: Data In -OR- SPI1: Chip Select GIO: GIO[009] SPI1_SDE NA[1] SPI1_SCL SPI1: Clock GIO: K C13 I/O/Z V DD GIO[010] GIO010 SPI1_SDE SPI1: Chip Select NA[0] E13 I/O/Z V DD GIO: GIO[011] GIO011 UART1_T UART1: Transmit Data XD R17 I/O/Z V DD GIO: GIO[012] GIO012 UART1_R UART1: Receive Data XD R15 I/O/Z V DD GIO: GIO[013] GIO013 I2C_SCL I2C: Serial Clock GIO: R14 I/O/Z V DD GIO014 GIO[014] I2C_SDA I2C: Serial Data R13 I/O/Z V DD GIO015 GIO: GIO[015] CLKOUT3 CLKOUT: Output Clock C11 I/O/Z V DD GIO016 GIO: GIO[016] CLKOUT2 CLKOUT: Output Clock A11 I/O/Z V DD GIO017 GIO: GIO[017] CLKOUT1 CLKOUT: Output Clock D12 I/O/Z V DD GIO018 GIO: GIO[018] MMCSD1 _DATA0 MMCSD1: DATA0 GIO019 A18 I/O/Z V DD GIO: GIO[019] UART2_T UART2: Transmit Data XD (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. MMCSD1 _DATA1 MMCSD1: DATA1 GIO020 B15 I/O/Z V DD GIO: GIO[020] UART2_R UART2: Receive Data XD MMCSD1 _DATA2 MMCSD1: DATA2 GIO021 A16 I/O/Z V DD GIO: GIO[021] UART2_C UART2: CTS TS MMCSD1 _DATA3 MMCSD1: DATA3 GIO022 B16 I/O/Z V DD GIO: GIO[022] UART2_R UART2: RTS TS MMCSD1 MMCSD1: Command _CMD A17 I/O/Z V DD GIO: GIO[023] GIO023 MMCSD1 MMCSD1: Clock _CLK C15 I/O/Z V DD GIO: GIO[024] GIO024 ASP0_FS ASP0: Receive Frame Synch R F16 I/O/Z V DD GIO: GIO[025] GIO025 ASP0_CL ASP0: Receive Clock KR F17 I/O/Z V DD GIO: GIO[026] GIO026 ASP0_DR ASP0: Receive Data E18 I/O/Z V DD GIO027 GIO: GIO[027] ASP0_FS ASP0: Transmit Frame Synch X G17 I/O/Z V DD GIO: GIO[028] GIO028 ASP0_CL ASP0: Transmit Clock KX F18 I/O/Z V DD GIO: GIO[029] GIO029 ASP0_DX ASP0: Transmit Data H15 I/O/Z V DD GIO030 GIO: GIO[030] EM_CLK E19 I/O/Z V DD OneNAND: Clock signal for OneNAND flash interface GIO: GIO[031] GIO031 EM_ADV PD OneNAND: Address Valid Detect for OneNAND interface H16 I/O/Z GIO032 V DD GIO: GIO[032] EM_WAIT PU Async EMIF: Async WAIT NAND/SM/xD: RDY/_BSY input G18 I/O/Z GIO033 V DD GIO: GIO[033] Async EMIF: Output Enable EM_OE F19 I/O/Z V DD NAND/SM/xD: RE (Read Enable) output GIO034 GIO: GIO[034] Async EMIF: Write Enable EM_WE J15 I/O/Z V DD NAND/SM/xD: WE (Write Enable) output GIO035 GIO: GIO[035] Async EMIF: Second Chip Select., Can be programmed to be used for standard EM_CE1 G19 I/O/Z V DD asynchronous memories (example: flash), OneNand or NAND memory. GIO036 GIO: GIO[036] Async EMIF: Lowest numbered Chip Select. Can be programmed to be used for EM_CE0 standard asynchronous memories (example: flash), OneNand or NAND memory. J16 I/O/Z V DD GIO037 Used for the default boot and ROM boot modes. GIO: GIO[037] EM_D00 Async EMIF: Data Bus bit[00] H18 I/O/Z V DD GIO038 GIO: GIO[038] Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. EM_D01 Async EMIF: Data Bus bit[01] J17 I/O/Z V DD GIO039 GIO: GIO[039] EM_D02 Async EMIF: Data Bus bit[02] H19 I/O/Z V DD GIO040 GIO: GIO[040] EM_D03 Async EMIF: Data Bus bit[03] J18 I/O/Z V DD GIO041 GIO: GIO[041] EM_D04 Async EMIF: Data Bus bit[04] L15 I/O/Z V DD GIO042 GIO: GIO[042] EM_D05 Async EMIF: Data Bus bit[05] J19 I/O/Z V DD GIO043 GIO: GIO[043] EM_D06 Async EMIF: Data Bus bit[06] K17 I/O/Z V DD GIO044 GIO: GIO[044] EM_D07 Async EMIF: Data Bus bit[07] K19 I/O/Z V DD GIO045 GIO: GIO[045] EM_D08 Async EMIF: Data Bus bit[08] L16 I/O/Z V DD GIO046 GIO: GIO[046] EM_D09 Async EMIF: Data Bus bit[09] K18 I/O/Z V DD GIO047 GIO: GIO[047] EM_D10 Async EMIF: Data Bus bit[10] L19 I/O/Z V DD GIO048 GIO: GIO[048] EM_D11 Async EMIF: Data Bus bit[11] L17 I/O/Z V DD GIO049 GIO: GIO[049] EM_D12 Async EMIF: Data Bus bit[12] L18 I/O/Z V DD GIO050 GIO: GIO[050] EM_D13 Async EMIF: Data Bus bit[13] M15 I/O/Z V DD GIO051 GIO: GIO[051] EM_D14 Async EMIF: Data Bus bit[14] M19 I/O/Z V DD GIO052 GIO: GIO[052] EM_D15 Async EMIF: Data Bus bit[15] M18 I/O/Z V DD GIO053 GIO: GIO[053] Async EMIF: Bank Address signal 8-bit address. In 8-bit mode, lowest EM_BA0 address bit. Or, can be used as an extra Address line (bit[14] when using 16-bit GIO054 N19 I/O/Z V DD memories. EM_A14 GIO: GIO[054] Async EMIF: Bank Address signal 16-bit address. In 16-bit mode, lowest EM_BA1 P19 I/O/Z V DD address bit. In 8-bit mode, second lowest address bit GIO055 GIO: GIO[055] Async EMIF: Address Bus bit[00] Note that the EM_A0 is always a 32-bit EM_A00 M16 I/O/Z V DD address GIO056 GIO: GIO[056] EM_A03 Async EMIF: Address Bus bit[03] N18 I/O/Z V DD GIO057 GIO: GIO[057] EM_A04 Async EMIF: Address Bus bit[04] P15 I/O/Z V DD GIO058 GIO: GIO[058] EM_A05 Async EMIF: Address Bus bit[05] R19 I/O/Z V DD GIO059 GIO: GIO[059] EM_A06 Async EMIF: Address Bus bit[06] P18 I/O/Z V DD GIO060 GIO: GIO[060] EM_A07 Async EMIF: Address Bus bit[07] P16 I/O/Z V DD GIO061 GIO: GIO[061] Used by ROM Bootloader to provide progress status via LED Async EMIF: Address Bus bit[08] EM_A08 PU GIO: GIO[062] AECFG[0] sets default for PinMux2.EM_A0_BA1: AEMIF GIO062 T19 I/O/Z V DD Address Width (OneNAND or NAND) PinMux2.EM_A13_3: AEMIF Address AECFG[0] Width (OneNAND or NAND) Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. Async EMIF: Address Bus bit[09] EM_A09 PD GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF GIO063 P17 I/O/Z V DD Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 AECFG[1] Definition (EM_BA0, EM_A14, GIO[054], rsvd) Async EMIF: Address Bus bit[10] EM_A10 PU GIO: GIO[064] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF GIO064 R18 I/O/Z V DD Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 AECFG[2] Definition (EM_BA0, EM_A14, GIO[054], rsvd) Async EMIF: Address Bus bit[11] EM_A11 PU GIO: GIO[065] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF GIO065 R16 I/O/Z V DD Configuration AECFG[3] sets default for PinMux2.EM_D15_8: AEMIF Default AECFG[3] Bus Width (16 or bits) EM_A12 Async EMIF: Address Bus bit[12] PD GIO066 U19 I/O/Z GIO: GIO[066] System: BTSEL[1:0] sampled at Power-on-Reset to determine V DD BTSEL[0] Boot method Async EMIF: Address Bus bit[13] EM_A13 PD GIO: GIO[067] System: BTSEL[1:0] sampled at Power-on-Reset to determine GIO067 V19 I/O/Z V DD Boot method Used to drive Boot Status LED signal (active low) in ROM boot BTSEL[1] modes VCLK Video Encoder: Video Output Clock I/O/Z V DD_VOUT GIO068 GIO: GIO[068] EXTCLK Video Encoder: External clock input, used if clock rates MHz are needed, GIO069 PD I/O/Z e.g. 74.25 MHz for HDTV digital output V DD_VOUT GIO: GIO[069] Digital Video Out: PWM3D PWM3D FIELD GIO070 Video Encoder: Field identifier for interlaced display formats I/O/Z V DD_VOUT GIO: GIO[070] Digital Video Out: PWM3C PWM3C VSYNC PD Video Encoder: Vertical Sync I/O/Z GIO072 V DD_VOUT GIO: GIO[072] HSYNC PD Video Encoder: Horizontal Sync I/O/Z GIO073 V DD_VOUT GIO: GIO[073] COUT0- Digital Video Out: VENC settings determine function GIO: GIO[074] I/O/Z V DD_VOUT GIO074 PWM3B PWM3B COUT1- Digital Video Out: VENC settings determine function GIO: GIO[075] I/O/Z V DD_VOUT GIO075 PWM3A PWM3A COUT2- Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D GIO076 I/O/Z V DD_VOUT RTO3 PWM2D RTO3 COUT3- Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C GIO077 I/O/Z V DD_VOUT RTO2 PWM2C RTO2 COUT4- Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B GIO078 I/O/Z V DD_VOUT RTO1 PWM2B RTO1 Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. COUT5- Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A GIO079 I/O/Z V DD_VOUT RTO0 PWM2A RTO0 COUT6- Digital Video Out: VENC settings determine function GIO: GIO[080] I/O/Z V DD_VOUT GIO080 PWM1 PWM1 COUT7- Digital Video Out: VENC settings determine function GIO: GIO[081] I/O/Z V DD_VOUT GIO081 PWM0 PWM0 PCLK PD I/O/Z Pixel clock input (strobe for lines CI7 through YI0) GIO: GIO[082] GIO082 V DD_VIN Write enable input signal is used by external device (AFE/TG) to gate the DDR CAM_WE output of the CCDC module. Alternately, the field identification input signal is PD N_FIELD I/O/Z used by external device (AFE/TG) to indicate the which of two frames is input to V DD_VIN GIO083 the CCDC module for sensors with interlaced output. CCDC handles or 2-field sensors in hardware. GIO: GIO[083] Vertical synchronization signal that can be either an input (slave mode) or an CAM_VD PD I/O/Z output (master mode). Tells the CCDC when a new frame starts. GIO084 V DD_VIN GIO: GIO[084] Horizontal synchronization signal that can be either an input (slave mode) or an CAM_HD PD I/O/Z output (master mode). Tells the CCDC when a new line starts. GIO085 V DD_VIN GIO: GIO[085] Standard CCD/CMOS input: raw[00] YCC 16-bit: time multiplexed between luma: YIN0 PD Y[00] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO086 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[00] GIO: GIO[086] Standard CCD/CMOS input: raw[01] YCC 16-bit: time multiplexed between luma: YIN1 PD Y[01] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO087 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[01] GIO: GIO[087] Standard CCD/CMOS input: raw[02] YCC 16-bit: time multiplexed between luma: YIN2 PD Y[02] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO088 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[02] GIO: GIO[088] Standard CCD/CMOS input: raw[03] YCC 16-bit: time multiplexed between luma: YIN3 PD Y[03] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO089 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[03] GIO: GIO[089] Standard CCD/CMOS input: raw[04] YCC 16-bit: time multiplexed between luma: YIN4 PD Y[04] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO090 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[04] GIO: GIO[090] Standard CCD/CMOS input: raw[05] YCC 16-bit: time multiplexed between luma: YIN5 PD Y[05] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO091 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[05] GIO: GIO[091] Standard CCD/CMOS input: raw[06] YCC 16-bit: time multiplexed between luma: YIN6 PD Y[06] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO092 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[06] GIO: GIO[092] Standard CCD/CMOS input: raw[07] YCC 16-bit: time multiplexed between luma: YIN7 PD Y[07] YCC 08-bit (which allows for simultaneous decoder inputs), it is time I/O/Z GIO093 V DD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[07] GIO: GIO[093] Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-11. GPIO Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. Standard CCD/CMOS input: raw[08] YCC 16-bit: time multiplexed between chroma: CB/CR[00] YCC 08-bit (which allows for simultaneous decoder CIN0 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. GIO094 V DD_VIN Y/CB/CR[00] GIO: GIO[094] Standard CCD/CMOS input: raw[09] YCC 16-bit: time multiplexed between chroma: CB/CR[01] YCC 08-bit (which allows for simultaneous decoder CIN1 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. GIO095 V DD_VIN Y/CB/CR[01] GIO: GIO[095] Standard CCD/CMOS input: raw[10] YCC 16-bit: time multiplexed between chroma: CB/CR[02] YCC 08-bit (which allows for simultaneous decoder CIN2 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. GIO096 V DD_VIN Y/CB/CR[02] GIO: GIO[096] Standard CCD/CMOS input: raw[11] YCC 16-bit: time multiplexed between chroma: CB/CR[03] YCC 08-bit (which allows for simultaneous decoder CIN3 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. GIO097 V DD_VIN Y/CB/CR[03] GIO: GIO[097] CIN4 Standard CCD/CMOS input: raw[12] YCC 16-bit: time multiplexed between GIO098 chroma: CB/CR[04] YCC 08-bit (which allows for simultaneous decoder SPI2_SDI PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. V DD_VIN Y/CB/CR[04] SPI: SPI2 Data In -OR- SPI2 Chip select SPI2_SDE GIO: GIO[098] NA[1] Standard CCD/CMOS input: raw[13] YCC 16-bit: time multiplexed between CIN5 chroma: CB/CR[05] YCC 08-bit (which allows for simultaneous decoder GIO099 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. SPI2_SDE V DD_VIN Y/CB/CR[05] SPI: SPI2 Chip Select NA[0] GIO: GIO[99] Standard CCD/CMOS input: NOT USED YCC 16-bit: time multiplexed between CIN6 chroma: CB/CR[06] YCC 08-bit (which allows for simultaneous decoder GIO100 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. SPI2_SD V DD_VIN Y/CB/CR[06] SPI: SPI2 Data Out O GIO: GIO[100] Standard CCD/CMOS input: NOT USED YCC 16-bit: time multiplexed between CIN7 chroma: CB/CR[07] YCC 08-bit (which allows for simultaneous decoder GIO101 PD I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel. SPI2_SCL V DD_VIN Y/CB/CR[07] SPI: SPI2 Clock K GIO: GIO[101] SPI0_SDI SPI0: Data In A12 I/O/Z V DD GIO102 GIO: GIO[102] SPI0_SDE SPI0: Chip Select NA[0] B12 I/O/Z V DD GIO: GIO[103] GIO103 Device Overview Submit Documentation Feedback

2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The DM355 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the MMC/SD and SDIO protocol. Table 2-12. MMC/SD Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. MMCSD0_ A15 I/O/Z V DD MMCSD0: Clock CLK MMCSD0_ C14 I/O/Z V DD MMCSD0: Command CMD MMCSD0_ B14 I/O/Z V DD MMCSD0: DATA0 DATA0 MMCSD0_ D14 I/O/Z V DD MMCSD0: DATA1 DATA1 MMCSD0_ B13 I/O/Z V DD MMCSD0: DATA2 DATA2 MMCSD0_ A14 I/O/Z V DD MMCSD0: DATA3 DATA3 MMCSD1_ MMCSD1: Clock CLK/ C15 I/O/Z V DD GIO: GIO[024] GIO024 MMCSD1_ MMCSD1: Command CMD/ A17 I/O/Z V DD GIO: GIO[023] GIO023 MMCSD1_ DATA0/ MMCSD1: DATA0 GIO019/ A18 I/O/Z V DD GIO: GIO[019] UART2_T UART2: Transmit data XD MMCSD1_ DATA1/ MMCSD1: DATA1 GIO020/ B15 I/O/Z V DD GIO: GIO[020] UART2_R UART2: Receive data XD MMCSD1_ DATA2/ MMCSD1: DATA2 GIO021/ A16 I/O/Z V DD GIO: GIO[021] UART2_C UART2: CTS TS MMCSD1_ DATA3/ MMCSD1: DATA3 GIO022/ B16 I/O/Z V DD GIO: GIO[022] UART2_R UART2: RTS TS (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

2.4.7 Universal Serial Bus (USB) Interface 2.4.8 Audio Interfaces TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-role Host/Slave support. However, no charge pump is included. Table 2-13. USB Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. USB (differential signal pair). USB_DP A I/O/Z V DDA33_USB When USB is not used, this signal should be connected to V SS_USB USB (differential signal pair). USB_DM A I/O/Z V DDA33_USB When USB is not used, this signal should be connected to V SS_USB USB reference current output Connect to V SS_USB_REF via 10K ohm resistor placed as close to the device USB_R1 A I/O/Z as possible. When USB is not used, this signal should be connected to V SS_USB USB operating mode identification pin For Device mode operation only, pull up this pin to V DD with a 1.5K ohm resistor. For Host mode operation only, pull down this pin to ground SS with a 1.5K ohm USB_ID A I/O/Z V DDA33_USB resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration. When USB is not used, this signal should be connected to V SS_USB For host or device mode operation, tie the VBUS/USB power signal to the USB connector. USB_VBUS A I/O/Z V DD When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector. When the USB is not used, tie VBUS to V SS_USB Digital output to control external V supply USB_DRVVBUS O/Z V DD When USB is not used, this signal should be left as a No Connect. USB Ground Reference V SS_USB_REF GND V DD Connect directly to ground and to USB_R1 via 10K ohm, resistor placed as close to the device as possible. Analog 3.3 V power USBPHY V DDA33_USB PWR V DD When USB is not used, this signal should be connected to V SS_USB Common mode 3.3 V power for USB PHY (PLL) V DDA33_USB_PLL PWR V DD When USB is not used, this signal should be connected to V SS_USB Analog 1.3 V power for USB PHY V DDA13_USB PWR V DD When USB is not used, this signal should be connected to V SS_USB Digital 1.3 V power for USB PHY V DDD13_USB PWR V DD When USB is not used, this signal should be connected to V SS_USB (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) The DM355 includes two Audio Serial Ports (ASP ports), which are backward compatible with other TI ASP serial ports and provide I2S audio interface. One interface is multiplexed with GIO signals. Table 2-14. ASP Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. ASP0_CL ASP0: Receive Clock KR/ F17 I/O/Z V DD GIO: GIO[026] GIO026 (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Device Overview Submit Documentation Feedback

2.4.9 UART Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-14. ASP Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. ASP0_CL ASP0: Transmit Clock KX F18 I/O/Z V DD GIO: GIO[029] GIO029 ASP0_DR ASP0: Receive DataF E18 I/O/Z V DD GIO: GIO[027] GIO027 ASP0_DX ASP0: Transmit Data H15 I/O/Z V DD GIO: GIO[030] GIO030 ASP0_FS ASP0: Receive Frame Synch R F16 I/O/Z V DD GIO: GIO[025] GIO025 ASP0_FS X G17 I/O/Z V DD ASP0: Transmit Frame SynchGIO: GIO[028] GIO028 ASP1_CL D18 I/O/Z V DD ASP1: Receive Clock KR ASP1_CL D17 I/Z V DD ASP1: Master Clock KS ASP1_CL D19 I/O/Z V DD ASP1: Transmit Clock KX ASP1_DR C19 I/O/Z V DD ASP1: Receive Data ASP1_DX C18 I/O/Z V DD ASP1: Transmit Data ASP1_FS E17 I/O/Z V DD ASP1: Receive Frame Synch R ASP1_FS E16 I/O/Z V DD ASP1: Transmit Frame Sync X The DM355 includes three UART ports. These ports are multiplexed with GIO and other signals. Table 2-15. UART Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. UART0_RXD U18 I V DD UART0: Receive data. Used for UART boot mode UART0_TXD T18 O V DD UART0: Transmit data. Used for UART boot mode UART1_RXD/ UART1: Receive data. R15 I/O/Z V DD GIO013 GIO: GIO013 UART1_TXD/ UART1: Transmit data. R17 I/O/Z V DD GIO012 GIO: GIO012 MMCSD1_DA MMCSD1: DATA2 TA2/ A16 I/O/Z V DD GIO: GIO021 GIO021/ UART2: CTS UART2_CTS MMCSD1_DA MMCSD1: DATA3 TA3/ B16 I/O/Z V DD GIO: GIO022 GIO022/ UART2: RTS UART2_RTS MMCSD1_DA MMCSD1: DATA1 TA1/ B15 I/O/Z V DD GIO: GIO020 GIO020/ UART2: RXD UART2_RXD (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

2.4.10 I C Interface 2.4.11 Serial Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-15. UART Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. MMCSD1_DA MMCSD1: DATA0 TA0/ A18 I/O/Z V DD GIO: GIO019 GIO019/ UART2: TXD UART2_TXD The DM355 includes an I C two-wire serial interface for control of external peripherals. This interface is multiplexed with GIO signals. Table 2-16. I C Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. I2C_SDA/ I2C: Serial data R13 I/O/Z V DD GIO015 GIO: GIO015 I2C_SCL/ I2C: Serial clock R14 I/O/Z V DD GIO014 GIO: GIO014 (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) The DM355 includes three independent serial ports. These interfaces are multiplexed with GIO and other signals. Table 2-17. SPI Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. SPI0_SCLK C12 I/O/Z V DD SPI0: Clock SPI0_SDENA[0]/ SPI0: Chip select B12 I/O/Z V DD GIO103 GIO: GIO[103] GIO007 GIO: GIO[007] C17 I/O/Z V DD SPI0_SDENA[1] SPI0: Chip select SPI0_SDI/ SPI0: Data in A12 I/O/Z V DD GIO102 GIO: GIO[102] SPI0_SDO B11 I/O/Z V DD SPI0: Data out SPI1_SCLK/ SPI1: Clock C13 I/O/Z V DD GIO010 GIO: GIO[010] SPI1: Chip select SPI1_SDENA[0]/ E13 I/O/Z V DD GIO: GIO[011] Active low during MMC/SD boot (can be used as GIO011 MMC/SD power control) SPI1_SDI/ SPI1: Data in or GIO009/ A13 I/O/Z V DD SPI1: Chip select SPI1_SDENA[1] GIO: GIO[09] SPI1_SDO/ SPI1: Data out E12 I/O/Z V DD GIO008 GIO: GIO[008] (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Device Overview Submit Documentation Feedback

2.4.12 Clock Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-17. SPI Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. Standard CCD/CMOS input: Not used YCC 16-bit: time multiplexed between chroma. CB/CR[07] CIN7/ YCC 8-bit (which allows for two simultaneous decoder inputs), it is PD GIO101/ I/O/Z time multiplexed between luma and chroma of the upper channel. V DD_VIN SPI2_SCLK Y/CB/CR[07] SPI: SPI2 clock GIO: GIO[101] Standard CCD/CMOS input: Raw[13] YCC 16-bit: time multiplexed between chroma. CB/CR[05] CIN5/ YCC 8-bit (which allows for two simultaneous decoder inputs), it is PD GIO099/ I/O/Z time multiplexed between luma and chroma of the upper channel. V DD_VIN SPI2_SDENA[0] Y/CB/CR[07] SPI: SPI2 chip select GIO: GIO[099] Standard CCD/CMOS input: Raw[12] YCC 16-bit: time multiplexed between chroma. CB/CR[04] CIN4/ YCC 8-bit (which allows for two simultaneous decoder inputs), it is GIO098/ PD I/O/Z time multiplexed between luma and chroma of the upper channel. SPI2_SDI/ V DD_VIN Y/CB/CR[04] SPI2_SDENA[1] SPI: SPI2 Data in -OR- SPI2 Chip select GIO: GIO[0998] Standard CCD/CMOS input: Not used YCC 16-bit: time multiplexed between chroma. CB/CR[06] CIN6/ YCC 8-bit (which allows for two simultaneous decoder inputs), it is PD GIO100/ I/O/Z time multiplexed between luma and chroma of the upper channel. V DD_VIN SPI2_SDO/ Y/CB/CR[06] SPI: SPI2 Data out GIO: GIO[100] The DM355 provides interface with the system clocks. Table 2-18. Clocks Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. CLKOUT1 CLKOUT: Output Clock D12 I/O/Z V DD GIO018 GIO: GIO[018] CLKOUT2 CLKOUT: Output Clock A11 I/O/Z V DD GIO017 GIO: GIO[017] CLKOUT3 CLKOUT: Output Clock C11 I/O/Z V DD GIO016 GIO: GIO[016] MXI1 I V DD Crystal input for system oscillator (24 MHz or MHz) Output for system oscillator (24 MHz or MHz). When the MX02 is not used, MXO1 O V DD the MX02 signal can be left open. Crystal input for video oscillator (27 MHz) Optional, use only if 27MHz derived from MXI1 and PLL does not provide sufficient performance for Video DAC. MXI2 I V DD When the MXI2 is not used and powered down, the MXI2 signal should be left as a No Connect Output for video oscillator (27 MHz) Optional, use only if 27MHz derived from MXI1 and PLL does not provide sufficient performance for Video DAC When the MXO2 O V DD MXO2 is not used and powered down, the MXO2 signal should be left as a No Connect. (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

2.4.13 Real Time Output (RTO) Interface 2.4.14 Pulse Width Modulator (PWM) Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 provides Real Time Output (RTO) interface. Table 2-19. RTO Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. COUT5- Digital Video Out: VENC settings determine function GIO: GIO[079] GIO079 I/O/Z V DD_VOUT PWM2A PWM2A RTO0 RTO0 COUT4- Digital Video Out: VENC settings determine function GIO: GIO[078] GIO078 I/O/Z V DD_VOUT PWM2B PWM2B RTO1 RTO1 COUT3- Digital Video Out: VENC settings determine function GIO: GIO[077] GIO077 I/O/Z V DD_VOUT PWM2C PWM2C RTO2 RTO2 COUT2- Digital Video Out: VENC settings determine function GIO: GIO[076] GIO076 I/O/Z V DD_VOUT PWM2D PWM2D RTO3 RTO3 (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) The DM355 provides Pulse Width Modulator (PWM) interface. Table 2-20. PWM Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. COUT7- Digital Video Out: VENC settings determine function GIO: GIO[081] I/O/Z V DD_VOUT GIO081 PWM0 PWM0 COUT6- Digital Video Out: VENC settings determine function GIO: GIO[080] I/O/Z V DD_VOUT GIO080 PWM1 PWM1 COUT5- Digital Video Out: VENC settings determine function GIO: GIO[079] GIO079 I/O/Z V DD_VOUT PWM2A PWM2A RTO0 RTO0 COUT4- Digital Video Out: VENC settings determine function GIO: GIO[078] GIO078 I/O/Z V DD_VOUT PWM2B PWM2B RTO1 RTO1 (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Device Overview Submit Documentation Feedback

2.4.15 System Configuration Interface TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-20. PWM Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. COUT3- Digital Video Out: VENC settings determine function GIO: GIO[077] GIO077 I/O/Z V DD_VOUT PWM2C PWM2C RTO2 RTO2 COUT2- Digital Video Out: VENC settings determine function GIO: GIO[076] GIO076 I/O/Z V DD_VOUT PWM2D PWM2D RTO3 RTO3 COUT1- Digital Video Out: VENC settings determine function GIO: GIO[075] I/O/Z V DD_VOUT GIO075 PWM3A PWM3A COUT0- Digital Video Out: VENC settings determine function GIO: GIO[074] I/O/Z V DD_VOUT GIO074 PWM3B PWM3B FIELD Video Encoder: Field identifier for interlaced display formats GIO: GIO[070] GIO070 I/O/Z V DD_VOUT Digital Video Out: PWM3C PWM3C EXTCLK Video Encoder: External clock input, used if clock rates MHz are needed, GIO069 PD I/O/Z e.g. 74.25 MHz for HDTV digital output GIO: GIO[069] Digital Video Out: V DD_VOUT PWM3D PWM3D The DM355 provides interfaces for system configuration and boot load. Table 2-21. System/Boot Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. Async EMIF: Address bus bit EM_A13/ PD GIO: GIO[067] GIO067/ V19 I/O/Z V DD System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used BTSEL[1] to drive boot status LED signal (active low) in ROM boot modes. EM_A12/ Async EMIF: Address bus bit PD GIO066/ U19 I/O/Z GIO: GIO[066] V DD BTSEL[0] System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Async EMIF: Address bus bit EM_A11/ GIO: GIO[065] PU GIO065/ R16 I/O/Z System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration. V DD AECFG[3] AECFG[3] sets default fo PinMux2.EM_D15_8. AEMIF default bus width (16 or bits). Async EMIF: Address bus bit EM_A10/ GIO: GIO[064] PU GIO064/ R18 I/O/Z System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration. V DD AECFG[2] AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition: (EM,_BA0, EM_A14, GIO[054], rsvd) Async EMIF: Address bus bit EM_A09/ GIO: GIO[063] PD GIO063/ P17 I/O/Z System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration. V DD AECFG[1] AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition: (EM,_BA0, EM_A14, GIO[054], rsvd) (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Submit Documentation Feedback Device Overview

2.4.16 Emulation TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-21. System/Boot Terminal Functions (continued) TERMINAL TYPE (1) OTHER (2) (3) NO. Async EMIF: Address bus bit GIO: GIO[062] EM_A08/ PU System: AECFG[0] sets default for: GIO062/ T19 I/O/Z V DD AECFG[0] PinMux2.EM_A0_BA1 AEMIF address width (OneNAND, or NAND) PinMux2.EM_A13_3 AEMIF address width (OneNAND, or NAND) The emulation interface allow software and hardware debugging. Table 2-22. Emulation Terminal Functions TERMINAL TYPE (1) OTHER (2) (3) NO. TCK E10 I V DD JTAG test clock input PU TDI I JTAG test data input V DD TDO O V DD JTAG test data output PU TMS I JTAG test mode select V DD PD TRST I JTAG test logic reset (active low) V DD RTCK E11 O V DD JTAG test clock output JTAG emulation I/O PU EMU0 I/O/Z EMU[1:0] Force Debug Scan chain (ARM and ARM ETB TAPs connected) V DD EMU[1:0] Normal Scan chain (ICEpick only) JTAG emulation I/O PU EMU1 I/O/Z EMU[1:0] Force Debug Scan chain (ARM and ARM ETB TAPs connected) V DD EMU[1:0] Normal Scan chain (ICEpick only) (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) Device Overview Submit Documentation Feedback

2.5 Pin List TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23 provides a complete pin order. Table 2-23. DM355 Pin Descriptions Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State CIN7 GIO101 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: NOT USED PINMUX0[1:0].CIN_ SPI2_SCLK GIO YCC 16-bit: time multiplexed between SPI2 chroma: CB/CR[07] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[07] SPI: SPI2 Clock GIO: GIO[101] CIN6 GIO100 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: NOT USED PINMUX0[3:2].CIN_ SPI2_SDO GIO YCC 16-bit: time multiplexed between SPI2 chroma: CB/CR[06] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[06] SPI: SPI2 Data Out GIO: GIO[100] CIN5 GIO099 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[13] PINMUX0[5:4].CIN_ SPI2_SDENA[0] GIO SPI2 YCC 16-bit: time multiplexed between chroma: CB/CR[05] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[05] SPI: SPI2 Chip Select GIO: GIO[99] CIN4 GIO098 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[12] PINMUX0[7:6].CIN_ SPI2_SDI GIO SPI2_SDENA[1] SPI2 SPI2 YCC 16-bit: time multiplexed between chroma: CB/CR[04] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[04] SPI: SPI2 Data In -OR- SPI2 Chip select GIO: GIO[098] (1) I Input, O Output, Z High impedance, S Supply voltage, GND Ground, A Analog signal. (2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 Power Supplies for more detail. (3) PD pull-down, PU pull-up. (To pull up a signal to the opposite supply rail, a k Ω resistor should be used.) (4) To reduce EMI and reflections, depending on the trace length, approximately Ω to Ω damping resistors are recommend on the following outputs placed near the DM355: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths should be minimized. Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State CIN3 GIO097 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[11] PINMUX0[8].CIN_32 GIO YCC 16-bit: time multiplexed between chroma: CB/CR[03] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[03] GIO: GIO[097] CIN2 GIO096 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[10] PINMUX0[8].CIN_32 GIO YCC 16-bit: time multiplexed between chroma: CB/CR[02] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[02] GIO: GIO[096] CIN1 GIO095 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[09] PINMUX0[9].CIN_10 GIO YCC 16-bit: time multiplexed between chroma: CB/CR[01] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[01] GIO: GIO[095] CIN0 GIO094 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[08] PINMUX0[9].CIN_10 GIO YCC 16-bit: time multiplexed between chroma: CB/CR[00] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the upper channel. Y/CB/CR[00] GIO: GIO[094] YIN7 GIO093 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[07] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[07] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[07] GIO: GIO[093] YIN6 GIO092 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[06] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[06] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[06] GIO: GIO[092] Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State YIN5 GIO091 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[05] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[05] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[05] GIO: GIO[091] YIN4 GIO090 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[04] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[04] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[04] GIO: GIO[090] YIN3 GIO089 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[03] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[03] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[03] GIO: GIO[089] YIN2 GIO088 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[02] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[02] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[02] GIO: GIO[088] YIN1 GIO087 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[01] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[01] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[01] GIO: GIO[087] YIN0 GIO086 I/O CCDC V DD_VIN PD in Standard CCD/CMOS input: raw[00] PINMUX0[10].YIN_7 GIO YCC 16-bit: time multiplexed between luma: Y[00] YCC 08-bit (which allows for simultaneous decoder inputs), it is time multiplexed between luma and chroma of the lower channel. Y/CB/CR[00] GIO: GIO[086] Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State CAM_HD I/O CCDC V DD_VIN PD in Horizontal synchronization signal that can be PINMUX0[11].CAM_ GIO085 GIO either an input (slave mode) or an output HD (master mode). Tells the CCDC when a new line starts. GIO: GIO[085] CAM_VD I/O CCDC V DD_VIN PD in Vertical synchronization signal that can be PINMUX0[12].CAM_ GIO084 GIO either an input (slave mode) or an output VD (master mode). Tells the CCDC when a new frame starts. GIO: GIO[084] CAM_WEN_FIE I/O CCDC V DD_VIN PD in Write enable input signal is used by external PINMUX0[13].CAM_ LD GIO083 GIO device (AFE/TG) to gate the DDR output of WEN the CCDC module. Alternately, the field identification input plus signal is used by external device (AFE/TG) to indicate the which of two frames is input to the CCDC module for sensors with interlaced output. CCDC handles or 2-field sensors in hardware. GIO: GIO[083] CCDC.MODE[7].CC DMD CCDC.MODE[5].SW EN PCLK GIO082 I/O CCDC V DD_VIN PD in Pixel clock input (strobe for lines CI7 through PINMUX0[14].PCLK GIO YI0) GIO: GIO[082] YOUT7-R7 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT6-R6 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT5-R5 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT4-R4 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT3-R3 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT2-G7 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT1-G6 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) YOUT0-G5 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine function (4) COUT7-G4 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[1:0].COU GIO081 PWM0 GIO function T_7 PWM0 GIO: GIO[081] PWM0 COUT6-G3 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[3:2].COU GIO080 PWM1 GIO function T_6 PWM1 GIO: GIO[080] PWM1 (4) Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State COUT5-G2 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[5:4].COU GIO079 GIO function T_5 PWM2A RTO0 PWM2 RTO GIO: GIO[079] PWM2A RTO0 (4) COUT4-B7 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[7:6].COU GIO078 GIO function T_4 PWM2B RTO1 PWM2 RTO GIO: GIO[078] PWM2B RTO1 (4) COUT3-B6 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[9:8].COU GIO077 GIO function T_3 PWM2C RTO2 PWM2 RTO GIO: GIO[077] PWM2C RTO2 (4) COUT2-B5 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[11:10].CO GIO076 GIO function UT_2 PWM2D RTO3 PWM2 RTO GIO: GIO[076] PWM2D RTO3 (4) COUT1-B4 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[13:12].CO GIO075 GIO function UT_1 PWM3A PWM3 GIO: GIO[075] PWM3A (4) COUT0-B3 I/O VENC V DD_VOUT in Digital Video Out: VENC settings determine PINMUX1[15:14].CO GIO074 GIO function UT_0 PWM3B PWM3 GIO: GIO[074] PWM3B (4) HSYNC I/O VENC V DD_VOUT PD in Video Encoder: Horizontal Sync PINMUX1[16].HVSY GIO073 GIO NC GIO: GIO[073] (4) VSYNC I/O VENC V DD_VOUT PD in Video Encoder: Vertical Sync PINMUX1[16].HVSY GIO072 GIO NC GIO: GIO[072] (4) LCD_OE I/O VENC V DD_VOUT in Video Encoder: LCD Output Enable or PINMUX1[17].DLCD GIO071 GIO BRIGHT signal GIO: GIO[071] (4) Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State FIELD GIO070 I/O VENC V DD_VOUT in Video Encoder: Field identifier for interlaced PINMUX1[19:18].FI PWM3C GIO display formats ELD VENC PWM3 GIO: GIO[070] Digital Video Out: PWM3C (4) EXTCLK I/O VENC V DD_VOUT PD in Video Encoder: External clock input, used if PINMUX1[21:20].EX GIO069 GIO clock rates MHz are needed, e.g. 74.25 TCLK PWM3D VENC MHz for HDTV digital output PWM3 GIO: GIO[069] Digital Video Out: PWM3D (4) VCLK GIO068 I/O VENC V DD_VOUT out L Video Encoder: Video Output Clock PINMUX1[22].VCLK GIO GIO: GIO[068] (4) VREF A I/O Video Video DAC: Reference voltage output DAC (0.45V, 0.1uF to GND) IOUT A I/O Video Video DAC: Pre video buffer DAC output DAC (1000 ohm to VFB) IBIAS A I/O Video Video DAC: External resistor (2550 Ohms to DAC GND) connection for current bias configuration VFB A I/O Video Video DAC: Pre video buffer DAC output DAC (1000 ohm to IOUT, 1070 ohm to TVOUT) TVOUT A I/O Video V DDA18_DAC Video DAC: Analog Composite NTSC/PAL DAC output (See Figure 5-31 and Figure 5-32 for circuit connection) V DDA18V_DAC PWR Video Video DAC: Analog 1.8V power DAC V SSA_DAC GND Video Video DAC: Analog 1.8V ground DAC DDR_CLK I/O DDR V DD_DDR out L DDR Data Clock DDR_CLK I/O DDR V DD_DDR out H DDR Complementary Data Clock DDR_RAS I/O DDR V DD_DDR out H DDR Row Address Strobe DDR_CAS I/O DDR V DD_DDR out H DDR Column Address Strobe DDR_WE W10 I/O DDR V DD_DDR out H DDR Write Enable (active low) DDR_CS I/O DDR V DD_DDR out H DDR Chip Select (active low) DDR_CKE V10 I/O DDR V DD_DDR out L DDR Clock Enable DDR_DQM[1] U15 I/O DDR V DD_DDR out L Data mask outputs: DDR_DQM1: For DDR_DQ[15:8] DDR_DQM[0] T12 I/O DDR V DD_DDR out L Data mask outputs: DDR_DQM0: For DDR_DQ[7:0] DDR_DQS[1] V15 I/O DDR V DD_DDR in Data strobe input/outputs for each byte of the bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading. DDR_DQS1: For DDR_DQ[15:8] Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State DDR_DQS[0] V12 I/O DDR V DD_DDR in Data strobe input/outputs for each byte of the bit data bus used to synchronize the data transfers. Output to DDR when writing and inputs when reading. DDR_DQS0: For DDR_DQ[7:0] DDR_BA[2] I/O DDR V DD_DDR out L Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[1] I/O DDR V DD_DDR out L Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[0] I/O DDR V DD_DDR out L Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_A13 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A12 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A11 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A10 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A09 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A08 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A07 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A06 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A05 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A04 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A03 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A02 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A01 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_A00 I/O DDR V DD_DDR out L DDR Address Bus bit DDR_DQ15 W17 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ14 V16 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ13 W16 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ12 U16 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ11 W15 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ10 W14 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ09 V14 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ08 U13 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ07 W13 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ06 V13 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ05 W12 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ04 U12 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ03 T11 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ02 U11 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ01 W11 I/O DDR V DD_DDR in DDR Data Bus bit DDR_DQ00 V11 I/O DDR V DD_DDR in DDR Data Bus bit DDR_ W18 I/O DDR V DD_DDR DDR: Loopback signal for external DQS DQGATE0 gating. Route to DDR and back to DDR_DQGATE1 with same constraints as used for DDR clock and data. DDR_ V17 I/O DDR V DD_DDR DDR: Loopback signal for external DQS DQGATE1 gating. Route to DDR and back to DDR_DQGATE0 with same constraints as used for DDR clock and data. Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State DDR_VREF U10 PWR DDRI V DD_DDR DDR: Voltage input for the SSTL_18 IO O buffers V SSA_DLL R11 GND DDRD V SSA_DLL DDR: Ground for the DDR DLL LL V DDA33_DDRDLL R10 PWR DDRD V DDA33_DDR DDR: Power (3.3 Volts) for the DDR DLL LL DLL DDR_ZN I/O DDRI V DD_DDR DDR: Reference output for drive strength O calibration of N and P channel outputs. Tie to ground via ohm resistor 0.5% tolerance. EM_A13 V19 I/O AEMI V DD PD in L Async EMIF: Address Bus bit[13] PINMUX2[0].EM_A1 GIO067 F 3_3, BTSEL[1] GIO syste m GIO: GIO[067] default set by AECFG[0] System: BTSEL[1:0] sampled at Power-on-Reset to determine Boot method (00:NAND, 01:Flash, 10:MMC/SD, 11:UART EM_A12 U19 I/O AEMI V DD PD in L Async EMIF: Address Bus bit[12] PINMUX2[0].EM_A1 GIO066 F 3_3, BTSEL[0] GIO syste m GIO: GIO[066] default set by AECFG[0] System: BTSEL[1:0] sampled at Power-on-Reset to determine Boot method (00:NAND, 01:Flash, 10:MMC/SD, 11:UART) EM_A11 R16 I/O AEMI V DD PU in H Async EMIF: Address Bus bit[11] PINMUX2[0].EM_A1 GIO065 F 3_3, AECFG[3] GIO syste m GIO: GIO[065] default set by AECFG[0] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF Configuration AECFG[3] sets default for PinMux2.EM_D15_8: AEMIF Default Bus Width (0:16 or 1:8 bits) EM_A10 R18 I/O AEMI V DD PU in H Async EMIF: Address Bus bit[10] PINMUX2[0].EM_A1 GIO064 F 3_3, AECFG[2] GIO syste m GIO: GIO[064] default set by AECFG[0] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 Definition (00: EM_BA0, 01: EM_A14, 10:GIO[054], 11:rsvd) Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State EM_A09 P17 I/O AEMI V DD PD in L Async EMIF: Address Bus bit[09] PINMUX2[0].EM_A1 GIO063 F 3_3, AECFG[1] GIO syste m GIO: GIO[063] default set by AECFG[0] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0 Definition (00: EM_BA0, 01: EM_A14, 10:GIO[054], 11:rsvd) EM_A08 T19 I/O AEMI V DD PU in H Async EMIF: Address Bus bit[08] PINMUX2[0].EM_A1 GIO062 F 3_3, AECFG[0] GIO syste m GIO: GIO[062] default set by AECFG[0] AECFG[0] sets default for PinMux2.EM_A0_BA1: AEMIF Address Width (OneNAND or NAND) PinMux2.EM_A13_3: AEMIF Address Width (OneNAND or NAND) (0:AEMIF address bits, 1:GIO[67:57]) EM_A07 P16 I/O AEMI V DD out L Async EMIF: Address Bus bit[07] PINMUX2[0].EM_A1 GIO061 F 3_3, GIO GIO: GIO[061] Used by ROM Bootloader to default set by provide progress status via LED (active low) AECFG[0] EM_A06 P18 I/O AEMI V DD out L Async EMIF: Address Bus bit[06] PINMUX2[0].EM_A1 GIO060 F 3_3, GIO GIO: GIO[060] default set by AECFG[0] EM_A05 R19 I/O AEMI V DD out L Async EMIF: Address Bus bit[05] PINMUX2[0].EM_A1 GIO059 F 3_3, GIO GIO: GIO[059] default set by AECFG[0] EM_A04 P15 I/O AEMI V DD out L Async EMIF: Address Bus bit[04] PINMUX2[0].EM_A1 GIO058 F 3_3, GIO GIO: GIO[058] default set by AECFG[0] EM_A03 N18 I/O AEMI V DD out L Async EMIF: Address Bus bit[03] PINMUX2[0].EM_A1 GIO057 F 3_3, GIO GIO: GIO[057] default set by AECFG[0] EM_A02 N15 I/O AEMI V DD out L Async EMIF: Address Bus bit[02] F NAND/SM/xD: CLE Command Latch Enable output Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State EM_A01 N17 I/O AEMI V DD out L Async EMIF: Address Bus bit[01] F NAND/SM/xD: ALE Address Latch Enable output EM_A00 M16 I/O AEMI V DD out L Async EMIF: Address Bus bit[00] Note that PINMUX2[1].EM_A0 GIO056 F the EM_A0 is always a 32-bit address _BA1, GIO GIO: GIO[056] default set by AECFG[0] EM_BA1 P19 I/O AEMI V DD out H Async EMIF: Bank Address signal 16-bit PINMUX2[1].EM_A0 GIO055 F address. _BA1, GIO In 16-bit mode, lowest address bit. default set by AECFG[0] In 8-bit mode, second lowest address bit GIO: GIO[055] EM_BA0 N19 I/O AEMI V DD out H Async EMIF: Bank Address signal 8-bit PINMUX2[3:2].EM_ GIO054 F address. BA0, EM_A14 GIO In 8-bit mode, lowest address bit. default set by AECFG[2:1] Or, can be used as an extra Address line (bit[14] when using 16-bit memories. GIO: GIO[054] EM_D15 M18 I/O AEMI V DD in Async EMIF: Data Bus bit[15] PINMUX2[4].EM_D1 GIO053 F 5_8, GIO GIO: GIO[053] default set by AECFG[3] EM_D14 M19 I/O AEMI V DD in Async EMIF: Data Bus bit[14] PINMUX2[4].EM_D1 GIO052 F 5_8, GIO GIO: GIO[052] default set by AECFG[3] EM_D13 M15 I/O AEMI V DD in Async EMIF: Data Bus bit[13] PINMUX2[4].EM_D1 GIO051 F 5_8, GIO GIO: GIO[051] default set by AECFG[3] EM_D12 L18 I/O AEMI V DD in Async EMIF: Data Bus bit[12] PINMUX2[4].EM_D1 GIO050 F 5_8, GIO GIO: GIO[050] default set by AECFG[3] EM_D11 L17 I/O AEMI V DD in Async EMIF: Data Bus bit[11] PINMUX2[4].EM_D1 GIO049 F 5_8, GIO GIO: GIO[049] default set by AECFG[3] EM_D10 L19 I/O AEMI V DD in Async EMIF: Data Bus bit[10] PINMUX2[4].EM_D1 GIO048 F 5_8, GIO GIO: GIO[048] default set by AECFG[3] Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State EM_D09 K18 I/O AEMI V DD in Async EMIF: Data Bus bit[09] PINMUX2[4].EM_D1 GIO047 F 5_8, GIO GIO: GIO[047] default set by AECFG[3] EM_D08 L16 I/O AEMI V DD in Async EMIF: Data Bus bit[08] PINMUX2[4].EM_D1 GIO046 F 5_8, GIO GIO: GIO[046] default set by AECFG[3] EM_D07 K19 I/O AEMI V DD in Async EMIF: Data Bus bit[07] PINMUX2[5].EM_D7 GIO045 F GIO GIO: GIO[045] EM_D06 K17 I/O AEMI V DD in Async EMIF: Data Bus bit[06] PINMUX2[5].EM_D7 GIO044 F GIO GIO: GIO[044] EM_D05 J19 I/O AEMI V DD in Async EMIF: Data Bus bit[05] PINMUX2[5].EM_D7 GIO043 F GIO GIO: GIO[043] EM_D04 L15 I/O AEMI V DD in Async EMIF: Data Bus bit[04] PINMUX2[5].EM_D7 GIO042 F GIO GIO: GIO[042] EM_D03 J18 I/O AEMI V DD in Async EMIF: Data Bus bit[03] PINMUX2[5].EM_D7 GIO041 F GIO GIO: GIO[041] EM_D02 H19 I/O AEMI V DD in Async EMIF: Data Bus bit[02] PINMUX2[5].EM_D7 GIO040 F GIO GIO: GIO[040] EM_D01 J17 I/O AEMI V DD in Async EMIF: Data Bus bit[01] PINMUX2[5].EM_D7 GIO039 F GIO GIO: GIO[039] EM_D00 H18 I/O AEMI V DD in Async EMIF: Data Bus bit[00] PINMUX2[5].EM_D7 GIO038 F GIO GIO: GIO[038] EM_CE0 J16 I/O AEMI V DD out H Async EMIF: Lowest numbered Chip Select. PINMUX2[6].EM_CE GIO037 F Can be programmed to be used for standard GIO asynchronous memories (example:flash), OneNand or NAND memory. Used for the default boot and ROM boot modes. GIO: GIO[037] EM_CE1 G19 I/O AEMI V DD out H Async EMIF: Second Chip Select., Can be PINMUX2[7].EM_CE GIO036 F programmed to be used for standard GIO asynchronous memories (example: flash), OneNand or NAND memory. GIO: GIO[036] Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State EM_WE J15 I/O AEMI V DD out H Async EMIF: Write Enable PINMUX2[8].EM_W GIO035 F E_OE GIO NAND/SM/xD: WE (Write Enable) output GIO: GIO[035] EM_OE F19 I/O AEMI V DD out H Async EMIF: Output Enable PINMUX2[8].EM_W GIO034 F E_OE GIO NAND/SM/xD: RE (Read Enable) output GIO: GIO[034] EM_WAIT G18 I/O AEMI V DD PU in H Async EMIF: Async WAIT PINMUX2[9].EM_W GIO033 F AIT GIO NAND/SM/xD: RDY/_BSY input GIO: GIO[033] EM_ADV H16 I/O AEMI V DD PD in L OneNAND: Address Valid Detect for PINMUX2[10].EM_A GIO032 F OneNAND interface DV GIO GIO: GIO[032] EM_CLK E19 I/O AEMI V DD out L OneNAND: Clock signal for OneNAND flash PINMUX2[11].EM_C GIO031 F interface LK GIO GIO: GIO[031] ASP0_DX H15 I/O ASP0 V DD in ASP0: Transmit Data PINMUX3[0].GIO30 GIO030 GIO GIO: GIO[030] ASP0_CLKX F18 I/O ASP0 V DD in ASP0: Transmit Clock PINMUX3[1].GIO29 GIO029 GIO GIO: GIO[029] ASP0_FSX G17 I/O ASP0 V DD in ASP0: Transmit Frame Synch PINMUX3[2].GIO28 GIO028 GIO GIO: GIO[028] ASP0_DR E18 I/O ASP0 V DD in ASP0: Receive Data PINMUX3[3].GIO27 GIO027 GIO GIO: GIO[027] ASP0_CLKR F17 I/O ASP0 V DD in ASP0: Receive Clock PINMUX3[4].GIO26 GIO026 GIO GIO: GIO[026] ASP0_FSR F16 I/O ASP0 V DD in ASP0: Receive Frame Synch PINMUX3[5].GIO25 GIO025 GIO GIO: GIO[025] MMCSD1_CLK C15 I/O MMC V DD in MMCSD1: Clock PINMUX3[6].GIO24 GIO024 SD GIO GIO: GIO[024] MMCSD1_CMD A17 I/O MMC V DD in MMCSD1: Command PINMUX3[7].GIO23 GIO023 SD GIO GIO: GIO[023] Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State MMCSD1_DAT B16 I/O MMC V DD in MMCSD1: DATA3 PINMUX3[9:8].GIO2 GIO022 SD UART2_RTS GIO UART GIO: GIO[022] UART2: RTS MMCSD1_DAT A16 I/O MMC V DD in MMCSD1: DATA2 PINMUX3[11:10].GI GIO021 SD O21 UART2_CTS GIO UART GIO: GIO[021] UART2: CTS MMCSD1_DAT B15 I/O MMC V DD in MMCSD1: DATA1 PINMUX3[13:12].GI GIO020 SD O20 UART2_RXD GIO UART GIO: GIO[020] UART2: Receive Data MMCSD1_DAT A18 I/O MMC V DD in MMCSD1: DATA0 PINMUX3[15:14].GI GIO019 SD O19 UART2_TXD GIO UART GIO: GIO[019] UART2: Transmit Data CLKOUT1 D12 I/O Clocks V DD in CLKOUT: Output Clock PINMUX3[16].GIO1 GIO018 GIO GIO: GIO[018] CLKOUT2 A11 I/O Clocks V DD in CLKOUT: Output Clock PINMUX3[17].GIO1 GIO017 GIO GIO: GIO[017] CLKOUT3 C11 I/O Clocks V DD in CLKOUT: Output Clock PINMUX3[18].GIO1 GIO016 GIO GIO: GIO[016] I2C_SDA R13 I/O I2C V DD in I2C: Serial Data PINMUX3[19].GIO1 GIO015 GIO GIO: GIO[015] I2C_SCL R14 I/O I2C V DD in I2C: Serial Clock PINMUX3[20].GIO1 GIO014 GIO GIO: GIO[014] UART1_RXD R15 I/O UART V DD in UART1: Receive Data PINMUX3[21].GIO1 GIO013 GIO GIO: GIO[013] UART1_TXD R17 I/O UART V DD in UART1: Transmit Data PINMUX3[22].GIO1 GIO012 GIO GIO: GIO[012] SPI1_SDENA[0] E13 I/O SPI1 V DD in SPI1: Chip Select PINMUX3[23].GIO1 GIO011 GIO GIO: GIO[011] Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State SPI1_SCLK C13 I/O SPI1 V DD in SPI1: Clock PINMUX3[24].GIO1 GIO010 GIO GIO: GIO[010] SPI1_SDI A13 I/O SPI1 V DD in SPI1: Data In -OR- SPI1: Chip Select PINMUX3[26:25].GI GIO009 GIO SPI1_SDENA[1] SPI1 GIO: GIO[009] SPI1_SDO E12 I/O SPI1 V DD in SPI1: Data Out PINMUX3[27].GIO8 GIO008 GIO GIO: GIO[008] GIO007 C17 I/O GIO V DD in GIO: GIO[007] PINMUX3[28].GIO7 SPI0_SDENA[1] debou nce SPI0 SPI0: Chip Select GIO006 B18 I/O GIO V DD in GIO: GIO[006] debou nce GIO005 D15 I/O GIO V DD in GIO: GIO[005] debou nce GIO004 B17 I/O GIO V DD in GIO: GIO[004] debou nce GIO003 G15 I/O GIO V DD in GIO: GIO[003] debou nce GIO002 F15 I/O GIO V DD in GIO: GIO[002] debou nce GIO001 E14 I/O GIO V DD in GIO: GIO[001] debou nce GIO000 C16 I/O GIO V DD in GIO: GIO[000] debou nce USB_DP A I/O USBP V DDA33_USB USB (differential signal pair) HY USB_DM A I/O USBP V DDA33_USB USB (differential signal pair) HY USB_R1 A I/O USBP USB Reference current output HY Connect to V SS_USB_REF via 10K Ω resistor placed as close to the device as possible. USB_ID A I/O USBP V DDA33_USB USB operating mode identification pin HY For Device mode operation only, pull up this pin to V DD with a 1.5K ohm resistor. For Host mode operation only, pull down this pin to ground SS with a 1.5K ohm resistor. If using an OTG or mini-USB connector, this pin will be set properly via the cable/connector configuration. Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State USB_VBUS A I/O USBP For host or device mode operation, tie the HY VBUS/USB power signal to the USB connector. When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector. When the USB is not used, tie VBUS to V SS_USB USB_DRVVBU O USBP V DD Digital output to control external V supply S HY V SS_USB_REF GND USBP V DD USB Ground Reference HY Connect directly to ground and to USB_R1 via 10K Ω resistor placed as close to the device as possible. V DDA33_USB PWR USBP V DD Analog 3.3 V power USB PHY (Transceiver) HY V SS_USB GND USBP V DD Analog 3.3 V ground for USB PHY HY (Transceiver) V DDA33_USB_PLL PWR USBP V DD Common mode 3.3 V power for USB PHY HY (PLL) V SS_USB GND USBP V DD Common mode 3.3 V ground for USB PHY HY (PLL) V DDA13_USB PWR USBP V DD Analog 1.3 V power for USB PHY HY V SS_USB GND USBP V DD Analog 1.3 V ground for USB PHY HY V DDD13_USB PWR USBP V DD Digital 1.3 V power for USB PHY HY MMCSD0_CLK A15 I/O MMC V DD out L MMCSD0: Clock PINMUX4[2].MMCS SD0 D0_MS MMCSD0_CMD C14 I/O MMC V DD in MMCSD0: Command PINMUX4[2].MMCS SD0 D0_MS MMCSD0_DAT A14 I/O MMC V DD in MMCSD0: DATA3 PINMUX4[2].MMCS SD0 D0_MS MMCSD0_DAT B13 I/O MMC V DD in MMCSD0: DATA2 PINMUX4[2].MMCS SD0 D0_MS MMCSD0_DAT D14 I/O MMC V DD in MMCSD0: DATA1 PINMUX4[2].MMCS SD0 D0_MS MMCSD0_DAT B14 I/O MMC V DD in MMCSD0: DATA0 PINMUX4[2].MMCS SD0 D0_MS UART0_RXD U18 I UART V DD in UART0: Receive Data Used for UART boot mode UART0_TXD T18 O UART V DD out H UART0: Transmit Data Used for UART boot mode SPI0_SDENA[0] B12 I/O SPI0 V DD in SPI0: Enable Chip Select PINMUX4[0].SPI0_S GIO103 GIO DENA GIO: GIO[103] SPI0_SCLK C12 I/O SPI0 V DD in SPI0: Clock SPI0_SDI A12 I/O SPI0 V DD in SPI0: Data In PINMUX4[1].SPI0_S GIO102 GIO DI GIO: GIO[102] SPI0_SDO B11 I/O SPI0 V DD in SPI0: Data Out Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State ASP1_DX C18 I/O ASP1 V DD in ASP1: Transmit Data ASP1_CLKX D19 I/O ASP1 V DD in ASP1: Transmit Clock ASP1_FSX E16 I/O ASP1 V DD in ASP1: Transmit Frame Sync ASP1_DR C19 I/O ASP1 V DD in ASP1: Receive Data ASP1_CLKR D18 I/O ASP1 V DD in ASP1: Receive Clock ASP1_FSR E17 I/O ASP1 V DD in ASP1: Receive Frame Synch ASP1_CLKS D17 I ASP1 V DD in ASP1: Master Clock RESET D11 I V DD PU in Global Chip Reset (active low) MXI1 I Clocks V DD in Crystal input for system oscillator (24 MHz) MXO1 O Clocks V DD out Output for system oscillator (24 MHz) MXI2 I Clocks V DD in Crystal input for video oscillator (27 MHz). This crystal is not required V DD MXO2 O Clocks V DD out Output for video oscillator (27 MHz). This crystal is not required. V DD TCK E10 I EMUL V DD PU in JTAG test clock input ATIO N TDI I EMUL V DD PU in JTAG test data input ATIO N TDO O EMUL V DD out L JTAG test data output ATIO N TMS I EMUL V DD PU in JTAG test mode select ATIO N TRST I EMUL V DD PD in JTAG test logic reset (active low) ATIO N RTCK E11 O EMUL V DD out L JTAG test clock output ATIO N EMU0 I/O EMUL V DD PU in JTAG emulation I/O ATIO V DD N V DD EMU1 I/O EMUL V DD PU in JTAG emulation I/O ATIO EMU[1:0] Force Debug Scan chain N (ARM and ARM ETB TAPs connected) EMU[1:0] Normal Scan chain (ICEpick only) RSV01 A Reserved. This signal should be left as a No I/O/Z Connect or connected to V SS RSV02 A Reserved. This signal should be left as a No I/O/Z Connect or connected to V SS RSV03 A Reserved. This signal should be left as a No I/O/Z Connect or connected to V SS RSV04 A Reserved. This signal should be left as a No I/O/Z Connect or connected to V SS RSV05 A Reserved. This signal should be connected I/O/Z to V SS Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State RSV06 PWR Reserved. This signal should be connected to V SS RSV07 GND Reserved. This signal should be connected to V SS NC No connect V DD_VIN PWR Power for Digital Video Input IO (3.3 V DD_VIN PWR Power for Digital Video Input IO (3.3 V DD_VIN PWR Power for Digital Video Input IO (3.3 V DD_VOUT PWR Power for Digital Video Output IO (3.3 V DD_VOUT PWR Power for Digital Video Output IO (3.3 V DD_VOUT PWR Power for Digital Video Output IO (3.3 V DD_DDR PWR Power for DDR I/O (1.8 V DD_DDR PWR Power for DDR I/O (1.8 V DD_DDR P10 PWR Power for DDR I/O (1.8 V DD_DDR P11 PWR Power for DDR I/O (1.8 V DD_DDR P12 PWR Power for DDR I/O (1.8 V DD_DDR P13 PWR Power for DDR I/O (1.8 V DD_DDR P14 PWR Power for DDR I/O (1.8 V DD_DDR PWR Power for DDR I/O (1.8 V DD_DDR R12 PWR Power for DDR I/O (1.8 V DD_DDR T14 PWR Power for DDR I/O (1.8 V DDA_PLL1 G12 PWR Analog Power for PLL1 (1.3 V DDA_PLL2 PWR Analog Power for PLL2 (1.3 CV DD PWR Core power (1.3 CV DD A10 PWR Core power (1.3 CV DD B19 PWR Core power (1.3 CV DD PWR Core power (1.3 CV DD PWR Core power (1.3 CV DD G11 PWR Core power (1.3 CV DD H10 PWR Core power (1.3 CV DD H13 PWR Core power (1.3 CV DD H17 PWR Core power (1.3 CV DD J11 PWR Core power (1.3 CV DD J12 PWR Core power (1.3 CV DD J13 PWR Core power (1.3 CV DD PWR Core power (1.3 CV DD K11 PWR Core power (1.3 CV DD K12 PWR Core power (1.3 CV DD L11 PWR Core power (1.3 CV DD L12 PWR Core power (1.3 CV DD PWR Core power (1.3 CV DD PWR Core power (1.3 CV DD PWR Core power (1.3 CV DD T17 PWR Core power (1.3 CV DD W19 PWR Core power (1.3 V DD PWR Power for Digital IO (3.3 V DD F10 PWR Power for Digital IO (3.3 Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State V DD F11 PWR Power for Digital IO (3.3 V DD F12 PWR Power for Digital IO (3.3 V DD F13 PWR Power for Digital IO (3.3 V DD F14 PWR Power for Digital IO (3.3 V DD PWR Power for Digital IO (3.3 V DD G14 PWR Power for Digital IO (3.3 V DD PWR Power for Digital IO (3.3 V DD K15 PWR Power for Digital IO (3.3 V DD PWR Power for Digital IO (3.3 V DD L13 PWR Power for Digital IO (3.3 V DD M10 PWR Power for Digital IO (3.3 V DD M11 PWR Power for Digital IO (3.3 V DD M12 PWR Power for Digital IO (3.3 V DD M13 PWR Power for Digital IO (3.3 V DD N11 PWR Power for Digital IO (3.3 V DD N12 PWR Power for Digital IO (3.3 V SS_MX1 C10 GND System oscillator (24 MHz) ground V SS_MX2 GND Video oscillator (27 MHz) ground V SSA_PLL1 H12 GND Analog Ground for PLL1 V SSA_PLL2 GND Analog Ground for PLL2 V SS GND Digital ground V SS GND Digital ground V SS A19 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS B10 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS E15 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS H11 GND Digital ground V SS H14 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS J10 GND Digital ground V SS J14 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS K10 GND Digital ground V SS K14 GND Digital ground V SS GND Digital ground V SS GND Digital ground Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 2-23. DM355 Pin Descriptions (continued) Name BGA Type Group Power PU Reset (4) Mux Control ID (1) Supply (2) PD (3) State V SS L10 GND Digital ground V SS L14 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS M14 GND Digital ground V SS M17 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS N14 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS T15 GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS GND Digital ground V SS U14 GND Digital ground V SS U17 GND Digital ground V SS GND Digital ground V SS V18 GND Digital ground V SS GND Digital ground Submit Documentation Feedback Device Overview

2.6 Device Support 2.6.1 Development Tools 2.6.2 Device Nomenclature TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com TI offers an extensive line of development tools for DM355 systems, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). The following products support development of DM355 based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Hardware Development Tools: Extended Development System (XDS Emulator (supports TMS320DM355 DMSoC multiprocessor system debug) EVM (Evaluation Module) For a complete listing of development-support tools for the TMS320DM355 DMSoC platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications. TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. TMS Fully-qualified production device. Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product. TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate is undefined. Only qualified production devices are to be used in production. Device Overview Submit Documentation Feedback

TMX = Experimental□device TMS□=□Qualified□device DEVICE□FAMILY 320□= DSPfamilyTMS320 PACKAGE□TYPE(A) ZCE□=□337-pin□plastic□BGA,□with□Pb-free□soldered□ballsDEVICE(B) A. BGA =□Ball□Grid Array (□□□) SILICON□REVISION Blank□=□Initial□Silicon1.1 SPEED□GRADE 216□MHz 270□MHz (□□□□) (□□□□) TEMPERATURE□RANGE□(DEFAULT:□0°C□TO□85°C) 0°C□to□85°C,□commercial□temperature A = 40°C□to□10 °C– 0 ,□extended□temperature Blank□= 135□MHz 2.6.3 Device Documentation 2.6.3.1 Related Documentation From Texas Instruments TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZCE), the temperature range (for example, "Blank" is the commercial temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz). The following figure provides a legend for reading the complete device name for any TMS320DM355 DMSoC platform member. Figure 2-5. Device Nomenclature The following documents describe the TMS320DM35x Digital Media System-on-Chip (DMSoC). Copies of these documents are available on the internet at www.ti.com SPRS463 TMS320DM355 Digital Media System-on-Chip (DMSoC) Data Manual This document describes the overall TMS320DM355 system, including device architecture and features, memory map, pin descriptions, timing characteristics and requirements, device mechanicals, etc. SPRZ264 TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functional specifications for the TMS320DM355 DMSoC. SPRUFB3 TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide This document describes the ARM Subsystem in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is responsible for configuration and control of the device; including the components of the ARM Subsystem, the peripherals, and the external memories. SPRUED1 TMS320DM35x Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) Reference Guide This document describes the asynchronous external memory interface (EMIF) in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of external devices. SPRUED2 TMS320DM35x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB) Controller Reference Guide This document describes the universal serial bus (USB) controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices and also supports host negotiation. SPRUED3 TMS320DM35x Digital Media System-on-Chip (DMSoC) Audio Serial Port (ASP) Submit Documentation Feedback Device Overview

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Reference Guide This document describes the operation of the audio serial port (ASP) audio interface in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface. SPRUED4 TMS320DM35x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI) Reference Guide This document describes the serial peripheral interface (SPI) in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length to bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communication between the DMSoC and external peripherals. Typical registers, display drivers, SPI EPROMs and analog-to-digital converters. SPRUED9 TMS320DM35x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Reference Guide This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU. SPRUEE0 TMS320DM35x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C) Peripheral Reference Guide This document describes the inter-integrated circuit (I2C) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DMSoC through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification. SPRUEE2 TMS320DM35x Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure Digital (SD) Card Controller Reference Guide This document describes the multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of storage. The MMC/SD controller provides an interface to external MMC and SD cards. The communication between the MMC/SD controller and MMC/SD card(s) is performed by the MMC/SD protocol. SPRUEE4 TMS320DM35x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller Reference Guide This document describes the operation of the enhanced direct memory access (EDMA3) controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfers between two memory-mapped slave endpoints on the DMSoC. SPRUEE5 TMS320DM35x Digital Media System-on-Chip (DMSoC) 64-bit Timer Reference Guide This document describes the operation of the software-programmable 64-bit timers in the TMS320DM35x Digital Media System-on-Chip (DMSoC). Timer Timer and Timer are used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer is used only as a watchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanced direct memory access (EDMA) synchronization events and Real Time Output (RTO) events (Timer only). The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting code loop. SPRUEE6 TMS320DM35x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output (GPIO) Reference Guide This document describes the general-purpose input/output (GPIO) Device Overview Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. When configured as an input, you can detect the state of the input by reading the state of an internal register. When configured as an output, you can write to an internal register to control the state driven on the output pin. SPRUEE7 TMS320DM35x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM) Reference Guide This document describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). SPRUEH7 TMS320DM35x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Reference Guide This document describes the DDR2/mDDR memory controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM and mobile DDR devices. SPRUF71 TMS320DM35x Digital Media System-on-Chip (DMSoC) Video Processing Front End (VPFE) Reference Guide This document describes the Video Processing Front End (VPFE) in the TMS320DM35x Digital Media System-on-Chip (DMSoC). SPRUF72 TMS320DM35x Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE) Reference Guide This document describes the Video Processing Back End (VPBE) in the TMS320DM35x Digital Media System-on-Chip (DMSoC). SPRUF74 TMS320DM35x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller Reference Guide This document describes the Real Time Out (RTO) controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). SPRUFC8 TMS320DM35x Digital Media System-on-Chip (DMSoC) Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM35x Digital Media System-on-Chip (DMSoC). SPRAAR3 Implementing DDR2/mDDR PCB Layout on the TMS320DM35x DMSoC This provides board design recommendations and guidelines for DDR2 and mobile DDR. SPRAAR7 USB 2.0 Board Design and Layout Guidelines This provides board design recommendations and guidelines for high speed USB. Submit Documentation Feedback Device Overview

3.1 ARM Subsystem Overview 3.1.1 Components of the ARM Subsystem TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com This section provides a detailed overview of the DM355 device. The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of the overall DM355 system, including the components of the ARM Subsystem, the peripherals, and the external memories. The ARM is responsible for handling system functions such as system-level initialization, configuration, user interface, user command execution, connectivity functions, interface and control of the subsystem, etc. The ARM is master and performs these functions because it has a large program memory space and fast context switching capability, and is thus suitable for complex, multi-tasking, and general-purpose control tasks. The ARM Subsystem in DM355 consists of the following components: ARM926EJ-S RISC processor, including: coprocessor (CP15) MMU 16KB Instruction cache 8KB Data cache Write Buffer Java accelerator ARM Internal Memories 32KB Internal RAM (32-bit wide access) 8KB Internal ROM (ARM bootloader for non-AEMIF boot options) Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) System Control Peripherals ARM Interrupt Controller PLL Controller Power and Sleep Controller System Control Module The ARM also manages/controls all the device peripherals: DDR2 mDDR EMIF Controller AEMIF Controller, including the OneNAND and NAND flash interface Enhanced DMA (EDMA) UART Timers Real Time Out (RTO) Pulse Width Modulator (PWM) Inter-IC Communication (I2C) Multi-Media Card/Secure Digital (MMC/SD) Audio Serial Port (ASP) Universal Serial Bus Controller (USB) Serial Port Interface (SPI) Video Processing Front End (VPFE) CCD Controller (CCDC) Detailed Device

16K□I$ 8K□D$ MMU CP15 Arbiter Arbiter I-AHB D-AHB Master IF DMA Bus I-TCM D-TCM 16K RAM0RAM1 16K ROM Arbiter Slave IF Master□IF CFG□Bus ARM Interrupt Controller (AINTC) Control System PLLC2 PLLC1 (PSC) Controller Sleep Power Peripherals... 3.2 ARM926EJ-S RISC CPU TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Image Pipe (IPIPE) H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure) Video Processing Back End (VPBE) On Screen Display (OSD) Video Encoder Engine (VENC) Figure 3-1 shows the functional block diagram of the DM355 ARM Subsystem. Figure 3-1. DM355 ARM Subsystem Block Diagram The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: ARM926EJ integer core CP15 system control coprocessor Memory Management Unit (MMU) Separate instruction and data Caches Write buffer Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces Separate instruction and data AHB bus interfaces Submit Documentation Feedback Detailed Device

3.2.1 CP15 3.2.2 MMU 3.2.3 Caches and Write Buffer TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available at http://www.arm.com The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode. The ARM926EJ-S MMU provides virtual memory Linux, WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU are: Standard ARM architecture and MMU mapping sizes, domains and access protection scheme. Mapping sizes are: 1MB (sections) 64KB (large pages) 4KB (small pages) 1KB (tiny pages) Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions) Hardware page table walks Invalidate entire TLB, using CP15 register Invalidate TLB entry, selected by MVA, using CP15 register Lockdown of TLB entries, using CP15 register The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following features: Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA) Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables. Critical-word first cache refilling Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address. Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory. Detailed Device

3.2.4 Tightly Coupled Memory (TCM) 3.2.5 Advanced High-performance Bus (AHB) 3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB) 3.3 Memory Mapping 3.3.1 ARM Internal Memories 3.3.2 External Memories TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry. ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt Vector table. ARM internal ROM boot options include NAND, UART, and MMC/SD. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers. Instruction and Data accesses are differentiated via accessing different memory map regions, with the instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000, as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB each, which allows simultaneous instruction and data accesses to be accomplished if the code and data are in separate banks. The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the configuration bus and the external memories bus. To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in DM355 also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts: Trace Port provides real-time trace capability for the ARM9. Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers. The DM355 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data. The ARM memory map is shown in Table 2-2 and Table 2-3 This section describes the memories and interfaces within the ARM's memory map. The ARM has access to the following ARM internal memories: 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data (D-TCM) to the different memory regions. 8KB ARM Internal ROM The ARM has access to the following External memories: Submit Documentation Feedback Detailed Device

3.3.3 Peripherals 3.4 ARM Interrupt Controller (AINTC) 3.4.1 Interrupt Mapping TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com DDR2 mDDR Synchronous DRAM Asynchronous EMIF OneNAND NAND Flash Flash card devices: MMC/SD xD SmartMedia The ARM has access to all of the peripherals on the DM355 device. The DM355 ARM Interrupt Controller (AINTC) has the following features: Supports up to interrupt channels (16 external channels) Interrupt mask for each channel Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt. Hardware prioritization of simultaneous interrupts Configurable interrupt priority levels of FIQ and levels of IRQ) Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference Manual for detailed information about the ARM s FIQ and IRQ interrupts. Each interrupt channel is mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding highest priority ISR s address is stored in the INTC s ENTRY register. The IRQ or FIQ interrupt routine can read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a software dispatcher to determine the asserted interrupt. The AINTC takes up to ARM device interrupts and maps them to either the IRQ or to the FIQ of the ARM. Each interrupt is also assigned one of priority levels for FIQ, for IRQ). For interrupts with the same priority level, the priority is determined by the hardware interrupt number (the lowest number has the highest priority). Table 3-1 shows the connection of device interrupts to the ARM. Table 3-1. AINTC Interrupt Connections (1) Interrupt Acronym Source Interrupt Acronym Source Number Number VPSSINT0 VPSS INT0, TINT0 Timer TINT12 Configurable via VPSSBL register: INTSEL VPSSINT1 VPSS INT1 TINT1 Timer TINT34 VPSSINT2 VPSS INT2 TINT2 Timer TINT12 VPSSINT3 VPSS INT3 TINT3 Timer TINT34 VPSSINT4 VPSS INT4 PWMINT0 PWM0 VPSSINT5 VPSS INT5 PWMINT1 PWM (1) The total number of interrupts in DM355 exceeds 64, which is the maximum value of the AINTC module. Therefore, several interrupts are multiplexed and you must use the register ARM_INTMUX in the System Control Module to select the interrupt source for multiplexed interrupts. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3) for more information on the System Control Module register ARM_INTMUX. Detailed Device

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 3-1. AINTC Interrupt Connections (continued) Interrupt Acronym Source Interrupt Acronym Source Number Number VPSSINT6 VPSS INT6 PWMINT2 PWM2 VPSSINT7 VPSS INT7 I2CINT I2C VPSSINT8 VPSS INT8 UARTINT0 UART0 Reserved UARTINT1 UART1 Reserved SPINT0-0 SPI0 Reserved SPINT0-1 SPI0 USBINT USB OTG Collector GPIO0 GPIO RTOINT or RTO or GPIO1 GPIO TINT4 Timer TINT12 SYS.ARM_INTMUX UARTINT2 or UART2 or GPIO2 GPIO TINT5 Timer TINT34 TINT6 Timer TINT12 GPIO3 GPIO CCINT0 EDMA CC Region GPIO4 GPIO SPINT1-0 or SPI1 or GPIO5 GPIO CCERRINT EDMA CC Error SPINT1-1 or SPI1 or GPIO6 GPIO TCERRINT0 EDMA TC0 Error SPINT2-0 or SPI2 or GPIO7 GPIO TCERRINT1 EDMA TC1 Error PSCINT PSC ALLINT GPIO8 GPIO SPINT2-1 SPI2 GPIO9 GPIO TINT7 Timer3 TINT34 GPIOBNK0 GPIO SDIOINT0 MMC/SD0 GPIOBNK1 GPIO MBXINT0 or ASP0 or GPIOBNK2 GPIO MBXINT1 ASP1 MBRINT0 or ASP0 or GPIOBNK3 GPIO MBRINT1 ASP1 MMCINT0 MMC/SD0 GPIOBNK4 GPIO MMCINT1 MMC/SC1 GPIOBNK5 GPIO PWMINT3 PWM3 GPIOBNK6 GPIO DDRINT DDR EMIF COMMTX ARMSS AEMIFINT Async EMIF COMMRX ARMSS SDIOINT1 SDIO1 EMUINT E2ICE Submit Documentation Feedback Detailed Device

3.5 Device Clocking 3.5.1 Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 requires one primary reference clock The reference clock frequency may be generated either by crystal input or by external oscillator. The reference clock is the clock at the pins named MXI1/MXO1. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1 generates the clocks required by the ARM, MPEG4 and JPEG coprocessor, VPBE, VPSS, and peripherals. PLL2 generates the clock required by the DDR PHY. A block diagram of DM355's clocking architecture is shown in Figure 3-2 The PLLs are described further in Section 3.6 Detailed Device

ARM□Subsystem MPEG/JPEG Coprocessor SYSCLK1 SYSCLK2 VPFE VPBE DAC DDR□PHY DDR PLLDIV1□(/1) BPDIV□(/8) PLL Controller□2 PLL Controller□1 PLLDIV3□(/n) PLLDIV2□(/4) PLLDIV1□(/2) SYSCLK3 I2C Timers□(x4) PWMs□(x4) SPI□(x3) MMC/SD□(x2) EMIF/NAND ASP (x2) GPIO UART2 ARM□INTC USB 60□MHz Reference Clock (MXI/MXO) (24□MHz□or 36□MHz) Reference□Clock (MXI/MXO) 24□MHz□or□36□MHz PCLK AUXCLK□(/1) BPDIV□(/3) SYSCLK1 CLKOUT3 SYSCLKBP CLKOUT2 EDMA Bus□Logic Sys□Logic PSC IcePick EXTCLK RTO USB□Phy SYSCLKBP AUXCLK PLLDIV4□(/4□or□/2) VPSS UART0,□1 CLKOUT1 Sequencer SYSCLK4 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 3-2. Device Clocking Block Diagram Submit Documentation Feedback Detailed Device

3.5.2 Supported Clocking Configurations for DM355-135 3.5.2.1 Supported Clocking Configurations for DM355-135 (24 MHz reference) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com This section describes the only supported device clocking configurations for DM355-135. The DM355 supports either MHz (typical) or MHz reference clock (crystal or external oscillator input). Configurations are shown for both cases. 3.5.2.1.1 DM355-135 PLL1 (24 MHz reference) All supported clocking configurations for DM355-135 PLL1 with MHz reference clock are shown in Table 3-2 Table 3-2. PLL1 Supported Clocking Configurations for DM355-135 (24 MHz reference) PREDIV PLLM POSTDIV PLL1 ARM Peripherals VENC VPSS VCO MPEG4 and JPEG Coprocessor (/8 fixed) programmable) (/2 or (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or (MHz) programmable) programmable) bypass bypass bypass bypass 2.4 180 270 135 67.5 135 162 243 121.5 60.75 121.5 144 216 108 108 126 189 94.5 47.25 94.5 108 162 40.5 3.5.2.1.2 DM355-135 PLL2 (24 MHz reference) All supported clocking configurations for DM355-135 PLL2 with MHz reference clock are shown in Table 3-3 Table 3-3. PLL2 Supported Clocking Configurations for DM355-135 (24 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 133 266 266 133 100 200 200 100 100 160 160 Detailed Device

3.5.2.2 Supported Clocking Configurations for DM355-135 (36 MHz reference) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 3.5.2.2.1 DM355-135PLL1 (36 MHz reference) All supported clocking configurations for DM355-135 PLL1 with MHz reference clock are shown in Table 3-4 Table 3-4. PLL1 Supported Clocking Configurations DM355-135 (36 MHz reference) PREDIV PLLM or PLL1 ARM Peripherals VENC VPSS programmable VCO MPEG4 and JPEG Coprocessor (/8 fixed) (/2 fixed) (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or (MHz) programmable) programmable) bypass bypass bypass bypass 3.6 120 270 135 67.5 135 108 243 121.5 60.75 121.5 216 108 108 3.5.2.2.2 DM355-135 PLL2 (36 MHz reference) All supported clocking configurations for DM355-135 PLL2 with MHz reference clock are shown in Table 3-5 Table 3-5. PLL2 Supported Clocking Configurations for DM355-135 (36 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 133 266 266 133 150 200 200 100 120 160 160 Submit Documentation Feedback Detailed Device

3.5.3 Supported Clocking Configurations for DM355-216 3.5.3.1 Supported Clocking Configurations for DM355-216 (24 MHz reference) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com This section describes the only supported device clocking configurations for DM355-216. The DM355 supports either MHz (typical) or MHz reference clock (crystal or external oscillator input). Configurations are shown for both cases. 3.5.3.1.1 DM355-216 PLL1 (24 MHz reference) All supported clocking configurations for DM355-216 PLL1 with MHz reference clock are shown in Table 3-2 Table 3-6. PLL1 Supported Clocking Configurations for DM355-216 (24 MHz reference) PREDIV PLLM POSTDIV PLL1 ARM Peripherals VENC VPSS VCO MPEG4 and JPEG Coprocessor (/8 fixed) programmable) (/2 or (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or (MHz) programmable) programmable) bypass bypass bypass bypass 2.4 144 432 216 108 108 135 405 202.5 101.25 101.25 126 378 189 94.5 94.5 117 351 175.5 87.75 87.75 108 324 162 297 148.5 74.25 74.25 180 270 135 67.5 135 162 243 121.5 60.75 121.5 144 216 108 108 126 189 94.5 47.25 94.5 108 162 40.5 3.5.3.1.2 DM355-216 PLL2 (24 MHz reference) All supported clocking configurations for DM355-216 PLL2 with MHz reference clock are shown in Table 3-3 Table 3-7. PLL2 Supported Clocking Configurations for DM355-216 (24 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 114 342 342 171 108 324 324 162 102 306 306 153 288 288 144 133 266 266 133 100 200 200 100 100 160 160 Detailed Device

3.5.3.2 Supported Clocking Configurations for DM355-216 (36 MHz reference) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 3.5.3.2.1 DM355-216 PLL1 (36 MHz reference) All supported clocking configurations for DM355-216 PLL1 with MHz reference clock are shown in Table 3-4 Table 3-8. PLL1 Supported Clocking Configurations DM355-216 (36 MHz reference) PREDIV PLLM POSTDIV PLL1 ARM Peripherals VENC VPSS VCO MPEG4 and JPEG Coprocessor (/8 fixed) programmable) (/2 or (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or (MHz) programmable) programmable) bypass bypass bypass bypass 3.6 432 216 108 108 180 405 202.5 101.25 101.25 168 378 189 94.5 94.5 156 351 175.5 87.75 87.75 144 324 162 132 297 148.5 74.25 74.25 120 270 135 67.5 135 108 243 121.5 60.75 121.5 216 108 108 3.5.3.2.2 DM355-216 PLL2 (36 MHz reference) All supported clocking configurations for DM355-216 PLL2 with MHz reference clock are shown in Table 3-5 Table 3-9. PLL2 Supported Clocking Configurations for DM355-216 (36 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 114 342 342 171 108 324 324 162 102 306 306 153 288 288 144 133 266 266 133 150 200 200 100 120 160 160 Submit Documentation Feedback Detailed Device

3.5.4 Supported Clocking Configurations for DM355-270 3.5.4.1 Supported Clocking Configurations for DM355-270 (24 MHz reference) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com This section describes the only supported device clocking configurations for DM355-270. The DM355 supports either MHz (typical) or MHz reference clock (crystal or external oscillator input). Configurations are shown for both cases. Note DM355-270 devices support only commercial temperature ranges. 3.5.4.1.1 DM355-270 PLL1 (24 MHz reference) All supported clocking configurations for DM355-270 PLL1 with MHz reference clock are shown in Table 3-2 Table 3-10. PLL1 Supported Clocking Configurations for DM355-270 (24 MHz reference) PREDIV PLLM or PLL1 ARM Peripherals VENC VPSS programmable VCO MPEG4 and JPEG Coprocessor (/8 fixed) programmable) (/2 fixed) (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 (/2 fixed) (MHz) (/4 fixed) (MHz) (/n programmable) (MHz) (/4 or (MHz) programmable) bypass bypass bypass bypass 2.4 180 540 270 135 135 171 513 256.5 128.25 128.25 162 486 243 121.5 121.5 153 459 229.5 114.75 114.75 144 432 216 108 108 135 405 202.5 101.25 101.25 126 378 189 94.5 94.5 117 351 175.5 87.75 87.75 108 324 162 297 148.5 74.25 74.25 180 270 135 67.5 135 162 243 121.5 60.75 121.5 144 216 108 108 126 189 94.5 47.25 94.5 108 162 40.5 3.5.4.1.2 DM355-270 PLL2 (24 MHz reference) All supported clocking configurations for DM355-270 PLL2 with MHz reference clock are shown in Table 3-3 Table 3-11. PLL2 Supported Clocking Configurations for DM355-270 (24 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 144 432 432 216 138 414 414 207 132 396 396 198 126 378 378 189 120 360 360 180 114 342 342 171 108 324 324 162 102 306 306 153 288 288 144 133 266 266 133 100 200 200 100 100 160 160 Detailed Device

3.5.4.2 Supported Clocking Configurations for DM355-270 (36 MHz reference) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 3.5.4.2.1 DM355-270 PLL1 (36 MHz reference) All supported clocking configurations for DM355-270 PLL1 with MHz reference clock are shown in Table 3-4 Table 3-12. PLL1 Supported Clocking Configurations for DM355-270 (36 MHz reference) PREDIV PLLM or PLL1 ARM Peripherals VENC VPSS programmab VCO MPEG4 and JPEG le Coprocessor (/8 fixed) programmable) (/2 fixed) (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4 (/2 fixed) (MHz) (/4 fixed) (MHz) (/n programmable) (MHz) (/4 or (MHz) programmable) bypass bypass bypass bypass 3.6 120 540 270 135 135 114 513 256.5 128.25 128.25 108 486 243 121.5 121.5 102 459 229.5 114.75 114.75 432 216 108 108 180 405 202.5 101.25 202.5 168 378 189 94.5 189 156 351 175.5 87.75 175.5 144 324 162 162 132 297 148.5 74.25 148.5 120 270 135 67.5 135 108 243 121.5 60.75 121.5 216 108 108 Submit Documentation Feedback Detailed Device

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com 3.5.4.2.2 DM355-270 PLL2 (36 MHz reference) All supported clocking configurations for DM355-270 PLL2 with MHz reference clock are shown in Table 3-5 Table 3-13. PLL2 Supported Clocking Configurations for DM355-270 (36 MHz reference) PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock (/n programmable) programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK (/1 fixed) (MHz) (MHz) bypass bypass bypass bypass 144 432 432 216 138 414 414 207 132 396 396 198 126 378 378 189 120 360 360 180 114 342 342 171 108 324 324 162 102 306 306 153 288 288 144 133 266 266 133 150 200 200 100 120 160 160 Detailed Device

3.5.5 Peripheral Clocking Considerations 3.5.5.1 Video Processing Back End Clocking 3.5.5.2 USB Clocking TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The Video Processing Back End (VPBE) is a sub-module of the Video Processing Subsystem (VPSS). The VPBE is designed to interface with a variety of LCDs and an internal DAC module. There are two asynchronous clock domains in the VPBE: an internal clock domain and an external clock domain. The internal clock domain is driven by the VPSS clock (PLL1 SYSCLK4). The external clock domain is configurable; you can select one of five source: MHz crystal input at MXI1 MHz crystal input at MXI2 (optional feature, not typically used) PLL1 SYSCLK3 EXTCLK pin (external VPBE clock input pin) PCLK pin (VPFE pixel clock input pin) See the TMS320DM35x Digital Media System-on-Chip Video Processing Back End (VPBE) Reference Guide (literature number SPRUF72 for complete information on VPBE clocking. The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of the USB PHY. NOTE For proper USB 2.0 function, SYSCLK2 must be greater than MHz. The USB PHY takes an input clock that is configurable by the USB PHY clock source bits (PHYCLKSRC) in the USB PHY control register (USB_PHY_CTL) in the System Control Module. When a MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to This will present a MHz clock to the USB PHY. When a MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to This will present a MHz clock (36 MHz divided internally by three) to the USB PHY. The USB PHY is capable of accepting only MHz and MHz; thus you must use either a MHz or MHz crystal at MXI1/MXO1. See the TMS320DM355 DMSoC Universal Serial Bus (USB) Controller User's Guide (literature number SPRUED2 for more information. See the TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 for more information on the System Control Module. Submit Documentation Feedback Detailed Device

3.6 PLL Controller (PLLC) 3.6.1 PLL Controller Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 for more information on the PLL controllers. The DM355 has two PLL controllers that provide clocks to different components of the chip. PLL controller (PLLC1) provides clocks to most of the components of the chip. PLL controller (PLLC2) provides clocks to the DDR PHY. As a module, the PLL controller provides the following: Glitch-free transitions (on changing PLL settings) Domain clocks alignment Clock gating PLL bypass PLL power down The various clock outputs given by the PLL controller are as follows: Domain clocks: SYSCLKn Bypass domain clock: SYSCLKBP Auxiliary clock from reference clock: AUXCLK Various dividers that can be used are as follows: Pre-PLL divider: PREDIV Post-PLL divider: POSTDIV SYSCLK divider: PLLDIV1, PLLDIVn SYSCLKBP divider: BPDIV Multipliers supported are as follows: PLL multiplier control: PLLM Detailed Device

3.6.2 PLLC1 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1 registers. The following list, Table 3-14 and Figure 3-3 describe the customizations of PLLC1 in the DM355. Provides primary DM355 system clock Software configurable Accepts clock input or internal oscillator input PLL pre-divider value is fixed to (/8) PLL multiplier value is programmable PLL post-divider Only SYSCLK[4:1] are used SYSCLK1 divider value is fixed to (/2) SYSCLK2 divider value is fixed to (/4) SYSCLK3 divider value is programmable SYSCLK4 divider value is programmable to (/4) or (/2) SYSCLKBP divider value is fixed to (/3) SYSCLK1 is routed to the ARM Subsystem SYSCLK2 is routed to peripherals SYSCLK3 is routed to the VPBE module SYSCLK4 is routed to the VPSS module AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1 SYSCLKBP is routed to the output pin CLKOUT2 Table 3-14. PLLC1 Output Clocks Output Clock Used By PLLDIV Notes Divider SYSCLK1 ARM Subsystem MPEG4 and JPEG Coprocessor Fixed divider SYSCLK2 Peripherals Fixed divider SYSCLK3 VPBE (VENC module) Programmable divider (used to get MHz for VENC) SYSCLK4 VPSS or Programmable divider AUXCLK Peripherals, CLKOUT1 none No divider SYSCLKBP CLKOUT2 Fixed divider Submit Documentation Feedback Detailed Device

PLLDIV1□(/2) PLLDIV2□(/4) PLLDIV3□(/3) SYSCLK1 (ARM□and□MPEG4/ JPEG□Coprocessor) SYSCLK2 (Peripherals) SYSCLK3 (VPBE) PLL CLKMODE CLKIN OSCIN PLLEN AUXCLK (Peripherals, CLKOUT1) SYSCLKBP (CLKOUT2) Pre-DIV (/8) Post-DIV (/2□or□/1) PLLM (Programmable) BPDIV□(/3) PLLDIV4 (/4□or□/2) SYSCLK4 (VPSS) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 3-3. PLLC1 Configuration in DM355 Detailed Device

3.6.3 PLLC2 PLLDIV1□(/1) PLL CLKMODE CLKIN OSCIN PLLEN SYSCLK1 (DDR□PHY) SYSCLKBP (CLKOUT3) BPDIV□(/8) PLLM (Programmable) Pre-DIV (Programmable) Post-DIV (/1) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 PLLC2 provides the DDR PHY clock and CLKOUT3. Software controls PLLC2 operation through the PLLC2 registers. The following list, Table 3-15 and Figure 3-4 describe the customizations of PLLC2 in the DM355. Provides DDR PHY clock and CLKOUT3 Software configurable Accepts clock input or internal oscillator input (same input as PLLC1) PLL pre-divider value is programmable PLL multiplier value is programmable PLL post-divider value is fixed to (/1) Only SYSCLK[1] is used SYSCLK1 divider value is fixed to (/1) SYSCLKBP divider value is fixed to (/8) SYSCLK1 is routed to the DDR PHY SYSCLKBP is routed to the output pin CLKOUT3 AUXCLK is not used. Table 3-15. PLLC2 Output Clocks Output Clock Used by PLLDIV Divider Notes SYSCLK1 DDR PHY Fixed divider SYSCLKBP CLKOUT3 Fixed divider Figure 3-4. PLLC2 Configuration in DM355 Submit Documentation Feedback Detailed Device

3.7 Power and Sleep Controller (PSC) arm_clock arm_mreset arm_power AINTC ARM module_power module_mreset MODxmodule_clock Always□on domain Interrupt PSC clksPLLC Emulation RESET VDD DMSoC 3.8 System Control Module TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com In the DM355 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5 Many of the operations of the PSC are transparent to software, such as power-on-reset operations. However, the PSC provides you with an interface to control several important clock and reset operations. The PSC includes the following features: Manages chip power-on/off, clock on/off, and resets Provides a software interface to: Control module clock ON/OFF Control module resets Supports IcePick emulation features: power, clock, and reset For more information on the PSC, see the TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 Figure 3-5. DM355 Power and Sleep Controller (PSC) The DM355 s system control module is a system-level module containing status and top-level control logic required by the device. The system control module consists of a miscellaneous set of status and control registers, accessible by the ARM and supporting all of the following system operations: Device identification Device configuration Pin multiplexing control Device boot configuration status ARM interrupt and EDMA event multiplexing control Special peripheral status and control Timer64+ USB PHY control VPSS clock and video DAC control and status DDR VTP control Clockout circuitry GIO de-bounce control Detailed Device

3.9 Pin Multiplexing 3.9.1 Hardware Controlled Pin Multiplexing TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Power management Deep sleep mode Bandwidth Management Bus master DMA priority control For more information on the System Control Module refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 The DM355 makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. In order to accomplish this, pin multiplexing is controlled using a combination of hardware configuration (at device reset) and software control. No attempt is made by the DM355 hardware to ensure that the proper pin muxing has been selected for the peripherals or interface mode being used, thus proper pin muxing configuration is the responsibility of the board and software designers. An overview of the pin multiplexing is shown in Table 3-16 Table 3-16. Peripheral Pin Mux Overview Peripheral Muxed With Primary Function Secondary Function Tertiary Function VPFE (video in) GPIO and SPI2 VPFE (video in) SPI2 GPIO VPBE (video out) GPIO, PWM, and RTO VPBE (video out) PWM and RTO GPIO AEMIF GPIO AEMIF GPIO none ASP0 GPIO ASP0 GPIO none MMC/SD1 GPIO and UART2 MMC/SD1 GPIO UART2 CLKOUT GPIO CLKOUT GPIO none I2C GPIO I2C GPIO none UART1 GPIO UART1 GPIO none SPI1 GPIO SPI1 GPIO none SPI0 GPIO SPI0 GPIO none Use the Asynchronous EMIF configuration pins (AECFG[3:0]) for hardware pin mux control. AECFG[3:0] control the partitioning of the AEMIF addresses and GPIOs at reset, which allows you to properly configure the number of AEMIF address pins required by the boot device while unused addresses pins are available as GPIOs. These settings may be changed by software after reset by programming the PinMux2 register The PinMux2 register is in the System Control Module. As shown in Table 3-17 the number of address bits enabled on the AEMIF is selectable from to 16. Pins that are not assigned to another peripheral and not enabled as address signals become GPIOs (except EM_A[2:1]). The enabled address signals are always contiguous from EM_BA[1] upwards; bits cannot be skipped. The exception to this are EM_A[2:1]. These signals (can be used to) represent the ALE and CLE signals for the NAND Flash mode of the AEMIF and are always enabled. Note that EM_A[0] does not represent the lowest AEMIF address bit. DM355 supports only 16-bit and 8-bit data widths for the AEMIF. In 16-bit mode, EM_BA[1] represents the LS address bit (the half-word address) and EM_BA[0] represents the MS address bit (A[14]). In 8-bit mode, EM_BA[1:0] represent the LS address bits. Note that additional selections are available by programming the PinMux2 register in software after boot. Note that AECFG selection of 0010 selects OneNAND interface. The AEMIF needs to operate in the half-rate mode (full_rate to meet frequency requirements. Software should not change the PINMUX2 register setting to affect the AEMIF rate operation. A soft reset of the AEMIF should be performed any time a rate change is made. Submit Documentation Feedback Detailed Device

3.9.2 Software Controlled Pin Multiplexing 3.10 Device Reset TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 3-17. AECFG (Async EMIF Configuration) Pin Mux Coding 1101(NAND) 1100 1010 1000 (8-bit SRAM) 0010 (16-bit SRAM, 0000 OneNAND) GPIO[54] GPIO[54] EM_A[14] EM_BA[0] EM_A[14] EM_BA[0] GPIO[55] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] GPIO[56] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] GPIO[57] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] GPIO[58] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] GPIO[59] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] GPIO[60] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] GPIO[61] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] GPIO[62] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] GPIO[63] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] GPIO[64] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] GPIO[65] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] GPIO[66] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] GPIO[67] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] GPIO[46] GPIO[46] GPIO[46] GPIO[46] EM_D[8] EM_D[8] GPIO[47] GPIO[47] GPIO[47] GPIO[47] EM_D[9] EM_D[9] GPIO[48] GPIO[48] GPIO[48] GPIO[48] EM_D[10] EM_D[10] GPIO[49] GPIO[49] GPIO[49] GPIO[49] EM_D[11] EM_D[11] GPIO[50] GPIO[50] GPIO[50] GPIO[50] EM_D[12] EM_D[12] GPIO[51] GPIO[51] GPIO[51] GPIO[51] EM_D[13] EM_D[13] GPIO[52] GPIO[52] GPIO[52] GPIO[52] EM_D[14] EM_D[14] GPIO[53] GPIO[53] GPIO[53] GPIO[53] EM_D[15] EM_D[15] All pin multiplexing options are configurable by software via pin mux registers that reside in the System Control Module. The PinMux0 Register controls the Video In muxing, PinMux1 register controls Video Out signals, PinMux2 register controls AEMIF signals, PinMux3 registers control the multiplexing of the GIO signals, the PinMux4 register controls the SPI and MMC/SD0 signals. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 for complete descriptions of the pin mux registers. There are five types of reset in DM355. The types of reset differ by how they are initiated and/or by their effect on the chip. Each type is briefly described in Table 3-18 and further described in TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 Table 3-18. Reset Types Type Initiator Effect POR (Power-On-Reset) RESET pin low and TRST low Total reset of the chip (cold reset). Resets all modules including memory and emulation. Warm Reset RESET pin low and TRST high (initiated by ARM Resets all modules including memory, except ARM emulator). emulation. Max Reset ARM emulator or Watchdog Timer (WDT). Same effect as warm reset. Detailed Device

3.11 Default Device Configurations 3.11.1 Device Configuration Pins TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 3-18. Reset Types (continued) Type Initiator Effect System Reset ARM emulator Resets all modules except memory and ARM emulation. It is a soft reset that maintains memory

states. Module Reset ARM software Resets a specific module. Allows the ARM to independently reset any module. Module reset is intended as a debug tool not as a tool to use in production. After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF. NOTE Default configuration is the configuration immediately after POR, warm reset, and max reset and just before the boot process begins. The boot ROM updates the configuration. See Section 3.12 for more information on the boot process. The device configuration pins are described in Table 3-19 The device configuration pins are latched at reset and allow you to configure all of the following options at reset: ARM Boot Mode Asynchronous EMIF pin configuration These pins are described further in the following sections. NOTE The device configuration pins are multiplexed with AEMIF pins. After the device configuration pins are sampled at reset, they automatically change to function as AEMIF pins. Pin multiplexing is described in Section 3.8 Table 3-19. Device Configuration Default Setting (by internal Device Sampled pull-up/ Configuration Input Function Pin pull-down) Device Configuration Affected BTSEL[1:0] Selects ARM boot mode EM_A[13:12] If any ROM boot mode is selected, GIO61 Boot from ROM (NAND) (NAND) is used to indicated boot status. Boot from AEMIF If NAND boot is selected, CE0 is used for Boot from ROM NAND. Use AECFG[3:0] to configure (MMC/SD) AEMIF pins for NAND. Boot from ROM (UART) If AEMIF boot is selected, CE0 is used for AEMIF device (OneNAND, ROM). Use AECFG[3:0] to configure AEMIF pins for NAND. If MMC/SD boot is selected, MMC/SD0 is used. AECFG[3:0] Selects AEMIF pin EM_A[11:8] 1101 Selects the AEMIF pin configuration. Refer configuration (NAND) to pin-muxing information in Section 3.9.1 Note that AECFG[3:0] affects both AEMIF (BTSEL[1:0]=01) and NAND (BTSEL[1:0]=00) boot modes. Submit Documentation Feedback Detailed Device

3.11.2 PLL Configuration 3.11.3 Power Domain and Module State Configuration TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1 (typically MHz) drives the chip after reset. For more information on device clocking, see Section 3.5 and Section 3.6 The default state of the PLLs is reflected in the default state of the register bits in the PLLC registers. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 for PLLC register descriptions. Only a subset of modules are enabled after reset by default. Table 3-20 shows which modules are enabled after reset. Table 3-20 as shows that the following modules are enabled depending on the sampled state of the device configuration pins: EDMA (CC, TC0 and TC1), AEMIF, MMC/SD0, UART0, and Timer0. For example, UART0 is enabled after reset when the device configuration pins (BTSEL[1:0] Enable UART) select UART boot mode. For more information on module configuration refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 Detailed Device

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 3-20. Module Configuration Default States Module Module Name Power Domain Power Domain State Module State Number VPSS Master AlwaysOn ON SyncRst VPSS Slave AlwaysOn ON SyncRst EDMA (CC) AlwaysOn ON BTSEL[1:0] Enable (NAND) BTSEL[1:0] Enable (OneNAND) EDMA (TC0) AlwaysOn ON BTSEL[1:0] SyncRst (MMC/SD) BTSEL[1:0] Enable (UART) EDMA (TC1) AlwaysOn ON Timer3 AlwaysOn ON SyncRst SPI1 AlwaysOn ON SyncRst MMC/SD1 AlwaysOn ON SyncRst ASP1 AlwaysOn ON SyncRst USB AlwaysOn ON SyncRst PWM3 AlwaysOn ON SyncRst SPI2 AlwaysOn ON SyncRst RTO AlwaysOn ON SyncRst DDR EMIF AlwaysOn ON SyncRst AEMIF AlwaysOn ON BTSEL[1:0] Enable (NAND) BTSEL[1:0] Enable (OneNAND) BTSEL[1:0] SyncRst (MMC/SD) BTSEL[1:0] Enable (UART) MMC/SD0 AlwaysOn ON BTSEL[1:0] SyncRst (NAND) BTSEL[1:0] SyncRst (OneNAND) BTSEL[1:0] Enable (MMC/SD) BTSEL[1:0] SyncRst (UART) Reserved ASP AlwaysOn ON SyncRst I2C AlwaysOn ON SyncRst UART0 AlwaysOn ON BTSEL[1:0] SyncRst (NAND) BTSEL[1:0] SyncRst (OneNAND) BTSEL[1:0] SyncRst (MMC/SD) BTSEL[1:0] Enable (UART) UART1 AlwaysOn ON SyncRst UART2 AlwaysOn ON SyncRst SPI0 AlwaysOn ON SyncRst PWM0 AlwaysOn ON SyncRst PWM1 AlwaysOn ON SyncRst PWM2 AlwaysOn ON SyncRst GPIO AlwaysOn ON SyncRst TIMER0 AlwaysOn ON BTSEL[1:0] Enable (NAND) BTSEL[1:0] Enable (OneNAND) BTSEL[1:0] Enable (MMC/SD) BTSEL[1:0] Enable (UART) TIMER1 AlwaysOn ON SyncRst TIMER2 AlwaysOn ON Enable System Module AlwaysOn ON Enable ARM AlwaysOn ON Enable Submit Documentation Feedback Detailed Device

3.11.4 ARM Boot Mode Configuration 3.11.5 AEMIF Configuration 3.11.5.1 AEMIF Pin Configuration 3.11.5.2 AEMIF Timing Configuration 3.12 Device Boot Modes TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 3-20. Module Configuration (continued) Default States BUS AlwaysOn ON Enable BUS AlwaysOn ON Enable BUS AlwaysOn ON Enable BUS AlwaysOn ON Enable BUS AlwaysOn ON Enable BUS AlwaysOn ON Enable BUS AlwaysOn ON Enable Reserved Reserved Reserved Reserved VPSS DAC Always On ON SyncRst The input pins BTSEL[1:0] determine whether the ARM will boot from its ROM or from the Asynchronous EMIF (AEMIF). When ROM boot is selected (BTSEL[1:0] 00, 10, or 11), a jump to the start of internal ROM (address 0x0000: 8000) is forced into the first fetched instruction word. The embedded ROM boot loader code (RBL) then performs certain configuration steps, reads the BOOTCFG register to determine the desired boot method, and branches to the appropriate boot routine (i.e., a NAND, MMC/SD, or UART loader routine). If AEMIF boot is selected (BTSEL[1:0] 01), a jump to the start of AEMIF (address 0x0200: 0000) is forced into the first fetched instruction word. The ARM then continues executing from external asynchronous memory using the default AEMIF timings until modified by software. NOTE For AEMIF boot, the OneNAND must be connected to the first AEMIF chip select space (EM_CE0). Also, the AEMIF does not support direct execution from NAND Flash. Boot modes are further described in Section 3.12 The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0] to properly configure the pins of the AEMIF. Refer to the section on pin multiplexing in Section 3.9 Also, see the Asynchronous External Memory Interface (AEMIF) Peripheral Reference Guide (literature number SPRUED1 for more information on the AEMIF. When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is cycles per access (16 cycles of setup, cycles of strobe, and cycles of hold). Thus, with a MHz clock at MXI1, the AEMIF is configured to run at MHz/88 which equals approximately kHz by default. See the Asynchronous External Memory Interface (AEMIF) Peripheral Reference Guide (literature number SPRUED1 for more information on the AEMIF. The DM355 ARM can boot from either Async EMIF (AEMIF/OneNand) or from ARM ROM, as determined by the setting of the device configuration pins BTSEL[1:0]. The BTSEL[1:0] pins can define the ROM boot mode further as well. The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[1:0] 01, indicating AEMIF (AEMIF/OneNand) boot. See Section 3.11.1 for information on the boot selection pins. Detailed Device

3.12.1 Boot Modes Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 DM355 s ARM ROM boot loader (RBL) executes when the BTSEL[1:0] pins indicate a condition other than the normal ARM EMIF boot. If BTSEL[1:0] Asynchronous EMIF (AEMIF) boot. This mode is handled by hardware control and does not involve the ROM. In the case of OneNAND, the user is responsible for putting any necessary boot code in the OneNAND's boot page. This code shall configure the AEMIF module for the OneNAND device. After the AEMIF module is configured, booting will continue immediately after the OneNAND s boot page with the AEMIF module managing pages thereafter. The RBL supports distinct boot modes: BTSEL[1:0] ARM NAND Boot BTSEL[1:0] ARM MMC/SD Boot BTSEL[1:0] ARM UART Boot If NAND boot fails, then MMC/SD mode is tried. If MMC/SD boot fails, then MMC/SD boot is tried again. If UART boot fails, then UART boot is tried again. RBL uses GIO61 to indicate boot status (can use to blink LED): After reset, GIO61 is initially driven low (e.g LED off) If NAND boot fails,then GIO61 shall toggle at 4Hz while MMC/SD boot is tried. If MMC/SD boot fails, then GIO61 shall toggle at 4Hz while MMC/SD boot is retried. If UART boot fails, then GIO61 shall toggle at 2Hz while UART boot is retried. When boot is successful, just before program control is given to UBL, GIO61 is driven high (e.g. LED on) DM355 Timer0 shall be used to accurately toggle GIO61 at 4Hz and 2Hz ARM ROM Boot NAND Mode No support for a full firmware boot. Instead, copies a second stage user boot loader (UBL) from NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL. Support for NAND with page sizes up to 8192 bytes. Support for magic number error detection and retry (up to times) when loading UBL Support for up to 30KB UBL (32KB IRAM ~2KB for RBL stack) Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while loading UBL) Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported) Supports 4-bit ECC (1-bit ECC is not supported) Supports NAND flash that requires chip select to stay low during the tR read time ARM ROM Boot MMC/SD Mode No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from MMC/SD to ARm Internal RAM (AIM) and transfers control to the user software. Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported) Support for descriptor error detection and retry (up to times) when loading UBL Support for up to 30KB UBL (32KB ~2KB for RBL stack) ARM ROM Boot UART mode No support for a full firmware boot. Instead, loads a second stage user boot loader (UBL) via UART to ARM internal RAM (AIM) and transfers control to the user software. Support for up to 30KB UBL (32KB ~2KB for RBL stack) The general boot sequence is shown in Figure 3-6 For more information, refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 Submit Documentation Feedback Detailed Device

Boot□from NAND□flash Internal□ROM Boot□OK□? No Yes Boot□from UART Boot□from MMC/SD Boot□OK□? Boot□OK□? Yes No Invoke□loaded Program Invoke OneNAND No Yes 3.13 Power Management TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 3-6. Boot Mode Functional Block Diagram The DM355 is designed for minimal power consumption. There are two components to power consumption: active power and leakage power. Active power is the power consumed to perform work and scales with clock frequency and the amount of computations being performed. Active power can be reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to complete the required operation in the required timeline or to run at a clock setting until the work is complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be performed. Leakage power is due to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage power can only be avoided by removing power completely from a device or subsystem. The DM355 includes several power management 3-17. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 for more information on power management. Table 3-21. Power Management

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 3-21. Power Management (continued) Power Management a minimum. Registers and memory are preserved. I/O Management USB Phy power-down The USB Phy can be powered-down to reduce USB I/O power DAC power-down The DAC's can be powered-down to reduce DAC power DDR self-refresh and power down The DDR mDDR device can be put into self-refresh and power down states Submit Documentation Feedback Detailed Device

3.14 64-Bit Crossbar Architecture 3.14.1 Crossbar Connections 3.14.2 EDMA Controller TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 uses a 64-bit crossbar architecture to control access between device processors, subsystems and peripherals. It includes an EDMA Controller consisting of a DMA Transfer Controller (TC) and a DMA Channel Controller (CC). The TC provides two DMA channels for transfer between slave peripherals. The CC provides a user and event interface to the EDMA system. It includes up to event channels to which all system synchronization events can be mapped and auto submit quick channels (QDMA). In most ways, these channels are identical. A channel refers to a specific event that can cause a transfer to be submitted to the TC as a Transfer Request. There are five transfer masters (TCs have separate read and write connections) connected to the crossbar; ARM, the Video Processing Sub-system (VPSS), the master peripherals (USB), and two EDMA transfer controllers. These can be connected to four separate slave ports; ARM, the DDR EMIF, and CFG bus peripherals. Not all masters may connect to all slaves. Connection paths are indicated by at intersection points shown in Table 3-22 Table 3-22. Crossbar Connection Matrix Slave Module DMA Master ARM Internal MPEG4/JPEG Config Bus Registers and DDR EMIF Memory Memory Coprocessor Memory Memory ARM VPSS DMA Master Peripherals (USB) EDMA3TC0 EDMA3TC1 The EDMA controller handles all data transfers between memories and the device slave peripherals on the DM355 device. These are summarized as follows: Transfer to/from on-chip memories ARM program/data RAM MPEG4/JPEG Coprocessor memory Transfer to/from external storage DDR2 mDDR SDRAM Asynchronous EMIF OneNAND flash NAND flash Smart Media, SD, MMC, xD media storage Transfer to/from peripherals ASP SPI I2C PWM RTO GPIO Timer/WDT UART MMC/SD Detailed Device

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event interface for the EDMA system. The CC supports 64-event channels and QDMA channels. The CC consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering, channel-chaining, auto-reloading, and memory protection. The EDMA Channel Controller has the following features: Fully orthogonal transfer transfers: one dimension serviced per event AB- synchronized transfers: two dimensions serviced per event Independent indexes on source and destination Chaining feature allows 3-D transfer based on single event Flexible transfer definition Increment and constant addressing modes Linking mechanism allows automatic PaRAM set update Chaining allows multiple transfers to execute with one event Interrupt generation for: DMA completion Error conditions Debug visibility Queue watermarking/threshold Error and status recording to facilitate debug DMA channels Event synchronization Manual synchronization (CPU(s) write to event set register) Chain synchronization (completion of one transfer chains to next) QDMA channels QDMA channels are triggered automatically upon writing to a PaRAM set entry Support for programmable QDMA channel to PaRAM mapping 128 PaRAM sets Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining) Two transfer controllers/event queues. The system-level priority of these queues is user programmable event entries per event queue External events (for example, ASP TX Evt and RX Evt) The EDMA Transfer Controller has the following features: Two transfer controllers 64-bit wide read and write ports per channel Up to four in-flight transfer requests (TR) Programmable priority level Supports two dimensional transfers with independent indexes on source and destination (EDMA3CC manages the 3rd dimension) Support for increment and constant addressing modes Interrupt and error support Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in Parameter RAM (PaRAM) within the CC. DM355 provides 128 PaRAM entries, one for each of the DMA channels and for QDMA Linked DMA entries. Submit Documentation Feedback Detailed Device

3.14.2.1 EDMA Channel Synchronization Events TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com DMA Channels: Can be triggered by: External events (for example, ASP TX Evt and RX Evt), Software writing a '1' to the given bit location, or channel, of the Event Set register, or, Chaining to other DMAs. QDMA: The Quick DMA (QDMA) function is contained within the CC. DM355 implements QDMA channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer. A QDMA transfer is submitted immediately upon writing of the "trigger" parameter (as opposed to the occurrence of an event as with EDMA). The QDMA parameter RAM may be written by any Config bus master through the Config Bus and by DMAs through the Config Bus bridge. QDMA Channels: Triggered by a configuration bus write to a designated 'QDMA trigger word'. QDMAs allow a minimum number of linear writes (optimized for GEM IDMA feature) to be issued to the CC to force a series of transfers to take place. The EDMA supports up to EDMA channels which service peripheral devices and external memory. Table 3-23 lists the source of EDMA synchronization events associated with each of the programmable EDMA channels. For the DM355 device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320DM35x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRUEE4 Table 3-23. DM355 EDMA Channel Synchronization Events (1) (2) EDMA EVENT NAME EVENT TIMER3: TINT6 Timer Interrupt (TINT6) Event TIMER3 TINT7 Timer Interrupt (TINT7) Event ASP0: XEVT ASP0 Transmit Event ASP0: REVT ASP0 Receive Event VPSS: EVT1 VPSS Event VPSS: EVT2 VPSS Event VPSS: EVT3 VPSS Event VPSS: EVT4 VPSS Event ASP1: XEVT or TIMER2: ASP1 Transmit Event or Timer interrupt (TINT4) Event TINT4 ASP1: REVT or TIMER2: ASP1 Receive Event or Timer interrupt (TINT5) Event TINT5 SPI2: SPI2XEVT SPI2 Transmit Event SPI2: SPI2REVT SPI2 Receive Event Reserved Reserved SPI1: SPI1XEVT SPI1 Transmit Event SPI1: SPI1REVT SPI1 Receive Event SPI0: SPI0XEVT SP0I Transmit Event SPI0: SPI0REVT SPI0 Receive Event UART0: URXEVT0 UART Receive Event (1) In addition to the events shown in this table, each of the channels can also be synchronized with the transfer completion or intermediate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320DM35x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRUEE4 (2) The total number of EDMA events in DM355 exceeds 64, which is the maximum value of the EDMA module. Therefore, several events are multiplexed and you must use the register EDMA_EVTMUX in the System Control Module to select the event source for multiplexed events. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 for more information on the System Control Module register EDMA_EVTMUX. Detailed Device

3.15 MPEG4/JPEG Overview TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 3-23. DM355 EDMA Channel Synchronization Events (continued) EDMA EVENT NAME EVENT UART0: UTXEVT0 UART Transmit Event UART1: URXEVT1 UART Receive Event UART1: UTXEVT1 UART Transmit Event UART2: URXEVT2 UART Receive Event UART2: UTXEVT2 UART Transmit Event Reserved GPIO: GPINT9 GPIO Interrupt Event MMC0RXEVT MMC/SD0 Receive Event MMC0TXEVT MMC/SD0 Transmit Event I2CREVT I2C Receive Event I2CXEVT I2C Transmit Event MMC1RXEVT MMC/SD1 Receive Event MMC1TXEVT MMC/SD1 Transmit Event GPINT0 GPIO Interrupt Event GPINT1 GPIO Interrupt Event GPINT2 GPIO Interrupt Event GPINT3 GPIO Interrupt Event GPINT4 GPIO Interrupt Event GPINT5 GPIO Interrupt Event GPINT6 GPIO Interrupt Event GPINT7 GPIO Interrupt Event GPBNKINT0 GPIO Bank Interrupt Event GPBNKINT1 GPIO Bank Interrupt Event GPBNKINT2 GPIO Bank Interrupt Event GPBNKINT3 GPIO Bank Interrupt Event GPBNKINT4 GPIO Bank Interrupt Event GPBNKINT5 GPIO Bank Interrupt Event GPBNKINT6 GPIO Bank Interrupt Event GPINT8 GPIO Interrupt Event TIMER0: TINT0 Timer Interrupt Event TIMER0: TINT1 Timer Interrupt Event TIMER1: TINT2 Timer Interrupt Event TIMER1: TINT3 Timer Interrupt Event PWM0 PWM Event PWM1 PWM Event PWM2 PWM Event PWM3 PWM Event Reserved The DM355 supports the computational operations used for image processing, JPEG compression and MPEG4 video and imaging standard. Submit Documentation Feedback Detailed Device

4.1 Absolute Maximum Ratings Over Operating Case Temperature Range TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com (Unless Otherwise Noted) (1) (2) All 1.3 V supplies -0.5 V to 1.7 V All digital 1.8 V supplies -0.5 V to 2.5 V Supply voltage ranges All analog 1.8 V supplies -0.5 V to 1.89 V All 3.3 V supplies -0.5 V to 4.4 V All 1.8 V I/Os -0.5 V to 2.3 V Input voltage ranges All 3.3 V I/Os -0.5 V to 3.8 V VBUS 0.0 V to 5.5 V Clamp current for input or output (3) I clamp -20 mA to mA Commercial T c C to C Operating case temperature ranges Extended Temperature [A216 and A135 devices] T c -40 C to 100 C Storage temperature ranges T stg -65 C to 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to V SS. (3) Clamp current flows from an input or output pad to a supply rail through a clamp circuit or an intrinsic diode. Positive current results from an applied input or output voltage that is more than 0.5 V higher (more positive) than the supply voltage, V DD DDA_PLL1/2 DD_USB DD_DDR for dual-supply macros. Negative current results from an applied voltage that is more than 0.5 V less (more negative) than the V SS voltage.. Device Operating Conditions Submit Documentation Feedback

4.2 Recommended Operating Conditions TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 MIN NOM MAX UNIT CV DD Supply voltage, Core 1.235 1.3 1.365 V V DDA_PLL1 Supply voltage, PLL1 1.235 1.3 1.365 V V DDA_PLL2 Supply voltage, PLL2 1.235 1.3 1.365 V V DDD13_USB Supply voltage, USB Digital 1.235 1.3 1.365 V V DDA13_USB Supply voltage, USB Analog 1.235 1.3 1.365 V V DDA33_USB Supply voltage, USB Analog 3.135 3.3 3.465 V Supply Voltage V DDA33_USB_PLL Supply voltage, USB Common PLL 3.135 3.3 3.465 V V DD_DDR Supply voltage, DDR2 MDDR 1.71 1.8 1.89 V V DDA33_DDRDLL Supply voltage, DDR DLL Analog 3.135 3.3 3.465 V V DD_VIN Supply voltage, Digital video In 3.135 3.3 3.465 V V DD_VOUT Supply voltage, Digital Video Out 3.135 3.3 3.465 V V DDA18_DAC Supply voltage, DAC Analog 1.71 1.8 1.89 V V DD Supply voltage, I/Os 3.135 3.3 3.465 V V SS Supply ground, Core, USB Digital V V SSA_PLL1 Supply ground, PLL1 V V SSA_PLL2 Supply ground, PLL2 V V SS_USB Supply ground, USB V Supply Ground V SSA_DLL Supply ground, DLL V V SSA_DAC Supply ground, DAC Analog V V SS_MX1 MXI1 osc ground (1) V V SS_MX2 MXI2 osc ground (1) V Voltage Input High V IH High-level input voltage (2) V Voltage Input Low V IL Low-level input voltage (2) 0.8 V V REF DAC reference voltage 450 mV R BIAS DAC full-scale current adjust resistor 2550 Ω DAC (3) R LOAD Output resistor 499 Ω C BG Bypass capacitor 0.1 µ F R OUT Output resistor (ROUT), between TVOUT and VFB pins 1070 Ω R FB Feedback resistor, between VFB and IOUT pins. 1000 Video Buffer (3) R BIAS DAC full-scale current adjust resistor 2550 Ω C BG Bypass capacitor 0.1 µ A USB_VBUS USB external charge pump input 4.85 5.25 V USB USB reference resistor (4) 9.9 10.1 k Ω Commercial C Extended Temperature T c Operating case temperature range (A216 and -40 100 C A135 devices) (1) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (see Section 5.5.1 (2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec. (3) See Section 5.9.2.4 Also, resistors should be E-96 spec line digits with accuracy). (4) Connect USB_R1 to V SS_USB_REF via 10K ohm, resistor placed as close to the device as possible. Submit Documentation Feedback Device Operating Conditions

4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT V OH High-level output voltage (2) V DD =MIN, I OH =MAX 2.4 Voltage V Output V OL Low-level output voltage (2) V DD =MIN, I OL =MAX 0.6 Input current for I/O without I I V I V SS to V DD internal pull-up/pull-down Input current for I/O with I I(pullup) V I V SS to V DD 190 internal pull-up (3) (4) Input current for I/O with Current I I(pulldown) V I V SS to V DD -190 -40 µ A internal pull-down (3) (4) Input/Output I OH High-level output current -100 I OL Low-level output current 4000 V O V DD or V SS internal pull I OZ I/O off-state output current disabled C I Input capacitance Capacitance pF C O Output capacitance Resolution Resolution Bits R LOAD 499 Ω Video buffer INL Integral non-linearity, best fit LSB disabled DAC R LOAD 499 Ω Video buffer DNL Differential non-linearity 0.5 LSB disabled Compliance Output compliance range IFS 1.4 mA, R LOAD 499 Ω 0.700 V Output high voltage (top of V OH(VIDBUF) 1.55 75% NTSC or PAL colorbar) (5) Video Buffer V Output low voltage (bottom of V OL(VIDBUF) 0.470 sync tip) (1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. (2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec. (3) This specification applies only to pins with an internal pullup (PU) or pulldown (PD). See Section 2.4 or Section 2.5 for pin descriptions. (4) To pull up a signal to the opposite supply rail, a k Ω resistor is recommended. (5) 100% color bars are not supported. 100% color bars require 1.2 V peak-to-peak. The video buffer only provides 1.0 V peak-to-peak. Device Operating Conditions Submit Documentation Feedback

5.1 Parameter Information Device-Specific Information Transmission□Line 4.0□pF 1.85□pF Z0□=□50 Ω (see□note) Tester Pin□Electronics Data Sheet□Timing□Reference□Point Output Under Test 42 Ω 3.5□nH Device□Pin (see□note) 5.1.1 Signal Transition Levels Vref Vref =□VIL MAX□(or□VOL MAX) Vref =□VIH MIN□(or□VOH MIN) 5.1.2 Timing Parameters and Board Routing Analysis TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of Volts per nanosecond V/ns) at the device pin. Figure 5-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All input and output timing parameters are referenced to V ref for both "0" and "1" logic levels. For 3.3 V I/O, V ref 1.65 For 1.8 V I/O, V ref 0.9 Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V IL MAX and V IH MIN for input clocks, V OL MAX and V OH MIN for output clocks. Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.2 Recommended Clock and Control Signal Transition Behavior 5.3 Power Supplies TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 All clocks and control signals should transition between V IH and V IL (or between V IL and V IH in a monotonic manner. The power supplies of DM355 are summarized in Table 5-1 Table 5-1. Power Supplies Customer Tolerance Package Chip Plane 1.3 V 1.3 V CV DD Core V DD V DDA_PLL1 PLL1 V DDA V DDA_PLL2 PLL2 V DDA V DDD13_USB USB 1.3 V supply V DDA13_USB USB 1.3 V supply 3.3 V 3.3 V V DD IO V DD for LVCMOS V DDSHV V DD IO V DD for MXI/O1 V DDSHV V DD IO V DD for MXI/O2 V DDSHV1 V DD IO V DD for ISB DRVVBUS V DDSHV2 V DDA33_DDRDLL DDR DLL analog V DD V DDA33_USB Analog 3.3 V power USB PHY V DDA33_USB_PLL Common mode 3.3 V power for USB PHY (PLL) V DD IO V DD for peripherals 3.3 V 3.3 V V DD_VIN IO V DD for VideoIN I/F V DD_VOUT IO V DD for VideoOUT I/F 1.8 V 1.8 V V DD_DDR 1.8 V 1.8 V V DDA18 Analog 1.8 V power 1.8 V 1.8 V V DDA18_DAC Place decoupling caps (0.1 µ F/10 µ close to chip V n/a V V SS_MX1 Connect to external crystal capacitor ground V n/a V V SS_MX2 Connect to external crystal capacitor ground V n/a V V SS Chip ground USB ESD ground ground V SS V n/a V V SSA ground Keep separate from digital ground V SS V n/a V V SSA_PLL1 PLL1 V SSA V n/a V V SSA_PLL2 PLL2 V SSA V n/a V V SSA_DLL DLL ground V n/a V V SS_USB USB ground V SSA13_USB V SSA13_USB V SSA33_USB V SSA33_USB_PLL V n/a V V SS_USB_REF USB PHY reference ground V SSREF V n/a V V SSA_DAC DAC ground Keep separate from digital ground V SS V DDS *0.5 V DDS *0.5 V REFSSTL DRR ref voltage V DDS divided by through board resistors V V USB_VBUS VBUS Connect to external charge pump Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications

5.3.1 Power-Supply Sequencing 5.3.1.1 Power-Supply Design Considerations 5.3.1.2 Power-Supply Decoupling TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com In order to ensure device reliability, the DM355 requires the following power supply power-on and power-off sequences. See table Table 5-1 for a supplies. Power-On: Power on 1.3 CV DD V DDA_PLL1/2 V DDD13_USB V DDA13_USB Power on 1.8 V DD_DDR V DDA18_DAC Power on 3.3 D VDD V DDA33_DDRDLL V DDA33_USB V DDA33_USB_PLL V DD_VIN V DD_VOUT You may power-on the 1.8 V and 3.3 V power supplies simultaneously. Power-Off: Power off 3.3 D VDD V DDA33_DDRDLL V DDA33_USB V DDA33_USB_PLL V DD_VIN V DD_VOUT Power off 1.8 V DD_DDR V DDA18_DAC Power off 1.3 CV DD V DDA_PLL1/2 V DDD13_USB V DDA13_USB You may power-off the 1.8 V and 3.3 V power supplies simultaneously. Power-off the 1.8v/3.3V supply before or within 10usec of power-off of the 1.3 V supply. Note that when booting the DM355 from OneNAND, you must ensure that the OneNAND device is ready with valid program instructions before the DM355 attempts to read program instructions from it. In particular, before you release DM355 reset, you must allow time for OneNAND device power to stabilize and for the OneNAND device to complete its internal copy routine. During the internal copy routine, the OneNAND device copies boot code from its internal non-volatile memory to its internal boot memory section. Board designers typically achieve this requirement by design of the system power and reset supervisor circuit. Refer to your OneNAND device datasheet for OneNAND power ramp and stabilization times and for OneNAND boot copy times. Core and I/O supply voltage regulators should be located close to the DM355 to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance device, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors. In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible close to DM355. These caps need to be close to the DM355 power pins, no more than 1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small package) should be next closest. TI recommends no less than small and medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior". Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 µ should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint. Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product s production lifetime should be considered. See also Section 5.5.1 and Section 5.5.2 for additional recommendations on power supplies for the oscillator/PLL supplies. DM355 Peripheral Information and Electrical Specifications 100 Submit Documentation Feedback

5.4 Reset 5.4.1 Reset Electrical Data/Timing 2 3 RESET Boot□Configuration□Pins (BTSEL[1:0],□AECFG[3:0]) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-2. Timing Requirements for Reset (1) (2) (see Figure 5-4 DM355 NO. UNIT MIN MAX t w(RESET) Active low width of the RESET pulse 12C ns t su(BOOT) Setup time, boot configuration pins valid before RESET rising edge 12C ns t h(BOOT) Hold time, boot configuration pins valid after RESET rising edge 12C ns (1) BTSEL[1:0] and AECFG[4:0] are the boot configuration pins during device reset. (2) C MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is MHz use C 41. ns. Figure 5-4. Reset Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 101

5.5 Oscillators and Clocks 5.5.1 MXI1 (24-MHz) Oscillator Crystal 24□MHz□or 36□MHz C1 C2 MXI1/CLKIN MXO1 V SS_MX1 0.1 F 1 F VDDA_PLL1 VSSA_PLL1 CL C1C2 (C1 C2) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com DM355 has two oscillator input/output pairs (MXI1/MXO1 and MXI2/MXO2) usable with external crystals or ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are MHz (MXI1/MXO1) and MHz (MXI2/MXO2). Optionally, the oscillator inputs are configurable for use with external clock oscillators. If external clock oscillators are used, to minimize the clock jitter, a single clean power supply should power both the DM355 and the external oscillator circuit and the minimum CLKIN rise and fall times must be observed. The electrical requirements and characteristics are described in this section. The timing parameters for CLKOUT[3:1] are also described in this section. The DM355 has three output clock pins (CLKOUT[3:1]). See Section 3.5 and Section 3.6 for more information on CLKOUT[3:1]. The MXI1 (typically MHz, can also be MHz) oscillator provides the primary reference clock for the DM355 device. The on-chip oscillator requires an external crystal connected across the MXI1 and MXO1 pins, along with two load capacitors, as shown in Figure 5-5 The external crystal load capacitors must be connected only to the oscillator ground pin SS_MX1 Do not connect to board ground SS Also, the PLL power pin DDA_PLL1 should be connected to the power supply through a ferrite bead, in the example circuit shown in Figure 5-5 Figure 5-5. MXI1 (24-MHz) Oscillator The load capacitors, and C2, should be chosen such that the equation is satisfied (typical values are pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (MXI1 and MXO1) and to the V SS_MX1 pin. 102 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator) Crystal 27□MHz C1 C2 MXI2 MXO2 V SS_MX2 VDDA_PLL2 VSSA_PLL2 0.1 F 1 F CL C1C2 (C1 C2) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-3. Switching Characteristics Over Recommended Operating Conditions for 24-MHz System Oscillator PARAMETER MIN TYP MAX UNIT Start-up time (from power up until oscillating at stable frequency) ms Oscillation frequency or MHz ESR Ω Frequency stability +/-50 ppm The MXI2 (27 MHz) oscillator provides an optional reference clock for the DM355's VPSS module. The on-chip oscillator requires an external 27-MHz crystal connected across the MXI2 and MXO2 pins, along with two load capacitors, as shown in Figure 5-6 The external crystal load capacitors must be connected only to the 27-MHz oscillator ground pin SS_MX2 Do not connect to board ground SS Also, the PLL power pin DDA_PLL2 should be connected to the power supply through a ferrite bead, in the example circuit shown in Figure 5-6 Figure 5-6. MXI2 (27-MHz) System Oscillator The load capacitors, and C2, should be chosen such that the equation is satisfied (typical values are pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (MXI and MXO) and to the V SS_MX2 pin. Table 5-4. Switching Characteristics Over Recommended Operating Conditions for 27-MHz System Oscillator PARAMETER MIN TYP MAX UNIT Start-up time (from power up until oscillating at stable frequency) ms Oscillation frequency MHz ESR Ω Frequency stability +/-50 ppm Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 103

5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks) MXI/CLKIN 5 1 MXI/CLKIN 5 1 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-5. Timing Requirements for MXI1/CLKIN1 (1) (2) (see Figure 5-7 DM355 NO UNIT MIN TYP MAX t c(MXI1) Cycle time, MXI1/CLKIN1 27. (3) 41. (3) ns t w(MXI1H) Pulse duration, MXI1/CLKIN1 high 0.45C 0.55C ns t w(MXI1L) Pulse duration, MXI1/CLKIN1 low 0.45C 0.55C ns t t(MXI1) Transition time, MXI1/CLKIN1 0.05C ns t J(MXI1) Period jitter, MXI1/CLKIN1 0.02C ns (1) The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN. (2) C MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is MHz use C 41. ns. (3) tc(MXI1) 41. ns and tc(MXI1) 27. ns are the only supported cycle times for MXI1/CLKIN1. Figure 5-7. MXI1/CLKIN1 Timing Table 5-6. Timing Requirements for MXI2/CLKIN2 (1) (2) (see Figure 5-7 NO. DM355 UNIT MIN TYP MAX t c(MXI2) Cycle time, MXI2/CLKIN2 37. 037 (3) 37. 037 (3) ns t w(MXI2H) Pulse duration, MXI2/CLKIN2 high 0.45C 0.55C ns t w(MXI2L) Pulse duration, MXI2/CLKIN2 low 0.45C 0.55C ns t t(MXI2) Transition time, MXI2/CLKIN2 0.05C ns t J(MXI2) Period jitter, MXI2/CLKIN2 0.02C ns (1) The reference points for the rise and fall transitions are measured at V IL MAX and V IH MIN. (2) C MXI2/CLKIN2 cycle time in ns. For example, when MXI2/CLKIN2 frequency is MHz use C 37. 037 ns. (3) tc(MXI2) 37. 037 ns is the only supported cycle time for MXI2/CLKIN2. Figure 5-8. MXI2/CLKIN2 Timing 104 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1 (1) (2) (see Figure 5-9 DM355 UNI NO. PARAMETER T MIN TYP MAX t C(CLKOUT1) Cycle time, CLKOUT1 t c(MXI1) ns t w(CLKOUT1H) Pulse duration, CLKOUT1 high 0.45P 0.55P ns t w(CLKOUT1L) Pulse duration, CLKOUT1 low 0.45P 0.55P ns t t(CLKOUT1) Transition time, CLKOUT1 0.05P ns t d(MXI1H- Delay time, MXI1/CLKIN1 high to CLKOUT1 high ns CLKOUT1H) t d(MXI1L- Delay time, MXI1/CLKIN1I low to CLKOUT1 low ns CLKOUT1L) (1) The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN. (2) P 1/CLKOUT1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is MHz use P 41. ns. Figure 5-9. CLKOUT1 Timing Table 5-8. Switching Characteristics Over Recommended Operating Conditions for CLKOUT2 (1) (2) (see Figure 5-10 DM355 NO. PARAMETER UNIT MIN TYP MAX t C(CLKOUT2) Cycle time, CLKOUT2 t c(MXI1) t w(CLKOUT2H) Pulse duration, CLKOUT2 high 0.45P 0.55P ns t w(CLKOUT2L) Pulse duration, CLKOUT2 low 0.45P 0.55P ns t t(CLKOUT2) Transition time, CLKOUT2 0.05P ns t d(MXI1H- Delay time, MXI1/CLKIN1 high to CLKOUT2 high ns CLKOUT2H) t d(MXI1L- Delay time, MXI1/CLKIN1 low to CLKOUT2 low ns CLKOUT2L) (1) The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN. (2) P 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is MHz use P 125 ns. Figure 5-10. CLKOUT2 Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 105

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (1) (2) (see Figure 5-11 DM355 NO. PARAMETER UNIT MIN TYP MAX t C(CLKOUT3) Cycle time, CLKOUT3 t c(MXI1) t w(CLKOUT3H) Pulse duration, CLKOUT3 high 0.45P 0.55P ns t w(CLKOUT3L) Pulse duration, CLKOUT3 low 0.45P 0.55P ns t t(CLKOUT3) Transition time, CLKOUT3 0.05P ns t d(MXI2H- Delay time, CLKIN/MXI high to CLKOUT3 high ns CLKOUT3H) t d(MXI2L- Delay time, CLKIN/MXI low to CLKOUT3 low ns CLKOUT3L) (1) The reference points for the rise and fall transitions are measured at V OL MAX and V OH MIN. (2) P 1/CLKOUT3 clock frequency in nanoseconds (ns). For example, when CLKOUT3 frequency is MHz use P 333. ns. Figure 5-11. CLKOUT3 Timing 106 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.6 General-Purpose Input/Output (GPIO) 5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs. When configured as an output, a write to an internal register can control the state driven on the output pin. When configured as an input, the state of the input is detectable by reading the state of an internal register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices. The GPIO pins are grouped into banks of pins per bank (i.e., bank consists of GPIO [0:15]). There are a total of GPIO banks in the DM355, because the DM355 has 104 GPIOs. The DM355 GPIO peripheral supports the following: Up to 104 3.3v GPIO pins, GPIO[103:0] Interrupts: Up to unique GPIO[9:0] interrupts from Bank Up to GPIO (bank aggregated) interrupt signals, one from each of the banks of GPIOs Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO signal DMA events: Up to unique GPIO DMA events from Bank Up to GPIO (bank aggregated) DMA event signals, one from each of the banks of GPIOs Set/clear functionality: Firmware writes to corresponding bit position(s) to set or to clear GPIO signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to anther process during GPIO programming). Separate Input/Output registers Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can be toggled by direct write to the output register(s). Output register, when read, reflects output drive status. This, in addition to the input register reflecting pin status and open-drain I/O cell, allows wired logic be implemented. For more detailed information on GPIOs, see the TMS320DM35x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRUEE6 Table 5-10. Timing Requirements for GPIO Inputs (see Figure 5-12 DM355 NO. UNIT MIN MAX t w(GPIH) Pulse duration, GPIx high ns t w(GPIL) Pulse duration, GPIx low ns Table 5-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 5-12 DM355 NO. PARAMETER UNIT MIN MAX t w(GPOH) Pulse duration, GPOx high (1) ns t w(GPOL) Pulse duration, GPOx low (1) ns (1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 107

5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing EXT_INTx TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 5-12. GPIO Port Timing Table 5-12. Timing Requirements for External Interrupts/EDMA Events (1) (see Figure 5-13 DM355 NO. UNIT MIN MAX t w(ILOW) Width of the external interrupt pulse low ns t w(IHIGH) Width of the external interrupt pulse high ns (1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have DM355 to recognize the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow DM355 enough time to access the GPIO register through the internal bus. Figure 5-13. GPIO External Interrupt Timing 108 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.7 External Memory Interface (EMIF) 5.7.1 Asynchronous EMIF (AEMIF) 5.7.1.1 NAND (NAND, SmartMedia, xD) 5.7.1.2 OneNAND TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 DM355 supports several memory and external device interfaces, including: Asynchronous EMIF (AEMIF) for interfacing to SRAM. OneNAND flash memories NAND flash memories DDR2/mDDR Memory Controller for interfacing to SDRAM. The EMIF supports the following features: SRAM, etc. on up to asynchronous chip selects addressable up to 64KB each Supports 8-bit or 16-bit data bus widths Programmable asynchronous cycle timings Supports extended wait mode Supports Select Strobe mode The NAND follows: NAND flash on up to asynchronous chip selects and 16-bit data bus widths Programmable cycle timings Performs 1-bit and 4-bit ECC calculation NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory cards The OneNAND follows. NAND flash on up to asynchronous chip selects Only 16-bit data bus widths Supports asynchronous writes and reads Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads with wrap burst modes) Programmable cycle timings for each chip select in asynchronous mode Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 109

5.7.1.3 AEMIF Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module (1) (see Figure 5-14 and Figure 5-15 DM355 NO UNIT MIN Nom MAX READS and WRITES Pulse duration, EM_WAIT assertion and t w(EM_WAIT) ns deassertion READS t su(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high ns t h(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high ns t su (EMOEL- Setup time EM_WAIT asserted before EM_OE ns EMWAIT) high (2) READS (OneNAND Synchronous Burst Read) Setup time, EM_D[15:0] valid before EM_CLK t su(EMDV-EMCLKH) ns high t h(EMCLKH-EMDIV) Hold time, EM_D[15:0] valid after EM_CLK high ns WRITES t su (EMWEL- Setup time, EM_WAIT asserted before EM_WE ns EMWAIT) high (2) (1) E PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example, when PLLC output clock 432 MHz, E 9.259 ns. See Section 3.5 for more information. (2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 5-16 and Figure 5-17 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (1) (2) (3) (see Figure 5-14 and Figure 5-15 DM355 UNI NO. PARAMETER T MIN Nom MAX READS and WRITES t d(TURNAROUND) Turn around time (TA)*E ns READS EMIF read cycle time (EW (RS+RST+RH)*E ns t c(EMRCYCLE) (RS+RST+RH+(EWC* EMIF read cycle time (EW ns 16))*E Output setup time, EM_CE[1:0] low to (RS)*E ns EM_OE low (SS t su(EMCEL-EMOEL) Output setup time, EM_CE[1:0] low to ns EM_OE low (SS Output hold time, EM_OE high to (RH)*E ns EM_CE[1:0] high (SS t h(EMOEH-EMCEH) Output hold time, EM_OE high to ns EM_CE[1:0] high (SS (1) TA Turn around, RS Read setup, RST Read strobe, RH Read hold, WS Write setup, WST Write strobe, WH Write hold, MEWC Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (literature number SPRUED1 for more information. (2) E PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example, when PLLC output clock 432 MHz, E 9.259 ns. See Section 3.5 for more information (3) EWC external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (literature number SPRUED1 for more information. 110 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15 (continued) DM355 UNI NO. PARAMETER T MIN Nom MAX Output setup time, EM_BA[1:0] valid to t su(EMBAV-EMOEL) (RS)*E ns EM_OE low Output hold time, EM_OE high to t h(EMOEH-EMBAIV) (RH)*E ns EM_BA[1:0] invalid Output setup time, EM_A[13:0] valid to t su(EMBAV-EMOEL) (RS)*E ns EM_OE low Output hold time, EM_OE high to t h(EMOEH-EMAIV) (RH)*E ns EM_A[13:0] invalid EM_OE active low width (EW (RST)*E ns t w(EMOEL) EM_OE active low width (EW (RST+(EWC*16))*E ns t d(EMWAITH- Delay time from EM_WAIT deasserted to ns EMOEH) EM_OE high READS (OneNAND Synchronous Burst Read) MH f c(EM_CLK) Frequency, EM_CLK z t c(EM_CLK) Cycle time, EM_CLK 1000 ns t su(EM_ADVV- Output setup time, EM_ADV valid before ns EM_CLKH) EM_CLK high t h(EM_CLKH- Output hold time, EM_CLK high to EM_ADV ns EM_ADVIV) invalid t su(EM_AV- Output setup time, EM_A[13:0]/EM_BA[1] ns EM_CLKH) valid before EM_CLK high t h(EM_CLKH- Output hold time, EM_CLK high to ns EM_AIV) EM_A[13:0]/EM_BA[1] invalid t w(EM_CLKH) Pulse duration, EM_CLK high t c(EM_CLK) ns t w(EM_CLKL) Pulse duration, EM_CLK low t c(EM_CLK) ns WRITES EMIF write cycle time (EW (WS+WST+WH)*E ns t c(EMWCYCLE) (WS+WST+WH+(EW EMIF write cycle time (EW ns C*16))*E Output setup time, EM_CE[1:0] low to (WS)*E ns EM_WE low (SS t su(EMCEL-EMWEL) Output setup time, EM_CE[1:0] low to ns EM_WE low (SS Output hold time, EM_WE high to (WH)*E ns EM_CE[1:0] high (SS t h(EMWEH-EMCEH) Output hold time, EM_WE high to ns EM_CE[1:0] high (SS Output setup time, EM_BA[1:0] valid to t su(EMBAV-EMWEL) (WS)*E ns EM_WE low Output hold time, EM_WE high to t h(EMWEH-EMBAIV) (WH)*E ns EM_BA[1:0] invalid Output setup time, EM_A[13:0] valid to t su(EMAV-EMWEL) (WS)*E ns EM_WE low Output hold time, EM_WE high to t h(EMWEH-EMAIV) (WH)*E ns EM_A[13:0] invalid EM_WE active low width (EW (WST)*E ns t w(EMWEL) EM_WE active low width (EW (WST+(EWC*16))*E ns t d(EMWAITH- Delay time from EM_WAIT deasserted to ns EMWEH) EM_WE high Output setup time, EM_D[15:0] valid to t su(EMDV-EMWEL) (WS)*E ns EM_WE low Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 111

EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_OE EM_D[15:0] EM_WE EM_CE[1:0] EM_BA[1:0] EM_A[13:0] EM_WE EM_D[15:0] EM_OE TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15 (continued) DM355 UNI NO. PARAMETER T MIN Nom MAX Output hold time, EM_WE high to t h(EMWEH-EMDIV) (WH)*E ns EM_D[15:0] invalid Figure 5-14. Asynchronous Memory Read Timing for EMIF Figure 5-15. Asynchronous Memory Write Timing for EMIF DM355 Peripheral Information and Electrical Specifications 112 Submit Documentation Feedback

EM_CE[1:0] Asserted Deasserted EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_OE EM_WAIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD EM_CE[1:0] Asserted Deasserted EM_BA[1:0] EM_A[13:0] EM_D[15:0] EM_WE EM_W AIT SETUP STROBE Extended Due to EM_WAIT STROBE HOLD TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 5-16. EM_WAIT Read Timing Requirements Figure 5-17. EM_WAIT Write Timing Requirements Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 113

Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+n Da+n+1 EM_CLK EM_CE[1:0] EM_ADV EM_BA0, EM_A[13:0], EM_BA1 EM_D[15:0] EM_OE EM_WAIT TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 5-18. Synchronous OneNAND Flash Read Timing 114 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.7.2 DDR2/mDDR Memory Controller 5.7.2.1 DDR2/mDDR Memory Controller Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The DDR2 mDDR Memory Controller is a dedicated interface to DDR2 mDDR SDRAM. It supports JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices. DDR2 mDDR SDRAM plays a key role in a DM355-based system. Such a system is expected to require a significant amount of high-speed external memory for all of the following functions: Buffering of input image data from sensors or video sources Intermediate buffering for processing/resizing of image data in the VPFE Numerous OSD display buffers Intermediate buffering for large raw Bayer data image files while performing image processing functions Buffering for intermediate data while performing video encode and decode functions Storage of executable code for the ARM The DDR2 mDDR Memory Controller supports the following features: JESD79D-2A standard compliant DDR2 SDRAM Mobile DDR SDRAM 256 MByte memory space Data bus width bits CAS latencies: DDR2: and mDDR: and Internal banks: DDR2: and mDDR: and Burst length: Burst type: sequential CS signal Page sizes: 256, 512, 1024, and 2048 SDRAM autoinitialization Self-refresh mode Partial array self-refresh (for mDDR) Power down mode Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters Little endian For details on the DDR2 Memory Controller, refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) DDR2/mDDR Memory Controller Reference Guide (literature number SPRUEH7 The Implementing DDR2/mDDR PCB Layout on the TMS320DM35x DMSoC Application Report (literature number SPRAAR3 specifies a complete DDR2 and mDDR interface solution for the DM355 as well as a list of compatible DDR2/mDDR devices. TI has performed the simulation and system characterization to ensure all DDR2 and mDDR interface timings in this solution are met. TI only supports board designs that follow the guidelines outlined in the Implementing DDR2/mDDR PCB Layout on the TMS320DM35x DMSoC Application Report (literature number SPRAAR3 Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 115

5.8 MMC/SD 5.8.1 MMC/SD Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 includes two separate MMC/SD Controllers which are compliant with MMC V3.31, Secure Digital Part Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V1.0 specifications. The DM355 MMC/SD Controller has following features: MultiMediaCard (MMC). Secure Digital (SD) Memory Card. MMC/SD protocol support. SDIO protocol support. Programmable clock frequency. 256 bit Read/Write FIFO to lower system overhead. Slave EDMA transfer capability. The DM355 MMC/SD Controller does not support SPI mode. Table 5-15. Timing Requirements for MMC/SD Module (see Figure 5-20 and Figure 5-22 DM355 NO. FAST MODE STANDARD MODE UNIT MIN MAX MIN MAX t su(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK high ns t h(CLKH-CMDV) Hold time, SD_CMD valid after SD_CLK high 2.5 (1) ns t su(DATV-CLKH) Setup time, SD_DATx valid before SD_CLK high ns t h(CLKH-DATV) Hold time, SD_DATx valid after SD_CLK high 2.5 ns (1) For this parameter, you may include margin in your board design so that the toh 2.5 ns of the MMC/SD device is not degraded at the DM355 input pin. Table 5-16. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see Figure 5-19 through Figure 5-22 DM355 STANDARD NO. PARAMETER FAST MODE UNIT MODE MIN MAX MIN MAX f (CLK) Operating frequency, SD_CLK MHz f (CLK_ID) Identification mode frequency, SD_CLK 400 400 KHz t W(CLKL) Pulse width, SD_CLK low ns t W(CLKH) Pulse width, SD_CLK high ns t r(CLK) Rise time, SD_CLK ns t f(CLK) Fall time, SD_CLK ns t d(CLKL- Delay time, SD_CLK low to SD_CMD transition -7.5 -7.5 ns CMD) t d(CLKL-DAT) Delay time, SD_CLK low to SD_DATx transition -7.5 -7.5 ns DM355 Peripheral Information and Electrical Specifications 116 Submit Documentation Feedback

ST ART XMIT V alid Valid Valid END SD_CLK SD_CMD 13 13 13 ST ART XMIT V alid Valid Valid END SD_CLK SD_CMD 1097 ST ART D0 D1 Dx END SD_CLK SD_DA Tx 1414 14 14 Start D0 D1 Dx End SD_CLK SD_DA Tx 3 3 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 5-19. MMC/SD Host Command Timing Figure 5-20. MMC/SD Card Response Timing Figure 5-21. MMC/SD Host Write Timing Figure 5-22. MMC/SD Host Read and Card CRC Status Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 117

5.9 Video Processing Sub-System (VPSS) Overview 5.9.1 Video Processing Front-End (VPFE) 5.9.1.1 CCD Controller (CCDC) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 contains a Video Processing Sub-System (VPSS) that provides an input interface (Video Processing Front End or VPFE) for external imaging peripherals such as image sensors, video decoders, etc.; and an output interface (Video Processing Back End or VPBE) for display devices, such as analog SDTV displays, digital LCD panels, HDTV video encoders, etc. In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure efficient use of the DDR2 burst bandwidth. The shared buffer logic/memory is a unique block that is tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the primary source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from/to DDR2. In order to efficiently utilize the external DDR2 bandwidth, the shared buffer logic/memory interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer logic/memory also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared buffer logic/memory (divided into the read write buffers and arbitration logic) is capable of performing the following functions. It is imperative that the VPSS utilize DDR2 bandwidth efficiently due to both its large bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible to configure the VPSS modules in such a way that DDR2 bandwidth is exceeded, a set of user accessible registers is provided to monitor overflows or failures in data transfers. The VPFE or Video Processing Front-End block is comprised of the CCD Controller (CCDC), Image Pipe (IPIPE), and Hardware Statistic Generator (H3A). These modules are described in the sections that follow. The CCDC is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or CCD). In addition, the CCDC can accept YUV video data in numerous formats, typically from so-called video decoder devices. In the case of raw inputs, the CCDC output requires additional image processing to transform the raw input image to the final processed image. This processing can be done either on-the-fly in the Preview Engine hardware ISP or in software on the ARM and MPEG4/JPEG coprocessor subsystems. In parallel, raw data input to the CCDC can also used for computing various statistics (3A, Histogram) to eventually control the image/video tuning parameters. The CCDC is programmed via control and parameter registers. DM355 performance is enhanced by its dedicated hard-wired MPEG4/JPEG coprocessor (MJCP). The MJCP performs all the computational operations required for JPEG and MPEG4 compression. These operations can be invoked using the xDM (xDIAS for Digital Media) APIs. For more information, refer to the xDIAS-DM (xDIAS for Digital Media) User's Guide (literature number SPRUEC8 The following module. Support for conventional Bayer pattern. Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the external timing generator. Support for progressive and interlaced sensors (hardware support for up to fields and firmware support for higher number of fields, typically 3-, 4-, and 5-field sensors). Support for up to 75-MHZ sensor pixel clock if H3A is not used, otherwise the pixel clock must be less than 67.5 MHZ Support for ITU-R BT.656 standard format, either 8-bit or 16-bit. Support for YCbCr 422 format, either or 16-bit with discrete HSYNC and VSYNC signals. Support for up to 14-bit input. Support for color space conversion Generates optical black clamping signals. Support for shutter signal control. Support for digital clamping and black level compensation. Fault pixel correction based on a lookup table that contains row and column position of the pixel to be DM355 Peripheral Information and Electrical Specifications 118 Submit Documentation Feedback

5.9.1.2 IPIPE Image Pipe TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 corrected. Support for program lens shading correction. Support for 10-bit to 8-bit A-law compression. Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, pixels each in the left and right edges of each line are cropped from the output. Support for generating output to range from 14-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area). Support for down sampling via programmable culling patterns. Ability to control output to the DDR2 via an external write enable signal. Support for up to 32K pixels (image size) in both the horizontal and vertical direction. The hardware Image Pipe (IPIPE) is a programmable hardware image processing module that is responsible for transforming raw (unprocessed) image/video data from a sensor (CMOS or CCD) into YCbCr 422 data that is amenable for compression or display. The IPIPE can also be configured to operate in a resize only mode, which allows YCbCr 422 to be resized without applying the processing of every module in the IPIPE. Typically, the output of the IPIPE is used for both video compression and displaying it on an external display device such as a NTSC/PAL analog encoder or a digital LCD. The IPIPE is programmed via control and parameter registers. The following IPIPE. The input interface extracts valid raw data from the CCD raw data, and then various modules in IPIPE process the raw CCD data. The noise filter module reduces impulse noise in the raw data and adjusts the resolution of the input image. The pre-filter adjusts the resolution of the input image and remove line crawl noise. The white balance module applies two gain adjustments to the data: a digital gain (total gain) and a white balance gain. The Color Filter Array (CFA) interpolation module implements CFA interpolation. The output from the CFA interpolation module is always RGB formatted data. The RGB2RGB blending module applies a 3x3 matrix transform to the RGB data generated by the CFA interpolation module. The gamma correction module independently applies gamma correction to each RGB component. Gamma is implemented using a piece-wise linear interpolation approach with a 512 entry look up table for each color. The RGB2YCbCr conversion module applies 3x3 matrix transformation to the RGB data to convert it to YCbCr data. This module also implements offset. The 4:2:2 conversion module applies the chroma low pass filter and down samples Cb and Cr, so that IPIPE output data is in YCbCr-4:2:2 format. The edge enhancer module improves image clarity with luminance non-linear filter. This module also has contrast and brightness adjustment functions. The chroma suppression module reduces faulty-color using luminance (Y) value or high-pass-filtering Y value. The H-resizer and V-resizer modules resize horizontal and vertical image sizes, respectively. The output interface module transfers data from IPIPE to SDRAM, in the form of YCbCr-422 or RGB (32bit/16bit). The histogram function can record histograms of up to distinct areas into up to 256 bins. IPIPE has three different processing paths: Case The CCD raw data directly leads to IPIPE and stores the YCbCr (or RGB) data to SDRAM. Case IPIPE reads CCD raw data and stores the Bayer pattern data after white balance to SDRAM. Case IPIPE reads YCbCr-422 data and apply edge enhance, chroma suppression and Resize to output YCbCr (or RGB) data to SDRAM. Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 119

5.9.1.3 Hardware (H3A) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the various parameters for processing the imaging/video data. There are main blocks in the H3A module: Auto Focus (AF) engine Auto Exposure (AE) Auto White Balance (AWB) engine The AF engine extracts and filters the red, green, and blue data from the input image/video data and provides either the accumulation or peaks of the data in a specified region. The specified region is a two-dimensional block of data and is referred to as a "paxel" for the case of AF. The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a "window". Thus, other than referring them by different names, a paxel and a window are essentially the same thing. However, the number, dimensions, and starting position of the AF paxels and the AE/AWB windows are separately programmable. The following engine: Support for input from DDR2 mDDR SDRAM (in addition to the CCDC port) Support for a Peak Mode in a Paxel Paxel is defined as a two dimensional block of pixels). Accumulate the maximum Focus Value of each line in a Paxel Support for an Accumulation/Sum Mode (instead of Peak mode). Accumulate Focus Value in a Paxel. Support for up to Paxels in the horizontal direction and up to 128 Paxels in the vertical direction. The number of horizontal paxels is limited by the memory size (and cost), while the vertical number of paxels is not. Therefore, the number of paxels in horizontal direction is smaller than the number of paxels in vertical direction. Programmable width and height for the Paxel. All paxels in the frame will be of same size. Programmable red, green, and blue position within a 2x2 matrix. Separate horizontal start for paxel and filtering. Programmable vertical line increments within a paxel. Parallel IIR filters configured in a dual-biquad configuration with individual coefficients filters with coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on. The following engine: Support for input from DDR2 mDDR SDRAM (in addition to the CCDC port) Accumulate clipped pixels along with all non-saturated pixels Support for up to horizontal windows. Support for up to 128 vertical windows. Programmable width and height for the windows. All windows in the frame will be of same size. Separate vertical start co-ordinate and height for a black row of paxels that is different than the remaining color paxels. Programmable Horizontal Sampling Points in a window Programmable Vertical Sampling Points in a window DM355 Peripheral Information and Electrical Specifications 120 Submit Documentation Feedback

5.9.1.4 VPFE Electrical Data/Timing PCLK TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (1) (see Figure 5-23 NO. MIN MAX UNIT H3A not used 13.33 or P (2) 100 ns t c(PCLK) Cycle time, PCLK H3A used 100 ns t w(PCLKH) Pulse duration, PCLK high 5.7 ns t w(PCLKL) Pulse duration, PCLK low 5.7 ns t t(PCLK) Transition time, PCLK ns (1) P 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 135 MHz, use P 7.41 ns. See Section 3.5 Device Clocking for more information on the supported clock configurations of the DM355. (2) Use whichever value is greater. Figure 5-23. VPFE PCLK Timing Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24 DM355 NO. UNIT MIN MAX t su(CCDV-PCLK) Setup time, CCD valid before PCLK edge ns t h(PCLK-CCDV) Hold time, CCD valid after PCLK edge ns t su(HDV-PCLK) Setup time, HD valid before PCLK edge ns t h(PCLK-HDV) Hold time, HD valid after PCLK edge ns t su(VDV-PCLK) Setup time, VD valid before PCLK edge ns t h(PCLK-VDV) Hold time, VD valid after PCLK edge ns t su(CAM_WEN_FIELD Setup time, CAM_WEN_FIELD valid before PCLK edge ns V-PCLK) t h(CAM_WEN_FIELDV Hold time, C_WEN_FIELD valid after PCLK edge ns -PCLK) Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 121

(Positive□Edge□Clocking) PCLK (Negative□Edge□Clocking) 7,□9 HD/VD CI[7:0]/YI[7:0]/ CCD[13:0] 8,□10 CAM_WEN_FIELD PCLK (Positive□Edge□Clocking) 15 16 23 24 CI[7:0]/YI[7:0]/ CCD[13:0] CAM_WEN_FIELD PCLK (Positive□Edge□Clocking) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing Table 5-19. Timing Requirements for VPFE (CCD) Master Mode (1) (see Figure 5-25 DM355 NO. UNIT MIN MAX t su(CCDV-PCLK) Setup time, CCD valid before PCLK edge ns t h(PCLK-CCDV) Hold time, CCD valid after PCLK edge ns t su(CAM_WEN_FIELD Setup time, CAM_WEN_FIELD valid before PCLK edge ns V-PCLK) t h(PCLK- Hold time, CAM_WEN_FIELD valid after PCLK edge ns CAM_WEN_FIELDV) (1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced. Figure 5-25. VPFE (CCD) Master Mode Input Data Timing 122 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

(Positive□Edge□Clocking) HD VD PCLK (Negative□Edge□Clocking) 5.9.2 Video Processing Back-End (VPBE) 5.9.2.1 On-Screen Display (OSD) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-20. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master Mode (see Figure 5-26 DM355 NO. PARAMETER UNIT MIN MAX t d(PCLKL-HDIV) Delay time, PCLK edge to HD invalid ns t d(PCLKL-VDIV) Delay time, PCLK edge to VD invalid ns Figure 5-26. VPFE (CCD) Master Mode Control Output Data Timing The Video Processing Back-End of VPBE module is comprised of the On Screen Display (OSD) module and the Video Encoder Digital LCD Controller (VENC/DLCD). The primary function of the OSD module is to gather and blend video data and display/bitmap data and then pass it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from external DDR2/mDDR memory. The OSD is programmed via control and parameter registers. The following are the primary OSD. Support for two video windows and two OSD bitmapped windows that can be displayed simultaneously (VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1). Video windows supports YCbCr data in 422 format from external memory, with the ability to interchange the order of the CbCr component in the 32-bit word OSD bitmap windows support /4/8 bit width index data of color palette In addition one OSD bitmap window at a time can be configured to one of the following: YUV422 (same as video data) RGB format data in 16-bit mode (R=5bit, G=6bit, B=5bit) 24-bit mode (each R/G/B=8bit) with pixel level blending with video windows Programmable color palette with the ability to select between a RAM/ROM table with support for 256 colors. Support for ROM tables, one of which can be selected at a given time Separate enable/disable control for each window Programmable width, height, and base starting coordinates for each window External memory address and offset registers for each window Support for and zoom in both the horizontal and vertical direction Pixel-level blending/transparency/blinking attributes can be defined for OSDWIN0 when OSDWIN1 is configured as an attribute window for OSDWIN0. Support for blinking intervals to the attribute window Ability to select either field/frame mode for the windows (interlaced/progressive) An eight step blending process between the bitmap and video windows Transparency support for the bitmap and video data (when a bitmap pixel is zero, there will be no Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 123

5.9.2.2 Video Encoder Digital LCD Controller (VENC/DLCD) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com blending for that corresponding video pixel) Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows Horizontal rescaling x1.5 is supported Support for a rectangular cursor window and a programmable background color selection. The width, height, and color of the cursor is selectable The display priority is: Rectangular-Cursor OSDWIN1 OSDWIN0 VIDWIN1 VIDWIN0 background color Support for attenuation of the YCbCr values for the REC601 standard. The following restrictions exist in the OSD module. If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 720 currently. This is due to the limitation in the size of the line memory. It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM while another uses ROM. The VENC/DLCD consists of three major blocks; the video encoder that generates analog video output, the digital LCD controller that generates digital RGB/YCbCr data output and timing signals, and the timing generator. The video encoder for analog video supports the following features: Master Clock Input MHz (x2 Upsampling) Programmable Timing Generator SDTV Support Composite NTSC-M, PAL-B/D/G/H/I Non-Interlace option CGMS/WSS Line Closed Caption Data Encoding Chroma Low Pass Filter 1.5MHz/3MHz Programmable SC-H phase 10-bit Over-Sampling D/A Converter (27MHz) Internal analog video buffer Optional 7.5% Pedestal 16-235/0-255 Input Amplitude Selectable Programmable Luma Delay Master/Slave Operation Internal Color Bar Generation (75%) The digital LCD controller supports the following features: Programmable DCLK Programmable Timing Generator Various Output Format YCbCr 16bit YCbCr 8bit ITU-R BT. 656 Parallel RGB 16-bit/18-bit Serial 8-bit RGB Low Pass Filter for Digital RGB Output Master/Slave Operation DM355 Peripheral Information and Electrical Specifications 124 Submit Documentation Feedback

5.9.2.3 VPBE Electrical Data/Timing PCLK 56 4 EXTCLK TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Internal Color Bar Generation (100%/75%) YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27 DM355 NO. UNIT MIN MAX t c(PCLK) Cycle time, PCLK (1) 13.33 160 ns t w(PCLKH) Pulse duration, PCLK high 5.7 ns t w(PCLKL) Pulse duration, PCLK low 5.7 ns t t(PCLK) Transition time, PCLK ns t c(EXTCLK) Cycle time, EXTCLK 13.33 160 ns t w(EXTCLKH) Pulse duration, EXTCLK high 5.7 ns t w(EXTCLKL) Pulse duration, EXTCLK low 5.7 ns t t(EXTCLK) Transition time, EXTCLK ns (1) For timing specifications relating to PCLK see Table 5-17 Timing Requirements for VPFE PCLK Master/Slave Mode Figure 5-27. VPBE PCLK and EXTCLK Timing Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK (1) (2) (3) (see Figure 5-28 DM355 NO. UNIT MIN MAX t su(VCTLV-VCLKIN) Setup time, VCTL valid before VCLKIN edge ns t h(VCLKIN-VCTLV) Hold time, VCTL valid after VCLKIN edge ns (1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced. (2) VCTL HSYNC, VSYNC, and FIELD (3) VCLKIN PCLK or EXTCLK Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 125

VCLKIN(A) (Positive Edge Clocking) VCLKIN(A) (Negative Edge Clocking) VCTL(B) A. VCLKIN□=□PCLK□or□EXTCLK B. VCTL□=□HSYNC,□VSYNC,□and□FIELD VCLKIN(A) (Positive Edge Clocking) VCLKIN(A) (Negative Edge Clocking) 1 1 VCTL(B) A. VCLKIN□=□PCLK□or□EXTCLK B. VCTL□=□HSYNC,□VSYNC,□FIELD,□and□LCD_OE C. VDATA□□=□COUT[7:0],□YOUT[7:0],□R[7:3],□G[7:2],□and□B[7:3] VDA T A (C) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to PCLK and EXTCLK (1) (2) (3) (see Figure 5-29 DM355 NO. PARAMETER UNIT MIN MAX t d(VCLKIN-VCTLV) Delay time, VCLKIN edge to VCTL valid 13.3 ns t d(VCLKIN-VCTLIV) Delay time, VCLKIN edge to VCTL invalid ns t d(VCLKIN-VDATAV) Delay time, VCLKIN edge to VDATA valid 13.3 ns t d(VCLKIN-VDATAIV) Delay time, VCLKIN edge to VDATA invalid ns (1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced. (2) VCLKIN PCLK or EXTCLK (3) VCTL HSYNC, VSYNC, FIELD, and LCD_OE Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK 126 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

(Positive Edge Clocking) VCLK (Negative Edge Clocking) VCTL(B) VDA T A(C) 1822 23 24 25 26 VCLKIN(A) A. VCLKIN□=□PCLK□or□EXTCLK B. VCTL□=□HSYNC,□VSYNC,□FIELD,□and□LCD_OE C. VDATA□□=□COUT[7:0],□YOUT[7:0],□R[7:3],□G[7:2],□and□B[7:3] 2020 5.9.2.4 DAC and Video Buffer Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and Data Output With Respect to VCLK (1) (2) (see Figure 5-30 DM355 NO. PARAMETER UNIT MIN MAX t c(VCLK) Cycle time, VCLK 13.33 160 ns t w(VCLKH) Pulse duration, VCLK high 5.7 ns t w(VCLKL) Pulse duration, VCLK low 5.7 ns t t(VCLK) Transition time, VCLK ns t d(VCLKINH-VCLKH) Delay time, VCLKIN high to VCLK high ns t d(VCLKINL-VCLKL) Delay time, VCLKIN low to VCLK low ns t d(VCLK-VCTLV) Delay time, VCLK edge to VCTL valid ns t d(VCLK-VCTLIV) Delay time, VCLK edge to VCTL invalid ns t d(VCLK-VDATAV) Delay time, VCLK edge to VDATA valid ns t d(VCLK-VDATAIV) Delay time, VCLK edge to VDATA invalid ns (1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced. (2) VCLKIN PCLK or EXTCLK. For timing specifications relating to PCLK, see Table 5-17 Timing Requirements for VPFE PCLK Master/Slave Mode Figure 5-30. VPBE Control and Data Output Timing With Respect to VCLK The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer configuration. In the DAC only configuration the internal video buffer is not used and an external video buffer is attached to the DAC. In the DAC and video buffer configuration, the DAC and internal video buffer are both used and a TV cable may be attached directly to the output of the video buffer. See Figure 5-31 and Figure 5-32 for recommenced circuits for each configuration. Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 127

DIN□<9:0> MSB LSB DAC□Digital□Input Example□for□External□Circuit Iout□[mA] 1.4□mA DAC□Output□Current CBG

0.1 F/c109

Video□DAC RBIAS 2550/c87 IBIAS RLOAD 499/c87 IOUT Buffer VFB TVOUT TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Connect IOUT to a high-impedance video buffer device. Place capacitors and resistors as close as possible to the DM355. Configure the VDAC_CONFIG register in the system control module as follows: DINV PWD_GBZ PWD_VBUFZ ACCUP_EN See the TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 and the TMS320DM35x Digital Media System-on-Chip Video Processing Back End (VPBE) Reference Guide (literature number SPRUF72 for more information on VDAC_CONFIG. Figure 5-31. DAC Only Application Example 128 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

DIN□<9:0> DAC□Digital□Input CBG Video□DAC□and□Buffer RBIAS 2550 Ω IBIAS Rfb = 1000 Ω IOUT VFB TVOUT Rout =□□1070 Ω TV□monitor TVOUT□[V] Video□Buffer□Output□Voltage MSB LSB VOL(VIDBUF) VOH(VIDBUF) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Place capacitors and resistors as close as possible to the DM355. You must use the circuit shown in this diagram. Also you must configure the VDAC_CONFIG register in the System Control module as follows: TRESB4R4 0x3, TRESB4R2 0x8, TRESB4R1 0x8, TRIMBITS 0x34, PWD_BGZ (power up VREF), SPEED (faster), TVINT don't care, PWD_VBUFZ (power up video buffer), VREFSET don't care, ACCUP_EN (no A/C coupling), DINV (invert). See TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFB3 and the TMS320DM35x Digital Media System-on-Chip Video Processing Back End (VPBE) Reference Guide (literature number SPRUF72 for more information on the VDAC_CONFIG register and Video Buffer. For proper TVOUT voltage, you must connect the pin TVOUT directly to the TV. No A/C coupling capacitor or termination resistor is necessary on your DM355 board. Also, it is assumed that the TV has no internal A/C coupling capacitor but does have an internal termination resistor, as shown in this diagram. TVOUT voltage will range from V OL(VIDBUF) to V OH(VIDBUF) See Section 4.3 for the voltage specifications. Figure 5-32. DAC With Buffer Circuit Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 129

5.10 USB 2.0 5.10.1 USB2.0 Electrical Data/Timing tr tf VCRS 90%□VOH 10%□VOL USB_DM USB_DP tper − tjr TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 USB2.0 peripheral supports the following features: USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: Mb/s) USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s) All transfer modes (control, bulk, interrupt, and isochronous) Four Transmit (TX) and four Receive (RX) endpoints in addition to endpoint FIFO RAM bytes shared by all endpoints. Programmable FIFO size Includes a DMA sub-module that supports four TX and four RX channels of CPPI 3.0 DMAs RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB USB OTG extensions, i.e. session request protocol (SRP) and host negotiation protocol (HNP) The DM355 USB2.0 peripheral does not support the following features: On-chip charge pump High bandwidth ISO mode is not supported (triple buffering) RNDIS mode acceleration for USB sizes that are not multiples of bytes Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 16, 32, 64, and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined) Table 5-25. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see Figure 5-33 DM355 LOW SPEED FULL SPEED HIGH SPEED (1) NO. PARAMETER UNIT 1.5 Mbps Mbps 480 Mbps MIN MAX MIN MAX MIN MAX t r(D) Rise time, USB_DP and USB_DM signals (2) 300 0.5 ns t f(D) Fall time, USB_DP and USB_DM signals (2) 300 0.5 ns t frfm Rise/Fall time, matching (3) 125 111.11 V CRS Output signal cross-over voltage (2) 1.3 1.3 V t jr(source)NT Source (Host) Driver jitter, next transition ns t jr(FUNC)NT Function Driver jitter, next transition ns t jr(source)PT Source (Host) Driver jitter, paired transition (4) ns t jr(FUNC)PT Function Driver jitter, paired transition ns t w(EOPT) Pulse duration, EOP transmitter 1250 1500 160 175 ns t w(EOPR) Pulse duration, EOP receiver 670 ns t (DRATE) Data Rate 1.5 480 Mb/s Z DRV Driver Output Resistance 49.5 40.5 49.5 Ω (1) For more detailed specification information, see the Universal Serial Bus Specification Revision 2.0, Chapter Electrical. (2) Low Speed: C L 200 pF, Full Speed: C L pF, High Speed: C L pF (3) t frfm r f x 100. [Excluding the first transaction from the Idle state.] (4) t jr t px(1) t px(0) Figure 5-33. USB2.0 Integrated Transceiver Interface Timing DM355 Peripheral Information and Electrical Specifications 130 Submit Documentation Feedback

VSS_USB_REF USB_R1 USB 10□K ±1%Ω TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 5-34. USB Reference Resistor Routing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 131

5.11 Universal Asynchronous Receiver/Transmitter (UART) 5.11.1 UART Electrical Data/Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 contains separate UART modules with hardware flow control). These modules performs serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial conversion on data received from the CPU. Each UART also includes a programmable baud rate generator capable of dividing the 24MHz reference clock by divisors from to 65,535 to produce a x clock driving the internal logic. The UART modules support the following features: Frequency pre-scale values from to 65,535 to generate appropriate baud rates 16-byte storage space for both the transmitter and receiver FIFOs Unique interrupts, one for each UART Unique EDMA events, both received and transmitted data for each UART or byte selectable receiver FIFO trigger level for autoflow control and DMA Programmable auto-rts and auto-cts for autoflow control (supported on UART2) Programmable serial data formats or 8-bit characters Even, odd, or no parity bit generation and detection 1.5, or stop bit generation False start bit detection Line break generation and detection Internal diagnostic capabilities Loopback controls for communications link fault isolation Break, parity, overrun, and framing error simulation Modem control functions: CTS, RTS (supported on UART2) Table 5-26. Timing Requirements for UARTx Receive (see Figure 5-35 DM355 NO. UNIT MIN MAX t w(URXDB) Pulse duration, receive data bit (RXDn) 0.99U (1) 1.05U (1) ns t w(URXSB) Pulse duration, receive start bit 0.99U (1) 1.05U (1) ns (1) U UART baud time 1/programmed baud rate. Table 5-27. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see Figure 5-35 DM355 NO. PARAMETER UNIT MIN MAX UART0/1 Maximum programmable baud rate 1.5 f (baud) MHz UART2 Maximum programmable baud rate t w(UTXDB) Pulse duration, transmit data bit (TXDn) U (1) U (1) ns t w(UTXSB) Pulse duration, transmit start bit U (1) U (1) ns (1) U UART baud time 1/programmed baud rate. DM355 Peripheral Information and Electrical Specifications 132 Submit Documentation Feedback

Data□Bits UART_TXDn UART_RXDn Data□Bits Bit Start TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 5-35. UART Transmit/Receive Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 133

5.12 Serial Port Interface (SPI) 5.12.1 SPI Electrical Data/Timing SPIx_CLK (Clock□Polarity□=□0) SPIx_CLK (Clock□Polarity□=□1) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 contains separate SPI modules. These modules provide a programmable length shift register which allows serial communication with other SPI devices through a or wire interface (Clock, Data In, Data Out, and Enable). The SPI supports the following features: Master mode operation chip selects for interfacing to multiple slave SPI devices. or wire interface (Clock, Data In, Data Out, and Enable) Unique interrupt for each SPI port Separate DMA events for SPI Receive and Transmit 16-bit shift register Receive buffer register Programmable character length to bits) Programmable SPI clock frequency range 8-bit clock prescaler Programmable clock phase (delay or no delay) Programmable clock polarity The SPI modules do not support the following features: Slave mode. Only Master mode is supported in DM355 (Master mode means that DM355 provides the serial clock). GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are multiplexed with GPIO signals. Table 5-28. Timing Requirements for SPI (All Modes) (1) (see Figure 5-36 DM355 NO. UNIT MIN MAX t c(CLK) Cycle time, SPI_CLK 37. 037 ns ns t w(CLKH) Pulse duration, SPI_CLK high (All Master Modes) 0.45*T 0.55*T ns t w(CLKL) Pulse duration, SPI_CLK low (All Master Modes 0.45*T 0.55*T ns (1) T t c(CLK) SPI_CLK period is equal to the SPI module clock divided by a configurable divider. Figure 5-36. SPI_CLK Timing DM355 Peripheral Information and Electrical Specifications 134 Submit Documentation Feedback

SPI_CLK (Clock□Polarity□=□0) SPI_CLK (Clock□Polarity□=□1) SPI_DI (Input) SPI_DO (Output) MSB□IN DATA LSB□IN LSB□OUTMSB□OUT DATA SPI_EN TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 SPI Master Mode Timings (Clock Phase Table 5-29. Timing Requirements for SPI Master Mode [Clock Phase (1) (see Figure 5-37 DM355 NO. UNIT MIN MAX Setup time, SPI_DI (input) valid before SPI_CLK (output) t su(DIV-CLKL) Clock Polarity .5P ns falling edge Setup time, SPI_DI (in put) valid before SPI_CLK (output) t su(DIV-CLKH) Clock Polarity .5P ns rising edge Hold time, SPI_DI (input) valid after SPI_CLK (output) falling t h(CLKL-DIV) Clock Polarity .5P ns edge Hold time, SPI_DI (input) valid after SPI_CLK (output) rising t h(CLKH-DIV) Clock Polarity 2.5P ns edge (1) P 1/SYSCLK2 in nanoseconds (ns). For example, if the SYSCLK2 frequency is 135 MHz, use P 7.41 ns. See Section 3.5 Device Clocking for more information on the supported clock configurations of the DM355. Table 5-30. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase (see Figure 5-37 DM355 NO. PARAMETER UNIT MIN MAX Delay time, SPI_CLK (output) rising edge to SPI_DO t d(CLKH-DOV) Clock Polarity ns (output) transition Delay time, SPI_CLK (output) falling edge to SPI_DO t d(CLKL-DOV) Clock Polarity ns (output) transition Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling t d(ENL-CLKH/L) (1) (1) ns edge P+.5C t d(CLKH/L-ENH) Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output) rising edge (2) ns (1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (literature number SPRUED4 (2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (literature number SPRUED4 Figure 5-37. SPI Master Mode External Timing (Clock Phase Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 135

SPI_CLK (Clock□Polarity□=□0) SPI_CLK (Clock□Polarity□=□1) SPI_DI (Input) SPI_DO (Output) MSB□IN DATA LSB□IN LSB□OUTMSB□OUT DATA SPI_EN TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com SPI Master Mode Timings (Clock Phase Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase (see Figure 5-38 DM355 NO. UNIT MIN MAX Setup time, SPI_DI (input) valid before SPI_CLK (output) t su(DIV-CLKL) Clock Polarity .5P ns rising edge Setup time, SPI_DI (in put) valid before SPI_CLK (output) t su(DIV-CLKH) Clock Polarity .5P ns falling edge Hold time, SPI_DI (input) valid after SPI_CLK (output) rising t h(CLKL-DIV) Clock Polarity .5P ns edge Hold time, SPI_DI (input) valid after SPI_CLK (output) falling t h(CLKH-DIV) Clock Polarity .5P ns edge Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode [Clock Phase (see Figure 5-38 DM355 NO. PARAMETER UNIT MIN MAX Delay time, SPI_CLK (output) falling edge to SPI_DO t d(CLKL-DOV) Clock Polarity ns (output) transition Delay time, SPI_CLK (output) rising edge to SPI_DO t d(CLKH-DOV) Clock Polarity ns (output) transition Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling 2P+.5C t d(ENL-CLKH/L) (1) ns edge (1) t d(CLKL/H-DOHz) Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance P (2) (2) ns (1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (literature number SPRUED4 (2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface (SPI) User's Guide (literature number SPRUED4 Figure 5-38. SPI Master Mode External Timing (Clock Phase 136 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.13 Inter-Integrated Circuit (I2C) TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The inter-integrated circuit (I2C) module provides an interface between DM355 and other devices compliant with Philips Semiconductors Inter-IC bus C-bus) specification version 2.1 and connected by way of an I C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DM355 through the I2C module. The I2C port supports: Compatible with Philips I2C Specification Revision 2.1 (January 2000) Fast Mode up to 400 Kbps (no fail-safe I/O buffers) Noise Filter to Remove Noise ns or less Seven- and Ten-Bit Device Addressing Modes Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality Events: DMA, Interrupt, or Polling Slew-Rate Limited Open-Drain Output Buffers For more detailed information on the I2C peripheral, see the TMS320DM35x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C) Peripheral Reference Guide (literature number SPRUEE0 Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 137

5.13.1 I2C Electrical Data/Timing 5.13.1.1 Inter-Integrated Circuits (I2C) Timing 6 14 Stop Start Repeated Start Stop SDA SCL 1 1 9 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-33. Timing Requirements for I2C Timings (1) (see Figure 5-39 DM355 STANDARD NO. FAST MODE UNIT MODE MIN MAX MIN MAX t c(SCL) Cycle time, SCL 2.5 µ s Setup time, SCL high before SDA low (for a repeated START t su(SCLH-SDAL) 4.7 0.6 µ s condition) Hold time, SCL low after SDA low (for a START and a repeated t h(SCLL-SDAL) 0.6 µ s START condition) t w(SCLL) Pulse duration, SCL low 4.7 1.3 µ s t w(SCLH) Pulse duration, SCL high 0.6 µ s t su(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100 (2) ns t h(SDA-SCLL) Hold time, SDA valid after SCL low (For I C bus devices) (3) (3) 0.9 (4) µ s Pulse duration, SDA high between STOP and START t w(SDAH) 4.7 1.3 µ s conditions t r(SDA) Rise time, SDA 1000 0.1C b (5) 300 ns t r(SCL) Rise time, SCL 1000 0.1C b (5) 300 ns t f(SDA) Fall time, SDA 300 0.1C b (5) 300 ns t f(SCL) Fall time, SCL 300 0.1C b (5) 300 ns t su(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 0.6 µ s t w(SP) Pulse duration, spike (must be suppressed) ns C b (5) Capacitive load for each bus line 400 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. (2) A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t su(SDA-SCLH) 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r max t su(SDA-SCLH) 1000 250 1250 ns (according to the Standard-mode I C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum t h(SDA-SCLL) has only to be met if the device does not stretch the low period w(SCLL) of the SCL signal. (5) C b total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Figure 5-39. I2C Receive Timings DM355 Peripheral Information and Electrical Specifications 138 Submit Documentation Feedback

(DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-34. Switching Characteristics for I2C Timings (1) (see Figure 5-40 DM355 STANDARD NO. PARAMETER FAST MODE UNIT MODE MIN MAX MIN MAX t c(SCL) Cycle time, SCL 2.5 µ s Delay time, SCL high to SDA low (for a repeated START t d(SCLH-SDAL) 4.7 0.6 µ s condition) Delay time, SDA low to SCL low (for a START and a repeated t d(SDAL-SCLL) 0.6 µ s START condition) t w(SCLL) Pulse duration, SCL low 4.7 1.3 µ s t w(SCLH) Pulse duration, SCL high 0.6 µ s t d(SDAV-SCLH) Delay time, SDA valid to SCL high 250 100 ns t v(SCLL-SDAV) Valid time, SDA valid after SCL low (For I2C devices) 0.9 µ s Pulse duration, SDA high between STOP and START t w(SDAH) 4.7 1.3 µ s conditions t d(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 0.6 µ s C p Capacitance for each I2C pin pF (1) C b total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. CAUTION The DM355 I C pins use a standard 4-mA LVCMOS buffer, not the slow I/OP buffer defined in the I C specification. Series resistors may be necessary to reduce noise at the system level. Figure 5-40. I2C Transmit Timings Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 139

5.14 Audio Serial Port (ASP) TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com DM355 includes two separate ASP controllers. The primary use for the audio serial port (ASP) is for audio interface purposes. The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port receive and transmit operation, but is not intended to be used as a high-speed interface. The ASP is backward compatible with other TI ASPs. The ASP supports the following features: Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit External shift clock generation or an internal programmable frequency shift clock Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability is provided) Direct interface to IIS compliant devices Direct interface to SPI protocol in master mode only A wide selection of data sizes, including 12, 16, 20, 24, and bits µ -Law and A-Law companding 8-bit data transfers with the option of LSB or MSB first Programmable polarity for both frame synchronization and data clocks Highly programmable internal clock and frame generation For more detailed information on the ASP peripheral, see the TMS320DM35x Digital Media System-on-Chip (DMSoC) Audio Serial Port (ASP) Reference Guide (literature number SPRUED3 140 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.14.1 ASP Electrical Data/Timing 5.14.1.1 Audio Serial Port (ASP) Timing TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-35. Timing Requirements for ASP (1) (see Figure 5-41 DM355 NO. UNIT MIN MAX tc(CLK) Cycle time, CLK CLK ext 38.5 or (2) (3) ns OTG(CLKS) Pulse duration, CLKR/X high or CLKR/X low CLKS ext 19.25 or P (2) (3) (4) ns CLKR int t su(FRH-CKRL) Setup time, external FSR high before CLKR low ns CLKR ext CLKR int t h(CKRL-FRH) Hold time, external FSR high after CLKR low ns CLKR ext CLKR int t su(DRV-CKRL) Setup time, DR valid before CLKR low ns CLKR ext CLKR int t h(CKRL-DRV) Hold time, DR valid after CLKR low ns CLKR ext CLKX int t su(FXH-CKXL) Setup time, external FSX high before CLKX low ns CLKX ext CLKX int t h(CKXL-FXH) Hold time, external FSX high after CLKX low ns CLKX ext (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 (3) Use which ever value is greater. (4) The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met. Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 141

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP (1) (2) (see Figure 5-41 DM355 NO. PARAMETER UNIT MIN MAX t c(CKRX) Cycle time, CLKR/X CLKR/X int 38.5 or (3) (4) (5) ns td(CLKS-CLKRX) Delay time, CLKS high to internal CLKR/X CLKR/X int t w(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C (6) C (6) ns CLKR int t d(CKRH-FRV) Delay time, CLKR high to internal FSR valid ns CLKR ext CLKX int t d(CKXH-FXV) Delay time, CLKX high to internal FSX valid ns CLKX ext CLKX int ns tdis(CKXH- Disable time, DX high impedance following last data DXHZ) bit from CLKX high CLKX ext ns CLKX int ns t d(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext ns Delay time, FSX high to DX valid FSX int t d(FXH-DXV) ONLY applies when in data ns FSX ext delay (XDATDLY 00b) mode (1) CLKRP CLKXP FSRP FSXP If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) Minimum delay times also represent minimum output hold times. (3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements. (4) P (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 (5) Use which ever value is greater. (6) C H or L S sample rate generator input clock P if CLKSM 1/SYSCLK2, where SYSCLK2 is an output of PLLC1 (see Section 3.5 S sample rate generator input clock CLKS if CLKSM H CLKX high pulse width (CLKGDV/2 S if CLKGDV is even H (CLKGDV 1)/2 S if CLKGDV is odd or zero L CLKX low pulse width (CLKGDV/2) S if CLKGDV is even L (CLKGDV 1)/2 S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit (see footnote (3) above). DM355 Peripheral Information and Electrical Specifications 142 Submit Documentation Feedback

Bit(n-1) (n-2) (n-3) Bit□0 Bit(n-1) (n-2) (n-3) 13(A) 13(A) A. Parameter□No.□13□applies□to□the□first□data□bit only when□XDA TDLY≠ 0. CLKR FSR□(int) FSR□(ext) DR CLKX FSX□(int) FSX□(ext) FSX (XDATDLY=00b) DX CLKS TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Figure 5-41. ASP Timing Table 5-37. ASP as SPI Timing Requirements CLKSTP 10b, CLKXP (see Figure 5-42 MASTER NO. UNIT MIN MAX M30 t su(DRV-CKXL) Setup time, DR valid before CLKX low ns M31 t h(CKXL-DRV) Hold time, DR valid after CLKX low ns Table 5-38. ASP as SPI Switching Characteristics (1) (2) CLKSTP 10b, CLKXP (see Figure 5-42 MASTER NO. PARAMETER UNIT MIN MAX 38.5 or M33 tc(CKX) Cycle time, CLKX ns (1) (3) M24 t d(CKXL-FXH) Delay time, CLKX low to FSX high (2) T T ns M25 t d(FXL-CKXH) Delay time, FSX low to CLKX high (4) L L ns M26 t d(CKXH-DXV) Delay time, CLKX high to DX valid ns M27 t dis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L L ns (1) P (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 (2) T CLKX period CLKGDV) L CLKX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) when CLKGDV is even (3) Use which ever value is greater. (4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 143

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M31M30 M26M27 M25M24 CLKX FSX DX DR M33 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 5-42. ASP as SPI: CLKSTP 10b, CLKXP 144 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M39 M36M38M37 M35M34 CLKX FSX DX DR M40 M42 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-39. ASP as SPI Timing Requirements CLKSTP 11b, CLKXP MASTER NO. UNIT MIN MAX M39 t su(DRV-CKXH) Setup time, DR valid before CLKX high ns M40 t h(CKXH-DRV) Hold time, DR valid after CLKX high ns Table 5-40. ASP as SPI Switching Characteristics (1) (2) CLKSTP 11b, CLKXP (see Figure 5-43 MASTER NO. PARAMETER UNIT MIN MAX 38.5 or M42 tc(CKX) Cycle time, CLKX ns (1) (3) M34 t d(CKXL-FXH) Delay time, CLKX low to FSX high (4) L L ns M35 t d(FXL-CKXH) Delay time, FSX low to CLKX high (5) T T ns M36 t d(CKXL-DXV) Delay time, CLKX low to DX valid ns Disable time, DX high impedance following last data bit from M37 t dis(CKXL-DXHZ) ns CLKX low M38 t d(FXL-DXV) Delay time, FSX low to DX valid H H ns (1) P (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 (2) T CLKX period CLKGDV) L CLKX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) when CLKGDV is even H CLKX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 when CLKGDV is even (3) Use which ever value is greater. (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM FSXM CLKRM FSRM for master ASP (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 5-43. ASP as SPI: CLKSTP 11b, CLKXP Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 145

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M50M49 M45M46 M44M43 CLKX FSX DX DR M52 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-41. ASP as SPI Timing Requirements CLKSTP 10b, CLKXP (see Figure 5-44 MASTER NO. UNIT MIN MAX M49 t su(DRV-CKXH) Setup time, DR valid before CLKX high ns M50 t h(CKXH-DRV) Hold time, DR valid after CLKX high ns Table 5-42. ASP as SPI Switching Characteristics (1) (2) CLKSTP 10b, CLKXP (see Figure 5-44 MASTER NO. PARAMETER UNIT MIN MAX 38.5 or M52 tc(CKX) Cycle time, CLKX ns (1) (3) M43 t d(CKXH-FXH) Delay time, CLKX high to FSX high (4) T T ns M44 t d(FXL-CKXL) Delay time, FSX low to CLKX low (5) H H ns M45 t d(CKXL-DXV) Delay time, CLKX low to DX valid ns Disable time, DX high impedance following last data bit from M46 t dis(CKXH-DXHZ) H H ns CLKX high (1) P (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 (2) T CLKX period CLKGDV) H CLKX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 when CLKGDV is even (3) Use which ever value is greater. (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM FSXM CLKRM FSRM for master ASP (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 5-44. ASP as SPI: CLKSTP 10b, CLKXP DM355 Peripheral Information and Electrical Specifications 146 Submit Documentation Feedback

Bit□0 Bit(n-1) (n-2) (n-3) (n-4) Bit□0 Bit(n-1) (n-2) (n-3) (n-4) M59M58 M55M57M56 M54M53 CLKX FSX DX DR M62 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-43. ASP as SPI Timing Requirements CLKSTP 11b, CLKXP (see Figure 5-45 MASTER NO. UNIT MIN MAX M58 t su(DRV-CKXL) Setup time, DR valid before CLKX low ns M59 t h(CKXL-DRV) Hold time, DR valid after CLKX low ns Table 5-44. ASP as SPI Switching Characteristics (1) (2) CLKSTP 11b, CLKXP (see Figure 5-45 MASTER NO. PARAMETER UNIT MIN MAX 38.5 or M62 tc(CKX) Cycle time, CLKX ns (3) (3) M53 t d(CKXH-FXH) Delay time, CLKX high to FSX high (4) H H ns M54 t d(FXL-CKXL) Delay time, FSX low to CLKX low (5) T T ns M55 t d(CKXL-DXV) Delay time, CLKX low to DX valid ns Disable time, DX high impedance following last data bit from M56 t dis(CKXH-DXHZ) ns CLKX high M57 t d(FXL-DXV) Delay time, FSX low to DX valid L L ns (1) P (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 (2) T CLKX period CLKGDV) L CLKX low pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2) when CLKGDV is even H CLKX high pulse width T/2 when CLKGDV is odd or zero and (CLKGDV/2 when CLKGDV is even (3) Use which ever value is greater. (4) FSRP FSXP As a SPI master, FSX is inverted to provide active-low slave-enable output. CLKXM FSXM CLKRM FSRM for master ASP (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 5-45. ASP as SPI: CLKSTP 11b, CLKXP Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 147

5.15 Timer 5.15.1 Timer Electrical Data/Timing TIM_IN TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The DM355 contains four software-programmable timers. Timer Timer and Timer (general-purpose timers) can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode. Timer supports additional timers: external clock/event input, period reload, output event tied to Real Time Out (RTO) module, external event capture, and timer counter register read reset. Timer is used only as a watchdog timer. Timer is tied to device reset. 64-bit count-up counter Timer modes: 64-bit general-purpose timer mode (Timer Dual 32-bit general-purpose timer mode (Timer Watchdog timer mode (Timer Two possible clock sources: Internal clock External clock/event input via timer input pins (Timer Three possible operation modes: One-time operation (timer runs for one period then stops) Continuous operation (timer automatically resets after each period) Continuous operation with period reload (Timer Generates interrupts to the ARM CPU Generates sync event to EDMA Generates output event to device reset (Timer Generates output event to Real Timer Out (RTO) module (Timer External event capture via timer input pins (Timer For more detailed information, see the TMS320DM355 DMSoC 64-bit Timer User's Guide for more information (literature number SPRUEE5 Table 5-45. Timing Requirements for Timer Input (1) (2) (3) (see Figure 5-46 DM355 NO. UNIT MIN MAX t c(TIN) Cycle time, TIM_IN ns t w(TINPH) Pulse duration, TIM_IN high 0.45C 0.55C ns t w(TINPL) Pulse duration, TIM_IN low 0.45C 0.55C ns t t(TIN) Transition time, TIM_IN 0.05C ns (1) GPIO000, GPIO001, GPIO002, and GPIO003 can be used as external clock inputs for Timer See the TMS320DM355 DMSoC 64-bit Timer User's Guide for more information (literature number SPRUEE5 (2) P MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is MHz use P 41. ns. (3) C TIM_IN cycle time in ns. For example, when TIM_IN frequency is MHz use C 41. ns Figure 5-46. Timer Input Timing DM355 Peripheral Information and Electrical Specifications 148 Submit Documentation Feedback

5.16 Pulse Width Modulator (PWM) 5.16.1 PWM0/1/2/3 Electrical/Timing Data PWM0/1/2/3 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The DM355 contains separate Pulse Width Modulator (PWM) modules. The pulse width modulator (PWM) feature is very common in embedded systems. It provides a way to generate a pulse periodic waveform for motor control or can act as a digital-to-analog converter with some external components. This PWM peripheral is basically a timer with a period counter and a first-phase duration comparator, where bit width of the period and first-phase duration are both programmable. The Pulse Width Modulator (PWM) modules support the following features: 32-bit period counter 32-bit first-phase duration counter 8-bit repeat count for one-shot operation. One-shot operation will produce N periods of the waveform, where N is the repeat counter value. Configurable to operate in either one-shot or continuous mode Buffered period and first-phase duration registers One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or high-to-low). One-shot operation triggerable by the CCD VSYNC output of the video processing subsystem (VPSS), which allows any of the PWM instantiations to be used as a CCD timer. This allows the DM355 module to support the functions provided by the CCD timer feature (generating strobe and shutter signals). One-shot operation generates N+1 periods of waveform, N being the repeat count register value Configurable PWM output pin inactive state Interrupt and EDMA synchronization events Table 5-46. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2/3 Outputs (1) (see Figure 5-47 and Figure 5-48 DM355 NO. PARAMETER UNIT MIN MAX t w(PWMH) Pulse duration, PWMx high P ns t w(PWML) Pulse duration, PWMx low P ns t t(PWM) Transition time, PWMx .05P ns t d(CCDC-PWMV) Delay time, CCDC(VD) trigger event to PWMx valid ns (1) P MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is MHz use P 41. ns. Figure 5-47. PWM Output Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 149

VD(CCDC) INV ALID INV ALID INV ALID VALID V ALID VALID PWM0 PWM1 PWM2 INV ALID VALIDPWM3 TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Figure 5-48. PWM Output Delay Timing DM355 Peripheral Information and Electrical Specifications 150 Submit Documentation Feedback

5.17 Real Time Out (RTO) 5.17.1 RTO Electrical/Timing Data RTO0/1/2/3 TINT12/TINT34 (Timer3) INV ALID INV ALID INV ALID V ALID VALID V ALID RTO0 INV ALID V ALID RTO1 RTO2 RTO3 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 The DM355 Real Time Out (RTO) peripheral supports the following features: Four separate outputs Trigger on Timer3 event Table 5-47. Switching Characteristics Over Recommended Operating Conditions for RTO Outputs (see Figure 5-49 and Figure 5-50 DM355 NO. PARAMETER UNIT MIN MAX t w(RTOH) Pulse duration, RTOx high P ns t w(RTOL) Pulse duration, RTOx low P ns t t(RTO) Transition time, RTOx .1P ns t d(TIMER3-RTOV) Delay time, Timer (TINT12 or TINT34) trigger event to RTOx valid ns Figure 5-49. RTO Output Timing Figure 5-50. RTO Output Delay Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 151

5.18 IEEE 1149.1 JTAG TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The JTAG (1) interface is used for BSDL testing and emulation of the DM355 device. The DM355 device requires that both TRST and RESET be asserted upon power up to be properly initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required for proper operation. While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface and device's emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted. RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan instructions work correctly independent of current state of RESET For maximum reliability, DM355 includes an internal pulldown (PD) on the TRST pin to ensure that TRST will always be asserted upon power up and the device's internal emulation logic will always be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally drive TRST high before attempting any emulation or boundary scan operations. Following the release of RESET the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see the terminal functions section of this data sheet. (1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. 152 DM355 Peripheral Information and Electrical Specifications Submit Documentation Feedback

5.18.1 JTAG Test-Port Electrical Data/Timing RTCK TDO TDI TMS TCK 2 3 TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 Table 5-48. Timing Requirements for JTAG Test Port (see Figure 5-51 DM355 NO. UNIT MIN MAX t c(TCK) Cycle time, TCK ns tw(TCKH) Pulse duration, TCK high ns tw(TCKL) Pulse duration, TCK low ns t su(TDIV-RTCKH) Setup time, TDI valid before RTCK high ns t h(RTCKH-TDIIV) Hold time, TDI valid after RTCK high ns t su(TMSV-RTCKH) Setup time, TMS valid before RTCK high ns t h(RTCKH-TMSIV) Hold time, TMS valid after RTCK high ns Figure 5-51. JTAG Input Timing Submit Documentation Feedback DM355 Peripheral Information and Electrical Specifications 153

(DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see Figure 5-51 DM355 NO. PARAMETER UNIT MIN MAX t c(RTCK) Cycle time, RTCK ns tw(RTCKH) Pulse duration, RTCK high tw(RTCKL) Pulse duration, RTCK low t r(all JTAG outputs) Rise time, all JTAG outputs 1.3 ns t f(all JTAG outputs) Fall time, all JTAG outputs 1.3 ns 0.25*tc(RT t d(RTCKL-TDOV) Delay time, TCK low to TDO valid ns CK) Figure 5-52. JTAG Output Timing DM355 Peripheral Information and Electrical Specifications 154 Submit Documentation Feedback

(Revision TMS320DM355 Digital Media System-on-Chip (DMSoC) www.ti.com SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 This data sheet revision history highlights the technical changes made to the SPRS463 E device-specific data sheet to make it an SPRS463 F revision. Scope: Applicable updates to the DM35x DMSoC device family, specifically relating to the TMS320DM355 device, have been incorporated. The A135 and A216 DM355 devices both support extended temperature. ADDS/CHANGES/DELETES Global: Added Extended Temperature for 135-MHz devices Submit Documentation Feedback Revision History (Revision 155

7.1 Thermal Data for ZCE 7.1.1 Packaging Information TMS320DM355 Digital Media System-on-Chip (DMSoC) SPRS463F SEPTEMBER 2007 REVISED JANUARY 2009 www.ti.com The following table(s) show the thermal resistance characteristics for the PBGA ZCE mechanical package. Note that micro-vias are not required. Contact your TI representative for routing recommendations. The following table shows the thermal resistance characteristics for the PBGA ZCE mechanical package. Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZCE] NO. C/W (1) R Θ JC Junction-to-case 7.2 R Θ JB Junction-to-board 11.4 R Θ JA Junction-to-free air 27.0 Psi JT Junction-to-package top 0.1 Psi JB Junction-to-board 11.3 (1) The junction-to-case measurement was conducted in a JEDEC defined 2S2P system and will change based on environment as well as application. For more information, see these three EIA/JEDEC standards: EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document. Note that micro-vias are not required for this package. 156 Mechanical Data Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DM355SZCE135 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR DM355SZCE216 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR DM355SZCE270 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR DM355SZCEA135 ACTIVE NFBGA ZCE 337 200 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR DM355SZCEA216 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR TMS320DM355ZCE135 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR TMS320DM355ZCE216 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR TMS320DM355ZCE270 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR TMS320DM355ZCEA135 ACTIVE NFBGA ZCE 337 200 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR TMS320DM355ZCEA216 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2010 Addendum-Page 1

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DM355SZCE216 specifications and overview.

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DM355SZCE216 specifications and overview.

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