DIX4192IPFBR

DIX4192 BURR-BROWN | Alldatasheet

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(Ports A and Digital Audio Interface Transmitter (DIT) Synchronous Serial Interface to External Signal Processors, Data Converters, and Supports Sampling Rates Up to 216kHz Logic Includes Differential Line Driver and Slave or Master Mode Operation with CMOS Buffered Outputs Sampling Rates up to 216kHz Block-Sized Data Buffers for Both Channel Supports Left-Justified, Right-Justified, and Status and User Data Philips I S Data Formats Status Registers and Interrupt Generation Supports Audio Data Word Lengths Up to for Flag and Error Conditions Bits Digital Audio Interface Receiver (DIR) Four General-Purpose Digital Outputs PLL Lock Range Includes Sampling Rates Multifunction Programmable Via Control from 20kHz to 216kHz Registers Includes Four Differential Input Line Extensive Power-Down Support Receivers and an Input Multiplexer Functional Blocks May Be Disabled Bypass Multiplexer Routes Line Receiver Individually When Not In Use Outputs to Line Driver and Buffer Outputs Operates From +1.8V Core and +3.3V I/O Block-Sized Data Buffers for Both Channel Power Supplies Status and User Data Small TQFP-48 Package, Compatible with the Automatic Detection of Non-PCM Audio SRC4382 and SRC4392 Streams (DTS CD/LD and IEC 61937 formats) Audio CD Q-Channel Sub-Code Decoding DIGITAL AUDIO RECORDERS AND and Data Buffer MIXING DESKS Status Registers and Interrupt Generation DIGITAL AUDIO INTERFACES FOR for Flag and Error Conditions COMPUTERS Low Jitter Recovered Clock Output DIGITAL AUDIO ROUTERS AND User-Selectable Serial Host Interface: SPI DISTRIBUTION SYSTEMS or I C BROADCAST STUDIO EQUIPMENT Provides Access to On-Chip Registers and DVD/CD RECORDERS Data Buffers SURROUND SOUND DECODERS AND A/V RECEIVERS CAR AUDIO SYSTEMS Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Dolby is a registered trademark of Dolby Laboratories, Inc. I2C, I2S are trademarks of Koninklijke Philips Electronics N.V. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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DESCRIPTION

(1) DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 The DIX4192 is a highly-integrated CMOS device designed for use in professional and broadcast digital audio systems. The DIX4192 combines a digital audio interface receiver (DIR) and transmitter (DIT), two audio serial ports, and flexible distribution logic for interconnection of the function block data and clocks. The DIR and DIT are compatible with the AES3, S/PDIF, IEC 60958, and EIAJ CP-1201 interface standards. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR lock range includes sampling rates from 20kHz to 216kHz. The DIX4192 is configured using on-chip control registers and data buffers, which are accessed through either a 4-wire serial peripheral interface (SPI) port, or a 2-wire Philips I C bus interface. Status registers provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options via control register settings. A master reset input pin is provided for initialization by a host processor or supervisory functions. The DIX4192 requires a +1.8V core logic supply, in addition to a +3.3V supply for powering portions of the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from +1.65V to +3.6V, providing compatibility with low voltage logic interfaces typically found on digital signal processors and programmable logic devices. The DIX4192 is available in a lead-free, TQFP-48 package, and is pin- and register-compatible with the Texas Instruments SRC4382 and SRC4392 products. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA, PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER QUANTITY DIX4192IPFBT Tape and Reel, 250 DIX4192 TQFP-48 PFB C to +85 C DIX4192I DIX4192IPFBR Tape and Reel, 2000 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com Power supplies VDD18 0.3V to +2.0V VDD33 0.3V to +4.0V VIO 0.3V to +4.0V VCC 0.3V to +4.0V Digital input voltage: Digital logic 0.3V to (VIO 0.3V) RXCKI, CPM, CS CCLK, CDIN, CDOUT, INT RST MCLK, BLS, SYNC, BCKA, BCKB, LRCKA, LRCKB, SDINA, SDINB Line receiver input voltage (per pin) (VDD33 0.3) V PP RX1+, RX1 RX2+, RX2 RX3+, RX3 RX4+, RX4 Input current (all pins except power and ground) 10mA Ambient operating temperature C to +85 C Storage temperature C to +150 C (1) These limits are stress ratings only. Stresses beyond these limits may result in permanent damage. Extended exposure to absolute maximum ratings may degrade device reliability. Normal operation or performance at or beyond these limits is not specified or ensured. Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: General, DIR, and DIT DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 All specifications are at T A +25 VDD18 +1.8V, VDD33 +3.3V, VIO +3.3V, and VCC +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL I/O CHARACTERISTICS (All I/O pins except line receivers and line driver) High-level input voltage, V IH 0.7 VIO VIO V Low-level input voltage, V IL 0.3 VIO V High-level input current, I IH 0.5 µ A Low-level input current, V IL 0.5 µ A High-level output voltage, V OH I O 4mA 0.8 VIO VIO V Low-level output voltage, V OL I O +4mA 0.2 VIO V Input capacitance, C IN pF LINE RECEIVER INPUTS (RX1+, RX1 RX2+, RX2 RX3+, RX3 RX4+, RX4 Voltage across a given Differential input sensitivity, V TH 150 200 mV differential input pair Input hysteresis, V HY 150 mV LINE DRIVER OUTPUTS (TX+, TX Differential output voltage, V TXO R L 110 Ω Across TX+ and TX 5.4 V PP MASTER CLOCK INPUT Master clock input (MCLK) frequency, f MCLK 27.7 MHz Master clock input (MCLK) duty cycle, f MCLKD DIGITAL AUDIO INTERFACE RECEIVER (DIR) PLL lock range 216 kHz Reference clock input (RXCKI) frequency, f RXCKI 3.5 27.7 MHz Reference clock input (RXCKI) duty cycle, f RXCKID Recovered clock output (RXCKO) frequency, f RXCKO 3.5 27.7 MHz Recovered clock output (RXCKO) duty cycle, f RXCKOD Recovered clock output (RXCKO) intrinsic jitter Measured cycle-to-cycle 250 ps RMS DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) Intrinsic output jitter Measured cycle-to-cycle 200 ps RMS Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: Audio Serial Ports ELECTRICAL CHARACTERISTICS: SPI Interface DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 All specifications are at T A +25 VDD18 +1.8V, VDD33 +3.3V, VIO +3.3V, and VCC +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS AUDIO SERIAL PORTS (Port A and Port LRCK clock frequency, f LRCK 216 kHz LRCK clock duty cycle, t LRCKD BCK clock frequency, f BCK 13.824 MHz BCK high pulse width, t BCKH ns BCK low pulse width, t BCKL ns Audio data Input (SDIN) setup time, t AIS ns Audio data input (SDIN) hold time, t AISH ns Audio data output (SDOUT) delay, t ADD ns All specifications are at T A +25 VDD18 +1.8V, VDD33 +3.3V, VIO +3.3V, and VCC +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS HOST INTERFACE: SPI Mode Serial clock (CCLK) frequency, f CCLK MHz CS falling to CCLK rising, t CSCR ns CCLK falling to CS rising, t CFCS ns CDIN data setup time, t CDS ns CDIN data hold time, t CDH ns CCLK falling to CDOUT data valid, t CFDO ns CS rising to CDOUT high-impedance, t CSZ ns Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: I C Standard and Fast Modes DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 All specifications are at T A +25 VDD18 +1.8V, VDD33 +3.3V, VIO +3.3V, and VCC +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS HOST INTERFACE: I C Standard Mode (1) SCL clock frequency, f SCL 100 kHz Hold time repeated START condition, t HDSTA µ s Low period of SCL clock, t LOW 4.7 µ s High period of SCL clock, t HIGH µ s Setup time repeated START condition, t SUSTA 4.7 µ s Data hold time, t HDDAT (2) 3.45 (3) µ s Data setup time, t SUDAT 250 ns Rise time for Both SDA and SDL, t R 1000 ns Fall time for Both SDA and SDL, t F 300 ns Setup time for STOP condition, t SUSTO µ s Bus free time between START and STOP, t BUF 4.7 µ s Capacitive load for each bus Line, C B 400 pF Noise margin at low level (including hysteresis), V NL 0.1 VIO V Noise margin at high level (including hysteresis), V NH 0.2 VIO V HOST INTERFACE: I C Fast Mode (1) SCL clock frequency, f SCL 400 kHz Hold time repeated START condition, t HDSTA 0.6 µ s Low period of SCL clock, t LOW 1.3 µ s High period of SCL clock, t HIGH 0.6 µ s Setup time repeated START condition, t SUSTA 0.6 µ s Data hold time, t HDDAT (2) 0.9 (3) µ s Data setup time, t SUDAT 100 (4) ns Rise time for both SDA and SDL, t R 0.2C B (5) 300 ns Fall time for both SDA and SDL, t F 0.2C B (5) 300 ns Setup time for STOP condition, t SUSTO 0.6 µ s Bus free time between START and STOP, t BUF 1.3 µ s Spike pulse width suppressed by input filter, t SP ns Capacitive load for Each bus Line, C B 400 pF Noise margin at low level (including hysteresis), V NL 0.1 VIO V Noise margin at high level (including hysteresis), V NH 0.2 VIO V (1) All values referred to the V IH minimum and V IL maximum levels listed in the Digital I/O Characteristics section of the Electrical Characteristics: General, DIR, and DIT table. (2) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V IH minimum input level) to bridge the undefined region of the falling edge of SCL. (3) The maximum t HDDAT has only to be met if the device does not stretch the Low period LOW of the SCL signal. (4) A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement that t SUDAT be 250ns (minimum) must then be met. For the DIX4192, this condition is automatically the case, since the device does not stretch the Low period of the SCL signal. (5) C B is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times are allowed. Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: Power Supplies DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 All specifications are at T A +25 VDD18 +1.8V, VDD33 +3.3V, VIO +3.3V, and VCC +3.3V, unless otherwise noted. DIX4192 PARAMETER CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Recommended supply voltage range VDD18 +1.65 +1.8 +1.95 V VDD33 +3.0 +3.3 +3.6 V VIO +1.65 +3.3 +3.6 V VCC +3.0 +3.3 +3.6 V Supply current: initial startup All blocks powered down by default IDD18S VDD18 +1.8V µ A IDD33S VDD33 +3.3V µ A IIOS VIO +3.3V 300 µ A ICCS VCC +3.3V µ A Supply current: quiescent All blocks powered up with no clocks applied IDD18Q VDD18 +1.8V 2.3 mA IDD33Q VDD33 +3.3V 0.6 mA IIOQ VIO +3.3V 0.3 mA ICCQ VCC +3.3V 6.3 mA Supply current: dynamic All blocks powered up, f S 48kHz IDD18D VDD18 +1.8V 5.1 mA IDD33D VDD33 +3.3V 14.1 mA IIOD (1) VIO +3.3V mA ICCD VCC +3.3V 7.4 mA Supply current: high sampling rate All blocks powered up, f S 192kHz IDD18H VDD18 +1.8V 6.7 mA IDD33H VDD33 +3.3V mA IIOH (1) VIO +3.3V mA ICCH VCC +3.3V 7.5 mA Total power dissipation: initial startup All blocks powered down by default mW Total power dissipation: quiescent All blocks powered up with no clocks applied mW Total power dissipation: dynamic All blocks powered up, f S 48kHz 233 mW Total power dissipation: high sampling Rate All blocks powered up, f S 192kHz 242 mW (1) The typical VIO supply current is measured using the DIX4192EVM evaluation module with loading from the DAIMB mother-board circuitry. VIO supply current is dependent upon the loading on the logic output pins. Submit Documentation Feedback

www.ti.com TIMING DIAGRAMS LRCK BCK SDIN tAIS SDOUT tAIH tAOD tBCKL tBCKH CS CC KL CD□NI CDOUT tCFCS tCDH Hi□Z Hi□Z tCSCR tCDS tCFDO tCSZ SDA SCL S R P S tF tHDST A tLOW tR tHDDA T tSUDA T tF tBUF S□=□Start nCo dition R□=□Repea ed□Startt Condition P□=□Stop Co dition n tSUST A tSUSTO tHDST A tSP tR tHIGH DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Figure Audio Serial Port Timing Figure SPI Interface Timing Figure I C Standard and Fast Mode Timing Submit Documentation Feedback

www.ti.com PIN CONFIGURATION T op□View TQFP SYNC BLS AESOUT VDD33 TX+ TX/c45 DGND2 GPO4 GPO3 GPO2 GPO1 MCLK BCKBLRCKBSDINBSDOUTBBGNDDGND3VIO NC SDOUT A SDINALRCKABCKA RXCKI NC NC DGND1VDD18 CPMCS/A0 CCLK/SCL CDIN/A1 CDOUT/SDA INT RST RX1+ RX1/c45 RX2+ RX2/c45 RX3+ RX3/c45 RX4+ RX4/c45 VCC AGND LOCK RXCKO 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 DIX4192 NC□=□No□Connection DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PIN DESCRIPTIONS NAME PIN NUMBER I/O supply, +3.3V nominal AGND Ground DIR comparator and PLL power-supply ground LOCK Output DIR PLL lock flag (active low) RXCKO Output DIR recovered master clock (tri-state output) RXCKI Input DIR reference clock NC 14, 15, No internal signal connection, internally bonded to ESD pad DGND1 Ground Digital core ground VDD18 Power Digital core supply, +1.8V nominal CPM Input Control port mode, SPI mode, I C mode CS or Input Chip select (active low) for SPI mode or programmable slave address for I C mode CCLK or SCL Input Serial data clock for SPI mode or I C mode CDIN or Input SPI port serial data input or programmable slave address for I C mode CDOUT or SDA I/O SPI port serial data output (tri-state output) or serial data I/O for I C mode Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PIN DESCRIPTIONS (continued) NAME PIN NUMBER I/O (open-drain, active low) RST Input Reset (active low) MCLK Input Master clock GPO1 Output General-purpose output GPO2 Output General-purpose output GPO3 Output General-purpose output GPO4 Output General-purpose output DGND2 Ground DIR line receiver bias and DIT line driver digital ground TX Output DIT line driver inverting output TX+ Output DIT line driver noninverting output VDD33 Power DIR line receiver bias and DIT line driver supply, +3.3V nominal AESOUT Output DIT buffered AES3-encoded data BLS I/O DIT block start clock SYNC Output DIT internal sync clock BCKA I/O Audio serial Port A bit clock LRCKA I/O Audio serial Port A Left/Right clock SDINA Input Audio serial Port A data input SDOUTA Output Audio serial Port A data output VIO Power Logic I/O supply, +1.65V to +3.6V DGND3 Ground Logic I/O ground BGND Ground Substrate ground, connect to AGND (pin 10) SDOUTB Output Audio serial Port B data output SDINB Input Audio serial Port B data input LRCKB I/O Audio serial Port B left/right clock BCKB I/O Audio serial Port B bit clock Submit Documentation Feedback

www.ti.com PRODUCT OVERVIEW DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 The DIX4192 is an integrated digital audio interface receiver and transmitter (DIR and DIT). Two audio serial ports, Port A and Port support input and output interfacing to external data converters, signal processors, and logic devices. On-chip routing logic provides for flexible interconnection between the four functional blocks. The audio serial ports and DIT may be operated at sampling rates up to 216kHz. The DIR is specified for a PLL lock range that includes sampling rates from 20kHz to 216kHz. All function blocks support audio data word lengths up to bits. The DIX4192 requires an external host processor or logic for configuration control. The DIX4192 includes a user-selectable serial host interface, which operates as either a 4-wire serial peripheral interface (SPI) port or a 2-wire Philips I C bus interface. The SPI port operates at bit rates up to 40MHz. The I C bus interface may be operated in standard or fast modes, supporting operation at 100kbps and 400kbps, respectively. The SPI and I C interfaces provide access to internal control and status registers, as well as the buffers utilized for the DIR and DIT channel status and user data. The digital interface receiver (DIR) includes four differential input line receiver circuits, suitable for balanced or unbalanced cable interfaces. Interfacing to optical receiver modules and CMOS logic devices is also supported. The outputs of the line receivers are connected to a 1-of-4 data selector, referred to as the receiver input multiplexer, which is utilized to select one of the four line receiver outputs for processing by the DIR core. The outputs of the line receivers are also connected to a second data selector, the bypass multiplexer, which may be used to route input data streams to the DIT CMOS output buffer and differential line driver functions. This configuration provides a bypass signal path for AES3-encoded input data streams. The DIR core decodes the selected input stream data and separates the audio, channel status, user, validity, and parity data. Channel status and user data is stored in block-sized buffers, which may be accessed via the SPI or I C serial host interface, or routed directly to the general-purpose output pins (GPO1 through GPO4). The validity and parity bits are processed to determine error status. The DIR core recovers a low jitter master clock, which may be utilized to generate word and bit clocks using on-chip or external logic circuitry. The digital interface transmitter (DIT) encodes digital audio input data into an AES3-formatted output data stream. Two DIT outputs are provided, including a differential line driver and a CMOS output buffer. Both the line driver and buffer include 1-of-2 input data selectors, which are utilized to choose either the output of the DIT AES3 encoder, or the output of the bypass multiplexer. The line driver output is suitable for balanced or unbalanced cable interfaces, while the CMOS output buffer supports interfacing to optical transmitter modules and external logic or line drivers. The DIT includes block-sized data buffers for both channel status and user data. These buffers are accessed via either the SPI or I C host interface, or may be loaded directly from the DIR channel status and user data buffers. The DIX4192 includes four general-purpose digital outputs, or GPO pins. The GPO pins may be configured as simple logic outputs, which may be programmed to either a low or high state. Alternatively, the GPO pins may be connected to one of internal logic nodes, allowing them to serve as functional, status, or interrupt outputs. The GPO pins provide added utility in necessary. Submit Documentation Feedback

www.ti.com N Audio Serial Port□A Audio Serial Port□B Digital Interface Receiver□(DIR) Digital Interface Transmitter (DIT) TX+ TX/c45 SDINA SDOUTA LRCKA BC AK SDINB SDOUTB LRCKB BC BK CPM CS or A0 CCLK□or□SCL CDIN□or 1A CDOUT or□SDA INT RST Host Interface (SPI□or I C) and Gene a r l- Purp so e Outputs Master Cl cko Distribution MC KL RXCKI From□RXCKO GP 1O GP 2O GP 3O GP 4O AESOUT RXCKO LOCK RX +2 RX /c452 RX +3 RX /c453 RX +4 RX /c454 RX +1 RX /c451 BLS SY CN Control□and□Status Registers DIR□C□and U Data□Buffers DIT□C□and U Data□Buffers DIX4192 Power VDD18 DGND1 VDD33 DGND2 VIO DGND3 VCC AG DN BG DNInternally□Tied to□Substrate PORT□APORT□BDIRDIT RESET OPERATION DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure shows a simplified functional block diagram for the DIX4192. Additional details for each function block will be covered in respective sections of this datasheet. Figure Functional Block Diagram The DIX4192 includes an asynchronous active low reset input, RST (pin 24), which may be used to initialize the internal logic at any time. The reset sequence forces all registers and buffers to their default settings. The reset low pulse width must be a minimum of 500ns in length. The user should not attempt a write or read operation using either the SPI or I C port for at least 500 µ s after the rising edge of RST See Figure for the reset timing sequence of the DIX4192. In addition to reset input, the RESET bit in control register 0x01 may be used to force an internal reset, whereby all registers and buffers are forced to their default settings. Refer to the Control Registers section for details regarding the RESET bit function. Upon reset initialization, all functional blocks of the DIX4192 default to the power-down state, with the exception of the SPI or I C host interface and the corresponding control registers. The user may then program the DIX4192 to the desired configuration, and release the desired function blocks from the power-down state utilizing the corresponding bits in control register 0x01. Submit Documentation Feedback

www.ti.com RST 500ns (min) 500 s/c109 (min) Write or□Read via S I□orP I C MASTER AND REFERENCE CLOCKS DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure Reset Sequence Timing The DIX4192 includes two clock inputs, MCLK (pin 25) and RXCKI (pin 13). The MCLK clock input is typically used as the master clock source for the audio serial ports and/or the DIT. The MCLK may also be utilized as the reference clock for the DIR. The RXCKI clock input is typically used for the DIR reference clock source, although it may also be used as the master or reference clock source for the audio serial ports. In addition to the MCLK and RXCKI clock sources, the DIR core recovers a master clock from the AES3-encoded input data stream. This clock is suitable for use as a master or system clock source in many applications. The recovered master clock output, RXCKO (pin 12), may be utilized as the master or reference clock source for the audio serial ports and/or the DIT, as well as external audio devices. The master clock frequency for the audio serial ports (Port A and Port depends on the Slave or Master mode configuration of the port. In Slave mode, the ports do not require a master clock because the left/right word and bit clocks are inputs, sourced from an external audio device serving as the serial bus timing master. In Master mode, the serial ports derive the left/right word and bit clock outputs from the selected master clock source, MCLK, RXCKI, or RXCKO. The left/right word clock rate is derived from the selected master clock source using one of four clock divider settings (divide by 128, 256, 384, or 512). Refer to the Audio Serial Port Operation section for additional details. The DIT always requires a master clock source, which may be either the MCLK input, or the DIR recovered clock output, RXCKO. Like the audio serial ports, the DIT output frame rate is derived from the selected master clock using one of four clock divider settings (divide-by-128, -256, -384, or -512). Refer to the Digital Interface Transmitter (DIT) Operation section for additional details. The DIR reference clock may be any frequency that meets the PLL1 setup requirements, described in the Control Registers section. Typically, a common audio system clock rate, such as 11.2896MHz, 12.288MHz, 22.5792MHz, or 24.576MHz, may be used for this clock. It is recommended that the clock sources for MCLK and RXCKI input be generated by low-jitter crystal oscillators for optimal performance. In general, phase-locked loop (PLL) clock synthesizers should be avoided, unless they are designed and/or specified for low clock jitter. Submit Documentation Feedback

www.ti.com AUDIO SERIAL PORT OPERATION Master Clock Source Master Mo ed Clock Generation Serial Input Serial Output MC KL RXCKI RXCKO Audio Data Internal□Clocks OUTS[1:0] MU E T F T[1: M 0] M/S DIV□1: [ 0]CLK□1:[ 0] SD□NI A (pin□39)□or SDINB□(pin□4 ) 6 LRCKA (pin□3 )□or8 LRCKB□( i 47)p n BCKA□(pin□37)□or□BCKB□(pin□48) SDOUTA (pin□40)□or SDOUTB□(pin□45) Da□a t Source Port□A Port□B DIR DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The DIX4192 includes two audio serial ports, Port A and Port Both ports are 4-wire synchronous serial interfaces, supporting simultaneous input and output operation. Since each port has only one pair of left/right word and bit clocks, the input and output sampling rates are identical. A simplified block diagram is shown in Figure The audio serial ports may be operated at sampling rates up to 216kHz, and support audio data word lengths up to bits. Philips I Left-Justified, and Right-Justified serial data formats are supported. Refer to Figure The left/right word clock (LRCKA or LRCKB) and the bit clock (BCKA or BCKB) may be configured for either Master or Slave mode operation. In Master mode these clocks are outputs, derived from the selected master clock source using internal clock dividers. The master clock source may be 128, 256, 384, or 512 times the audio input/output sampling rate, with the clock divider being selected using control register bits for each port. In Slave mode the left/right word and bit clocks are inputs, and are sourced from an external audio device acting as the serial bus master. The LRCKA or LRCKB clocks operate at the input/output sampling rate, f S The BCKA and BCKB clock rates are fixed at times the left/right word clock rate in Master mode. For Slave mode, the minimum BCKA and BCKB clock rate is determined by the audio data word length multiplied by two, since there are two audio data channels per left/right word clock period. For example, if the audio data word length is bits, the bit clock rate must be at least times the left/right word clock rate, allowing one bit clock period for each data bit in the serial bit stream. Serial audio data is clocked into the port on the rising edge of the bit clock, while data is clocked out of the port on the falling edge of the bit clock. Refer to the Electrical Characteristics: Audio Serial Ports table for parametric information and Figure for a timing diagram related to audio serial port operation. The audio serial ports are configured using control registers 0x03 through 0x06. Refer to the Control Registers section for descriptions of the control register bits. Figure Audio Serial Port Block Diagram Submit Documentation Feedback

www.ti.com MSB LSB MSB LSB MSB LSB MSB LSB LSBMSB LSBMSB LRCKA LRCKB BC AK BC BK Audio Da□a t LRCKA LRCKB BC AK BC BK Audio Da□a t LRCKA LRCKB BC AK BC BK Audio Da□a t (a) Left-Justified□Data For am t (b)□Right-Justif e Dai d ta□Form t a (c)□I S Data□Fo m tr a 1/fs Channel□1□(Left□Channel) Channel□2□(Right□Channel) OVERVIEW OF THE AES3 DIGITAL AUDIO INTERFACE PROTOCOL DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure Audio Data Formats This section introduces the basics of digital audio interface protocols pertaining to the transmitter (DIT) and receiver (DIR) blocks of the DIX4192. Emphasis is placed upon defining the basic terminology and characteristics associated with the AES3-2003 standard protocol, the principles of which may also be applied to a number of consumer-interface variations, including S/PDIF, IEC-60958, and EIAJ CP-1201. It is assumed that the reader is familiar with the AES3 and S/PDIF interface formats. Additional information is available from the sources listed in the Reference Documents section. The AES3-2003 standard defines a technique for two-channel linear PCM data transmission over 110 Ω shielded twisted-pair cable. The AES-3id document extends the AES3 interface to Ω coaxial cable connections. In addition, consumer transmission variants, such as those defined by the S/PDIF, IEC 60958, and CP-1201 standards, utilize the same encoding techniques but with different physical interfaces or transmission media. Channel status data definitions also vary between professional and consumer interface implementations. Submit Documentation Feedback

www.ti.com X Channel□1 Y Channel□2 Channel□1Z Y Channel□2 X Channel□1 Y Channel□2 Frame 191 Frame 0 Frame 1 Block□Start One□Sub□Frame Bits: 0 3 4 7 8 27 28 29 30 31 MSB V U C PPreamble Audio□DataAudio□or Aux□Data Validity□Bit Use Dr ata Channel Status Data P rita y Bit DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) For AES3 transmission, data is encoded into frames, with each frame containing two subframes of audio and status data, corresponding to audio Channels and (or Left and Right, respectively, for stereophonic audio). Figure shows the AES3 frame and subframe formatting. Each subframe includes four bits for the preamble, up to bits for audio and/or auxiliary data, one bit indicating data validity (V), one bit for channel status data (C), one bit for user data (U), and one bit for setting parity (P). The 4-bit preamble is used for synchronization and identification of blocks and subframes. The X and Y preamble codes are used to identify the start of the Channel and Channel subframes, as shown in Figure However, the X preamble for the first subframe of every 192 frames is replaced by the Z preamble, which identifies the start of a new block of channel status and user data. Figure AES3 Frame and Subframe Encoding One block is comprised of 192 frames of data. This format translates to 192 bits each for channel status and user data for each channel. The 192 bits are organized into data bytes, which are defined by the AES3-2003 and consumer standards documents. The AES18 standard defines recommended usage and formatting of the user data bits, while consumer purposes. The DIX4192 also includes block-sized transmitter and receiver channel status and user data buffers, which have bytes each for the channel status and user data assigned to audio Channels and Refer to the Channel Status and User Data Buffer Maps section for the organization of the buffered channel status and user data for the receiver and transmitter functions. The audio data for Channel and Channel may be up to bits in length, and occupies bits through of the corresponding subframe. Bit is the LSB while bit is the MSB. If only bits are required for audio data, then bits through are utilized for audio data, while bits though are utilized for auxiliary data bits. The validity (V) bit indicates whether or not the audio sample word being transmitted is suitable for digital-to-analog (D/A) conversion or further digital processing at the receiver end of the connection. If the validity bit is then the audio sample is suitable for conversion or additional processing. If the validity bit is then the audio sample is not suitable for conversion or additional processing. The parity (P) bit is set to either a or such that bits through carry an even number of ones and zeros for even parity. The DIT block in the DIX4192 automatically manages the parity bit, setting it to a or as needed. The DIR block checks the parity of bits though and generates a parity error if odd parity is detected. Submit Documentation Feedback

www.ti.com Preceding□state: 0 1 Preamble: Channel□coding: Channel□coding: Description: X 111 000 10 000 11 1 01 Channel su 1 bframe Y 111 010 00 000 10 1 11 Channel su 2 bframe Z 111 100 00 000 01 1 11 Channel□1□subframe and□block□start Cl cko (2x□Source□Bi atet□R ) Source□Data□Coding (NR ) Z AES3□Channel□Coding (Biphase□Mark) Insert□Preamble Code Below Preceding□state,□fr of□the□previous□frameom□the□□Parity□bit . Preamble□Z□(Block□Start) Preamble□Coding DIGITAL INTERFACE TRANSMITTER (DIT) OPERATION DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The binary non-return to zero (NRZ) formatted audio and status source data for bits through of each subframe are encoded utilizing a Biphase Mark format for transmission. This format allows for clock recovery at the receiver end, as well as making the interface insensitive to the polarity of the balanced cable connections. The preambles at the start of each subframe are encoded to intentionally violate the Biphase Mark formatting, making their detection by the receiver reliable, as well as avoiding the possibility of audio and status data imitating the preambles. Figure shows the Biphase Mark and preamble encoding. Although the AES3 standard originally defined transmission for sampling rates up to 48kHz, the interface is capable of handling higher sampling rates, given that attention is paid to cable length and impedance matching. Equalization at the receiver may also be required, depending on the cable and matching factors. It is also possible to transmit and decode more than two channels of audio data utilizing the AES3 or related consumer interfaces. Special encoding and/or compression algorithms are utilized to support multiple channels, including the Dolby AC-3, DTS, MPEG-1/2, and other data reduced audio formats. Figure Biphase Mark Encoding The DIT encodes a given two-channel or data-reduced audio input stream into an AES3-encoded output stream. In addition to the encoding function, the DIT includes differential line driver and CMOS-buffered output functions. The line driver is suitable for driving balanced or unbalanced line interfaces, while the CMOS-buffered output is designed to drive external logic or line drivers, as well as optical transmitter modules. Figure illustrates the functional block diagram for the DIT. The input of the DIT receives the audio data for Channels and from one of three possible sources: Port Port or the DIR. By default, Port A is selected as the source. The DIT also requires a master clock source, which may be provided by either the MCLK input (pin 25) or RXCKO (the DIR recovered master clock output). A master clock divider is utilized to select the frame rate for the AES3-encoded output data. The TXDIV[1:0] bits in control register 0x07 are utilized to select divide by 128, 256, 384, or 512 operation. Channel status and user data for Channels and are input to the AES3 encoder via the corresponding Transmitter Access (TA) data buffers. The TA data buffers are in turn loaded from the User Access (UA) buffers, which are programmed via the SPI or I C host interface, or loaded from the DIR Receiver Access (RA) data buffers. The source of the channel status and user data is selected utilizing the TXCUS[1:0] bits in control register 0x09. When the DIR is selected as the input source, the channel status and user data output from the DIT is delayed by one block in relation to the audio data. The validity (V) bit may be programmed using one of two sources. The VALSEL bit in control register 0x09 is utilized to select the validity data source for the DIT block. The default source is the VALID bit in control register 0x07, which is written via the SPI or I C host interface. The validity bit may also be transferred from the AES3 decoder output of the DIR, where the V bit for the DIT subframes tracks the decoded DIR value frame by frame. Submit Documentation Feedback

www.ti.com MCLK RXCKO User□Access (UA)□Buffers Transmitter□Access (TA)□Buffers Channel Status User Data From□Receiver Access□(RA) Buffer From□Receiver Access□(RA) Buffer T o/From SPI□or□I C Host□Interface T o/From SPI□or□I C Host□Interface TXCLK TXCUS[1:0] TXBTD TXIS[1:0] BLS□(pin□35) SYNC□(pin□36) AE 3S Encoder AESMUX LDMUX AESOFF TXOFF From Bypass Multiplexer Output TX+□(pin□32) TX (pin□31)/c45 AESOUT (pin□34) Master Clock Source Da□a t Source Channel Status User Da□a t TXMUTE BL MS Port□A Port□B DIR TXDIV[1:0] DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The Parity (P) bit will always be generated by the AES3 encoder internal parity generator logic, such that bits through of the AES3-encoded subframe are even parity. The AES3 encoder output is connected to the output line driver and CMOS buffer source multiplexers. As shown in Figure the source multiplexers allow the line driver or buffer to be driven by the AES3-encoded data from the DIT, or by the bypass multiplexer, which is associated with the outputs of the four differential input line receivers preceding the DIR core. The bypass multiplexer allows for one of the four line receiver outputs to be routed to the line driver or buffer output, thereby providing a bypass mode of operation. Both the line driver and CMOS output buffer include output disables, set by the TXOFF and AESOFF bits in control register 0x08. When the outputs are disabled, they are forced to a low logic state. The AES3 encoder includes an output mute function that sets all bits for both the Channel and audio and auxiliary data to zero. The preamble, and C bits are unaffected, while the P bit is recalculated. The mute function is controlled using the TXMUTE bit in control register 0x08. Figure 10. Digital Interface Transmitter (DIT) Functional Block Diagram The AES3 encoder includes a block start input/output pin, BLS (pin 35). The BLS pin may be programmed as an input or output. The input/output state of the BLS pin is programmed using the BLSM bit in control register 0x07. By default, the BLS pin is configured as an input. As an input, the BLS pin may be utilized to force a block start condition, whereby the start of a new block of channel status and user data is initiated by generating a Z preamble for the next frame of data. The BLS input must be synchronized with the DIT internal SYNC clock. This clock is output on SYNC (pin 36). The SYNC clock rising edge is aligned with the start of each frame for the AES3-encoded data output by the DIT. Figure illustrates the format required for an external block start signal, as well as indicating the format when the BLS pin is configured as an output. When the BLS pin is an output, the DIT generates the block start signal based upon the internal SYNC clock. For details regarding DIT control and status registers, as well as channel status and user data buffers, refer to the Control Registers and Channel Status and User Data Buffer Maps sections. Submit Documentation Feedback

www.ti.com SY CN BLS (input) BLS (output) Block Start (Frame 0□starts□here) DIGITAL INTERFACE RECEIVER (DIR) OPERATION PL 1L AE 3S Decoder Pulse Generator PL 2L 128fS 256fS 512fS Clock Divider Divide by 1,□2, 4,□or□8 Data□Stream De-M xu RX1+□(pin□1) RX1 (pin□2)/c45 RX2+□(pin□3) RX2 (pin□4)/c45 RX3+□(pin□5) RX3 (pin□6)/c45 RX4+□(pin□7) RX4 (pin□8)/c45 LOCK (pin 11) RXCKO (pin 12) RXCKO BYPMUX[1□0 : ] R MUX[X 1:0] RXCLK MC KL RXCKI RXCKOF[1:0] Ch□1 . (Left) Audio Ch□2 . (Right) Audio Cha nen l Status Channel Status User Da□a t User Da□a t User□Access (UA)□Buffers Receiver Access (RA)□Buffers T o DIT T o□SPI or□I C□Host□Interface Receiver Sy cn Generator RCV_SYNC Error□□and Status□Outputs T o□DIT Buffer and□Line Driver Reference Clock Source T o DIT DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure 11. DIT Block Start Timing The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure shows the functional block diagram for the DIR. Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with CMOS logic level inputs from optical receivers or external logic circuitry. See Figure for a simplified schematic for the line receiver. External connections are discussed in the Receiver Input Interfacing section. Figure 12. Digital Interface Receiver (DIR) Functional Block Diagram Submit Documentation Feedback

www.ti.com RX+ RX/c45 T o□Receiver Input□and Bypass Multiplexers 24k/c87 VDD33 24k/c87 24k/c87 24k/c87 3k/c87 3k/c87 DGND2 DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) Figure 13. Differential Line Receiver Circuit The outputs of the four line receivers are connected to two 1-of-4 data selectors: the receiver input multiplexer and the bypass multiplexer. The input multiplexer selects one of the four line receiver outputs as the source for the AES3-encoded data stream to be processed by the DIR core. The bypass multiplexer is utilized to route a line receiver output to either the DIT line driver or CMOS-buffered outputs, thereby bypassing all other internal circuitry. The bypass function is useful for simple signal distribution and routing applications. The DIR requires a reference clock, supplied by an external source applied at either the RXCKI (pin 13) or MCLK (pin 25) clock inputs. PLL1 multiplies the reference clock to a higher rate, which is utilized as the oversampling clock for the AES3 decoder. The decoder samples the AES3-encoded input stream in order to extract all of the audio and status data. The decoded data stream is sent on to a de-multiplexer, where audio and status data are separated for further processing and buffering. The pulse generator circuitry samples the encoded input data stream and generates a clock that is times the frame/sampling rate (or f S The 16f S clock is then processed by PLL2, which further multiplies the clock rate and provides low-pass filtering for jitter attenuation. The available PLL2 output clock rates include 512f S 256f S and 128f S The maximum available PLL2 output clock rate for a given input sampling rate is estimated by internal logic and made available for readback via status register 0x13. The output of PLL2 may be divided by a factor of two, four, or eight, or simply passed through to the recovered master clock output, RXCKO (pin 12). The RXCKO clock may also be routed internally to other function blocks, where it may be further divided to create left/right word and bit clocks. The RXCKO output may be disabled and forced to a high-impedance state by means of a control register bit, allowing other tri-state buffered clocks to be tied to the same external circuit node, if needed. By default, the RXCKO output (pin 12) is disabled and forced to a high-impedance state. Figure illustrates the frequency response of PLL2. Jitter attenuation starts at approximately 50kHz. Peaking is nominally 1dB, which is within the 2dB maximum allowed by the AES3 standard. The receiver jitter tolerance plot for the DIR is illustrated in Figure along with the required AES3 jitter tolerance template. The DIR jitter tolerance satisfies the AES3 requirements, as well as the requirements set forth by the IEC60958-3 specification. Figure was captured using a full-scale 24-bit, two-channel, AES3-encoded input stream with a 48kHz frame rate. The decoded audio data, along with the internally-generated sync clocks, may be routed to other function blocks, including Port Port and/or the DIT. The decoded channel status and user data are buffered in the corresponding Receiver Access (RA) data buffers, then transferred to the corresponding User Access (UA) data buffers, where it may be read back through either the SPI or I C serial host interface. The

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buffers; this transfer is illustrated in Figure The channel status and user data bits may also be output serially through the general-purpose output pins, GPO[4:1]. Figure illustrates the output format for the GPO pins when used for this purpose, along with the DIR block start (BLS) and frame synchronization (SYNC) clocks. The rising edges of the DIR SYNC clock output are aligned with the start of each frame for the received AES3 data. Submit Documentation Feedback

www.ti.com /c452 /c454 /c456 /c458 /c4510 /c4512 /c4514 /c4516 /c4518 /c4520 Jitter□Frequency□(Hz) Jitter□Attenuation□(dB) Peak□Jitter□(UI) /c4510 /c4520 /c4530 /c4540 /c4550 /c4560 /c4570 /c4580 /c4590 /c45100 /c45110 /c45120 /c45130 /c45140 /c45150 20 100 1k Sinusoidal□Jitter□Frequency□(Hz) 10k 100k THD+N□Ratio□(dB) 500m 200m 100m 50m 20m 10m THD+N Output□Jitter□Amplitude Input□Jitter□Amplitude BLS (output) SY CN (output) C□or□U da□a t (output) Bit 0 Bit 1 Bit 2 Bit 4 /c188 Block Start (Fr mea 0□St rts□Hea re) DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The DIR includes a dedicated, active low AES3 decoder and PLL2 lock output, named LOCK (pin 11). The lock output is active only when both the AES3 decoder and PLL2 indicate a lock condition. Additional DIR status flags may be output at the general-purpose output (GPO) pins, or accessed through the status registers via the SPI or I C host interface. Refer to the General-Purpose Digital Outputs and Control Registers sections for additional information regarding the DIR status functions. Figure 14. DIR Jitter Attenuation Characteristics Figure 15. DIR Jitter Tolerance Plot Figure 16. DIR Channel Status and User Data Serial Output Format Via the GPO Pins Submit Documentation Feedback

www.ti.com GENERAL-PURPOSE DIGITAL OUTPUTS HOST INTERFACE OPERATION: DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 PRODUCT OVERVIEW (continued) The DIX4192 includes four general-purpose digital outputs, GPO1 through GPO4 (pins through 29, respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be connected to one of internal logic nodes, allowing the GPO pin to inherit the function of the selected signal. Control registers 0x1B through 0x1E are utilized to select the function of the GPO pins. For details regarding GPO output configuration, refer to the Control Registers section. Table summarizes the available output options for the GPO pins. Table General-Purpose Output Pin Configurations GPOn3 GPOn2 GPOn1 GPOn0 GPOn FUNCTION GPOn is forced low (default) GPOn is forced high Reserved DIT interrupt flag; active low DIR interrupt flag; active low DIR µ s emphasis flag; active low DIR non-audio data flag; active high DIR non-valid data flag; active high DIR channel status data serial output DIR user data serial output DIR block start clock output DIR COPY bit output copyright asserted, copyright not asserted) DIR L (or origination) bit output 1st generation or higher, original) DIR Parity error flag; active high DIR internal sync clock output; may be used as the data clock for the channel status and user data serial outputs. DIT internal sync clock SERIAL PERIPHERAL INTERFACE (SPI) MODE The DIX4192 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI port supports high-speed serial data transfers up to 40Mbps. Register and data buffer write and read operations are supported. The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial data input for the port; the CDOUT output serves as the serial data output. The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of CCLK. Figure illustrates the SPI port protocol. Byte is referred to as the command byte, where the most significant bit (or MSB) is the read/write bit. For the R/W bit, a indicates a write operation, while a indicates a read operation. The remaining seven bits of the command byte are utilized for the register address targeted by the write or read operation. Byte is a don t care byte, and may be set to all zeroes. This byte is included in order to retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter products, including the DIT4096 DIT4192 the SRC418x series devices, and the SRC419x series devices. Submit Documentation Feedback

www.ti.com CS CD□NI CC KL Set =□1□here□to gister□location.write/read□one□reCS Hold =□0□to□enab de.le□auto-increment□moCS Byte□0 Byte□1 Byte□2 Byte□3 Byte□N R/W A6 A5 A0 A4 A1A3 A2 Set□to 0□for□Write ad.; Set□to or□Re1□f Byte□0: MSB LSB Byte□Defi itionn Header Register□Data Register□Address Byte□2 through□Byte□N: Register□D t a a CDOUT Hi□Z Hi□Z Data□for□A[ : ]+1 6 0Data□for□A[6:0] Data□for□A[ : ]+N2 0 Register□Data HOST INTERFACE OPERATION: PHILIPS I C MODE DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 The SPI port supports write and read operations for multiple sequential register addresses through the implementation of an auto-increment mode. As shown in Figure the auto-increment mode is invoked by simply holding the CS input low for multiple data bytes. The register address is automatically incremented after each data byte transferred, starting with the address specified by the command byte. Refer to the Electrical Characteristics: SPI Interface table and Figure for specifications and a timing diagram that highlight the key parameters for SPI interface operation. Figure 17. Serial Peripheral Interface (SPI) Protocol for the DIX4192 The DIX4192 supports a 2-wire Philips I C bus interface when CPM (pin 18) is forced high or pulled up to the VIO supply rail. The DIX4192 functions as a Slave-only device on the bus. Standard and Fast modes of operation are supported. Standard mode supports data rates up to 100kbps, while Fast mode supports data rates up to 400kbps. Fast mode is downward compatible with Standard mode, and these modes are sometimes referred to as Fast/Standard, or F/S mode. The I C Bus Specification (Version 2.1, January 2000), available from Philips Semiconductor, provides the details for the bus protocol and implementation. It is assumed that the reader is familiar with this specification. Refer to the Electrical Characteristics: I C Standard and Fast Modes table and Figure for specifications and a timing diagram that highlight the key parameters for I C interface operation. When the I C mode is invoked, pin becomes SCL (which serves as the bus clock) and pin becomes SDA (which carries the bi-directional serial data for the bus). Pins and become and A1, respectively, and function as the hardware configurable portion of the 7-bit slave address. The DIX4192 utilizes a 7-bit Slave address; see Figure (a). Bits through are fixed and bits and are hardware programmable using pins and 21, respectively. The programmable bits allow for up to four DIX4192 devices to be connected to the same bus. The slave address is followed by the Register Address Byte, which points to a specific register or data buffer location in the DIX4192 register map. The register address byte is comprised of seven bits for the address, and one bit for enabling or disabling auto-increment operation; see Figure (b). Auto-increment mode allows multiple sequential register locations to be written to or read back in a single operation, and is especially useful for block write and read operations. Figure illustrates the protocol for Standard and Fast mode Write operations. When writing a single register address, or multiple non-sequential register addresses, the single register write operation of Figure (a) may be used one or more times. When writing multiple sequential register addresses, the auto-increment mode of Figure (b) improves efficiency. The register address is automatically incremented by one for each successive byte of data transferred. Submit Documentation Feedback

www.ti.com A6 A5 A4 A3 A2 A1 A0 1 1 1 0 0 A1 A0 R/W Se yt b Pin 91 Se yt b Pin 12 MSB LSB Fir t s Byte After o itthe RSTA T/RESTART C ond i n Slave Address A6 A5 A4 A3 A2 A1 A0INC MSB LSB (a)□DIX419 lave2 S Address (b)□Regist r□Addree ss□Byte Auto-In ecrem nt 0□=□Disabled 1□=□Enabled S A A A P S A A A A A P Byte□1 Slave□Address with□R/W□=□0 Byte□2 Register□Address□Byte with□INC□=□0 Byte□3 Reg sti er Da□a t Byte□1 Slave□Address with□R/W□=□0 Byte□2 Register□Address□Byte with□INC□=□1 Byte□3 Register□Data Byte□4 Register□Data fo Addr ress□+□1 Byte□N Register Data for□Address□+□N (a)□Writing□a□Single□Register (b) rW iting ult isters□Using uto-Incr m nt□OperationM ip A ele□Se uential□R gq e e S□=□STAR oT n iCo d ti n A□=□Acknowl d ee g P□=□STOP□Condi□i nt o Transfer□from steMa r to Slave Transfer□from□Slave□to Master Legend DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Figure illustrates the protocol for Standard and Fast mode Read operations. The current address read operation of Figure (a) assumes the value of the register address from the previously executed write or read operation, and is useful for polling a register address for status changes. Figure (b) and Figure (c) illustrate read operations for one or more random register addresses, with or without auto-increment mode enabled. Figure 18. DIX4192 Slave Address and Register Address Byte Definitions Figure 19. Fast/Standard Mode Write Operations Submit Documentation Feedback

www.ti.com S A A A A A P Byte□1 Slav Ade dress wit Rh /W□=□0 Byte□2 Reg tis er□Address□Byte wit Ih NC□=□1 Byte□3 Slave□Address with□R/W□=□1 Byte□4 Reg tis er□Data Byte□N Reg tis er□Data for□Address□+□N (c)□Random□Read□Op ment□Enablederation,□Auto-Incre S□=□START□C dion tion A□=□Ackn w dgo le e A =□Not□Ackno ledgew R□=□Repeated TARTS P□=□STOP□Condi□i nt o Transfer□from steMa r to Slave Transfer□from ave□toSl Master L gende R S A A P Byte□1 Slave□Addre ss with□R/W□=□1 Byte□2 Reg tis er□Address□Byte with□INC□=□0 (a Cu) rrent□Ad res he□Register ddr ss f□the vio sd A e Pre us Read,□Assumes□t o S A A A P Byte□1 Slav Ade dress with□R/W□=□0 Byte□2 Reg tis er□Address□Byte with□INC□=□0 Byte□3 Slav Ade dress with□R/W□=□1 (b)□Random□Read□Op me t□Disablederation,□Auto-Incre n R A Byte□4 Register□Data INTERRUPT OUTPUT VIO 10k/c87 T o□the outputs□fINT or additional□DIX4192 devices Interrupt Logic DIX4192 MCU,□DSP , or□Logic INT 23 Interrupt Input DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Figure 20. Fast/Standard Mode Read Operations The DIX4192 includes multiple internal status bits, many of which may be set to trigger an interrupt signal. The interrupt signal is output at INT (pin 23), which is an active low, open-drain output. The INT pin requires a pull-up resistor to the VIO supply rail. The value of the pull-up is not critical, but a 10k Ω device should be sufficient for most applications. Figure shows the interrupt output pin connection. The open-drain output allows interrupt pins from multiple DIX4192 devices to be connected in a wired OR configuration. Figure 21. Interrupt Output Pin Connections Submit Documentation Feedback

www.ti.com device. Figure illustrates typical application connections for the DIX4192 using an SPI host interface. The SPI host will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to providing the SPI bus master, the host may be utilized to process interrupt and flag outputs from the DIX4192. The audio serial ports are connected to external digital audio devices, which may include data converters, digital signal processors, digital audio interface receivers/transmitters, or other logic devices. The DIR inputs and DIT outputs are connected to line, optical, or logic interfaces (see the Receiver Input Interfacing and Transmitter Output Interfacing sections). Master and DIR reference clock sources are also shown. Figure illustrates typical application connections for the DIX4192 using an I C bus interface. The I C bus master will typically be a microcontroller, digital signal processor, or a programmable logic device. In addition to providing the I C bus master, the host may be used to process interrupt and flag outputs from the DIX4192. Pull-up resistors are connected from SCL (pin 20) and SDA (pin 22) to the VIO supply rail. These resistors are required for the open drain outputs of the I C interface. All other connections to the DIX4192 are the same as the SPI host case discussed previously. Figure illustrates the recommended power-supply connections and bypassing for the DIX4192. In this case, it is assumed that the VIO, VDD33, and VCC supplies are powered from the same +3.3V power source. The VDD18 core supply is powered from a separate supply, or derived from the +3.3V supply using a linear voltage regulator, as illustrated with the optional regulator circuitry of Figure The 0.1 µ F bypass capacitors are surface-mount X7R ceramic, and should be located as close to the device as possible. These capacitors should be connected directly between the supply and corresponding ground pins of the DIX4192. The ground pin is then connected directly to the ground plane of the printed circuit board (PCB). The larger value capacitors, shown connected in parallel to the 0.1 µ F capacitors, are recommended. At a minimum, there should at least be footprints on the PCB for installation of these larger capacitors, so that experiments can be run with and without the capacitors installed, in order to determine the effect on the measured performance of the DIX4192. The larger value capacitors can be surface-mount X7R multilayer ceramic or tantalum chip. The substrate ground, BGND (pin 44), should be connected by a PCB trace to AGND (pin 10). The AGND pin is then connected directly to the ground plane. This connection helps to reduce noise in the DIR section of the device, aiding the overall jitter and noise tolerance for the receiver. A series resistor is shown between the +3.3V supply and VCC (pin connection. This resistor combines with the bypass capacitors to create a simple RC filter to remove higher frequency components from the VCC supply. The series resistor should be a metal film type for best filtering characteristics. As a substitute for the resistor, a ferrite bead can be utilized, although it may have to be physically large in order to contribute to the filtering. Submit Documentation Feedback

www.ti.com BCKA LRCKA SDINA SDOUTA NC VIO DGND3 BGND SDOUTB SDINB LRCKB BCKB RX1+ RX1/c45 RX2+ RX2/c45 RX3+ RX3/c45 RX4+ RX4/c45 VCC AGND LOCK RXCKO SYNC BLS AESOUT VDD33 TX+ TX/c45 DGND2 GPO4 GPO3 GPO2 GPO1 MCLK RST INT CDOUT CDIN CCLK CS CPM VDD18 DGND1 NC NC RXCKI DIX4192IPFB From□Digita Inpul ts (Line, Optical,□Logic) T o□Digital□Outputs (L ne,i O ca Lpti l, ogic) T o□Host o Exter alr n Logic T o□Host or xternalE Logic SPI Host Controller Audio I/O Device Audio I/O Device DIR Ref□Clock Master Clock DIR□Recovered□Clock VIO 10k/c87 BCKA LR KAC SDI AN SDOUTA NC VIO DGND3 BGND SDOUTB SDI BN LR KBC BCKB RX +1 RX /c451 RX +2 RX /c452 RX +3 RX /c453 RX +4 RX /c454 VCC AGND LOCK RX KOC SYNC BLS AESO TU VDD 33 TX+ TX/c45 DGND2 GP 4O GP 3O GP 2O GP 1O MCLK RST INT SDA SCL CPM VDD 81 DGND1 NC NC RX KIC DIX4192IPFB From□Digital□Inputs (Line, Optica ,□Logl ic) T o Digital Outputs (Line, Optical,□Logic) T o□Host or□Exte nalr Logic T o□Host or□Exte nalr Logic I C Ho t s Controller Audio I/O Device Audio I/O Device DIR Ref□Clock Master Clock DIR□Recovered□Clock VIO 10k/c87 2.7k/c87 Tie LO□or□HI DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 (continued) Figure 22. Typical Application Diagram Using SPI Host Interface (See Figure for Power-Supply Connections.) Figure 23. Typical Application Diagram Using I C Host Interface (See Figure for Power-Supply Connections.) Submit Documentation Feedback

www.ti.com 0.1/c109F 10 F/c109 0.1 F/c109 10 F/c1090.1 F/c109 +3. V3 10 30 4243

10 F/c109

R Connect pin□44 to pin 10. Pi 10n i then□connes cted□to the□ground□pl n .a e +3. V3 0.1 F/c109 0□01 F/c109. 2.2 F /c109 TPS79318DB RV DIX4192IPFB Optional□Regulator Circuit 1716 R□may□be set□from□2 t ced□b fe te□b/c87 y□a rri eo 10 or□repla/c87, ad. C□may□be set□to□10 F d□when□using□the□opt onal□r/c109 egulator□circuit., or□not□installe i 1 5 3 4 IN EN OUT NR GND +1.8V C

0.1 F/c109

(continued) Figure 24. Recommended Power-Supply Connections Transformers are shown in this data sheet for both receiver and transmitter balanced and unbalanced line interface implementations. For the Texas Instruments Pro Audio evaluation modules, transformers from Scientific Conversion are utilized. In addition to Scientific Conversion, there are other vendors that offer transformer products for digital audio interface applications. Please refer to the following manufacturer web sites for details regarding their products and services. Other transformer vendors may also be available by searching catalog and/or Internet resources. Scientific Conversion: http://scientificonversion.com Schott Corporation: http://schottcorp.com Pulse Engineering: http://pulseeng.com Submit Documentation Feedback

www.ti.com RECEIVER INPUT INTERFACING (1)□Insert□a□0.1 F□cap common-mode□DC□voltage./c109 acitor□when□blocking 1:1 110/c87 T o□RX+ T Ro /c45X XLR Digital□Input

110 B/c87 alanced

C (1) (1)□Insert□a□0.1 F□cap common-mode□DC/c109 acitor□when□blocking components. 1:1 75/c87 T o□RX+ T o□RX/c45 Dig tai l□Input

75 Unbalan/c87 ced

(RCA□or□BNC□Connector) C (1) (a)□Transformer-Coupled□Unbalanced□Line□Interface 75/c87 T o□RX+ T o□RX/c45 Digital□Input (RCA□or□BNC□Connector) (b)□Unbalanced□Line□Interface□Without□Transformer DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 (continued) This section details the recommended interfaces for the DIX4192 line receiver inputs. Balanced and unbalanced line interfaces, in addition to optical receiver and external logic interfacing, are discussed. For professional digital audio interfaces, 110 Ω balanced line interfaces are either required or preferred. Transformer coupling is commonly employed to provide isolation and to improve common-mode noise rejection. Figure shows the recommended transformer-coupled balanced line receiver interface for the DIX4192. The transformer is specified for a 1:1 turn ratio, and should exhibit low inter-winding capacitance for best performance. Due to the DC bias on the line receiver inputs, 0.1 µ F capacitors are utilized for AC-coupling the transformer to the line receiver inputs. On the line side of the transformer, an optional 0.1 µ F capacitor is shown for cases where a DC bias may be applied at the transmitter side of the connection. The coupling capacitors should be surface-mount ceramic chip type with an X7R or C0G dielectric. Figure 25. Transformer-Coupled Balanced Input Interface Unbalanced Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio applications. Designs with and without transformer line coupling may be utilized. Figure (a) shows the recommended Ω transformer-coupled line interface, which shares many similarities to the balanced design shown in Figure Once again, the transformer provides isolation and improved noise rejection. Figure (b) shows the transformer-free interface, which is commonly used for S/PDIF consumer connections. Figure 26. Unbalanced Line Input Interfaces Submit Documentation Feedback

www.ti.com VDD33 T o□RX+ T o□RX/c45 All-Plastic (5□or□10□meters□maximum) (1)□T oshiba□TORX141□or□equivalent. Optical Receiver (1) (1)□T oshiba□TORX173,□TORX176,□TORX179,□or□equivalent. +5V SN74L VC1G125 or□Equivalent 0.1/c109 F T RX+o T o□RX/c45 All-Plastic (5□or□10□meters□maximum) Optical Receiver (1) VDD33 3 1 DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 (continued) Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where interconnections are less than 10m in length. Optical receiver modules utilized for a digital audio interface operate from either a single +3.3V or +5V supply and have a TTL-, CMOS-, or low-voltage CMOS-compatible logic output. Interfacing to +3.3V optical receivers is straightforward when the optical receiver supply is powered from the DIX4192 VDD33 power source, as shown in Figure For the +5V optical receivers, the output high logic level may exceed the DIX4192 line receiver absolute maximum input voltage. A level translator is required, placed between the optical receiver output and the DIX4192 line receiver input. Figure shows the recommended input circuit when interfacing a +5V optical receiver to the DIX4192 line receiver inputs. The Texas Instruments SN74LVC1G125 single buffer IC is operated from the same +3.3V supply used for DIX4192 VDD33 supply. This buffer includes a +5V tolerant digital input, and provides the logic level translation required for the interface. Figure 27. Interfacing to a +3.3V Optical Receiver Module Figure 28. Interfacing to a +5V Optical Receiver Module Submit Documentation Feedback

www.ti.com SN74L VC1G125 or□Equivalent 0.1/c109 F T RX+o T o□RX/c45 From□+5V□Logic (TTL□or□CMOS) VDD33 3 1 SN74AVC1T45 or□Equivalent 0.1/c109 F T RX+o T o□RX/c45 From□+1.8V□or□+2.5V CMOS□Logic +1.8V□or□+2.5V VDD33 TRANSMITTER OUTPUT INTERFACING 1:1 Digital□Output (continued) The DIX4192 line receivers may also be driven directly from external logic or line receiver devices with TTL or CMOS outputs. If the logic driving the line receiver is operated from +3.3V, then logic level translation will not be required. However, if the external logic is operated from a power-supply voltage that exceeds the maximum VDD33 supply voltage of the DIX4192, or operates from a supply voltage lower than +3.3V, then level translation is required. Figure shows the recommended logic level translation methods, utilizing buffers and level translators available from Texas Instruments. Figure 29. CMOS/TTL Input Logic Interface This section details the recommended interfaces for the DIX4192 transmitter line driver and CMOS-buffered outputs. Balanced and unbalanced line interfaces, in addition to optical transmitter and external logic interfacing, will be discussed. For professional digital audio interfaces, 110 Ω balanced line interfaces are either required or preferred. Transformer coupling is commonly employed to provide isolation and to improve common-mode noise performance. Figure shows the recommended transformer-coupled balanced line driver interface for the DIX4192. The transformer is specified for a 1:1 turn ratio, and should exhibit low inter-winding capacitance for best performance. To eliminate residual DC bias, a 0.1 µ F capacitor is utilized for AC-coupling the transformer to the line driver outputs. The coupling capacitor should be a surface-mount ceramic chip type with an X7R or C0G dielectric. Figure 30. Transformer-Coupled Balanced Output Interface Unbalanced Ω coaxial cable interfaces are commonly employed in consumer and broadcast audio applications. Designs with and without transformer line coupling may be utilized. Figure (a) illustrates the recommended Ω transformer-coupled line driver interface, which shares many similarities to the balanced design shown in Figure Figure (b) illustrates the transformer-free line driver interface, which is commonly used for S/PDIF consumer connections. Submit Documentation Feedback

www.ti.com R1□and□R2□are□selected□to□achieve□the□desired□output□voltage□level□while□maintaining□the□required□75 transmitter□output□impedance./c87 The□TX+□output□impedance□is□negligible. (a)□Transformer-Coupled□Unbalanced□Output 1:1 Digital□Output (RCA□or□BNC□connector) (b)□Unbalanced□Output□Without□Transformer 0.1/c109F TX+ Digital□Output (RCA□or□BNC□connector) (1)□T oshiba□TOTX141,□TOTX173,□TOTX176,□TOTX179,□or□equivalent. SN74AVC1T45 or□Equivalent If□VIO□<□+3.0V. VIO +3.3V All-Plastic□Fiber (5□or□10□meters□maximum)AESOUT Optical Transmitter (1) DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 (continued) Figure 31. Unbalanced Line Output Interfaces Optical interfaces utilizing all-plastic fiber are commonly employed for consumer audio equipment where interconnections are less than 10m in length. Most optical transmitter modules utilized for a digital audio interface operate from a single +3.3V or +5V supply and have a TTL-compatible logic input. The CMOS-buffered transmitter output of the DIX4192, AESOUT (pin 34), is capable of driving the optical transmitter with VIO supply voltages down to +3.0V. If the VIO supply voltage is less than +3.0V, then level translation logic is required to drive the optical transmitter input. A good choice for this application is the Texas Instruments SN74AVC1T45 single bus transceiver. This device rails, one for the input side and one for the output side. For this application, the input side supply is powered from the VIO supply, while the output side is powered from a +3.3V supply. This configuration will boost the logic high level to a voltage suitable for driving the TTL-compatible input configuration. Figure shows the recommended optical transmitter interface circuits. Figure 32. Interfacing to an Optical Transmitter Module The AESOUT output may also be used to drive external logic or line driver devices directly. Figure illustrates the recommended logic interface techniques, including connections with and without level translation. Figure illustrates an external line driver interface utilizing the Texas Instruments SN75ALS191 dual differential line driver. If the VIO supply of the DIX4192 is set from +3.0V to +3.3V, no logic level translation will be required between the AESOUT output and the line driver input. If the VIO supply voltage is below this range, then the optional logic level translation logic of Figure will be required. The SN75ALS191 dual line driver is especially useful in Ω and 110 Ω line interfaces are required. Submit Documentation Feedback

www.ti.com SN74AHCT1G125 or□Equivalent +5V Direct□to□external□logic operating□from□the□VIO□supply.AESOUT T o□+5V□Logic (VIO□supply□=□+3.0V□to□+3.3V) SN74AVC1T45 or□Equivalent If□VIO□<□+3.0V. VIO +5V +3.3V T o□Balanced□or□Unbalanced Line□InterfaceAESOUT T o□Balanced□or□Unbalanced Line□Interface SN75ALS191 REGISTER AND DATA BUFFER ORGANIZATION DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 (continued) Figure 33. CMOS/TTL Output Logic Interface Figure 34. External Line Driver Interface The DIX4192 organizes the on-chip registers and data buffers into four pages. The currently active page is chosen by programming the Page Selection Register to the desired page number. The Page Selection Register is available on every register page at address 0x7F, allowing easy movement between pages. Table indicates the page selection corresponding to the Page Selection Register value. Table Register Page Selection Page Selection Register Value (Hex) Selected Register Page Page control and status registers Page DIR channel status and user data buffers Page DIT channel status and user data buffers Page reserved Register Page contains the control registers utilized to configure the various function blocks within the DIX4192. In addition, status registers are provided for flag and error conditions, with many of the status bits capable of generating an interrupt signal when enabled. See Table for the control and status register map. Register Page contains the digital interface receiver (or DIR) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the previously received block of the AES3-encoded data stream. The I C serial host interface and processed as needed by the host system. See Table for the DIR channel status buffer map, and Table for the DIR user data buffer map. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register Page contains the digital interface transmitter (or DIT) channel status and user data buffers. These buffers correspond to the data contained in the C and U bits of the transmitted AES3-encoded data stream. The I C serial host interface to configure the C and U bits of the transmitted AES3 data stream. The buffers may also be read for verification by the host system. See Table for the DIT channel status buffer map, and Table for the DIT user data buffer map. Register Page is reserved for factory test and verification purposes, and cannot be accessed without an unlock code. The unlock code remains private; the test modes disable normal operation of the device, and are not useful in customer applications. Submit Documentation Feedback

www.ti.com CONTROL REGISTERS DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 See Table for the control and status register map of the DIX4192. Register addresses 0x00 and 0x2D through 0x7E are reserved for factory or future use. All register addresses are expressed as hexadecimal numbers. The following pages provide detailed descriptions for each control and status register. Table Control and Status Register Map (Register Page ADDRESS (Hex) (MSB) REGISTER GROUP RESET PDALL PDPA PDPB PDTX PDRX Power-down and reset TX RX Global interrupt status AMUTE AOUTS1 AOUTS0 AM/S AFMT2 AFMT1 AFMT0 Port A control ACLK1 ACLK0 ADIV1 ADIV0 Port A control BMUTE BOUTS1 BOUTS0 BM/S BFMT2 BFMT1 BFMT0 Port B control BCLK1 BCLK0 BDIV1 BDIV0 Port B control TXCLK TXDIV1 TXDIV0 TXIS1 TXIS0 BLSM VALID BSSL Transmitter control BYPMUX1 BYPMUX0 AESMUX LDMUX TXBTD AESOFF TXMUTE TXOFF Transmitter control VALSEL TXCUS1 TXCUS0 Transmitter control TSLIP TBTI DIT status MTSLIP MTBTI DIT interrupt mask TSLIPM1 TSLIPM0 TBTIM1 TBTIM0 DIT interrupt mode RXBTD RXCLK RXMUX1 RXMUX Receiver control LOL RXAMLL RXCKOD1 RXCKOD0 RXCKOE Receiver control Receiver PLL configuration D13 D12 D11 D10 Receiver PLL configuration Receiver PLL configuration DTS CD/LD IEC61937 Non-PCM audio detection RXCKR1 RXCKR0 Receiver status CSCRC PARITY VBIT BPERR QCHG UNLOCK QCRC RBTI Receiver status OSLIP Receiver status MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI Receiver interrupt mask MOSLIP Receiver interrupt mask QCHGM1 QCHGM0 UNLOCKM1 UNLOCKM0 QCRCM1 QCRCM0 RBTIM1 RBTIM0 Receiver interrupt mode CSCRCM1 CSCRCM0 PARITYM1 PARITYM0 VBITM1 VBITM0 BPERRM1 BPERRM0 Receiver interrupt mode OSLIPM1 OSLIPM0 Receiver interrupt mode GPO13 GPO12 GPO11 GPO10 General-purpose out (GPO1) GPO23 GPO22 GPO21 GPO20 General-purpose out (GPO2) GPO33 GPO32 GPO31 GPO30 General-purpose out (GPO3) GPO43 GPO42 GPO41 GPO40 General-purpose out (GPO4) Audio CD Q-channel sub-code Q10 Q11 Q12 Q13 Q14 Q15 Audio CD Q-channel sub-code Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Audio CD Q-channel sub-code Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Audio CD Q-channel sub-code Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Audio CD Q-channel sub-code Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Audio CD Q-channel sub-code Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Audio CD Q-channel sub-code Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Audio CD Q-channel sub-code Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Audio CD Q-channel sub-code Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79 Audio CD Q-channel sub-code PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 PC burst preamble, high byte PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 PC burst preamble, low byte PD15 PD14 PD13 PD12 PD11 PD10 PD09 PD08 PD burst preamble, high byte PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 PD burst preamble, low byte PAGE1 PAGE0 Page selection Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 01: Power-Down and Reset Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) RESET PDALL PDPA PDPB PDTX PDRX PDRX Power-Down for the Receiver Function Block This bit is utilized to power-down the DIR and associated functions. All receiver outputs are forced low. PDRX Receiver Power-Down Mode Enabled (default) Disabled; the Receiver function block will operate normally based upon the applicable control register settings. PDTX Power-Down for the Transmitter Function Block This bit is utilized to power-down the DIT and associated functions. All transmitter outputs are forced low. PDTX Transmitter Power-Down Mode Enabled (default) Disabled; the Transmitter function block will operate normally based upon the applicable control register settings. PDPB Power-Down for Serial Port B This bit is utilized to power-down the audio serial I/O Port All port outputs are forced low. PDPB Port B Power-Down Mode Enabled (default) Disabled; Port B will operate normally based upon the applicable control register settings. PDPA Power-Down for Serial Port A This bit is utilized to power-down the audio serial I/O Port All port outputs are forced low. PDPA Port A Power-Down Mode Enabled (default) Disabled; Port A will operate normally based upon the applicable control register settings. PDALL Power-Down for All Functions This bit is utilized to power-down all function blocks except the host interface port and the control and status registers. PDALL All Function Power-Down Mode Enabled (default) Disabled; all function blocks will operate normally based upon the applicable control register settings. RESET Software Reset This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset via the RST input (pin 24). RESET Reset Function Disabled (default) Enabled; all control registers will be reset to the default state. Register 02: Global Interrupt Status (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) TX RX RX Receiver Function Block Interrupt Status (Active High) When set to this bit indicates an active interrupt from the DIR function block. This bit is active high. The user should then read status registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt. TX Transmitter Function Block Interrupt Status (Active High) When set to this bit indicates an active interrupt from the DIT function block. This bit is active high. The user should then read status register 0x0A in order to determine which of the sources has generated an interrupt. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 03: Port A Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) AMUTE AOUTS1 AOUTS0 AM/S AFMT2 AFMT1 AFMT0 AFMT[2:0] Port A Audio Data Format These bits are used to set the audio input and output data format for Port Refer to the Audio Serial Port Operation section for illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure for an applicable timing diagram and parameters. AFMT2 AFMT1 AFMT0 Audio Data Format 24-Bit Left-Justified (default) 24-Bit Philips I S Unused Unused 16-Bit Right-Justified 18-Bit Right-Justified 20-Bit Right-Justified 24-Bit Right-Justified AM/S Port A Slave/Master Mode This bit is used to set the audio clock mode for Port A to either Slave or Master. AM/S Slave/Master Mode Slave mode; the LRCK and BCK clocks are inputs generated by an external digital audio source. (default) Master mode; the LRCK and BCK clocks are outputs, derived from the Port A master clock source. AOUTS[1:0] Port A Output Data Source These bits are used to select the output data source for Port The data is output at SDOUTA (pin 40). AOUTS1 AOUTS0 Output Data Source Port A input, for data loop back. (default) Port B input DIR Reserved AMUTE Port A Output Mute This bit is used to mute the Port A audio data output. AMUTE Output Mute Disabled; SDOUTA is driven by the output data source. (default) Enabled; SDOUTA is forced low. Register 04: Port A Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) ACLK1 ACLK0 ADIV1 ADIV0 ADIV[1:0] Port A Master Clock Divider These bits are used to set the master clock divider for generating the LRCKA clock for Port A when configured for Master mode operation. BCKA is always set to times the LRCKA clock rate in Master mode. ADIV1 ADIV0 Master Mode Clock Divider Divide-by-128 (default) Divide-by-256 Divide-by-384 Divide-by-512 Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 ACLK[1:0] Port A Master Clock Source These bits are used to set the master clock source for Port A when configured for Master mode operation. ACLK1 ACLK0 Master Clock Source MCLK (default) RXCKI RXCKO Reserved Register 05: Port B Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) BMUTE BOUTS1 BOUTS0 BM/S BFMT2 BFMT1 BFMT0 BFMT[2:0] Port B Audio Data Format These bits are used to set the audio input and output data format for Port Refer to the Audio Serial Port Operation section for illustrations of the supported data formats. Refer to the Electrical Characteristics: Audio Serial Ports table and Figure for an applicable timing diagram and parameters. BFMT2 BFMT1 BFMT0 Audio Data Format 24-Bit Left-Justified (default) 24-Bit Philips I S Unused Unused 16-Bit Right-Justified 18-Bit Right-Justified 20-Bit Right-Justified 24-Bit Right-Justified BM/S Port B Slave/Master Mode This bit is used to set the audio clock mode for Port B to either Slave or Master. BM/S Slave/Master Mode Slave mode; the LRCK and BCK clocks are generated by an external source. (default) Master mode; the LRCK and BCK clocks are derived from the Port A master clock source. BOUTS[1:0] Port B Output Source These bits are used to select the output data source for Port The data is output at SDOUTB (pin 45). BOUTS1 BOUTS0 Output Data Source Port B input, for data loop back. (default) Port A input DIR Reserved BMUTE Port B Output Mute This bit is used to mute the Port B audio data output. BMUTE Output Mute Disabled; SDOUTB is driven by the output data source. (default) Enabled; SDOUTB is forced low. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 06: Port B Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) BCLK1 BCLK0 BDIV1 BDIV0 BDIV[1:0] Port B Master Mode Clock Divider These bits are used to set the master clock divider for generating the LRCKB clock for Port B when configured for Master mode operation. BCKB is always set to times the LRCKB clock rate in Master mode. BDIV1 BDIV0 Master Mode Clock Divider Divide-by-128 (default) Divide-by-256 Divide-by-384 Divide-by-512 BCLK[1:0] Port B Master Clock Source These bits are used to set the master clock source for Port B when configured for Master mode operation. BCLK1 BCLK0 Master Clock Source MCLK (default) RXCKI RXCKO Reserved Register 07: Transmitter Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) TXCLK TXDIV1 TXDIV0 TXIS1 TXIS0 BLSM VALID BSSL BSSL Block Start or Asynchronous Data Slip Interrupt Trigger Selection This bit is used to select the trigger source for the Transmitter TSLIP status and interrupt bit. BSSL TSLIP Interrupt Trigger Source Data slip condition (default) Block start condition VALID Validity (V) Data Bit This bit may be used to set the validity (or data bit in the AES3-encoded output. Refer to the VALSEL bit in control register 0x09 for V-bit source selection. VALID Transmitted Validity (V) Bit Data Indicates that the transmitted audio data is suitable for conversion to an analog signal or for further digital processing. (default) Indicates that the transmitted audio data is not suitable for conversion to an analog signal or for further digital processing. BLSM Transmitter Block Start Input/Output Mode This bit is used to select the input/output mode for the DIT block start pin, BLS (pin 35). BLSM BLS Pin Mode Input (default) Output TXIS[1:0] Transmitter Input Data Source These bits are used to select the audio data source for the DIT function block. TXIS1 TXIS0 Output Word Length Port A (default) Port B DIR Reserved Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 TXDIV[1:0] Transmitter Master Clock Divider These bits are used to select the Transmitter master clock divider, which determines the output frame rate. TXDIV1 TXDIV0 Clock Divider Divide the master clock by 128. (default) Divide the master clock by 256. Divide the master clock by 384. Divide the master clock by 512. TXCLK Transmitter Master Clock Source This bit is used to select the master clock source for the Transmitter block. TXCLK Transmitter Master Clock Source MCLK input (default) RXCKO; the recovered master clock from the DIR function block. Register 08: Transmitter Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) BYPMUX1 BYPMUX0 AESMUX LDMUX TXBTD AESOFF TXMUTE TXOFF TXOFF Transmitter Line Driver Output Enable This bit is used to enable or disable the TX+ (pin 32) and TX (pin 31) line driver outputs. TXOFF Transmitter Line Driver Enabled; the line driver outputs function normally. (default) Disabled; the line driver outputs are forced low. TXMUTE Transmitter Audio Data Mute This bit is used to set the bits of audio and auxiliary data to all zeros for both Channels and TXMUTE Transmitter Audio Data Mute Disabled (default) Enabled; the audio data for both channels and are set to all zeros. AESOFF AESOUT Output Enable This bit is used to enable or disable the AESOUT (pin 34) buffered AES3-encoded CMOS logic level output. AESOFF AESOUT Output Enabled; the AESOUT pin functions normally. (default) Disabled; the AESOUT pin is forced low. TXBTD Transmitter C and U Data Buffer Transfer Disable This bit is used to enable and disable buffer transfers between the DIT User Access (UA) and DIT Transmitter Access (TA) buffers for both channel status (C) and user (U) data. Buffer transfers may be disabled, allowing the user to write new C and U data to the UA buffers via the SPI or I C serial host interface. Once updated, UA-to-TA buffer transfers may then be re-enabled, allowing the TA buffer to be updated and the new C and U data to be transmitted at the start of the next block. TXBTD User Access (UA) to Transmitter Access (TA) Buffer Transfers Enabled (default) Disabled; allows the user to update DIT C and U data buffers. Note: The TXCUS0 and TXCUS1 bits in control register 0x09 must be set to a non-zero value in order for DIT UA buffer updates to occur. LDMUX Transmitter Line Driver Input Source Selection This bit is used to select the input source for the DIT differential line driver outputs. LDMUX Line Driver Input Source DIT AES3 encoder output (default) Bypass multiplexer output AESMUX AESOUT CMOS Buffer Input Source Selection This bit is used to select the input source for the AESOUT CMOS logic level output. AESMUX AESOUT Buffer Input Source DIT AES3 encoder output (default) Bypass multiplexer output Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 BYPMUX[1:0] Bypass Multiplexer Source Selection These bits select the line receiver output to be utilized as the bypass multiplexer data source. BYPMUX1 BYPMUX0 Line Receiver Output Selection RX1 (default) RX2 RX3 RX4 Register 09: Transmitter Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) VALSEL TXCUS1 TXCUS0 TXCUS[1:0] Transmitter Channel Status and User Data Source These bits select the source of the channel status (or data and user (or data which is used to load the DIT User Access (UA) buffers. TXCUS1 TXCUS0 DIT UA Buffer Source The buffers will not be updated. (default) The buffers are updated via the SPI or I C host interface. The buffers are updated via the DIR RA buffers. The first bytes of the buffers are updated via the SPI or I C host, while the remainder of the buffers are updated via the DIR RA buffers. VALSEL Transmitter Validity Bit Source This bit is utilized to select the source for the validity (or bit in the AES3-encoded output data stream. VALSEL Validity (or Bit Source Selection The VALID bit in control register 0x07. The V bit is transferred from the DIR block with zero latency. Register 0A: DIT Status (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) TSLIP TBTI TBTI Transmitter Buffer Transfer Status, Active High When DIT User Access (UA) to Transmitter Access (TA) buffer transfers are enabled (the TXBTD bit in control register 0x08 is set to 0), and the TBTI interrupt is unmasked (the MTBTI bit in control register 0x0B is set to 1), the TBTI bit will be set to when the UA-to-TA buffer transfer has completed. This configuration also causes the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set to indicating that an interrupt has occurred. TSLIP Transmitter Source Data Slip Status, Active High The TSLIP bit will be set to when either an asynchronous data slip or block start condition is detected, and the TSLIP interrupt is unmasked (the MTSLIP bit in control register 0x0B is set to 1). The BSSL bit in control register 0x07 is used to set the source for this interrupt. The TSLIP bit being forced to will also cause the INT output (pin 23) to be driven low and the TX bit in status register 0x02 to be set to indicating that an interrupt has occurred. Register 0B: DIT Interrupt Mask Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) MTSLIP MTBTI MBTI Transmitter Buffer Transfer Interrupt Mask MTBI BTI Interrupt Mask BTI interrupt is masked. (default) BTI interrupt is enabled. MTSLIP Transmitter TSLIP Interrupt Mask MTSLIP TSLIP Interrupt Mask TSLIP interrupt is masked. (default) TSLIP interrupt is enabled. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 0C: DIT Interrupt Mode Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) TSLIPM1 TSLIPM0 TBTIM1 TBTIM0 TBTIM[1:0] Transmitter Buffer Transfer Interrupt Mode These bits are utilized to select the active trigger state for the BTI interrupt. TBTIM1 TBTIM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved TSLIPM[1:0] Transmitter Data Source Slip Interrupt Mode These bits are utilized to select the active trigger state for the TSLIP interrupt. TSLIPM1 TSLIPM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved Register 0D: Receiver Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) RXBTD RXCLK RXMUX1 RXMUX0 RXMUX[1:0] Receiver Input Source Selection These bits are used to select the output of the line receiver to be used as the input data source for the DIR core. RXMUX1 RXMUX0 Input Selection RX1 (default) RX2 RX3 RX4 RXCLK Receiver Reference Clock Source This bit is used to select the reference clock source for PLL1 in the DIR core. RXCLK Receiver Reference Clock RXCKI (default) MCLK RXBTD Receiver C and U Data Buffer Transfer Disable This bit is used to enable and disable buffer transfers between the Receiver Access (RA) and User Access (UA) buffers for both channel status (C) and user (U) data. Buffer transfers are typically disabled to allow the customer to read C and U data from the DIR UA buffer via the SPI or I C serial host interface. Once read, the RA-to-UA buffer transfer can be re-enabled to allow the RA buffer to update the time. RXBTD Receiver Access (RA) to User Access (UA) Buffer Transfers Enabled (default) Disabled; the user may read C and U data from the DIR UA buffers. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 0E: Receiver Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) LOL RXAMLL RXCKOD1 RXCKOD0 RXCKOE RXCKOE RXCKOE Output Enable This bit is used to enable or disable the recovered clock output, RXCKO (pin 12). When disabled, the output is set to a high-impedance state. RXCKOE RXCKO Output State Disabled; the RXCKO output is set to high-impedance. (default) Enabled; the recovered master clock is available at RXCKO. RXCKOD[1:0] RXCKO Output Clock Divider These bits are utilized to set the clock divider at the output of PLL2. The output of the divider is the RXCKO clock, available internally or at the RXCKO output (pin 12). RXCKOD1 RXCKOD0 RXCKO Output Divider Passthrough; no division is performed. (default) Divide the PLL2 clock output by Divide the PLL2 clock output by Divide the PLL2 clock output by RXAMLL Receiver Automatic Mute for Loss of Lock This bit is used to set the automatic mute function for the DIR block when a loss of lock is indicated by both the AES3 decoder and PLL2. RXAMLL Receiver Auto-Mute Function Disabled (default) Enabled; audio data output from the DIR block is forced low for a loss of lock condition. LOL Receiver Loss of Lock Mode for the Recovered Clock (output from PLL2) This bit is used to set the mode of operation for PLL2 when a loss of lock condition occurs. LOL Receiver PLL2 Operation The PLL2 output clock is stopped for a loss of lock condition. (default) The PLL2 output clock free runs when a loss of lock condition occurs. Register 0F: Receiver PLL1 Configuration Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Register 10: Receiver PLL1 Configuration Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) D13 D12 D11 D10 Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 11: Receiver PLL1 Configuration Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Registers 0x0F through 0x11 are utilized to program PLL1 in the DIR core. PLL1 multiplies the DIR reference clock source to an oversampling rate which is adequate for AES3 decoder operation. PLL1 is programmed using the following relationship: (CLOCK P 98.304MHz where: CLOCK frequency of the DIR reference clock source. K J.D, where the integer part J to 63, and the fractional part D to 9999. P the pre-divider value, which may be set to any 4-bit value that meets the conditions stated below. The following conditions must be met for the values of and If D then: If D then: MHz (CLOCK MHz and J 55. MHz (CLOCK MHz and J 11. Referring to registers 0x0F through 0x11: P is programmed using bits P[3:0]. J is programmed using bits J[5:0]. D is programmed using bits D[13:0]. Table shows values for and D for common DIR reference clock rates. Table PLL1 Register Values for Common Reference Clock Rates REFERENCE CLOCK RATE (MHz) P J D ERROR (%) 8.1920 0.0000 11.2896 7075 0.0002 12.2880 0.0000 16.3840 0.0000 22.5792 7075 0.0002 24.5760 0.0000 27.0000 2818 0.0003 Register 12: Non-PCM Audio Detection Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) DTS CD/LD IEC61937 IEC61937 This bit is utilized to indicate the detection of an IEC 61937 data reduced audio format (includes Dolby AC-3, DTS, etc.) for DVD playback or general transmission purposes. IEC61937 Status Data is not an IEC61937 format. Data is an IEC61937 format. Refer to the PC and PD preamble registers (addresses 0x29 through 0x2C) for data type and burst length. DTS CD/LD This bit is used to indicate the detection of a DTS encoded audio compact disc (CD) or Laserdisc (LD) playback. DTS CD/LD Status The CD/LD is not DTS-encoded. DTS CD/LD playback detected. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 13: Receiver Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) RXCKR1 RXCKR0 RXCKR[1:0] Maximum Available Recovered Clock Rate These two bits indicate the maximum available RXCKO clock rate based upon the DIR detection circuitry, which determines the frame rate of the incoming AES3-encoded bit stream. Based upon the estimated frame rate, a maximum rate for the recovered clock output (RXCKO) is determined and output from PLL2, as well as being loaded into the RXCKR0 and RXCKR1 status bits. The status of the RXCKR0 and RXCKR1 bits may be utilized to determine the programmed value for the PLL2 output clock divider, set by the RXCKOD0 and RXCKOD1 bits in control register 0x0E. RXCKR1 RXCKR0 Maximum Available RXCKO Rate Clock rate not determined. 128f S 256f S 512f S Register 14: Receiver Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) CSCRC PARITY VBIT BPERR QCHG UNLOCK QCRC RBTI Note: Status bits must be unmasked in control register 0x16 in order for the status interrupts to be generated. CSCRC Channel Status CRC Status CSCRC CRC Status No error CRC error detected PARITY Parity Status PARITY Parity Status No error Parity error detected VBIT Validity Bit Status VBIT Validity Bit Valid audio data indicated Non-valid data indicated BPERR Biphase Encoding Error Status BPERR Biphase Encoding Status No error Biphase encoding error detected QCHG Q-Channel Sub-Code Data Change Status QCHG Q-Channel Data Status No change in Q-channel sub-code data. Q-channel data has changed. May be used to trigger a read of the Q-channel sub-code data, registers 0x1F through 0x28. UNLOCK DIR Unlock Error Status UNLOCK DIR Lock Status No error; the DIR AES3 decoder and PLL2 are locked. DIR lock error; the AES3 decoder and PLL2 are unlocked. QCRC Q-Channel Sub-Code CRC Status QCRC Q-Channel CRC Status No error Q-channel sub-code data CRC error detected. RBTI Receiver Buffer Transfer Interrupt Status RBTI DIR RA Buffer-to-UA Buffer Transfer Status Buffer transfer incomplete, or no Buffer transfer interrupt indicated Submit Documentation Feedback

www.ti.com Y X Y X L R L R L R L R R L R L AES3□Bit□Stream DIR□SYNC LRCK,□I S□Format□(input) LRCK,□Left-□or□Right- Justified□Formats□(input) /c1775% /c1775% Data□Slip□or□Repeat□may□occur□when□the□LRCK□edges□indicated□are□within□the 5%□window./c177 DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Buffer transfer completed Register 15: Receiver Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) OSLIP Note: Status bits must be unmasked in control register 0x17 in order for the status interrupts to be generated. OSLIP Receiver Output Data Slip Error Status OSLIP Receiver OSLIP Error Status No error DIR output data Slip/Repeat error detected An OSLIP interrupt is possible when the DIR output is used as the source for either the Port A or Port B audio serial port and the port is configured to operate in slave mode. Figure shows the timing associated with the OSLIP interrupt. When only one audio serial port (Port A or Port is sourced by the DIR output, then the OSLIP status bit and interrupt applies to that port. If both Port A and Port B are sourced by the DIR output, then the OSLIP status bit and interrupt applies to Port A only. Figure 35. DIR Output Slip/Repeat (OSLIP) Behavior Register 16: Receiver Interrupt Mask Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) MCSCRC MPARITY MVBIT MBPERR MQCHG MUNLOCK MQCRC MRBTI MCSCRC Channel Status CRC Error Interrupt Mask MCSCRC CRC Interrupt Masked (default) Enabled MPARITY Parity Error Interrupt Mask MPARITY Parity Error Interrupt Masked (default) Enabled MVBIT Validity Error Interrupt Mask MVBIT Validity Error Interrupt Masked (default) Enabled Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 MBPERR Biphase Encoding Error Interrupt Mask MBPERR Biphase Error Interrupt Masked (default) Enabled MQCHG Q-Channel Sub-Code Data Change Interrupt Mask MQCHG Q-Channel Data Change Interrupt Masked (default) Enabled MUNLOCK DIR Unlock Error Interrupt Mask MUNLOCK DIR Unlock Interrupt Masked (default) Enabled MQCRC Q-Channel Sub-Code CRC Error Interrupt Mask MQCRC Q-Channel CRC Error Interrupt Masked (default) Enabled MRBTI Receiver Buffer Transfer Interrupt Mask MRBTI Receiver Buffer Transfer Interrupt Masked (default) Enabled Register 17: Receiver Interrupt Mask Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) MOSLIP MOSLIP Receiver Output Data Slip Error Mask MOSLIP Receiver OSLIP Error Interrupt Masked (default) Enabled Register 18: Receiver Interrupt Mode Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) QCHGM1 QCHGM0 UNLOCKM1 UNLOCKM0 QCRCM1 QCRCM0 RBTIM1 RBTIM0 QCHGM[1:0] Q-Channel Sub-Code Data Change Interrupt Mode QCHGM1 QCHGM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved UNLOCKM[1:0] DIR Unlock Error Interrupt Mode UNLOCKM1 UNLOCKM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved QCRCM[1:0] Q-Channel Sub-Code CRC Error Interrupt Mode QCRCM1 QCRCM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 RBTIM[1:0] Receive Buffer Transfer Interrupt Mode RBTIM1 RBTIM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved Register 19: Receiver Interrupt Mode Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) CSCRCM1 CSCRCM0 PARITYM1 PARITYM0 VBITM1 VBITM0 BPERRM1 BPERRM0 CSCRCM[1:0] Channel Status CRC Error Interrupt Mode CSCRCM1 CSCRCM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved PARITYM[1:0] Parity Error Interrupt Mode PARITYM1 PARITYM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved VBITM[1:0] Validity Error Interrupt Mode VBITM1 VBITM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved BPERRM[1:0] Biphase Encoding Error Interrupt Mode BPERRM1 BPERRM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved Register 1A: Receiver Interrupt Mode Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) OSLIPM1 OSLIPM0 OSLIPM[1:0] Receiver Output Data Slip Error Interrupt Mode OSLIPM1 OSLIPM0 Interrupt Active State Rising edge active (default) Falling edge active Level active Reserved Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 1B: General-Purpose Output (GPO1) Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) GPO13 GPO12 GPO11 GPO10 GPO[13:10] General-Purpose Output (GPO1) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO1. GPO13 GPO12 GPO11 GPO10 GPO1 Function GPO1 is forced low (default) GPO1 is forced high Reserved Transmitter interrupt, active low Receiver interrupt, active low Receiver µ s pre-emphasis, active low Receiver non-audio data, active high Receiver non-valid data, active high Receiver channel status bit Receiver user data bit Receiver block start clock Receiver COPY bit copyright asserted, copyright not asserted) Receiver L-bit first generation or higher, original) Receiver parity error, active high Receiver internal sync clock Transmitter internal sync clock Register 1C: General-Purpose Output (GPO2) Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) GPO23 GPO22 GPO21 GPO20 GPO[23:20] General-Purpose Output (GPO2) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO2. GPO23 GPO22 GPO21 GPO20 GPO2 Function GPO2 is forced low (default) GPO2 is forced high Reserved Transmitter interrupt, active low Receiver interrupt, active low Receiver µ s pre-emphasis, active low Receiver non-audio data, active high Receiver non-valid data, active high Receiver channel status bit Receiver user data bit Receiver block start clock Receiver COPY bit copyright asserted, copyright not asserted) Receiver L-bit first generation or higher, original) Receiver parity error, active high Receiver internal sync clock Transmitter internal sync clock Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 1D: General-Purpose Output (GPO3) Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) GPO33 GPO32 GPO31 GPO30 GPO[33:30] General-Purpose Output (GPO3) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO3. GPO33 GPO32 GPO31 GPO30 GPO3 Function GPO3 is forced low (default) GPO3 is forced high Reserved Transmitter interrupt, active low Receiver interrupt, active low Receiver µ s pre-emphasis, active low Receiver non-audio data, active high Receiver non-valid data, active high Receiver channel status bit Receiver user data bit Receiver block start clock Receiver COPY bit copyright asserted, copyright not asserted) Receiver L-bit first generation or higher, original) Receiver parity error, active high Receiver internal sync clock Transmitter internal sync clock Register 1E: General-Purpose Output (GPO4) Control Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) GPO43 GPO42 GPO41 GPO40 GPO[43:40] General-Purpose Output (GPO4) Configuration These bits are used to set the state or data source for the general-purpose digital output pin GPO4. GPO43 GPO42 GPO41 GPO40 GPO4 Function GPO4 is forced low (default) GPO4 is forced high Reserved Transmitter interrupt, active low Receiver interrupt, active low Receiver µ s pre-emphasis, active low Receiver non-audio data, active high Receiver non-valid data, active high Receiver channel status bit Receiver user data bit Receiver block start clock Receiver COPY bit copyright asserted, copyright not asserted) Receiver L-bit first generation or higher, original) Receiver parity error, active high Receiver internal sync clock Transmitter internal sync clock Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Registers through 28: Q-Channel Sub-Code Data Registers Registers 0x1F through 0x28 comprise the Q-channel sub-code buffer, which may be accessed for audio CD playback. The Q-channel data provides information regarding the playback status for the current disc. The buffer data is decoded by the DIR block. Register 1F: Q-Channel Sub-Code Data Register (Read-Only), Bits[7:0], Control and Address Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Register 20: Q-Channel Sub-Code Data Register (Read-Only), Bits[15:8], Track Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q10 Q11 Q12 Q13 Q14 Q15 Register 21: Q-Channel Sub-Code Data Register (Read-Only), Bits[23:16], Index Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Register 22: Q-Channel Sub-Code Data Register (Read-Only), Bits[31:24], Minutes Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Register 23: Q-Channel Sub-Code Data Register (Read-Only), Bits[39:32], Seconds Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q32 Q33 Q34 Q35 Q36 Q37 Q38 Q39 Register 24: Q-Channel Sub-Code Data Register (Read-Only), Bits[47:40], Frame Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q40 Q41 Q42 Q43 Q44 Q45 Q46 Q47 Register 25: Q-Channel Sub-Code Data Register (Read-Only), Bits[55:48], Zero Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q48 Q49 Q50 Q51 Q52 Q53 Q54 Q55 Register 26: Q-Channel Sub-Code Data Register (Read-Only), Bits[63:56], AMIN Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q56 Q57 Q58 Q59 Q60 Q61 Q62 Q63 Register 27: Q-Channel Sub-Code Data Register (Read-Only), Bits[71:64], ASEC Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q64 Q65 Q66 Q67 Q68 Q69 Q70 Q71 Register 28: Q-Channel Sub-Code Data Register (Read-Only), Bits[79:72], AFRAME Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) Q72 Q73 Q74 Q75 Q76 Q77 Q78 Q79 Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Registers through 2C: IEC61937 PC/PD Burst Preamble The PC and PD burst preambles are part of the IEC61937 standard for transmission of data reduced, non-PCM audio over a standard two-channel interface (IEC60958). Examples of data-reduced formats include Dolby AC-3, DTS, various flavors of MPEG audio (including AAC), and Sony ATRAC. The PA and PB preambles provide synchronization data, and are fixed values of 0xF872 and 0x4E1F, respectively. The PC preamble indicates the type of data being carried by the interface and the PD preamble indicates the length of the burst, given as number of bits. Registers 0x29 through 0x2C contain the PC and PD preambles as decoded by the DIR block. Register 29: Burst Preamble PC High-Byte Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) PC15 PC14 PC13 PC12 PC11 PC10 PC09 PC08 Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) PC07 PC06 PC05 PC04 PC03 PC02 PC01 PC00 PC[4:0], Hex Data Type Null Dolby AC-3 Reserved Pause MPEG-1 layer MPEG-1 layer or or MPEG-2 without extension MPEG-2 Data with extension MPEG-2 AAC ADTS MPEG-2 layer low sample rate MPEG-2 layer or low sample rate Reserved DTS type DTS type DTS type ATRAC ATRAC2/3 10-1F Reserved Bits PC[6:5] are both set to Bit PC[7] is an Error Flag, where: A valid burst-payload; Burst-payload may contain errors. Bits PC[12:8] are data-type dependent. Bits PC[15:13] indicate the stream number, which is set to Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) PD15 PD14 PD13 PD12 PD11 PD10 PD09 PD08 Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only) Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) PD07 PD06 PD05 PD04 PD03 PD02 PD01 PD00 Submit Documentation Feedback

www.ti.com CHANNEL STATUS AND USER DATA BUFFER MAPS DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Register 7F: Page Selection Register Bit (MSB) Bit Bit Bit Bit Bit Bit Bit (LSB) PAGE1 PAGE0 PAGE[1:0] Page Selection These bits are utilized to select one of three register pages for write and/or read access via the SPI or I C serial host interface. The Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary. PAGE1 PAGE0 Register/Buffer Page Selection Page control and status registers (default) Page DIR channel status and user data buffers Page DIT channel status and user data buffers Page reserved Table through Table show the buffer maps for the DIR and DIT channel status and user data buffers. For Table the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit of Byte defines the transmission mode, for Consumer mode, and for Professional mode. This is applicable for Table and Table For Table the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit of Byte defines the transmission mode, for Consumer mode, and for Professional mode. In Professional mode, Byte for each channel is reserved for CRC data, which is automatically calculated and encoded by the DIT. There is no need to program Byte for either channel in Professional mode. Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 CHANNEL STATUS AND USER DATA BUFFER MAPS (continued) Table DIR Channel Status Data Buffer Map (Register Page ADDRESS BIT (Hex) CHANNEL BYTE (MSB) BIT BIT BIT BIT BIT BIT BIT A B C D E F Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Table DIR User Data Buffer Map (Register Page ADDRESS BIT (Hex) CHANNEL BYTE (MSB) BIT BIT BIT BIT BIT BIT BIT Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Table DIT Channel Status Data Buffer Map (Register Page ADDRESS BIT (Hex) CHANNEL BYTE (MSB) BIT BIT BIT BIT BIT BIT BIT A B C D E F Submit Documentation Feedback

www.ti.com DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Table DIT User Data Buffer Map (Register Page ADDRESS BIT (Hex) CHANNEL BYTE (MSB) BIT BIT BIT BIT BIT BIT BIT Submit Documentation Feedback

www.ti.com REFERENCE DOCUMENTS DIX4192 SBFS031C JANUARY 2006 REVISED JUNE 2006 Throughout this data sheet, various standards and documents are repeatedly cited as references. Sources for these documents are listed here so that the reader may obtain the documents for further study. Audio Engineering Society (AES) standards documents, including the AES3, AES11, AES18, and related specifications are available from the AES web site: http://www.aes.org International Electrotechnical Committee (IEC) standards, including the IEC60958 and IEC61937 are available from the IEC web site: http://www.iec.ch or the ANSI web site: http://www.ansi.org The EIAJ CP-1212 (formerly CP-1201) standard is available from the Japanese Electronics and Information Technologies Industries Association (JEITA): http://www.jeita.or.jp/english The Philips I C bus specification is available from Philips: http://www.philips.com The version utilized as a reference for this product is Version 2.1, published in January 2000. Several papers regarding balanced and unbalanced transformer-coupled digital audio interfaces have been published and presented at past AES conventions by Jon Paul of Scientific Conversion, Inc. These papers are available for download from: http://www.scientificonversion.com Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DIX4192IPFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DIX4192IPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DIX4192IPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DIX4192IPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 10-Jul-2006 Addendum-Page 1

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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