DIR9001-Q1

DIR9001-Q1 BURR-BROWN | Alldatasheet

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/C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115

FEATURES

APPLICATIONS

DESCRIPTION

96-kHz, 24-Bit Digital Audio Interface Receiver Car Audio Head Units One-Chip Digital Audio Interface Receiver (DIR) Including Low-Jitter Clock-Recovery Car Audio External Amplifiers System Compliant With Digital Audio Interface Standards: IEC60958 (former IEC958), JEITA The DIR9001-Q1 is a digital audio interface receiver CPR-1205 (former EIAJ CP-1201, CP-340), that can receive a 28-kHz to 108-kHz sampling- AES3, EBU tech3250 frequency, 24-bit-data-word, biphase-encoded signal. The DIR9001-Q1 complies with IEC60958-3, JEITA Clock Recovery and Data Decode From CPR-1205 (Revised version of EIAJ CP-1201), AES3, Biphase Input Signal, Generally Called S/PDIF, EBUtech3250, and it can be used in various EIAJ CP-1201, IEC60958, AES/EBU a digital audio interface. Biphase Input Signal Sampling Frequency S The DIR9001-Q1 supports many output system clock Range: kHz to 108 kHz and output data formats and can be used flexibly in Low-Jitter Recovered System Clock: ps many application systems. As the all functions which Jitter Tolerance Compliant With IEC60958-3 the DIR9001-Q1 provides can be controlled directly through control pins, it can be used easily in an Selectable Recovered System Clock: 128 f S application system that does not have a 256 f S 384 f S 512 f S microcontroller. Also, as dedicated pins are provided Serial Audio Data Output Formats: 24-Bit I for the channel-status bit and user-data bit, MSB-First, 24-Bit Left-Justified; MSB-First 16-, processing of their information can be easily 24-Bit Right-Justified accomplished by connecting with a microcontroller, DSP, etc. User Data, Channel-Status Data Outputs Synchronized With Decoded Serial Audio Data The DIR9001-Q1 does not require an external clock No External Clock Required for Decode source or resonator for decode operation if the internal actual-sampling-frequency calculator is not Includes Actual Sampling Frequency used. Therefore, it is possible to reduce the cost of a Calculator (Needs External 24.576-MHz Clock) system. Function Control: Parallel (Hardware) The operating temperature range of the DIR9001-Q1 Functions Similar and Pin Assignments is specified as C to which makes it Equivalent to Those of DIR1703 suitable for automotive applications. Single Power Supply: 3.3 V (2.7 V to 3.6 Wide Operating Temperature Range: C to C V-Tolerant Digital Inputs Package: 28-pin TSSOP, Pin Pitch: 0,65 mm Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. SpAct is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2007 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V CC Supply voltage 0.3 to V V DD V CC to V DD Supply voltage differences 0.1 V AGND to DGND Ground voltage differences 0.1 V Digital input 0.3 to 6.5 Digital input voltage V Digital output 0.3 to DD 0.3) XTI, XTO 0.3 to CC 0.3) Analog input voltage V FILT 0.3 to CC 0.3) Input current (any pins except supplies) mA Ambient temperature under bias to 125 C Storage temperature to 150 C Junction temperature 150 C Lead temperature (soldering) 260 s Package temperature (reflow, peak) 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V CC Analog supply voltage 2.7 3.3 3.6 VDC V DD Digital supply voltage 2.7 3.3 3.6 VDC XTI is connected to clock source 24.576 MHz Digital input clock frequency XTI is connected to DGND Not required MHz Digital output load capacitance, except SCKO pF Digital output load capacitance (SCKO) pF T A Operating free-air temperature C Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com ELECTRICAL CHARACTERISTICS DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 All specifications at T A V DD V CC 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT CHARACTERISTICS V IH 0.7 V DD V DD Input logic level (1) VDC V IL 0.3 V DD V IH 5.5 Input logic level (2) VDC V IL 0.8 V OH I O mA 0.85 V DD Output logic level (3) VDC V OL I O mA 0.15 V DD I IH V IN V DD 100 Input leakage current (4) µ A I IL V IN V I IH V IN V DD Input leakage current (5) µ A I IL V IN V 100 I IH V IN V DD Input leakage current (6) µ A I IL V IN V BIPHASE SIGNAL INPUT AND PLL Input sampling frequency range 108 kHz Jitter tolerance (IEC60958-3) IEC60958-3 (2003-01) Compliant From biphase signal detection to error-out PLL lock-up time 100 ms release (ERROR RECOVERED CLOCK AND DATA Serial audio data width Bit 128 f S 3.584 13.824 256 f S 7.168 27.648 SCKO frequency MHz 384 f S 10.752 41.472 512 f S 14.336 55.296 BCKO frequency f S 1.792 6.912 MHz LRCKO frequency f S 108 kHz f S kHz, SCKO 256 f S measured SCKO jitter 100 ps rms periodic SCKO duty cycle 45% 55% XTI SOURCE CLOCK XTI is connected to clock source 24.576 XTI source clock frequency MHz XTI is connected to DGND Not required Frequency accuracy XTI is connected to clock source 100 100 ppm XTI input-clock duty cycle XTI is connected to clock source 45% 55% POWER SUPPLY AND SUPPLY CURRENT V CC 2.7 3.3 3.6 Operation voltage range VDC V DD 2.7 3.3 3.6 f S kHz, PLL locked, XTI connected 8.3 mA to DGND I CC Supply current (7) f S kHz, PLL locked, XTI connected 8.3 mA to 24.576-MHz resonator RXIN H or XTI RST L 130 µ A (1) CMOS compatible input: XTI (not 5-V tolerant) (2) 5-V tolerant TTL inputs: RXIN, FMT0, FMT1, PSCK0, PSCK1, CKSEL, RST RSV (3) CMOS outputs: XTO, SCKO, BCKO, LRCKO, DOUT, UOUT, COUT, BFRAME, ERROR, CLKST, AUDIO EMPH, FSOUT0, FSOUT1 (4) Internal pulldowns: FMT0, FMT1, PSCK0, PSCK1, CKSEL, RSV (5) Internal pullup: RST (6) No internal pullup and pulldown: RXIN, XTI (7) No load connected to SCKO, BCKO, LRCKO, DOUT, COUT, VOUT, BFRAME, FSOUT0, FSOUT1, CLKST, ERROR, EMPH, AUDIO Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com PIN ASSIGNMENTS

1 AUDIO

(TOP VIEW) P0043-04 DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V DD V CC 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f S kHz, PLL locked, XTI connected 8.3 mA to DGND I DD Supply current (7) f S kHz, PLL locked, XTI connected 12.4 mA to 24.576-MHz resonator RXIN H or XTI RST L µ A f S kHz, PLL locked, XTI connected mW to DGND P D Power dissipation (7) f S kHz, PLL locked, XTI connected mW to 24.576-MHz resonator RXIN H or XTI RST L 0.67 mW TEMPERATURE RANGE T A Operation temperature range C θ JA Thermal resistance 28-pin T-SSOP 105 C/W Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 TERMINAL FUNCTIONS TERMINAL PULL I/O REMARKS NO. AGND Analog ground AUDIO OUT CMOS Channel-status data information of non-audio sample word, active-low BCKO OUT CMOS Audio data bit clock output BFRAME OUT CMOS Indication of top block of biphase input signal CKSEL IN Pulldown 5-V tolerant TTL Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock (1) CLKST OUT CMOS Clock change/transition signal output COUT OUT CMOS Channel-status data serial output synchronized with LRCKO DGND Digital ground DOUT OUT CMOS 16-bit/24-bit decoded serial digital audio data output EMPH OUT CMOS Channel-status data information of pre-emphasis (50 µ s/15 µ ERROR OUT CMOS Indication of internal PLL or data parity error FILT External filter connection terminal; must connect recommended filter. FMT0 IN Pulldown 5-V tolerant TTL Decoded serial digital audio data output format selection (1) FMT1 IN Pulldown 5-V tolerant TTL Decoded serial digital audio data output format selection (1) FSOUT0 OUT CMOS Actual sampling frequency calculated result output FSOUT1 OUT CMOS Actual sampling frequency calculated result output LRCKO OUT CMOS Audio data latch enable output PSCK0 IN Pulldown 5-V tolerant TTL PLL source SCKO output frequency selection (1) PSCK1 IN Pulldown 5-V tolerant TTL PLL source SCKO output frequency selection (1) RST IN Pullup 5-V tolerant TTL Reset control input, active-low (2) RSV IN Pulldown Reserved, must be connected to DGND (1) RXIN IN 5-V tolerant TTL Biphase digital data input (3) SCKO OUT CMOS System clock output UOUT OUT CMOS User data serial output synchronized with LRCKO V CC Analog power supply, 3.3-V V DD Digital power supply, 3.3-V CMOS XTI IN Oscillation amplifier input, or external XTI source clock input Schmitt-trigger XTO OUT CMOS Oscillation amplifier output (1) TTL Schmitt-trigger input with internal pulldown (51 k Ω typical), 5-V tolerant (2) TTL Schmitt-trigger input with internal pullup (51 k Ω typical), 5-V tolerant (3) TTL Schmitt-trigger input, 5-V tolerant. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com BLOCK DIAGRAM Clock and Data Recovery SCKO BCKO LRCKO DOUT RXIN Divider FIL T XTOXTI FSOUT0 FSOUT1 RST OSC RESET CLKST EMPH UOUT COUT BFRAME VCO CKSEL DGND ERROR AUDIOPower Supply VDD DGND AGNDVCC PSCK0 PSCK1 FMT0 RSV PLL Divider Decoder FMT1 Preamble Detector Charge Pump Sampling Frequency Calculator Clock Decoder Biphase Data Decoder Serial Audio□Data Formatter ERROR Detector Function Control Audio□Data MUTE Control Channel Status and User□Data Output DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS POWER SUPPLY CURRENT fS − Sampling Frequency − kHz 30 40 50 60 70 80 90 100 ICC + IDD − Supply Current − mA G001 –40°C 25°C –25°C 0°C 50°C 85°C VCC = VDD = 3.3 V SCKO = 256 fS fS − Sampling Frequency − kHz 30 40 50 60 70 80 90 100 ICC + IDD − Supply Current − mA G002 3 V 3.6 V 3.3 V 2.7 V TA = 25/C0053C SCKO = 256 fS RECOVERED SYSTEM CLOCK (SCKO) JITTER fS − Sampling Frequency − kHz 100 120 140 160 180 200 30 40 50 60 70 80 90 100 Periodic Jitter − ps rms G003 128 fS 384 fS 256 fS 512 fS VCC = VDD = 3.3 V TA = 25/C0053C DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 Oscillation amplifier operating with crystal; 1-kHz, 0-dB, sine-wave data; no load SUPPLY CURRENT SUPPLY CURRENT vs vs LOCKED SAMPLING FREQUENCY LOCKED SAMPLING FREQUENCY Figure Figure SCKO JITTER vs LOCKED SAMPLING FREQUENCY Figure Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com DEVICE INFORMATION ACCEPTABLE BIPHASE INPUT SIGNAL AND BIPHASE INPUT PIN (RXIN) DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 can decode the biphase signal format which is specified in one of the following standards. Generally, these following standards may be called Sony/Philips digital interface format (S/PDIF) or AES/EBU. IEC60958 (revised edition of former IEC958) JEITA CPR-1205 (revised edition of former EIAJ CP-1201, CP-340) AES3 EBU tech3250 The sampling frequency range and data word length which DIR9001-Q1 can decode is as follows: Sampling frequency range is kHz to 108 kHz. Maximum audio sample word length is 24-bit. Note of others about the biphase input signal. The capture ratio of the built-in PLL complies with level III of sampling frequency accuracy (12.5%), which is specified in IEC60958-3. The jitter tolerance of the DIR9001-Q1 complies with IEC60958-3. The PLL may also lock in outside of the specified sampling-frequency range, but extended range is not assured. Notice about the signal level and transmission line of the biphase input signal. The signal level and the transmission line (optical, differential, single-ended) are different in each standard. The biphase input signal is connected to the RXIN pin of the DIR9001-Q1. The RXIN pin has a 5-V tolerant TTL-level input. An optical receiver module (optical to electric converter) such as TOSLINK, which is generally used in consumer applications, is connected directly to the RXIN pin without added external components. The output waveform of the optical receiver module varies depending on the characteristics of each product type, so a dumping resistor or buffer amplifier might be required between the optical receiver module output and the DIR9001-Q1 input. Careful handling is required if the optical receiver module and the DIR9001-Q1 are separated by a long distance. The DIR9001-Q1 needs an external amplifier if it is connected to a coaxial transmission line. The DIR9001-Q1 needs an external differential to single-ended converter, attenuator, etc., for general consumer used. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com SYSTEM RESET VDD 2.7 V Min. 100 ns Reset RST OperationUnknownDIR9001-Q1 Status T0260-01 DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 reset function is controlled by and external reset pin, RST The reset operation must be performed during the power-up sequence as shown in Figure Specifically, the DIR9001-Q1 requires reset operation with a 100-ns period after the supply voltage rises above 2.7 Figure Required System Reset Timing The state of each output pins during reset is shown in Table Table Output-Pin States During Reset Period CLASSIFICATION PIN NAME WHILE RST L BCKO L Clock LRCKO L SCKO L Data DOUT L AUDIO L BFRAME L CLKST L COUT L Flag and status EMPH L ERROR H FSOUT0 L FSOUT1 L UOUT L Oscillation amplifier XTO Output Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com OPERATION MODE AND CLOCK TRANSITION SIGNAL OUT Operation Mode DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 has the following three operation modes. These modes are selected by the connection of the CKSEL pin. PLL MODE: For demodulating a biphase input signal; always outputs PLL source clock XTI MODE: For clock generator; always outputs XTI source clock AUTO MODE: Automatic clock source selection; output source depends on ERROR pin. Notes about operation mode selection: Normally, the PLL mode: CKSEL L is selected to decode a biphase input signal. The XTI mode is a mode that supplies the XTI source clock to peripheral devices (A/D converters, etc); therefore, recovered clock and decoded data is not output. When the XTI source is not used, an XTI source is not required. In this case, clocks are not output in the XTI mode. At the time of XTI mode selection, biphase decode function continues to operate. Therefore, the biphase input status (ERROR) and the result of the sampling frequency calculator required XTI source for operation), are always monitored. That is, the following output pins: ERROR, BFRAME, FSOUT[1:0], CLKST, AUDIO and EMPH are always enabled. The details of these three modes are given in Table Table Operation Mode and Clock Source OPERATION CKSEL PIN ERROR DOUT DATA AUDIO FSOUT BFRAME COUT SCKO, BCKO, LRCKO MODE SETTING PIN EMPH [1:0] UOUT CLOCK SOURCE STATUS H PLL (VCO) free-running MUTE (Low) LOW HL LOW LOW clock (1) PLL L L PLL recovered clock Decoded data OUT OUT OUT OUT H XTI clock MUTE (Low) LOW HL LOW LOW XTI H L XTI clock MUTE (Low) OUT OUT OUT LOW H XTI clock MUTE (Low) LOW HL LOW LOW Connected to AUTO ERROR pin L PLL recovered clock Decoded data OUT OUT OUT OUT (1) The VCO free-running frequency is not a constant frequency, because the VCO oscillation frequency is dependent on supply voltage, temperature, and process variations. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com Clock and Data Recovery SCKO BCKO LRCKO DOUT RXIN Divider FIL T XTOXTI FSOUT0 FSOUT1 OSC CLKST VCO CKSEL DGND ERROR PLL Divider Decoder Preamble Detector Charge Pump Clock Decoder Biphase Data Decoder Serial Audio□Data Formatter ERROR Detector Audio□Data MUTE Control Sampling Frequency Calculator Clock Transition Signal Out DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 Figure Clock Source, Source Selector, and Data Path The DIR9001-Q1 provides an output pulse that is synchronized with the PLL s LOCK/UNLOCK status change. The CLKST pin outputs the PLL status change between LOCK and UNLOCK. The CLKST output pulse depends only on the status change of the PLL. This clock change/transition signal is output through CLKST. As this signal indicates a clock transition period due to a PLL status change, it can be used for muting or other appropriate functions in an application. A clock source selection caused by the CLKSEL pin does not affect the output of CLKST. CLKST does change due to PLL status change even if CKSEL H in the XTI source mode. When DIR9001-Q1 is reset in the state where it is locked to the biphase input signal, the pulse signal of CLKST is not output. That is, the priority of reset is higher than CLKST. The relation among the lock-in/unlock process, the CLKST and ERROR outputs, the output clocks (SCKO, BCKO, LRCKO), and data (DOUT) is shown in Figure Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com AUTO□Mode□[CKSEL =□ERROR] XTI□Mode□[CKSEL =□High] PLL Mode□[CKSEL =□Low] DIR9001-Q1□Status Note: means clock source change. RXIN Non-Biphase Biphase Non-Biphase Unlock Unlock CLKST tCLKST ERROR Lock Up Time XTO MUTE (Low)Demodulated DataDOUT XTI SourceXTO XTI Source DOUT Always MUTE (Low) XTI SourceXTO XTI Source PLL Source XTI Source DOUT MUTE (Low) Lock Demodulated Data Built-In□PLL Status SCKO,□BCKO, LRCKO SCKO,□BCKO, LRCKO MUTE□(Low) MUTE□(Low) SCKO,□BCKO, LRCKO XTI□Source PLL Source (Transition) PLL Source (Lock□Frequency) PLL Source (Transition) PLL Source (Free-Run) tCLKST PLL Source (Free-Run) T0261-01 DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 PARAMETERS MIN TYP MAX UNIT t CLKST CLKST pulse duration, high µ s Figure Lock-In and Unlock Process Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com CLOCK clock. PLL source (128 f S 256 f S 384 f S 512 f S are available, recovered by built-in PLL) XTI source (One 24.576-MHz resonator or external clock source is required.) Two clock sources are used for the following purpose. PLL source: Recovered system clock from the biphase input signal XTI source: Clock source for peripheral devices (for example, A/D converter, microcontroller, etc.) Measurement reference clock for the internal actual-sampling-frequency calculator (including VCO). The PLL clock source frequency is selectable from 128 f S 256 f S 384 f S 512 f S by PSCK[1:0]. When the PLL is in the locked condition, the PLL clock source is the clock recovered from the biphase input signal. When PLL is in the unlocked condition, the PLL clock source is the built-in free-running clock of the VCO. The frequency of the PLL clock source in the unlocked condition is not constant. (The VCO free-running frequency is dependent on supply voltage, temperature, and variations in the die s wafer.) signal. Therefore, if the DIR9001-Q1 is used only for recovering the clock and decoding data from the biphase input signal, an XTI clock source is not required. In this case, the XTI pin must be connected to the DGND pin. (The DIR9001-Q1 does not have a selection pin for using an XTI clock source or not using one.) The selection method of clock source The output clock is selected from two clock sources by the level of the CKSEL pin. The selection of the system clock source depends only on the input level of CKSEL pin. CKSEL L setting is required for recovering the clock and decoding data from biphase input. CKSEL H setting is required for XTI clock source output. The continuity of clock during the clock source transition between the XTI source and the PLL source is not assured. Method of automatic clock source selection (CLOCK SOURCE MODE: AUTO) This method enables selection of the clock source automatically, using the DIR9001-Q1 ERROR status. The PLL source clock is output when ERROR the XTI source is output when ERROR To enable automatic clock source selection, the CKSEL pin must be connected to the ERROR pin. If XTI clock source is needed during the ERROR period, this method is recommended. Because the clock source during ERROR status is XTI, if an XTI clock source is not provided to the XTI pin, then SCKO, BCKO, and LRCKO are not output during the ERROR period. The relationship between the clock/data source and the combination of CKSEL pin and PLL status inputs is shown in Table The clock tree system is shown in Figure Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com SCKO (O) BCKO (O) LRCKO (O) XTI (I) XTO (O) VCORXIN Built-in PLL Clock Recovery 1/N 1/NPLL Clock Source 1/N XTI Clock Source CKSEL (I) Oscillation Amplifier Clock□Source Selector [PSCK1] [PSCK0] PLL Clock Source (Built-In PLL and VCO) (including VCO) for recovering the clock from the biphase input signal. The clock that is output from the built-in VCO is defined as the PLL clock source. In the locked state, the built-in PLL generates a system clock that synchronizes with the biphase input signal. In the unlocked state, the built-in PLL (VCO) generates a free-running clock. (The frequency is not constant.) The PLL can support a system clock of 128 f S 256 f S 384 f S or 512 f S where f S is the sampling frequency of the biphase input signal. The system clock frequency of the PLL is selected by PSCK[1:0]. The DIR9001-Q1 can decode a biphase input signal through its sampling-frequency range of kHz to 108 kHz, independent of the setting of PSCK[1:0]. Therefore, the DIR9001-Q1 can decode a biphase input signal with a sampling frequency from kHz to 108 kHz at all settings of PSCK[1:0] The relationship between the PSCK[1:0] selection and the output clock (SCKO, BCKO, LRCKO) from the PLL source is shown in Table Table SCKO, BCKO, and LRCKO Frequencies Set by PSCK[1:0] PSCK[1:0] SETTING OUTPUT CLOCK FROM PLL SOURCE PSCK1 PSCK0 SCKO BCKO LRCKO L L 128 f S f S f S L H 256 f S f S f S H L 384 f S f S f S H H 512 f S f S f S Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com Required PLL Loop Filter (CKSEL L), output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock. The relationship between frequencies of LRCKO, BCKO, and SCKO at different sampling frequencies f S of the biphase input signal are shown in Table Table Output Clock Frequency in PLL Locked State (CKSEL LRCKO BCKO SCKO (Depending on PSCK[1:0] Setting) f S f S 128 f S 256 f S 384 f S 512 f S kHz 2.048 MHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz 44.1 kHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz kHz 3.072 MHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz 88.2 kHz 5.6448 MHz 11.2896 MHz 22.5792 MHz 33.8688 MHz 45.1584 MHz kHz 6.144 MHz 12.288 MHz 24.576 MHz 36.864 MHz 49.152 MHz The DIR9001-Q1 incorporates a PLL for generating a clock synchronized with the biphase input signal. The built-in PLL requires an external loop filter, which is specified as follows. Operation and performance is assured for recommended filter components R1, C1, and C2. Notes about Loop Filter Components and Layout The resistor and capacitors which comprise the filter should be located and routed as close as possible to the DIR9001-Q1. A carbon film resistor or metal film resistor, with tolerance less than 5%, is recommended. Film capacitors, with tolerance is less than 5%, is recommended. If ceramic capacitors are used for and C2, parts with a low voltage coefficient and low temperature coefficient, such as CH or C0G, are recommended. The external loop filter must be placed on FILT pins. The GND node of the external loop filter must be directly connected with the AGND pin of the DIR9001-Q1; it must be not combined with other signals. The configuration of external loop filter and the connection with the DIR9001-Q1 is shown in Figure Figure Loop Filter Connection The recommended values of loop filter components is shown in Table Table Recommended Value of Loop Filter Components REF. NO. RECOMMENDED VALUE PARTS TYPE TOLERANCE 680 Ω Metal film or carbon 0.068 µ F Film or ceramic (CH or C0G) 0.0047 µ F Film or ceramic (CH or C0G) Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com XTI Clock Source and Oscillation Amplifier 24.576-MHz Internal□Clock DIR9001-Q1 Resonator□Connection XTO CL1 CL2 Rd External Clock Must□Be Open XTI XTO Crystal OSC Circuit 24.576-MHz Internal□Clock DIR9001-Q1 External□Clock□Input□Connection B0241-01 DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 This clock, driven by the built-in oscillation amplifier or input into the XTI pin from an external clock, is defined as the XTI source. A 24.576-MHz fundamental resonator or external 24.576-MHz clock is used as the XTI source. The DIR9001-Q1 requires an XTI source for following purposes: The measurement reference clock of actual-sampling-frequency calculator The clock source for the XTI source mode (CKSEL H setting) (That is, the DIR9001-Q1 does not require an XTI source if it is only decoding the biphase input signal.) The XTI clock source is supplied in one of the following two ways; the details are described in Figure Setting up an oscillation circuit by connecting a resonator with the built-in amplifier Applying a clock from an external oscillator circuit or oscillator module To set up an oscillation circuit by connecting a resonator with the built-in amplifier: Connect a 24.576-MHz resonator between the XTI pin and XTO pin. The resonator should be a fundamental-mode type. A crystal resonator or ceramic resonator can be used. The load capacitor C C and the current-limiting resistor R d depend on the characteristics of the resonator. No external feedback resistor between the XTI pin and XTO pin is required, as an appropriate resistor is incorporated in the device. No load other than the resonator is allowed on the XTO pin. To connect an external oscillator circuit or oscillator module: Provide a 24.576-MHz clock on the XTI pin Note that the XTI pin is not 5-V tolerant; it is simple CMOS input. The XTO pin must be open. Figure XTI and XTO Connection Diagram operation: The built-in oscillation amplifier is always working. If the XTI source clock is not used, then the XTI pin must be connected to DGND. For reducing power dissipation, it is recommended to not use the XTI source clock. In XTI mode (CKSEL H), output clocks (SCKO, BCKO, LRCKO) are generated from XTI source clock. The relation between output clock frequency (SCKO, BCKO, LRCKO) and the XSCK pin setting in XTI source mode is shown in Table Table SCKO, BCKO, LRCKO Output Frequency at XTI Mode XTI FREQUENCY OUTPUT CLOCK FREQUENCY IN XTI SOURCE MODE (CKSEL SCKO BCKO LRCKO 24.576 MHz 24.576 MHz 6.144 MHz kHz Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com DATA Biphase□Signal□(IN) tLATE BFRAME□(OUT) LRCKO□(OUT) (I S) LRCKO□(OUT) (Except□I S) DOUT (OUT) B W M W0L 0R 1L 1R 0L 0R 1L 1R 17□BCK DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 supports following 4-data formats for the decoded data. 16-bit, MSB-first, right-justified 24-bit, MSB-first, right-justified 24-bit, MSB-first, left-justified 24-bit, MSB-first, I S Decoded data is MSB first and 2s-complement in all formats. The decoded data is provided through the DOUT pin. The format of the decoded data is selected by the FMT[1:0] pins. The data formats for each FMT[1:0] pin setting are shown in Table Table Serial Audio Data Output Format Set by FMT[1:0] FMT[1:0] SETTINGS DOUT SERIAL AUDIO DATA OUTPUT FORMAT FMT1 FMT0 L L 16-bit, MSB-first, right-justified L H 24-bit, MSB-first, right-justified H L 24-bit MSB-first, left-justified H H 24-bit, MSB-first, I S PARAMETERS MIN TYP MAX UNIT t LATE LRCKO/DOUT latency 3/f S s Figure 10. Latency Time Between Biphase Input and LRCKO/DOUT Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com Right Justified (MSB First, 24-bit, 16-bit) 22 23 24DOUT DOUT LRCKO BCKO 14 15 16 R-channelL-channel 1/fS MSB LSB 15 16 MSB LSB 23 24 MSB LSB 15 16 MSB LSB 23 24 Left Justified (MSB First) DOUT LRCKO BCKO R-channelL-channel 1/fS MSB LSB 23 24 MSB LSB 23 24 DOUT LRCKO BCKO R-channelL-channel 1/fS MSB LSB 21 23 24 MSB LSB 23 24 Data□Length:□16-bit Data□Length:□24-bit Data□Length:□24-bit Data□Length:□24-bit I S□Format□(MSB□First) DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The relationships among BCKO, LRCKO, and DOUT for each format are shown in Figure Figure 11. Decoded Serial Audio Data Output Formats Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com tBCH tBCL tBCDOtBCY BCKO (OUT) LRCKO (OUT) DOUT (OUT) SCKO (OUT) V /2DD tCKLR tSCBC tSCY V /2DD V /2DD V /2DD DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 PARAMETERS MIN TYP MAX UNIT t SCY System clock pulse cycle time ns t SCBC Delay time of SCK rising edge to BCK rising edge ns t CKLR Delay time of BCKO falling edge to LRCKO valid 0.5 0.5 ns t BCY BCKO pulse cycle time 1/64f S s t BCH BCKO pulse duration, HIGH ns t BCL BCKO pulse duration, LOW ns t BCDO Delay time of BCKO falling edge to DOUT valid ns t r Rising time of all signals ns t f Falling time of all signals ns NOTE: Load capacitance of the LRCKO, BCKO, and DOUT pins is pF. DOUT, LRCKO, and BCKO are synchronized with SCKO. Figure 12. Decoded Audio Data Output Timing Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com Channel-Status Data and User Data Serial Outputs UOUT COUT BFRAME Recovered LRCKO (I S) Recovered LRCKO (Except□I S) U0L U0RU191R U1L U1R U2L U2R C0L C0RC191R C1L C1R C2L C2R DOUT 0L 0R191R 1L 1R 2L 2R 3L 17□BCK Channel-Status Data Information Output Terminal DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 can output channel-status data and user data synchronized with audio data from the biphase input signal. Each output data has its own dedicated output pin. Channel-status data (C, hereinafter) is output through COUT pin. User data (U, hereinafter) is output through UOUT pin. The C and U outputs are synchronized with LRCKO recovered from the biphase input signal. The polarity of LRCKO recovered from the biphase input signal depends on FMT[1:0] setting. For detecting the top of the block of channel-status data or user data, the BFRAME pin is provided. The BFRAME pin outputs a high level for an 8-LRCK period if the preamble B is detected in the received biphase signal. In processing these data by a microcontroller or register circuit, LRCKO is used as the data input clock, and the output pulse on the BFRAME pin is used as the top-of-block signal. The relationship among LRCKO, BFRAME, DOUT, COUT, and UOUT is shown in Figure When in the XTI mode and the PLL-locked state, COUT and UOUT output NOTE: The numbers through 191 of DOUT, COUT, and UOUT indicate frame numbers of the biphase input. Figure 13. LRCKO, DOUT, BFRAME, COUT, UOUT Output Timing The DIR9001-Q1 can output part of the channel-status information (bit bit through two dedicated pins, AUDIO and EMPH. The channel-status information which can be output from dedicated pins is limited to information from the L-channel. If channel-status information other than AUDIO or EMPH is required, or information from the R-channel, then the channel-status data on the COUT pin, which is synchronized with biphase input signal, can be used. These outputs are synchronized with the top of block. The information that can be output through the dedicated pins is shown as follows. Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com AUDIO Pin EMPH Pin LRCKO (Except□□I S) AUDIO LRCKO (I S) DOUT 0L Bit□1□of□Previous□Block 191R 1L 1R 2L 2R 3L EMPH Bit 3□of□Previous□Block DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 This is the output pin for the audio sample word information of the channel-status data bit Table Audio Sample Word Information AUDIO L Audio sample word represents linear PCM samples. H Audio sample word is used for other purposes. This is the output pin for the emphasis information of the channel-status data bit Table Pre-Emphasis Information EMPH L Two audio channels without pre-emphasis H Two audio channels with µ s µ s pre-emphasis NOTE: The numbers through 191 of DOUT indicate frame numbers of the biphase input. Figure 14. AUDIO and EMPH Output Timing Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com ERRORS AND ERROR PROCESSING Error Output Detected□Parity□Error Data□Error B0242-01 Parity Error Processing DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 Error detection and data error processing for PLL errors PLL responds with unlock for data in which the rule of biphase encoding is lost (biphase error and frame-length error). PLL responds with unlock for data in which the preamble W can not be detected. Error processing function and error output pins The DIR9001-Q1 has a data error detect function and an error output pin, ERROR. The ERROR pin is defined as the logical OR of data error and parity error detection. The ERROR rising edge is synchronized with CLKST. The ERROR falling edge is synchronized with LRCK. The relationship between data error and detected parity error is shown in Figure Figure 15. ERROR Output The state of the ERROR pin and the details of error are shown in Table Table 10. State of ERROR Output Pin ERROR L Lock state of PLL and nondetection of parity error H Unlock state of PLL or detection of parity error Error detection and error processing for parity errors For PCM data, interpolation processing by previous data is performed. For non-PCM data, interpolation is not performed and data is directly output with no processing. (Non-PCM data is data with channel-status data bit 1.) The processing for parity error occurrence is shown in Figure Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com AUDIO Internal□LOCK Ln LRCKO□(I MUTE□(Low) ERROR DOUT Parity□Error Interpolation□Processing by□Previous□Data AUDIO Internal□LOCK LRCKO□(I ERROR DOUT Parity□Error [ =□L]AUDIO [ =□H]AUDIO Rn Ln+1 Rn+1 Ln+1 Rn+2 Rn+3Ln+3 LnMUTE□(Low) Rn Ln+1 Rn+1 Ln+2 Rn+2 Rn+3Ln+3 Other Error DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 Figure 16. Processing for Parity Error Occurrence Error for sampling frequency change: A rapid continuous change or a discontinuous change of the input sampling frequency causes the PLL to lose lock. Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com CALCULATION OF ACTUAL SAMPLING FREQUENCY DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 calculates the actual sampling frequency of the biphase input signal and outputs its result through dedicated pins. To use this function, a 24.576-MHz clock source must be supplied to the XTI pin. The 24.576-MHz clock is used as a measurement reference clock to calculate the actual sampling frequency. If the XTI pin is connected to DGND, calculation of the actual sampling frequency is not performed. If there is an error in the XTI clock frequency, the calculation result and range are shifted correspondingly. This output is the result of calculating the sampling frequency, it is not the sampling frequency information of the channel-status data (bit bit 27). The sampling frequency information of the channel-status data (bit bit 27) is not output through these pins. The calculation result is decoded into 2-bit data, which is output on the FSOUT[1:0] pins. If the PLL is locked but the sampling frequency is out-of-range, or if the PLL is unlocked, FSOUT[1:0] HL is output to indicate an abnormality. When the XTI source clock is not supplied before power on, FSOUT [1:0] always outputs LL. When the XTI source clock is stopped, the f S calculator holds the last value of the f S calculator result. If XTI source clock is supplied, the f S calculator resumes operation. The calculated value is held until reset. The relationship between the FSOUT[1:0] outputs and the range of sampling frequencies is shown in Table Table 11. Calculated Sampling Frequency Output NOMINAL f S ACTUAL SAMPLING FREQUENCY CALCULATED SAMPLING FREQUENCY OUTPUT RANGE FSOUT1 FSOUT0 Out of range Out of range or PLL unlocked H L kHz 31.2 kHz 32.8 kHz H H 44.1 kHz kHz 45.2 kHz L L kHz 46.8 kHz 49.2 kHz L H Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com TYPICAL CIRCUIT CONNECTION AUDIO Receiver Circuit 3.3-V VDD + C7 + C8C6 For Automatic Clock Source Selection Reset (active LOW) COUT DOUT UOUT EMPH BFRAME RST RSV RXIN CKSEL FILT DGND PSCK1 PSCK0 FSOUT0 BCKO LRCKO CLKST SCKO FSOUT1 ERROR XTI XTO AGND FMT1 FMT0 25 To Microcontroller Actual Sampling Frequency Output System Clock Frequency□Setting 384, 512□f (128, 256, Audio Data Processor Decoded□Data Format Setting 3.3-V VCC C1C2 VDD VCC DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 Figure illustrates typical circuit connection. NOTES: R Loop filter resistor, 680 Ω R Current-limiting resistor; generally, a 100 Ω 500 Ω resistor is used, but it depends on the crystal resonator. C Loop filter capacitor, 0.068 µ C Loop filter capacitor, 0.0047 µ C C OSC load capacitor; generally, a 10-pF 30-pF capacitor is used, but it depends on the crystal resonator and PCB layout. C C 10- µ F electrolytic capacitor typical, depending on power-supply quality and PCB layout. C C 0.1- µ F ceramic capacitor typical, depending on power-supply quality and PCB layout. X Crystal resonator, use a 24.576-MHz fundamental resonator when XTI clock source is needed. Figure 17. Typical Circuit Connection Diagram Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

www.ti.com APPLICATION INFORMATION Differences From DIR1703 DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The DIR9001-Q1 has many improved functions compared to the DIR1703. The DIR9001-Q1 functions are similar to those of the DIR1703. The DIR9001-Q1 pin assignment is equivalent to that of the DIR1703. The DIR9001-Q1 biphase input signal decoding function is almost equivalent to that of the DIR1703. The differences between the DIR9001-Q1 and DIR1703 are shown in Table Table 12. Main Differences Between DIR1703 and DIR9001-Q1 DIFFERENCE DIR1703 DIR9001-Q1 Operational supply-voltage range V to 3.6 V 2.7 V to 3.6 V Operation temperature range C to C C to C Package SSOP-28P, pin pitch: 0.65 mm TSSOP-28P, pin pitch: 0.65 mm Clock recovery architecture SpAct feature Conventional PLL IEC60958-3 jitter tolerance Not compliant Compliant IEC60958 sampling frequency accuracy Level II 1000 ppm) Level III 12.5%) Acceptable sampling frequency 32/44.1/48/88.2/96 kHz, 1500 ppm kHz to 108 kHz continuous Biphase input signal level CMOS level 5-V tolerant TTL level Connection of loop filter Between FILT pin and VCC Between FILT pin and AGND XTI source clock frequency One of the following clock sources or Optional 24.576-MHz (24.576-MHz clock is resonators must be connected to the XTI pin: only required to use the internal actual-sampling-frequency calculator or use 22.5792/24.576-MHz the DIR9001-Q1 as a 24.576-MHz clock generator.) BFRAME H period 32/f S 8/f S Channel status and user data Synchronous with LRCK transition 17-BCK delay from LRCK transition Latest tracked frequency hold Available Not available PLL mode clock at error Latest tracked frequency VCO free-running frequency Clock transition signal out CKTRNS pin, active H CLKST pin, active-high Oscillation amplifier External feedback resistor (typ. M Ω Internal feedback resistor Submit Documentation Feedback Copyright 2007 2008, Texas Instruments Incorporated Product Folder Link(s) DIR9001-Q1

www.ti.com DIR9001-Q1 SLLS843A JUNE 2007 REVISED FEBRUARY 2008 The differences between the DIR1703 and DIR9001-Q1 I/O pins are shown in Table Table 13. The Differences Between DIR1703 and DIR9001-Q1 in All I/O Pin PIN NO. DIR1703 DIR9001- DIFFERENCES DESCRIPTIONS OF DIR9001-Q1 ADFLG AUDIO Pin name only Channel-status data information of non-audio sample word, active-low BRATE0 FSOUT0 Pin name only Actual-sampling-frequency calculated result output BRATE1 FSOUT1 Pin name only Actual-sampling-frequency calculated result output SCKO SCKO Same function System clock output V DD V DD Same function Digital power supply, 3.3-V DGND DGND Same function Digital ground XTO XTO Same function Oscillation amplifier output XTI XTI Same function Oscillation amplifier input, or external XTI source clock input CKTRNS CLKST CLKST is active-high Clock change/transition signal output LRCKO LRCKO Same function Audio data latch enable output BCKO BCKO Same function Audio data bit clock output DOUT DOUT Same function bit bit decoded serial digital audio data output SCF0 PSCK0 Pin name only SCKO output frequency selection SCF1 PSCK1 Pin name only SCKO output frequency selection CSBIT COUT Pin name only Channel-status data serial output synchronized with LRCKO URBIT UOUT Pin name only User data serial output synchronized with LRCKO EMFLG EMPH Pin name only Channel-status data Information of pre-emphasis (50 µ s/15 µ BFRAME BFRAME Same function Indication of top block of biphase input signal BRSEL RSV Reserved Reserved, must be connected to DGND DIN RXIN Pin name only Biphase digital data input RST RST Same function Reset control input, active-low FILT FILT Same function External filter connection terminal. Recommended filter must be connected. AGND AGND Same function Analog ground V CC V CC Same function Analog power supply, 3.3-V FMT0 FMT0 Same function Decoded serial digital audio data output format selection FMT1 FMT1 Same function Decoded serial digital audio data output format selection UNLOCK ERROR Pin name only Indication of internal PLL or data parity error CKSEL CKSEL Same function Selection of system clock source, Low: PLL (VCO) clock, High: XTI clock Copyright 2007 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) DIR9001-Q1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DIR9001IPWQ1 ACTIVE TSSOP PW 28 50 TBD Call TI Call TI DIR9001IPWRQ1 ACTIVE TSSOP PW 28 2000 TBD Call TI Call TI DIR9001IPWRQ1G4 ACTIVE TSSOP PW 28 2000 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 13-May-2008 Addendum-Page 1

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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