DIR1703

DIR1703 BURR-BROWN | Alldatasheet

Document overview

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Technical content

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007– JULY 2001 /C0068/C0073/C0071/C0073/C0084/C0065/C0076 /C0065/C0085/C0068/C0073/C0079 /C0073/C0078/C0084/C0069/C0082/C0070/C0065/C0067/C0069 /C0082/C0069/C0067/C0069/C0073/C0086/C0069/C0082 1www.ti.com

FEATURES

/C0068Standard Digital Audio Interface Receiver (EIAJ1201) /C0068Sampling Rate: 32 / 44.1 / 48 / 88.2 / 96 kHz /C0068Recover 128 / 256 / 384 / 512 fs System Clock /C0068Very Low Jitter System Clock Output (75 ps Typically) /C0068On-Chip Master Clock Oscillator, Only an External Crystal Is Required:

4.096 MHz Crystals Are Available

/C0068Selectable Output PCM Audio Data Format /C0068Selectable Crystal Clock and PPL Clock Operation Mode /C0068Output User Bit Data, Flag Signals, and Channel Status Data With Block Start Signal /C0068Single 3.3-V Power Supply /C0068Package: 28 SSOP

APPLICATIONS

/C0068AV Receiver /C0068MD Player /C0068DAC Unit

DESCRIPTION

The DIR1703 is a digital audio interface receiver (DIR) which receives and decodes audio data up to 96 kHz according to the AES/EBU, IEC958, S/PDIF, and EIAJCP340/1201 consumer and professional format interface standards. The DIR1703 demultiplexes the channel status bit and user bit directly to serial output pins, and has dedicated output pins for the most important channel status bits. It also includes extensive errors reporting. The significant advantages of the DIR1703 are 96-kHz sampling rate capability and Low-jitter clock recovery by the Sampling Period Adaptive Controlled Tracking (SpAct ) system. The input signal is reclocked with the patented Sampling period Adaptive controlled tracking system for maximum quality. These features are required for recent consumer and professional audio instruments, in which the DIR has an interface to any kind of delta-sigma type ADC/DAC with a 96-kHz sampling rate. This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright  2001, Texas Instruments Incorporated SpAct and Burr-Brown are trademarks of Texas Instruments.

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007 – JULY 2001 2 www.ti.com ADFLG BRATE0 BRATE1 SCKO V DD DGND XTO XTI CKTRNS LRCKO BCKO DOUT SCF0 SCF1 CKSEL UNLOCK FMT1 FMT0 V CC AGND FILT RST DIN BRSEL BFRAME EMFLG URBIT CSBIT DIR1703 (TOP VIEW) PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER OPERATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER /C0125 TRANSPORT MEDIA DIR1703E SSOP 28 324† 25°Ct o 8 5°C DIR1703E DIR1703E Rails DIR1703E SSOP –28 324† –25°C to +85°C DIR1703E DIR1703E/2K Tape and Reel † TI equivalent no. 4040065. ‡ Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of DIR1703E/2K will get a single 2000-piece tape and reel. block diagram OSC OSC SelectorPLL1 PLL2SpAct FIFO SCKO BRSEL CKSEL BCKO LRCKO DOUT BFRAME URBIT CSBIT ADFLG EMFLG SCF FMT DGND AGND XTI RST Audio Clock And Data Generator XTO DIN BRATE UNLOCK CKTRNS FILT

100 MHZ

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007 – JULY 2001 3www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONSNAME PIN I/O DESCRIPTIONS ADFLG 1 O Audio data or digital data flag BRATE0 2 O fs rate flag 0 (32 k, 44.1 k, 48 k, and 88 k / 96 k) BRATE1 3 O fs rate flag 1 (32 k, 44.1 k, 48 k, and 88 k / 96 k) SCKO 4 O System clock output VDD 5 – Digital power supply, +3.3 V DGND 6 – Digital ground XTO 7 O Crystal oscillator output XTI 8 I Crystal oscillator input, external clock input CKTRNS 9 O Clock transition status output LRCKO 10 O Audio latch enable (LRCK, fs) output BCKO 11 O Audio bit clock output DOUT 12 O Audio serial data output SCF0 13 I System clock frequency select (128/256/384/512 fs) (see Note 1) SCF1 14 I System clock frequency select (128/256/384/512 fs) (see Note 1) CSBIT 15 O Channel status bit output (see Note 2) URBIT 16 O User bit output (see Note 2) EMFLG 17 O Emphasis flag BFRAME 18 O Block start clock (B-frame) BRSEL 19 I Default bit rate select (32 / 44.1 / 48 / 88.2 / 96 kHz) (see Note 1) DIN 20 I S/PDIF data digital input (see Note 4) RST 21 I Reset input, active LOW (see Note 3) FILT 22 – External filter AGND 23 – Analog ground VCC 24 – Analog power supply, 3.3V FMT0 25 I Audio data format select (see Note 1) FMT1 26 I Audio data format select (see Note 1) UNLOCK 27 O PLL unlock or parity error flag CKSEL 28 I System clock operation mode selected. Low: PLL, High: Crystal (see Note 1) NOTES: 1. Schmitt trigger input with internal pulldown (TYP 51 kΩ ), 5 V tolerant. 2. Serial outputs are utilized for both consumer and professional application. 3. Schmitt trigger input with internal pullup (TYP 51 kΩ ), 5 V tolerant. 4. CMOS level input with internal pulldown (TYP 51 kΩ ), 5 V tolerant.

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007 – JULY 2001 4 www.ti.com absolute maximum ratings† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007 – JULY 2001 5www.ti.com electrical characteristics, all specifications at TA = 25°C, VCC = VDD = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT VIH (5) 2 5.5 VIL (5) 0.8 VIH2 (6) Input logic level 70%V DD VDCVIL2 (6) Input logic level 30%V DD VDC VIH3 (7) 70%V DD 5.5 VIL3 (7) 30%V DD VOH (8) IO = 1 mA VDD –0.4 VOL (8) Output logic level IO = –2 mA 0.5 VDCVOH (9) Output logic level IO = 2 mA VDD –0.4 VDC VOL (9) IO = –4 mA 0.5 IIH(10) VIN = VDD 65 100 IIL(10) VIN = 0 V –10 10 IIH(11) Input leakage current VIN = VDD –10 10 µAIIL(11) Input leakage current VIN = 0 V –100 –65 µA IIH(6) VIN = VDD –10 10 IIL(6) VIN = 0 V –10 10 fs(12) Input sampling frequency 32 96 kHz SCKO System clock frequency 4.096 128/256/ 384/512 fs 49.152 MHz tj SCKO clock jitter 75 ps RMS SCKO duty cycle 50% XTI clock accuracy –500 See Table 3 500 ppm S/PDIF INPUT Duty cycle VIN = 1.5 V, fs = 96 kHz 15% 85% Jitter VIN = 1.5 V ±10 ns p-p POWER SUPPLY REQUIREMENTS VDD , VCC Voltage range 3 3.3 3.6 VDC ICC (VCC ) Supply current (see Note 13) 3.4 4.7 mAIDD (VDD ) Supply current (see Note 13) 26 36 mA PD Power dissipation 100 mW TEMPERATURE RANGE Operation temperature –25 85 °C θJA Thermal resistance 28-pin SSOP 100 °C/W NOTES: 5. TTL compatible, except pins 8, 20: XTI, DIN. 6. Pin 8: XTI (CMOS logic level). 7. Pin 20: DIN (CMOS logic level). 8. Pins 1–3, 9, 17–18, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK. 9. Pins 4, 10–12, 15–16: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. 10. Pins 13–14, 19–20, 25–26, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL. 11. Pin 21: RST 12. fs is defined as the incoming audio sampling frequency per channel. 13. No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock frequency.

operation modes are user selectable. giving very low jitter clock from S/PDIF data input. The DIR1703 has two PLLs, PLL1 and PLL2. SpAct is supplied with a 100 MHz executing clock from PLL1. XTI/XTO pins or applying an external clock input at the XTI pin as shown in Figure 1. is around 1 ms using the SpAct. pins simultaneously indicate the bit rate of the incoming S/PDIF signal. clock frequency, 128, 256, 384, or 512 fS is also selected by the SCF pins. to the incoming S/PDIF signal. Figure 1. System Clock Connections

oscillator clock (crystal mode) or the PLL clock (PLL mode) by the SpAct. SCKO can be generated from several crystal oscillators shown in Table 2. by control data at SCF0 and SCF1 pins shown in Table 4. detected. The required accuracy for clock frequency of the crystal resonator or external clock input is ±500 ppm. Table 1. Generated System Clock (SCKO) PLL Clock Operation Mode Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter

Table 2. Generated System Clock (SCKO) Crystal Clock Operation Mode Table 3. Selectable Crystal Oscillator

45.1584 MHz

49.152 MHz

Table 4. System Clock Selection

Table 5. System Clock Operation Mode † In the PLL mode, the DIR1703 will be the same frequencies as the crystal mode after RESET; however, the frequency error is below 1%. ‡ Holds the latest tracked frequency.

the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins. shows the same HL value. This state is not defined in the S/PDIF specifications. Table 6. Incoming Sample Frequency Bits Figure 3. PLL Lock Up Timing resonator, however, its error frequency is below 1% after reset. at the latest tracked bit rate.

Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing minimum of 200 ms. In this period, SCKO, BCKO, and LRCKO frequencies hold the latest tracked frequency. frequency, after at least 1 ms (before the UNLOCK flag becomes low). CKTRNS indicates the validity of SCKO. When CKTRNS is high, the frequency of SCKO, BCKO, and LRCKO is in transition.

The DIR1703 can produce 16-bit or 24-bit output data in standard format and 24-bit output data in IIS format. Table 7. Audio Output Data Format Select Figure 7. Audio Data Output Format

Figure 8. Audio Data Output Timing ADFLG is low, S/PDIF data includes PCM audio signal. In other cases, ADFLG is high. In the consumer mode EMFLG indicates 2-channel audio with a 50/15-µs time constant pre-emphasis. L-ch and R-ch information sequentially.

s x 32 (s), then BFRAME returns to low after 32 frames.

64 BCKO

Figure 9. Timing Chart for Audio Data and Channel Status

be at least 10 ms. All of the output pins except CKTRNS and UNLOCK are LOW during RST LOW. the change is needed, the reset sequence must be started by asserting RST again. Figure 10. After Power ON

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007 – JULY 2001 17www.ti.com typical circuit connection ADFLG BRATE0 BRATE1 SCKO VDD DGND XTO XTI CKTRNS LRCKO BCKO DOUT SCF0 SCF1 CKSEL UNLOCK FMT1 FMT0 VCC AGND FILT RST DIN BRSEL BFRAME EMFLG URBIT CSBIT C 7 C 8R 2 C 2

3.3 V VCC

Reset (Active LOW) Receiver Circuit BRSEL Connection Depends Upon Crystal Resonator Frequency.Audio Data Processor System Clock Frequency Select (128,256,348, 512 fs) C 6 R 1 C 5 C 1 C 3

3.3 V VDD

C 1 , C2: Bypass Capacitor, 1 µF to 10 µF C 3 , C4: Bypass Capacitor, 0.01 µF to 0.1 µF C 5 , C6: OSC Capacitor, 10 to 33 pF C 7: Loop Filter Capacitor, 0.068 µF C 8: Loop Filter Capacitor, 0.0082 µF R 1: OSC Resistor, 1 M Ω R 2: Loop Filter Resistor, 1.2 kΩ + + For Automatic System Clock Selection

/C0068/C0073/C0082/C0049/C0055/C0048/C0051 SLES007 – JULY 2001 18 www.ti.com DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065/D 09/00

28 PINS SHOWN

8,20 7,40 0,15 NOM 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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