DIR1700 BURR-BROWN | Alldatasheet
Document overview
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Technical content
1 DIR1700
49% FPO International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DIR1700 PRELIMINARY INFORMATION SUBJECT TO CHANGE WITHOUT NOTICE DIGITAL AUDIO INTERFACE RECEIVER
FEATURES
l STANDARD DIGITAL AUDIO INTERFACE RECEIVER (EIAJ1201) l SAMPLING RATE: 32 /44.1/48/96kHz l RECOVERS 256/384/512fS SYSTEM CLOCKS l VERY LOW CLOCK JITTER: 100ps (with 20pF load) l FLEXIBLE SYSTEM CLOCK OUTPUT l SELECTABLE OUTPUT PCM AUDIO DATA FORMAT l XTAL CLOCK/PLL CLOCK OPERATION MODES l SELECTABLE ERROR FLAG FUNCTION l OUTPUTS CHANNEL STATUS DATA FLAG WITH BLOCK START SIGNAL l OUTPUTS USER BIT DATA l SINGLE +5V POWER SUPPLY l 28-LEAD SSOP PACKAGE
DESCRIPTION
DIR1700 is a Digital Audio Interface Receiver (DIR) which is designed for consumer and professional digi- tal audio applications, such as digital AV receivers. DIR1700 has two system clock operation modes: internal PLL operation mode and XTAL clock opera- tion mode for systems which contain both digital and analog inputs. The advantages of the DIR1700 are very low clock jitter, and 96kHz sampling rate capa- bility. These features are now required for consumer and professional audio systems. DIR1700 PDS-1416© 1998 Burr-Brown Corporation PDS-1416 Printed in U.S.A. September, 1998 PLL 256/384/512 Select Xtal Bias Network Xtal Oscillation STOP VCO STOP 258/384/512fs PLL lock or unlock Data Mute Clocks Xtal Oscillation Clock Xtal Existence Auto-Detection CLKSEL OSCSEL Error Check Oscillation Select BLSTRT CSBIT UDAT Output Timing CS1 CS2 CS3 CS24 CS25 VLFLG DAT D1D0ERSNSERFDGNDVDD BCK LRCK SCLK DIN FIL AGND VCC Data Format Select XTO XTI Clock and Data Recover Parity
PRODUCT PACKAGE NUMBER (1) DIR1700E 28-Lead SSOP 324 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. DIR1700E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL FILTER PERFORMANCE Input Logic Level: VIH(1) 2.0 VDC VIL(1) 0.8 VDC VIH2(2) 70% V DD VDC VIL2(2) 30% V DD VDC VIH3(3) TBD VDC VIL3(3) TBD VDC Output Logic Level: VOH (4) IO = 2mA V DD 0.4 VDC VOL (4) IO = –4mA 0.5 VDC Input Leakage Current: IIN ±1.0 ±10 µA Input Sampling Frequency: fS +32 96 kHz System Clock Frequency SCLK(5) 8.192 256, 384, 512f S 36.864 MHz SCLK Clock Jitter 100 ps rms SCLK Duty Cycle 50 % Crystal Resonator Frequency 8.192 24.576 MHz POWER SUPPLY REQUIREMENTS Voltage Range V DD, VCC +4.5 +5 +5.5 VDC Supply Current: IA (VCC ) TBD mA ID (VDD ) TBD mA Power Consumption P D TBD mA NOTES: (1) Except CLKSEL DIN; TTL Compatible. (2) CLKSEL. (3) DIN, CMOS Logic Level. (4) Pins 6-8, 11-21, and 23. (5) fS is defined as the incoming audio sampling frequency per channel. (6) DIR1700 without load at SCLK, LRCK, BCK, DAT. Power supply current varies with system clock frequency. SPECIFICATIONS—Preliminary All specifications at +25°C and VCA = VCP = VDD = +5V, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION
3 DIR1700
1 CLKSEL In Clock Select (256f S, 384fS and 512fS)(1)
2 OSCSEL In Oscillation Select (PLL/Xtal) (2)
3V CC — Analog Power Supply
4 FIL — PLL Filter
5 AGND — Analog Ground
6 NC — No Connection
7 CS25 Out f
S Rate Flag (32k, 44.1k and 48k)(4) 8 CS24 Out f S Rate Flag (32k, 44.1k and 48k)(4)
9 XTI In Crystal In
10 XTO Out Crystal Out
11 BLSTRT Out Block Start Clock
(5)
12 UDAT Out User Data Out (5)
13 CSBIT Out Channel Status Bit (5)
14 VLFLG Out Validity Flag
15 CS3 Out Emphasis Flag
(4)
16 CS2 Out Copy Guard Flag (4)
17 CS1 Out Audio Data Flag (PCM/DATA) (4)
18 SCLK Out Audio System Clock Out
19 BCK Out Audio Bit Clock Out
20 DAT Out Audio Data Out
21 LRCK Out Audio Left/Right Clock Out
22 DIN In Data Input
23 ERF Out Error Flag Out (PLL Unlock/Parity Error)
24 DGND — Digital Ground
25 ERSNS In Error Sense Switch
(2)
26 V DD — Digital Power Supply
27 D1 In Data Format Select 1 (3)
28 D0 In Data Format Select 0 (3)
NOTES: (1) When “CLKSEL” is open, input level becomes 1/2 VDD by pull- up and pull-down resistors. (2) Pull-up. (3) Pull-down. (4) Channel status output pins become active for consumer applications. (5) Serial outputs are utilized for both consumer and professional applications. PIN ASSIGNMENTS NC = No Connection CLKSEL OSCSEL VCC FIL AGND NC CS25 CS24 XTI XTO BLSTRT UDAT CSBIT VLFLG V DD ERSNS DGND ERF DIN LRCK DAT BCK SCLK CS1 CS2 CS3 DIR1700E