DG894

DG894 VISHAY | Alldatasheet

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Document Number: 70072 S-52433—Rev. D, 06-Sep-99 www.siliconix.com FaxBack 408-970-5600 5-1 Component Video Selector Wide Bandwidth: 200 MHz Very Low Crosstalk: –70 dB at 5 MHz CMOS Compatible I2C Bus Compatible Fast Switching—tON: <200 ns Low rDS(on): 44 Single Supply Capability Low Insertion Loss Improved System Performance Reduced Power Consumption Easily Interfaced Future System Expansion via I2C Bus Component Video Switching: RGB + SYNC, S-VHS, Y-C, etc. Audio/Video Routing Digital TV ATE I2C Bus Audio/Video Systems SCART Video Switching The DG894 is a monolithic video selector designed for switching a variety of component video signals. The low on-resistance and low capacitance of the DG894 make it ideal for video/audio signal routing. Switch control can be through direct CMOS addressing or through the two-wire I2C bus. The DG894 is built on the Vishay Siliconix proprietary D/CMOS process that combines n-channel DMOS switching FETs with low-power CMOS control logic and drivers. Low-capacitance DMOS FETs are used to achieve high levels of off isolation at low cost. SMO SEL SDA SCL Function/Switch On I2C Bus Operation, Address A0 = “1” I2C Bus Operation, Address A0 = “0” All switches off Y0, C0 Y1, C1 Y2, C2 R1, G1, B1, F1 R2, G2, B2, F2 R1, G1, B1, F1, Y1, C1 R2, G2, B2, F2, Y2, C2 Temp Range Package Part Number –40 to 85C 28-Pin Plastic DIP DG894DJ –40 to 85C 28-Pin Wide Body SOIC DG894DW

www.siliconix.com FaxBack 408-970-5600 5-2 Document Number: 70072 S-52433—Rev. D, 06-Sep-99 V+ to GND –0.3 V to 19 V V+ to V– –0.3 V to 19 V V– to GND –10 V to 0.3 V Digital Inputs GND –0.3 V to (V+) +0.3 V or 20 mA, whichever occurs first Signal Inputs VSS –0.3 V to 8 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) 20 mA Current (Any Terminal) Pulsed 1 ms, 10% Duty Cycle Max 40 mA Storage Temperature –65 to 125C Power Dissipation (Package)a 28-Pin Plastic DIP 625 mW 28-Pin Wide Body SOIC 450 mW Notes: a. All leads welded or soldered to PC board. Test Conditions Unless Otherwise Specified Limits –40 to 85C Parameter Symbol VDD = 12 V, VSS = –5 V VINH = 3 V, VINL = 1.5 Ve Tempa Minc Typb Maxc Unit Analog Switch Analog Signal Ranged VANALOG VDD = 12 V, VSS = GND Full V Analog Signal Ranged VANALOG VDD = 12 V, VSS = –5 V Full V Drain-Source On-Resistance rDS(on) IS = –10 mA, VD = 0 V Room Full 100 150 Resistance Match Between Channels rDS(on) IS = –10 mA, VD = 0 V Room Source Off Leakage Current IS(off) VS = 4 V, VD = 0 V Room Full –10 –100 –0.05 100 Drain Off Leakage Current ID(off) VD = 4 V, VS = 0 V Room Full –10 –100 –0.05 100 nA Total Switch On Leakage Current ID(on) VD = VS = 4 V Room Full –10 –100 –0.07 100 Input Input Voltage High VINH Full 2.55 Input Voltage Low VINL Full 2.55 1.5 V Input Threshold Vth Room 2.55 Temp Coefficient of Input Threshold TCth Full –200 C Input Current IIN VIN = GND or VDD Room Full –20 0.05 A Output Voltage Low VOL Pin 21, During Acknowledge, IOL = 3 mA Room 0.4 V Dynamic Input Capacitanced Cin Pin 21, 22 Room F On State Input Capacitanced CS(on) VS = VD = 0 V Room pF Off State Input Capacitanced CS(off) VS = 0 V Room pF Off State Output Capacitanced CD(off) VD = 0 V Room Bandwidthd BW RL = 50 , See Figure 1 Room 200 500 MHz Turn On Time tON RL = 1 k, CL = 35 pF, 50% to 90% VSS = –5 V, 0 V, VS = 3 V, Room 200 ns Turn Off Time tOFF VSS = –5 V, 0 V, VS = 3 V, See Figure 1 Room 180 ns SCL Max Clock Frequency FSCL(MAX) Full 100 kHz Component Crosstalk XTALK(CO) RIN = 10 , RL = 1 k f 5 MH S Fi d 3 Room –85 dB Channel Crosstalk XTALK(CH) IN L f = 5 MHz, See Figure 2 and 3 Room –85 dB

Document Number: 70072 S-52433—Rev. D, 06-Sep-99 www.siliconix.com FaxBack 408-970-5600 5-3 Test Conditions Unless Otherwise Specified Limits –40 to 85C Parameter Symbol VDD = 12 V, VSS = –5 V VINH = 3 V, VINL = 1.5 Ve Tempa Minc Typb Maxc Unit Supply Voltage Positive Supply Current All Control Inputs 0 V, 5 V Room Full mA Negative Supply Current All Control Inputs 0 V, 5 V Room Full –10 –2.5 –3.0 mA Notes: Room = 25C, Full = as determined by the operating temperature suffix. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. Guaranteed by design, not subject to production test. VIN = input voltage to perform proper function. Purchase of Vishay Siliconix DG894 components conveys a license to use them in the I2C system as defined by Philips. rDS(on) vs. Drain Voltage tON vs. Bipolar Supply Voltage rDS(on) vs. Drain Voltage tOFF vs. Bipolar Supply Voltage rDS(on)– Drain-Source On-Resistance ( tON (ns) tOFF (ns) V+ – Positive Supply (V) V+ – Positive Supply (V) VD – Drain Voltage (V) VD – Drain Voltage (V) 200 180 160 140 120 100 200 180 160 140 120 100 V+ = 12 V V– = 0 V IS = –10 mA 25C 85C –40C 106 100 10.8 11.2 13.2 11.6 12.0 12.4 12.8 85C 25C –40C V– = –5 V See Figure 1 45.5 43.5 41.5 35.5 10.8 11.2 13.2 39.5 37.5 11.6 12.0 12.4 12.8 85C 25C –40C V– = –5 V See Figure 1 V+ = 12 V V– = –5 V IS = –10 mA 25C 85C –40C rDS(on)– Drain-Source On-Resistance (

www.siliconix.com FaxBack 408-970-5600 5-4 Document Number: 70072 S-52433—Rev. D, 06-Sep-99 Component Crosstalk Channel Crosstalk SDA Output Current vs. Supply Voltage SDA Output Current vs. Temperature tON vs. Unipolar Supply Voltage tOFF vs. Unipolar Supply Voltage tON (ns) tOFF (ns) Current (mA) dB Current (mA) dB f – Frequency (MHz) f – Frequency (MHz) VSUPPLY (V) Temperature (_C) V+ – Positive Supply (V) V+ – Positive Supply (V) 108 100 10.8 11.2 13.2 11.6 12.0 12.4 12.8 85C 25C –40C V– = 0 V See Figure 1 10.8 11.2 13.2 11.6 12.0 12.4 12.8 85C 25C –40C V– = 0 V See Figure 1 –40 –20 Specification Minimum Limit 100 V+= 12 V VOL = 0.4 V V– = –5 V V– = 0 V 120 100 110 VDS = +12 V VSS = –5 V RIN = 10 RL = 1 k See Figure 2 120 100 110 VDD = +12 V VSS = –5 V RIN = 10 RL = 1 k See Figure 3 10.8 11.2 13.2 11.6 12.0 12.4 12.8 V– = –5 V V– = 0 V VOL = 0.4 V TA = 25C Specification Minimum Limit

www.siliconix.com FaxBack 408-970-5600 5-6 Document Number: 70072 S-52433—Rev. D, 06-Sep-99 –5.5 –5.0 –2.5 –2.0 –1.5 –1.0 –0.5 –0.0 V+ – Positive Supply Voltage (V) V– – Negative Supply Voltage (V) f a Data Sheet Test Conditions Operating Voltage Area FIGURE 5. Symbol

Description

Y0, Y1, Y2 An analog channel input, typically luminance. C0, C1, C2 An analog channel input, typically chrominance. R1, R2, G1, G2, B1, B2, FB1, FB2 An analog channel input, typically “red”, “green”, “blue” or “fast blanking”, as appropriate. GND Analog and digital ground. VDD Positive supply voltagea VSS Negative supply voltage YOUT , COUT An analog channel output, typically luminance or chrominance, as appropriate ROUT , GOUT , BOUT , FBOUT An analog channel output, typically “red”, “green”, “blue” or “fast blanking”, as appropriate. SMO A low selects serial mode (I2C) operation. A high selects CMOS operation. SDA Serial data lineb SCL Serial clock lineb SEL CMOS control line or I2C addressc select line Notes: a. Both VDD pins (Pin 1 and Pin 26) must be connected for proper operation. b. SDA and SCL pins become CMOS control inputs when SMO = High. c. The SEL pin, in I2C bus operation (i.e., with SMO low), is the least significant bit of the device address. This allows two devices to operate on the same I2C bus, yet retain independent control.

Document Number: 70072 S-52433—Rev. D, 06-Sep-99 www.siliconix.com FaxBack 408-970-5600 5-7 FIGURE 6. FB1 ROUT GOUT BOUT FBOUT ROUT GOUT BOUT SYNCOUT FB2 SMO SEL SDA +5 V CLC114 VSS VDD –5 V +12 V SCL GND COUT YOUT –5 V +5 V Channel Select Control Logic Left Right Left1 Right1 SYNC1 Left2 Right2 SYNC2

www.siliconix.com FaxBack 408-970-5600 5-10 Document Number: 70072 S-52433—Rev. D, 06-Sep-99 STO tBUF tHD;STA tLOW tHIGH tHD;DAT tSU;DAT tSU;STO tR tF tHD;STA SDA SCL STA STA STO tSU;STA FIGURE 10.I2C Bus Timing Diagram Minimum Bit Stream to Set Up DG894 Switches STA R/W ACK X X X ACK STO STA = START CONDITION = 0 (programmable to “1” with metal mask change) = SEL. Address bit set by use (address is inverse of SEL logic level) R/W = READ/WRITE bit (must be “0”, only WRITE mode allowed for DG894) ACK = Acknowledge bit (“0”) generated by DG894 = 0 –– R2, G2, B2, and FB2 switches off = 1 –– R2, G2, B2, and FB2 switches on = 0 –– R1, G1, B1, and FB1 switches off = 1 –– R1, G1, B1, and FB1 switches on = 0 –– Y2, C2, switches off = 1 –– Y2, C2, switches on = 0 –– Y1, C1, switches off = 1 –– Y1, C1, switches on = 0 –– Y0 and C0 switches off = 1 –– Y0 and C0 switches on STO = STOP CONDITION Data Byte Address Byte