DG884

DG884 VISHAY | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Document Number: 70071 S-52433—Rev. G, 20-Dec-04 www.vishay.com 8 x 4 Wideband Video Crosspoint Array FEATURES BENEFITS APPLICATIONS /C0068Routes Any Input to Any Output /C0068Wide Bandwidth: 300 MHz /C0068Low Crosstalk: −85 dB @ 5 MHz /C0068Double Buffered TTL-Compatible Latches with Readback /C0068Low rDS(on): 45 /C0087 /C0068Optional Negative Supply /C0068Reduced Board Space /C0068Improved System Bandwidth /C0068Improved Channel Off-Isolation /C0068Simplified Logic Interfacing /C0068Allows Bipolar Signal Swings /C0068Reduced Insertion Loss /C0068High Reliability /C0068Wideband Signal Routing and Multiplexing /C0068High-End Video Systems /C0068NTSC, PAL, SECAM Switchers /C0068Digital Video Routing /C0068ATE Systems

DESCRIPTION

The DG884 contains a matrix of 32 T-switches configured in an 8 /C0032 4 crosspoint array. Any of the IN/OUT pins may be used as an input or output. Any of the IN pins may be switched to any or simultaneously to all OUT pins. The DG884 is built on a proprietary D/CMOS process that combines low capacitance switching DMOS FETs with low power CMOS control logic and drivers. The ground lines between adjacent signal input pins help to reduce crosstalk. The low on-resistance and low on-capacitance of the DG884 make it ideal for video and wideband signal routing. Control data is loaded individually into four Next Event latches. When all Next Event latches have been programmed, data is transferred into the Current Event latches via a SALVO command. Current Event latch data readback is available to poll array status. Output disable capabilities make it possible to parallel multiple DG884s to form larger switch arrays. DIS outputs provide control signals used to place external buffers in a power saving mode. For additional information see applications note AN504 (FaxBack document number 70610). FUNCTIONAL BLOCK DIAGRAM IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 OUT1 OUT2 OUT3 OUT4 A3 A2 A1 A0 CS WR I/O I/O Control Logic Decode Logic, Switch Drivers Current Event Latches Next Event Latches 8 4 Switch Matrix

4 Disable Outputs

654321 4 4 4 3 4 2 4 1 4 0 18 19 20 21 22 23 24 25 26 27 28 Top View GNDGND IN8 GNDGND GNDV− OUT1 GND2 OUT3 GND4 OUTV+ GND0 OUT1 IN DIS DIS DIS DIS B B DG884 Vishay Siliconix www.vishay.com Document Number: 70071 S-52433—Rev. G, 20-Dec-04 PIN CONFIGURATION AND ORDERING INFORMATION

ORDERING INFORMATION

Temp Range Package Part Number −40 to 85/C0095C 44-Pin PLCC DG884DN −55 to 125/C0095C 44-Pin CLCC DG884AM/883 TRUTH TABLE I RS I/O CS WR SALVO Actions 1 0 1 1 No change to Next Event latches 1 0 0 1 Next Event latches loaded as defined in table below 1 0 0 0 1 Next Event latches are transparent. 1 0 0 1 Next Event data latched-in 1 0 X 1 Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all new crosspoint addresses change simultaneously when SALVO goes low. 1 0 0 X 0 Current Event latches are transparent 1 0 X 1 Current Event data latched-in 1 0 0 0 0 Both next and Current Event latches are transparent 1 1 1 1 1 A0, A1, A2, A3 − High impedance 1 1 0 1 1 A0, A1, A2, A3 become outputs and reflect the contents of the Current Event latches. B0, B1 determine which Current Event latches are being read

0 X X 1 1 All crosspoints opened (but data in Next Event latches is preserved)

All other states are not recommended.

Document Number: 70071 S-52433—Rev. G, 20-Dec-04 www.vishay.com TRUTH TABLE II WR B1 B0 A3 A2 A1 A0 Next Event Latches 0 0 1 IN1 to OUT1 Loaded IN2 to OUT1 Loaded IN3 to OUT1 Loaded IN4 to OUT1 Loaded IN5 to OUT1 Loaded IN6 to OUT1 Loaded IN7 to OUT1 Loaded IN8 to OUT1 Loaded

0 X X X Turn Off OUT1 Loaded

0 X X X Turn Off OUT2 Loaded

0 X X X Turn Off OUT3 Loaded

0 X X X Turn Off OUT4 Loaded

Note: When WR = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect IN1 to OUT1 thru OUT4 requires A0, A1, A2 = 0 to be latched with each combination of B0, B1. When RS = 0, all four DIS outputs pull low simultaneously. ABSOLUTE MAXIMUM RATINGS or 20 mA, whichever occurs first or 20 mA, whichever occurs first Power Dissipation (Package)a Notes: a. All leads soldered or welded to PC board. b. Derate 6 mW/ /C0095C above 75/C0095C. c. Derate 16 mW/ /C0095C above 75/C0095C.

www.vishay.com Document Number: 70071 S-52433—Rev. G, 20-Dec-04 SPECIFICATIONSa Test Conditions Unless Specified A Suffix −55 to 125/C0095C D Suffix −40 to 85/C0095C Parameter Symbol VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V Tempb Typc Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Rangee VANALOG V− = −5 V Full −5 8 −5 8 V Drain-Source On-Resistance rDS(on) IS = −10 mA, VD = 0 V VAIH = 2 0 V VAIL = 0 8 V Room Full 45 90 120 120 /C0087 Resistance Match Between Channels /C0068rDS(on) VAIH = 2.0 V, VAIL = 0.8 V Sequence Each Switch On Room 3 9 9 /C0087 Source Off Leakage Current IS(off) VS = 8 V, VD = 0 V, RS = 0.8 V Room Full −20 −200 200 −20 −200 200 Drain Off Leakage Current ID(off) VS = 0 V, VD = 8 V, RS = 0.8 V Room Full −20 −200 200 −20 −200 200 nA Total Switch On Leakage Current ID(on) VS = VD = 8 V Room Full −20 −2000 2000 −20 −200 200 Digital Input/Output Input Voltage High VAIH Full 2 2 V Input Voltage Low VAIL Full 0.8 0.8 V Address Input Current IAI VAI = 0 V or 2 V or 5 V Room Full 0.1 −1 −10 −10 Address Output Current IAO VAO = 2.7 V, See Truth Table Room −600 −200 −200 /C0109A Address Output Current VAO = 0.4 V, See Truth Table Room 1500 500 500 DIS Pin Sink Current IDIS Room 1.5 mA Dynamic Characteristics On State Input Capacitancee CS(on)

1 In to 1 Out, See Figure 11 Room 30 40

On State Input Capacitancee CS(on)

1 In to 4 Out, See Figure 11 Room 120 160

Off State Input Capacitancee CS(off) Room 8 20 20 pF Off State Output Capacitancee CD(off) See Figure 11 Room 10 20 20 Transition Time tTRANS See Figure 5 Room 300 Break-Before-Make Interval tOPEN See Figure 5 Full 10 10 SALVO, WR Turn On Time tON RL= 1 k/C0087 , CL = 35 pF 50% Control to 90% Output Room Full 300 500 300 ns SALVO, WR Turn Off Time tOFF 50% Control to 90% Output See Figure 3 Room Full 175 300 175 Charge Injection Q See Figure 6 Room −100 pC Matrix Disabled Crosstalk XTALK(DIS) RIN = RL = 75 /C0087 f = 5 MHz, See Figure 10 Room −82 Adjacent Input Crosstalk XTALK(AI) RIN = 10 /C0087 , RL = 10 k/C0087 f = 5 MHz, See Figure 9 Room −85 dB All Hostile Crosstalk XTALK(AH) RIN = 10 /C0087 , RL = 10 k/C0087 f = 5 MHz, See Figure 8 Room −66 Bandwidth BW RL = 50 /C0087 , See Figure 7 Room 300 MHz

Document Number: 70071 S-52433—Rev. G, 20-Dec-04 www.vishay.com SPECIFICATIONSa Test Conditions Unless Specified A Suffix −55 to 125/C0095C D Suffix −40 to 85/C0095C Parameter Symbol VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V Tempb Typc Mind Maxd Mind Maxd Unit Power Supplies Positive Supply Current I+ Room Full 1.5 3 mA Negative Supply Current I− All Inputs At GND or 2 V RS = 2 V Room Full −1.5 −3 mA Digital GND Supply Current IDG RS = 2 V Full −275 −750 −750 /C0109A Logic Supply Current IL Full 200 500 500 /C0109A OS V+ to V− See Operating Voltage Range Full 13 20 13 20 Functional Operating Supply Volt- age Rangee V− to GND See Operating Voltage Range (Typical Characteristics) page 6 Full −5.5 0 −5.5 0 Vage Rangee V+ to GND (y p ) page 6 Full 10 20 10 20 Minimum Input Timing Requirements Address Write Time tAW Full 20 50 50 Minimum WR Pulse Width tWP Full 50 100 100 Write Address Time tWA Full −10 10 10 Chip Select Write Time tCW Full 50 100 100 Write Chip Select Time tWC Full 25 75 75 Minimum SALVO Pulse Width tSP Full 50 100 100 SALVO Write Time tSW See Figure 1 Full −10 10 10 ns Write SALVO Time tWS See Figure 1 Room 20 50 ns Input Output Time tIO Room 150 200 200 Address Output Time tAO Room 150 200 200 Chip Select Output Time tCO Room 150 200 200 Chip Select Address Time tCA Room 60 100 Reset to SALVO tRS Full 50 50 I/O Address Input Time tIA Room 50 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 /C0095C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. Guaranteed by design, not subject to production test.

www.vishay.com Document Number: 70071 S-52433—Rev. G, 20-Dec-04 TYPICAL CHARACTERISTICS (25/C0095C UNLESS NOTED) Adjacent Input Crosstalk All Hostile Crosstalk Matrix Disabled Crosstalk f − Frequency (MHz) f − Frequency (MHz) f − Frequency (MHz) (−dB)TALK(AI)X(−dB)TALK(AH)X (−dB)TALK(DIS)X Operating Voltage Area V− − Negative Supply (V) V+ − Positive Supply (V) 1 10 100 100 1 10 100 120 100 1 10 100 120 100 Operating Voltage Area

FIGURE 3. SALVO Turn On/Off Time FIGURE 4. WR Turn On/Off Time FIGURE 5. Transition Time and Break-Before-Make Interval

0 V 50%

FIGURE 6. Charge Injection FIGURE 7. −3 dB Bandwidth FIGURE 8. All Hostile Crosstalk FIGURE 9. Adjacent Input Crosstalk FIGURE 10. Matrix Disabled Crosstalk FIGURE 11. On-State and Off-State Capacitances

15 V−3 V

www.vishay.com Document Number: 70071 S-52433—Rev. G, 20-Dec-04 PIN DESCRIPTION Pin Symbol Description 18, 20, 41, 43 GND Analog Signal Ground

39 DGND Digital Ground

26 V+ Positive Supply Voltage

21 V− Negative Supply Voltage

38 VL Logic Supply Voltage—generally 5 V

5, 7, 9, 11, 13, 15, 17, 19 IN1 to IN8 8 Analog Input Channels 2, 40, 42, 44 OUT1 to OUT4 4 Analog Output Channels 29 I/O Determines whether data is being written into the Next Event latches or read from the Current Event latches

30 CS Chip Select—a logic input

31, 32, 33, 34 A0, A1, A2, A3 IN Address—logic inputs or outputs as defined by I /O pin, select one of eight IN channels 27, 28 B0, B1 OUT Address—logic inputs, select one of four OUT channels

35 WR Write command that latches A0, A1, A2, A3 into the Next Event latches

36 SALVO Master write command, that in one action, transfers all the data from Next Event latches into

37 RS Reset—a low will clear the Current Event latches

22, 23, 24, 25 DIS1 to DIS4 Open drain disable outputs—these outputs pull low when the corresponding OUT channel is off DEVICE DESCRIPTION The DG884 is the world’s first monolithic wideband crosspoint array that operates from dc to >100 MHz. The DG884 offers the ability to route any one of eight input signals to any one of four OUT pins. Any input can be routed to one, two, three or four OUTs simultaneously with no risk of shorting inputs together (guaranteed by design). Each crosspoint is configured as a “T” switch in which DMOS FETs are used due to their excellent low resistance and low capacitance characteristics. Each OUT line has a series switch that minimizes capacitive loading when the OUT is off. Interfacing The DG884 was designed to allow complex matrices to be developed while maintaining a simple control interface. The status of the I /O pin determines whether the DG884 is being written to or read from (see Figures 1 and 2). In order to WRITE to an individual latch, CS and I/O need to be low, while RS, WR and SALVO must be high. The IN to OUT path is selected by using address A0 through A3 to define the IN line and address B0 and B1 to define the OUT line. That is, The IN defined by A0 through A3 is electrically connected to the OUT defined by B0, B1. This chosen path is loaded into the Next Event latches when WR goes low and returns high again. This operation is repeated up to three more times if other crosspoint connections need to be changed. Upon completing all crosspoint connections that are to be changed in a single device, other DG884s can be similarly preset by taking the CS pin low on the appropriate device. When all DG884s are preset, the Current Event latches are simultaneously changed by a single SALVO command applied to all devices. In this manner the crosspoint configuration of any number of devices can be simultaneously updated. DIS Outputs Four open drain disable OUTs are provided to control external line drivers or to provide visual or electrical signaling. For example, any or all of the DIS OUTs can directly interface with a CLC410 Video Amplifier to place it into a high impedance, low-power standby mode when the corresponding OUT is not being used. (See Figure 15). The DIS outputs are low and sink to V− when corresponding OUT is open or RS is low. Reset The reset function (RS) allows the resetting of all crosspoints to a known state (open). At power up, the reset facility may be used to guarantee that all switches are open. It should be noted that RS clears the Current Event latches, but the Next Event latches remain unchanged. This useful facility allows the user to return the matrix to its previous state (prior to reset) by simply applying the SALVO command. Alternatively, the user can reprogram the Next Event latches, and then apply the SALVO command to reconfigure the matrix to a new state.

Document Number: 70071 S-52433—Rev. G, 20-Dec-04 www.vishay.com DEVICE DESCRIPTION Readback The I/O facility enables the user to write data to the Next Event latches or to read the contents of the Current Event latches. This feature permits the central controller to periodically monitor the state of the matrix. If a power loss to the controller occurs, the readback feature helps the matrix to recover rapidly. It also offers a means to perform PC board diagnostics both in production and in system operation. Mux 3 Decoder Q0 − Q3 Next Event Latch 3 Current Event Latch 3 Data Buffers CMOS Output Buffers

8 Analog Inputs

8 T-Switches

1 Series Switch

One of Four Blocks of Logic/Latches Shown FIGURE 12. Control Circuitry

APPLICATIONS

Two—Si584 Quad Unity-Gain Buffers CLC410 75 /C0087 75 /C0087 FIGURE 13. Fully Buffered 8 X 4 Crosspoint power down the Si582 amplifiers.

Document Number: 70071 S-52433—Rev. G, 20-Dec-04 www.vishay.com A typical switching threshold versus VL is shown in Figure 15. These devices feature an address readback facility whereby the last address written to the device may be read by the system. This allows improved status monitoring and hand shaking without additional external components. When the I /O assigns the address output condition, the A X address pins can sink or source current for logic low and high, respectively. Note that V L is the logic high output condition. This point must be respected if V L is varied for input logic threshold shifting. Note: Even though these devices are designed to be latchup resistant, V L must not exceed V+ by more than 0.3 V in operation or during power supply on/off sequencing. Layout The PLCC package pinout is optimized so that large crosspoint arrays can be easily implemented with a minimum number of PCB layers (see Figure 16). Crosstalk is minimized and off-isolation is optimized by having ground pins located adjacent to each input and output signal pins. Optimum off-isolation and low crosstalk performance can only be achieved by the proper use of RF layout techniques: avoid sockets, use ground planes, avoid ground loops, bypass the power supplies with high frequency type capacitors (low ESR, low ESL), use striplines to maintain transmission line impedance matching. Video In Bus Video In Bus Video In Bus Video In Bus Video Out Bus Video Out Bus Video Out Bus Video Out Bus Address Bus Address Bus FIGURE 16. 16 X 8 Expandable Crosspoint Matrix Using DG884

Document Number: 91000 www.vishay.com Revision: 08-Apr-05 1 Notice Specifications of the products displayed herein are subjec t to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.