DG508A

DG508A INTERSIL | Alldatasheet

Document overview

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• PDF pages: 9

Technical content

Features

• Low Power Consumption  TTL and CMOS-Compatible Address and Enable Inputs  44V Maximum Power Supply Rating  High Latch-Up Immunity  Break-Before-Make Switching  Alternate Source  Pb-free Available

Applications

 Data Acquisition Systems  Communication Systems  Signal Multiplexing/Demultiplexing  Audio Signal Multiplexing

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. DWG. # DG508AAK -55 to 125 16 Ld CERDIP F16.3 DG508ABK -25 to 85 16 Ld CERDIP F16.3 DG508ACJ 0 to 70 16 Ld PDIP E16.3 DG508ACJZ (See Note) 0 to 70 16 Ld PDIP (Pb-free) E16.3 NOTE: Intersil Pb-free products em ploy special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. Pinout DG508A (PDIP, CERDIP) TOP VIEW EN D GND DG508A A 2 A 1 A 0 EN ON SWITCH XXX0 N o n e 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 A 0, A1, A2, EN Logic “1” = VAH ≥ 2.4V, Logic “0” = VAL ≤ 0.8V Data Sheet September 13, 2004 [ /Title (DG50 6A, DG507 DG508 DG509 /Sub- ject (CMO S Ana- log Multi- plex- ers) /Autho r () /Key- words (Inter- sil Corpo- ration, semi- con- ductor, Multi- plexer, Mux, chan- nel, latched video) /Cre- ator () CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil and Design is a trademark of Intersil Americas Inc.|Copyright © Intersil Americas Inc. 2001, 2004

3 Line Binary Address Inputs

(1 0 1) and EN = 1 Above example shows channel 6 turned ON. S8 A 0 D ADDRESS DECODER

1 OF 8

A 1 A 2 EN (ENABLE INPUT) LOGIC TRIP POINT REF LOGIC INTERFACE AND LEVEL SHIFTER DECODER A X TYPICAL SWITCH SX D X GND LOGIC A X INPUT OR EN DG508A

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature Maximum Storage Temperature CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX , D, EN , or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified PARAMETER TEST CONDITIONS UNITS (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, tTRANSITION See Figure 1 - 0.6 1 - 0.6 - µs Break-Before-Make Interval, tOPEN See Figure 3 - 0.2 - - 0.2 - µs Enable Turn-ON Time, tON(EN) See Figure 2 - 1 1.5 - 1 - µs Enable Turn-OFF Time, tOFF(EN) See Figure 2 - 0.4 1.0 - 0.4 - µs OFF Isolation, OIRR V EN = 0V, RL = 1kΩ, CL = 15pF, VS =7 VRMS , f = 500kHz (Note 5) -6 8- -6 8- d B Source OFF Capacitance, C S(OFF) VS = 0V, VEN = 0V, f = 140kHz - 5 - - 5 - pF Drain OFF Capacitance, C D(OFF) VD = 0V, VEN = 0V, f = 140kHz - 25 - - 25 - pF Charge Injection, Q See Figure 4 - 4 - - 4 - pC DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, IAH VA = 15V - 0.006 10 - 0.006 10 µA Address Input Current Input Voltage Low, IAL VEN = 2.4V V A = 0V -10 -0.002 - -10 -0.002 - µA VEN = 0V -10 -0.002 - -10 -0.0002 - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Sequence Each Switch ON V AL = 0.8V, VAH = 2.4V IS = -200µA, VD = +10V - 270 400 - 270 450 Ω IS = -200µA, VD = -10V - 230 400 - 230 450 Ω rDS(ON) Matching Between Channels ∆rDS ON() rDS(ON)MAX rDS ON() MIN– rDS ON() AVG DG508A

Current, IS(OFF) VEN = 0V V S = +10V, VD = -10V -1 0.002 1 -5 0.002 5 nA VS = -10V, VD = +10V -1 -0.005 1 -5 -0.005 5 nA Drain OFF Leakage Current, ID(OFF) VEN = 0V V S = -10V, VD = +10V - 0.01 10 - 0.01 20 nA Drain ON Leakage Current, ID(ON) (Note 6) Sequence Each Switch ON V AL = 0.8V, VAH = 2.4V VD = VS(ALL) = +10V - 0.015 10 - 0.015 20 nA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ VEN = 5.0V (Enabled) or VEN = 0V (Standby), VA = 0V Negative Supply Current, I- -1.5 -0.7 - -1.5 -0.7 - mA Electrical SpecificationsTA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS UNITS (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX Electrical SpecificationsTA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified PARAMETER TEST CONDITIONS “A” SUFFIX UNITSMIN (NOTE 3) TYP MAX DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, IAH VA = 2.4V -30 - - µA VA = 15V - - 30 µA Address Input Current Input Voltage Low, IAL VEN = 2.4V V A = 0V -30 - - µA VEN = 0V -30 - - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG (Note 7) -15 - +15 V Drain-Source ON Resistance, rDS(ON) Sequence Each Switch ON VAL = 0.8V, VAH = 2.4V IS = -200µA, VD = +10V - - 500 Ω IS = -200µA, VD = -10V - - 500 Ω Source OFF Leakage Current, IS(OFF) VEN = 0V V S = +10V, VD = -10V - - 50 nA VS = -10V, VD = +10V -50 - - nA Drain OFF Leakage Current, ID(OFF) VEN = 0V V S = -10V, VD = +10V - - 200 nA VS = +10V, VD = -10V -200 - - nA Drain ON Leakage Current, ID(ON) (Note 6) Sequence Each Switch ON VAL = 0.8V, VAH = 2.4V VD = VS(ALL) = +10V - - 200 nA VD = VS(ALL) = -10V -200 - - nA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V EN = 5.0V, VA = 0V -3.2 - 4.5 mA Negative Supply Current, I- -3.2 - 4.5 mA Positive Standby Supply Current, I+ V EN = 0V, VA = 0V -3.2 - 4.5 mA Negative Standby Supply Current, I- -3.2 - 4.5 mA NOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet. 5. Off isolation = 20Log |VS |/|VD |, where VS = input to Off switch, and VD = output due to VS . 6. ID(ON) is leakage from driver into “ON” switch. 7. Parameter not tested. Parameter guaranteed by design or characterization. DG508A

DIE DIMENSIONS: 3100µm x 2083µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kÅ ±1.4kÅ Nitride: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG508A EN A 0 A 1 A 2 GND S4 DS 8 DG508A

Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli- able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com DG508A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N1 6 1 6 8 Rev. 0 4/94