DG506A

DG506A_07 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• Low Power Consumption
• TTL and CMOS-Compatible Address and Enable Inputs
• 44V Maximum Power Supply Rating
• High Latch-Up Immunity
• Break-Before-Make Switching
• Alternate Source

Applications

• Data Acquisition Systems
• Communication Systems
• Signal Multiplexing/Demultiplexing
• Audio Signal Multiplexing

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. DG506AAK -55 to 125 28 Ld CERDIP F28.6 DG506ACJ 0 to 70 28 Ld PDIP E28.6 DG506ACY 0 to 70 28 Ld SOIC M28.3 DG507ABK -25 to 85 28 Ld CERDIP F28.6 DG507ACJ 0 to 70 28 Ld PDIP E28.6 DG507ACY 0 to 70 28 Ld SOIC M28.3 DG508AAK -55 to 125 16 Ld CERDIP F16.3 DG508ABK -25 to 85 16 Ld CERDIP F16.3 DG508ACJ 0 to 70 16 Ld PDIP E16.3 DG509ACJ 0 to 70 16 Ld PDIP E16.3 DG509ACY 0 to 70 16 Ld SOIC M16.3 PART NUMBER TEMP. RANGE ( oC) PACKAGE PKG. NO. Pinouts DG506A (PDIP, CERDIP, SOIC) TOP VIEW DG507A (PDIP, CERDIP, SOIC) TOP VIEW DG508A (PDIP, CERDIP) TOP VIEW DG509A (PDIP, SOIC) TOP VIEW NC NC S S15 S14 S13 S12 S11 S10 GND NC A 3 D EN A 0 A 1 A 2 D B NC S8B S7B S6B S5B S4B S3B S2B S1B GND NC NC DA S8A S7A S6A S5A S3A S1A EN A 0 A 1 A 2 S4A S2A EN D GND EN S1A S2A S3A DA S4A S1B S2B S3B S4B DB GND Data Sheet November 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

A 3 A 2 A 1 A 0 EN ON SWITCH XXXX0 None 00001 1 00011 2 00101 3 00111 4 01001 5 01011 6 01101 7 01111 8 10001 9 10011 1 0 10101 1 1 10111 1 2 11001 1 3 11011 1 4 11101 1 5 11111 1 6 Logic “0” = V AL ,V ENL ≤ 0.8V, Logic “1” = VAH ,V ENH ≥ 2.4V. DG508A A 2 A 1 A 0 EN ON SWITCH X X X 0 None 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 A 0, A1, A2, EN Logic “1” = VAH ≥ 2.4V, Logic “0” = VAL ≤ 0.8V DG507A A 2 A 1 A 0 EN ON SWITCH X X X 0 None 0001 1 0011 2 0101 3 0111 4 1001 5 1011 6 1101 7 1111 8 Logic “0” = V AL , VENL ≤ 0.8V, Logic “1” = VAH , VENH ≥ 2.4V. DG509A A 1 A 0 EN ON SWITCH X X 0 None 0 0 1 1A, 1B 0 1 1 2A, 2B 1 0 1 3A, 3B 1 1 1 4A, 4B A 0, A1, EN Logic “1” = VAH ≥ 2.4V, Logic “0” = VAL ≤ 0.8V. DG506A, DG507A, DG508A, DG509A

4 Line Binary Address Inputs

(0 0 0 1) and EN = 5V Above example shows channel 2 turned ON. DG507A

3 Line Binary Address Inputs

(0 0 0) and EN = 5V Above example shows channels 1 A and 1B turned ON. DG508A (1 0 1) and EN = 1 Above example shows channel 6 turned ON. DG509A

2 Line Binary Address Inputs

(0 0) and EN = 1 Above example shows channels 1 A and 1B turned ON. S10 S11 S12 S13 S14 S15 A 0 D ADDRESS DECODER

1 OF 16

1 OF 4

1 OF 8

1 OF 2

A 1 A 2 EN (ENABLE INPUT)S8B DA D B S8 A 0 D ADDRESS DECODER A 1 A 2 EN (ENABLE INPUT) S1A S3A S2A S4A S1B S2B S3B S4B DA D B LOGIC TRIP POINT REF LOGIC INTERFACE AND LEVEL SHIFTER DECODER A X TYPICAL SWITCH SX D X GND LOGIC A X INPUT OR EN DG506A, DG507A, DG508A, DG509A

Absolute Maximum Ratings Thermal Information Digital Inputs, V Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC Maximum Storage Temperature (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX , DX, EN , or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified PARAMETER TEST CONDITIONS UNITS (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX DYNAMIC CHARACTERISTICS Switching Time of Multiplexer, t TRANSITION See Figure 1 - 0.6 1 - 0.6 - µs Break-Before-Make Interval, tOPEN See Figure 3 - 0.2 - - 0.2 - µs Enable Turn-ON Time, tON(EN) See Figure 2 - 1 1.5 - 1 - µs Enable Turn-OFF Time, tOFF(EN) See Figure 2 - 0.4 1.0 - 0.4 - µs OFF Isolation, OIRR V EN = 0V, RL = 1kΩ , CL = 15pF, VS = 7VRMS , f = 500kHz (Note 5) -6 8- -6 8- d B Source OFF Capacitance, C S(OFF) VS = 0V, VEN = 0V, f = 140kHz DG506A, DG507A - 6 - - 6 - pF DG508A, DG509A - 5 - - 5 - pF Drain OFF Capacitance, C D(OFF) VD = 0V, VEN = 0V, f = 140kHz DG506A - 45 - - 45 - pF DG507A - 23 - - 23 - pF DG508A - 25 - - 25 - pF DG509A - 12 - - 12 - pF Charge Injection, Q See Figure 4 DG506A, DG507A - 6 - - 6 - pC DG508A, DG509A - 4 - - 4 - pC DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, I AH VA = 15V - 0.006 10 - 0.006 10 µA Address Input Current Input Voltage Low, IAL VEN = 2.4V V A = 0V -10 -0.002 - -10 -0.002 - µA VEN = 0V -10 -0.002 - -10 -0.0002 - µA DG506A, DG507A, DG508A, DG509A

ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) Sequence Each Switch ON V AL = 0.8V VAH = 2.4V IS = -200µA, VD = +10V - 270 400 - 270 450 Ω IS = -200µA, VD = -10V - 230 400 - 230 450 Ω rDS(ON) Matching Between Channels Source OFF Leakage Current, IS(OFF) VEN = 0V V S = +10V, VD = -10V -1 0.002 1 -5 0.002 5 nA VS = -10V, VD = +10V -1 -0.005 1 -5 -0.005 5 nA Drain OFF Leakage Current, ID(OFF) VEN = 0V DG506A V S = -10V, VD = +10V -10 0.02 10 -20 0.02 20 nA VS = +10V, VD = -10V -10 -0.03 10 -20 -0.03 20 nA DG507A V S = -10V, VD = +10V -5 0.007 5 -10 0.007 10 nA VS = +10V, VD = -10V -5 -0.015 5 -10 -0.015 10 nA DG508A V S = -10V, VD = +10V - 0.01 10 - 0.01 20 nA DG509A V S = -10V, VD = +10V - 0.005 10 - 0.005 20 nA Drain ON Leakage Current, ID(ON) (Note 6) Sequence Each Switch ON V AL = 0.8V VAH = 2.4V DG506A V D = VS(ALL) = +10V -10 0.03 10 -20 0.03 20 nA VD = VS(ALL) = -10V -10 -0.06 10 -20 -0.06 20 nA DG507A V D = VS(ALL) = +10V -5 0.015 5 -10 0.015 10 nA VD = VS(ALL) = -10V -5 -0.03 5 -10 -0.03 10 nA DG508A V D = VS(ALL) = +10V - 0.015 10 - 0.015 20 nA DG509A V D = VS(ALL) = +10V - 0.007 10 - 0.007 20 nA POWER SUPPLY CHARACTERISTICS Positive Supply Current, V EN = 5.0V, VA = 0V (Enabled) Negative Supply Current, Positive Supply Current, I+ Standby VEN = 0V, VA = 0V (Standby) Negative Supply Current, I- Standby Electrical SpecificationsTA = 25oC, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS UNITS (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX (NOTE 4) MIN (NOTE 3) TYP (NOTE 4) MAX ∆ rDS ON() rDS(ON)MAX rDS ON() MIN– rDS ON() AVG DG506A, DG507A, DG508A, DG509A

Electrical SpecificationsTA = Over Operating Temperature Range, V+ = +15V, V- = -15V, GND = 0V, VEN = 2.4V, Unless Otherwise Specified PARAMETER TEST CONDITIONS UNITSMIN (NOTE 3) TYP MAX MIN (NOTE 3) TYP MAX DIGITAL INPUT CHARACTERISTICS Address Input Current, Input Voltage High, I AH VA = 15V - - 30 - - - µA Address Input Current Input Voltage Low, IAL VEN = 2.4V V A = 0V -30 - - - - - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG Drain-Source ON Resistance, rDS(ON) Sequence Each Switch ON V AL = 0.8V VAH = 2.4V Source OFF Leakage Current, IS(OFF) VEN = 0V V S = +10V, VD = -10V - - 50 - - - nA Drain OFF Leakage Current, ID(OFF) VEN = 0V DG506A V S = -10V, VD = +10V - - 300 - - - nA DG507A V S = -10V, VD = +10V - - 200 - - - nA DG508A V S = -10V, VD = +10V - - 200 - - - nA DG509A V S = -10V, VD = +10V - - 100 - - - nA Drain ON Leakage Current, ID(ON) (Note 6) Sequence Each Switch ON V AL = 0.8V VAH = 2.4V DG506A V D = VS(ALL) = +10V - - 300 - - - nA VD = VS(ALL) = -10V -300 - - - - - nA DG507A V D = VS(ALL) = +10V - - 200 - - - nA VD = VS(ALL) = -10V -200 - - - - - nA DG508A V D = VS(ALL) = +10V - - 200 - - - nA VD = VS(ALL) = -10V -200 - - - - - nA DG509A V D = VS(ALL) = +10V - - 100 - - - nA VD = VS(ALL) = -10V -100 - - - - - nA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V Negative Supply Current, I- -3.2 - 4.5 - - - mA Positive Standby Supply Current, I+ V Negative Standby Supply Current, I- -3.2 - 4.5 - - - mA NOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive value is a maximum, is used in this data sheet. 5. Off isolation = 20Log |V S |/|VD |, where VS = input to Off switch, and VD = output due to VS . 6. ID(ON) is leakage from driver into “ON” switch. 7. Parameter not tested. Parameter guaranteed by design or characterization. DG506A, DG507A, DG508A, DG509A

DIE DIMENSIONS: 3810µm x 2770µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kÅ ±1.4kÅ Nitride: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG506A NC NC V+ D V- GND NC A 3 A 2 A 1 A 0 EN S16 S15 S14 S13 S12 S11 S10 DG506A

DIE DIMENSIONS: 3810µm x 2770µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kÅ ±1.4kÅ Nitride: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG507A NC D B V+ D A V- S8A S7A S6A S5A S4A S3A S2A S1A GND NC NC A 2 A 1 A 0 EN S8B S7B S6B S5B S4B S3B S2B S1B DG507A

DIE DIMENSIONS: 3100µm x 2083µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kÅ ±1.4kÅww Nitride: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG508A EN A 0 A 1 A 2 GND S4 DS 8 DG508A

DIE DIMENSIONS: 3100µm x 2083µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride Thickness: PSG: 7kÅ ±1.4kÅ Nitride: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG509A EN A 0 A 1 GND S1B S2B S3B S4B S4A DA D B S1A S2A S3A DG509A

DG506A, DG507A, DG508A, DG509A Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3(JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93

DG506A, DG507A, DG508A, DG509A Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E28.6(JEDEC MS-001-BF ISSUE D)

28 LEAD NARROW BODY DUAL-IN-LINE PLASTIC

A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.380 1.565 35.1 39.7 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - e A 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N2 8 2 8 9 Rev. 0 12/93

DG506A, DG507A, DG508A, DG509A Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0o 8o 0o 8o - Rev. 0 12/93

DG506A, DG507A, DG508A, DG509A Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 8 2 8 7 α 0o 8o 0o 8o - Rev. 0 12/93

DG506A, DG507A, DG508A, DG509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F16.3MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N1 6 1 6 8 Rev. 0 4/94

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 DG506A, DG507A, DG508A, DG509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F28.6MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 1.490 - 37.85 5 E 0.500 0.610 12.70 15.49 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N2 8 2 8 8 Rev. 0 4/94