DG401883 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
  • ON-Resistance <35Ω
  • Low Power Consumption (P D <35µW)
  • Fast Switching Action -t ON <150ns -t OFF <100ns
  • Low Charge Injection
  • DG401/883 Dual SPST; Replaces HI-5041/883
  • DG403/883 Dual SPDT; Replaces DG190/883B, IH5043/883B, IH5151/883B, HI-5051/883, HI-5043/883B
  • DG405/883 Dual DPST; Replaces DG184/883B, HI-5045/883, IH5145/883B
  • TTL, CMOS Compatible
  • Single or Split Supply Operation

Applications

  • Audio Switching
  • Battery Operated Systems
  • Data Acquisition
  • Hi-Rel Systems
  • Sample and Hold Circuits
  • Communication Systems June 1994 Pinouts DG401/883 (CERDIP) TOP VIEW DG403/883, DG405/883 (CERDIP) TOP VIEW D 1 NC NC NC NC NC D NC GND V L IN IN1 (NC) NO CONNECTION D 1 NC D 3 D 4 D 2 NC GND VL IN2 IN1 (NC) NO CONNECTION

Description

The DG401/883, DG403/883 and DG405/883 monolithic CMOS analog switches have TTL and CMOS compatible digital inputs. These switches feature low analog ON resistance (<35Ω ) and fast switch time (t ON <150ns). Low charge injection sim- plifies sample and hold applications. The improvements in the DG401/403/405/883 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range per- mits controlling 30V peak-to-peak signals. Power supplies may be single-ended from +5V to +34V, or split from±5V to ±17V. The analog switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with ana- log signals is quite low over a±15V analog input range. The three different devices provide the equivalent of two SPST (DG401/883), two SPDT (DG403/883) or two DPST (DG405/883) relay switch contacts with CMOS or TTL level activation. The pinout is similar, permitting a standard layout to be used, choosing the switch function as needed.

Ordering Information

DG401AK/883 -55 oC to +125oC 16 Lead CERDIP DG403AK/883 -55 oC to +125oC 16 Lead CERDIP DG405AK/883 -55 oC to +125oC 16 Lead CERDIP Spec Number 512046 File Number 3703

DG401/883, DG403/883, DG405/883 Functional Diagrams Schematic Diagram Truth Table DG401/883 DG403/883 DG405/883 LOGIC DG401/883 DG403/883 DG405/883 SWITCH SWITCH 1, 2 SWITCH 3, 4 SWITCH

0 OFF OFF ON OFF

1 ON ON OFF ON

NOTE: Logic “0”≤0.8V. Logic “1”≥2.4V. 1S1 IN1 IN2 D 1 D 2 VL V+ GND V- 12 11 13 14 IN1 IN2 D 1 D 3 D 2 D 4 VL V+ GND V- 12 11 13 14 IN1 IN2 D 1 D 3 D 2 D 4 VL V+ GND V- 12 11 13 14 VL VIN GND DRAIN SOURCE Spec Number 512046

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Table 3 Intentionally Left Blank. TABLE 4. ELECTRICAL TEST REQUIREMENTS

  1. PDA applies to Subgroup 1 only.

DIE DIMENSIONS: 2150µm x 1720µm x 485± 25µm METALLIZATION: Type: Si - Al Thickness: 12k Å ± 1kÅ GLASSIVATION: Type: Nitride Thickness: 8k Å ± 1kÅ WORST CASE CURRENT DENSITY: 1.5 x 105A/cm2 Metallization Mask Layout DG401/883 D1 S1 IN1 GND VL IN2S2D2 NC NC NC NC Spec Number 512046

DG403/883, DG405/883 Die Characteristics DIE DIMENSIONS: 2150µm x 1720µm x 485± 25µm METALLIZATION: Type: Si - Al Thickness: 12k Å ± 1kÅ GLASSIVATION: Type: Nitride Thickness: 8k Å ± 1kÅ WORST CASE CURRENT DENSITY: 1.5 x 105A/cm2 Metallization Mask Layout DG403/883, DG405/883 D1 S1 IN1 GND VL IN2S2D2 Spec Number 512046

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com DG401/883, DG403/883, DG405/883 NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 11. Materials: Compliant to MIL-I-38535. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F16.3MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N1 6 1 6 8 Rev. 0 4/94 Ceramic Dual-In-Line Frit Seal Packages (CerDIP) Spec Number 512046