DG40135 MAXIM | Alldatasheet
Document overview
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Technical content
SCOPE: IMPROVED, DUAL, HIGH-SPEED CHANNEL ANALOG SWITCHES Device Type Generic Number
01 DG401A(x)/883B
02 DG403A(x)/883B
03 DG405A(x)/883B
Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows: Outline Letter Mil-Std-1835 Case Outline Package Code K GDIP1-T16 or CDIP2-T16 16 LEAD CERDIP J16 Z CQCC1-N20 20-Pin Ceramic LCC L20 Absolute Maximum Ratings Voltage Referenced to V- or 20mA whichever occu rs first. Thermal Resistance, Junction to Case, Θ JC: Thermal Resistance, Junction to Ambient, Θ JA: Recommended Operating Conditions 1/ Signals on SX, DX or INX exceeding V+ or V- are clamped by internal diodes. Limit forward current to maximum current ratings. 2/ Crosstalk performance is improved with case outline for 20LCC. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Page 2 of 7
TABLE 1. ELECTRICAL TESTS
V+=+15V, V-=-15V, GND=0V VINH=2.4V, VINL=0.8V, VL=5V Unless otherwise specified Group A Subgroup Device type Limits Min Limits Max Units DYNAMIC Turn-On Time tON Figure 2 9 All 150 ns Turn-Off Time tOFF Figure 2 9 All 100 ns Break-Before- Make Delay 4/ tD DG403 only, Figure 3 9 02 10 ns Charge Injection 4/ Q CL=1.0nF, VGEN=0V, RGEN=0Ω Figure 4
9 All 15 pC
NOTE 3: This data sheet uses the algebraic convention, where the most negative value is a minimum and the most positive value is a maximum. NOTE 4: Guaranteed by design. NOTE 5: ∆ rON=∆rON(max)-∆rON(min). On-resistance match between channels and flatness are guaranteed only with specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured at the extremes of the specified analog signal range. FIGURE 1: SWITCHING TIME TEST CIRCUIT: See Commercial Data Sheet FIGURE 2: SWITCHING TIME TEST CIRCUIT: See Commercial Data Sheet FIGURE 3: BREAK-BEFORE-MAKE INTERVAL: See Commercial Data Sheet FIGURE 4: CHARGE INJECTION: See Commercial Data Sheet ORDERING INFORMATION: DG401AK/883B 16 CDIP DG403AZ/883B 20 LCC DG401AZ/883B 20 LCC DG405AK/883B 16 CDIP DG403AK/883B 16 CDIP DG405AZ/883B 20 LCC TRUTH TABLES: DG401 DG401 DG403 DG403 DG403 DG405 DG405 LOGIC SWITCH LOGIC SWITCHES 1, 2 SWITCHES 3,4 LOGIC SWITCH
0 OFF 0 OFF ON 0 OFF
1 ON 1 ON OFF 1 ON
TERMINAL CONNECTIONS: DG401 DG401 DG403 DG403 DG405 DG405 J16 LCC20 J16 LCC20 J16 LCC20 1D 1 N CD 1 N C D 1 N C 2N CD 1N C D 1 N CD 1 3N CN CD 3 N C D 3 N C 4N CN CS 3D 3 S 3 D 3 5N CN CS 4S 3S 4 S 3 6N CN CD 4 N C D 4 N C 7N CN CN C S 4N CS 4 8D 2 N CD 2 D 4 D 2 D 4 9S 2 N CS 2N C S 2 N C
10 IN2 D2 IN2 D2 IN2 D2
11 V+ NC V+ NC V+ NC
12 V L S2 V L S2 V L S2
13 GND IN2 GND IN2 GND IN2
14 V- V+ V- V+ V- V+
15 IN1 V L IN1 V L IN1 V L
16 S1 NC S1 NC S1 NC
17 GND GND GND
18 V- V- V-
19 IN1 IN1 IN1
20 S1 S1 S1
- Test Condition, A, B, C, or D.
- Interim and final electrical test requirements shall be specified in Table 2.
- Tests as specified in Table 2.
- Selected subgroups in Table 1, Method 5005 of Mil-Std-883 shall be omitted.
a. End-point electrical parameters shall be specified in Table 1.
- Test condition A, B, C, D.
- Test duration, 1000 hours, except as permitted by Method 1005 of Mil-Std-883.
TABLE 2. ELECTRICAL TEST REQUIREMENTS
- PDA applies to Subgroup 1 only.
** Subgroups 10 and 11, if not tested shall be guaranteed to the limits of Table 1.